CN117200639B

CN117200639B - Decoding compensation method, system, device and medium for motor rotary transformer

Info

Publication number: CN117200639B
Application number: CN202311455014.8A
Authority: CN
Inventors: 顾聪; 盛田田
Original assignee: Suzhou Saideer Intelligent Technology Co ltd
Current assignee: Suzhou Saideer Intelligent Technology Co ltd
Priority date: 2023-11-03
Filing date: 2023-11-03
Publication date: 2024-01-26
Anticipated expiration: 2043-11-03
Also published as: CN117200639A

Abstract

The invention discloses a decoding compensation method, a system, a device and a medium of a rotary transformer of a motor, wherein the method comprises the steps of utilizing a demodulation unit to obtain a sine and cosine feedback signal after demodulation of the rotary transformer; respectively carrying out direct current bias compensation and amplitude asymmetry compensation on the sine and cosine feedback signals to obtain initial compensation sine and cosine signals; performing phase asymmetric compensation on the initial compensation sine and cosine signals to obtain target compensation sine and cosine signals; and carrying out carrier modulation on the target compensation sine and cosine signals by using a phase-locked loop unit, and outputting a target position signal and a target speed signal corresponding to the target compensation sine and cosine signals so as to drive the motor to operate. The invention can avoid feedback speed fluctuation and feedback position error caused by three types of low-frequency errors, obtain more accurate target compensation sine and cosine signals, further obtain accurate target position signals and target speed signals, realize decoding compensation of the rotary transformer and ensure stable and reliable motor driving system performance.

Description

Decoding compensation method, system, device and medium for motor rotary transformer

Technical Field

The invention relates to the technical field of motor driving, in particular to a decoding compensation method, a decoding compensation system, a decoding compensation device and a decoding compensation medium for a motor rotary transformer.

Background

The rotary transformer is an electromagnetic sensor, is a commonly used speed and position sensor in a motor driving system, is used for feeding back a speed signal and a position signal of a motor rotor in real time, and is widely applied to the fields of servo control systems, robot systems, automobiles, mechanical tools, aviation and the like. When the rotary transformer is used, the rotary transformer output rotary transformation signals (including sine signals, cosine signals and carrier signals) need to be decoded on hardware to obtain speed signals and position signals, namely 'hardware decoding'.

At present, in order to realize hardware decoding of a rotary transformer, only two parts of a demodulation unit and a phase-locked loop unit are generally configured, the demodulation unit is utilized to demodulate a rotary signal in the rotary transformer, and then the phase-locked loop unit is utilized to control carrier frequency, so that an input signal and an output signal of the rotary transformer keep carrier synchronization, and further a speed signal and a position signal for controlling motor driving are obtained. However, for the rotary transformer with low-frequency feedback error, feedback speed fluctuation and feedback position deviation can be generated, and a traditional demodulation unit and phase-locked loop unit architecture can generate larger feedback precision error of speed signals and position signals, so that the performance of a motor driving system is affected.

Disclosure of Invention

In view of the above, the present invention provides a method, a system, a device and a medium for decoding and compensating a rotary transformer of a motor, so as to solve the problem that the existing rotary transformer decoding technology can generate larger feedback precision errors of a speed signal and a position signal, thereby affecting the performance of a motor driving system.

The invention provides a decoding compensation method of a rotary transformer of a motor, wherein the rotary transformer is provided with a demodulation unit and a phase-locked loop unit, the demodulation unit is used for demodulating a rotary signal output by the rotary transformer, and the phase-locked loop unit is used for modulating an input signal of the rotary transformer by a carrier; the method comprises the following steps:

the demodulating unit is used for obtaining a sine and cosine feedback signal after demodulation of the rotary transformer;

respectively carrying out direct current bias compensation and amplitude asymmetry compensation on the sine and cosine feedback signals to obtain initial compensation sine and cosine signals;

performing phase asymmetric compensation on the initial compensation sine and cosine signals to obtain target compensation sine and cosine signals;

and carrying out carrier modulation on the target compensation sine and cosine signal by using the phase-locked loop unit, and outputting a target position signal and a target speed signal corresponding to the target compensation sine and cosine signal so as to drive a motor to operate.

Optionally, the sine and cosine feedback signals include sine feedback signals and cosine feedback signals; the initial compensation sine and cosine signals comprise initial compensation sine signals and initial compensation cosine signals;

the direct current bias compensation and the amplitude asymmetry compensation are respectively carried out on the sine and cosine feedback signals to obtain initial compensation sine and cosine signals, and the method comprises the following steps:

peak-to-valley sampling is carried out on the sine feedback signal and the cosine feedback signal respectively to obtain a first peak value and a first valley value corresponding to the sine feedback signal and a second peak value and a second valley value corresponding to the cosine feedback signal;

performing direct current bias compensation on the sinusoidal feedback signal based on the first peak value and the first valley value to obtain a first sinusoidal compensation signal; performing direct current offset compensation on the cosine feedback signal according to the second peak value and the second valley value to obtain a first cosine compensation signal;

performing amplitude asymmetric compensation on the sine feedback signal and the cosine feedback signal according to the first peak value, the first valley value, the second peak value and the second valley value to obtain a second sine compensation signal corresponding to the sine feedback signal and a second cosine compensation signal corresponding to the cosine feedback signal;

Obtaining the initial compensation sinusoidal signal according to the sinusoidal feedback signal, the first sinusoidal compensation signal and the second sinusoidal compensation signal; and obtaining the initial compensation cosine signal according to the cosine feedback signal, the first cosine compensation signal and the second cosine compensation signal.

Optionally, the direct current bias compensation is performed on the sinusoidal feedback signal based on the first peak value and the first valley value, so as to obtain a first sinusoidal compensation signal; performing dc offset compensation on the cosine feedback signal according to the second peak value and the second valley value to obtain a first cosine compensation signal, including:

adopting an addition operation method to respectively calculate a first direct current offset value between the first peak value and the first valley value and a second direct current offset value between the second peak value and the second valley value;

pre-establishing a first error regulator and a second error regulator;

taking the first direct current offset value as an input variable of the first error regulator, taking the first sine compensation signal as an output variable of the first error regulator, and obtaining the first sine compensation signal by using the first error regulator;

And taking the second direct current offset value as an input variable of the second error regulator, taking the first cosine compensation signal as an output variable of the second error regulator, and obtaining the first cosine compensation signal by using the second error regulator.

Optionally, the performing amplitude asymmetry compensation on the sine feedback signal and the cosine feedback signal according to the first peak value, the first valley value, the second peak value and the second valley value to obtain a second sine compensation signal corresponding to the sine feedback signal and a second cosine compensation signal corresponding to the cosine feedback signal, including:

a subtraction method is adopted to respectively calculate a first peak value between the first peak value and the first valley value and a second peak value between the second peak value and the second valley value;

calculating a first difference value of the second peak-to-peak value relative to the first peak-to-peak value by using the first peak-to-peak value as a reference and adopting the subtraction method, and taking the first difference value as a first amplitude error signal of the cosine feedback signal relative to the sine feedback signal;

pre-constructing a third error regulator;

Taking the sine feedback signal as a corresponding second sine compensation signal, taking the first amplitude error signal as an input variable of the third error regulator, taking the second cosine compensation signal as an output variable of the third error regulator, and obtaining the second cosine compensation signal corresponding to the cosine feedback signal by using the third error regulator;

or,

calculating a second difference value of the first peak-to-peak value relative to the second peak-to-peak value by using the second peak-to-peak value as a reference and adopting the subtraction method, and taking the second difference value as a second amplitude error signal of the sine feedback signal relative to the cosine feedback signal;

pre-constructing a fourth error regulator;

and taking the cosine feedback signal as the corresponding second cosine compensation signal, taking the second amplitude error signal as the input variable of the fourth error regulator, taking the second sine compensation signal as the output variable of the fourth error regulator, and obtaining the second sine compensation signal corresponding to the sine feedback signal by using the fourth error regulator.

Optionally, when the sinusoidal feedback signal is used as the corresponding second sinusoidal compensation signal, the initial compensation sinusoidal signal is obtained according to the sinusoidal feedback signal, the first sinusoidal compensation signal and the second sinusoidal compensation signal; obtaining the initial compensated cosine signal according to the cosine feedback signal, the first cosine compensation signal and the second cosine compensation signal, including:

adding the sinusoidal feedback signal and the first sinusoidal compensation signal to obtain the initial compensation sinusoidal signal; adding the cosine feedback signal, the first cosine compensation signal and the second cosine compensation signal to obtain the initial compensation cosine signal;

when the cosine feedback signal is used as the corresponding second cosine compensation signal, the initial compensation sine signal is obtained according to the sine feedback signal, the first sine compensation signal and the second sine compensation signal; obtaining the initial compensated cosine signal according to the cosine feedback signal, the first cosine compensation signal and the second cosine compensation signal, including:

adding the sinusoidal feedback signal, the first sinusoidal compensation signal and the second sinusoidal compensation signal to obtain the initial compensation sinusoidal signal; and adding the cosine feedback signal and the first cosine compensation signal to obtain the initial compensation cosine signal.

Optionally, the target compensated sine and cosine signals include a target compensated sine signal and a target compensated cosine signal;

the step of performing phase asymmetry compensation on the initial compensation sine and cosine signal to obtain a target compensation sine and cosine signal comprises the following steps:

multiplying the initial compensation sine signal and the initial compensation cosine signal to obtain a phase error signal between the initial compensation sine signal and the initial compensation cosine signal;

performing peak-to-valley value sampling on the phase error signal to obtain a third peak value and a third valley value corresponding to the phase error signal;

calculating a third direct current offset value between the third peak value and the third valley value by adopting an addition operation method;

based on the third direct current offset value, carrying out phase asymmetric compensation on the initial compensation sine signal by taking the initial compensation cosine signal as a reference to obtain a third sine compensation signal corresponding to the initial compensation sine signal; determining the initial compensation cosine signal as the corresponding target compensation cosine signal, and adding the initial compensation sine signal and the third sine compensation signal to obtain the target compensation sine signal; or, based on the third direct current offset value, carrying out phase asymmetric compensation on the initial compensation cosine signal by taking the initial compensation sine signal as a reference to obtain a third cosine compensation signal corresponding to the initial compensation cosine signal; and determining the initial compensation sine signal as the corresponding target compensation sine signal, and adding the initial compensation cosine signal and the third cosine compensation signal to obtain the target compensation cosine signal.

Optionally, based on the third dc offset value, the performing phase asymmetric compensation on the initial compensation sine signal with the initial compensation cosine signal as a reference to obtain a third sine compensation signal corresponding to the initial compensation sine signal, where the step of obtaining the third sine compensation signal includes:

pre-establishing a fifth error regulator;

taking the third direct current offset value as an input variable of the fifth error regulator, taking a third sine compensation signal as an output variable of the fifth error regulator, and obtaining the third sine compensation signal by using the fifth error regulator;

the step of performing phase asymmetry compensation on the initial compensation cosine signal based on the third dc offset value by using the initial compensation sine signal as a reference to obtain a third cosine compensation signal corresponding to the initial compensation cosine signal, including:

pre-establishing a sixth error regulator;

and taking the third direct current offset value as an input variable of the sixth error regulator, taking a third cosine compensation signal as an output variable of the sixth error regulator, and obtaining the third cosine compensation signal by using the sixth error regulator.

In addition, the invention also provides a decoding compensation system of the motor rotary transformer, wherein the rotary transformer is provided with a demodulation unit and a phase-locked loop unit, the demodulation unit is used for demodulating a rotary-change signal output by the rotary transformer, and the phase-locked loop unit is used for carrying out carrier modulation on an input signal of the rotary transformer; in the decoding compensation method applied to the motor rotary transformer, the system comprises the following steps:

The feedback signal acquisition module is used for acquiring a sine and cosine feedback signal demodulated by the rotary transformer by utilizing the demodulation unit;

the first compensation module is used for respectively carrying out direct current bias compensation and amplitude asymmetry compensation on the sine and cosine feedback signals to obtain initial compensation sine and cosine signals;

the second compensation module is used for carrying out phase asymmetric compensation on the initial compensation sine and cosine signal to obtain a target compensation sine and cosine signal;

and the target signal output module is used for carrying out carrier modulation on the target compensation sine and cosine signals by utilizing the phase-locked loop unit and outputting target position signals and target speed signals corresponding to the target compensation sine and cosine signals so as to drive a motor to operate.

In addition, the invention also provides a decoding compensation device of the motor rotary transformer, which comprises the following components:

the demodulation unit is in communication connection with the rotary transformer and is used for demodulating the rotary signal output by the rotary transformer to obtain a sine and cosine feedback signal;

the decoding compensation system of the motor rotary transformer is in communication connection with the demodulation unit and is used for obtaining the sine and cosine feedback signals demodulated by the demodulation unit of the rotary transformer, and obtaining target compensation sine and cosine signals after direct current offset compensation, amplitude asymmetry compensation and phase asymmetry compensation are carried out on the sine and cosine feedback signals; and

And the phase-locked loop unit is in communication connection with the decoding compensation system of the motor rotary transformer and is used for carrying out carrier modulation on the target compensation sine and cosine signals and outputting target position signals and target speed signals corresponding to the target compensation sine and cosine signals so as to drive the motor to operate.

Furthermore, the present invention provides a computer storage medium including: at least one instruction, when executed, implements the method steps of the aforementioned method of decode compensation of a motor resolver.

The invention has the beneficial effects that: demodulating the rotation signal by using a demodulation unit to obtain a sine and cosine feedback signal without carrier components, respectively carrying out direct current offset compensation and amplitude asymmetry compensation on the sine and cosine feedback signal, and then carrying out phase asymmetry compensation, so that three types of low-frequency errors in the sine and cosine feedback signal, including direct current offset, amplitude asymmetry and phase asymmetry (or phase non-orthogonality), can be overcome, feedback speed fluctuation and feedback position error caused by the low-frequency errors are avoided, and further a more accurate target compensation sine and cosine signal is obtained; and finally, by utilizing the carrier modulation function of the phase-locked loop unit, the signals at the input end and the output end of the phase-locked loop unit can keep carrier synchronization, and accurate target position signals and target speed signals are obtained based on the accurate target compensation sine and cosine signals, so that the decoding compensation of the rotary transformer is realized, and the stable and reliable motor driving system performance is ensured.

Drawings

The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and should not be construed as limiting the invention in any way, in which:

fig. 1 is a flowchart of a method for decoding and compensating a resolver of a motor according to a first embodiment of the present invention;

fig. 2A is a signal waveform diagram showing that the sine and cosine feedback signals do not contain low frequency errors in the first embodiment of the present invention;

fig. 2B shows a signal waveform diagram of a sine and cosine feedback signal including a dc offset according to a first embodiment of the present invention;

fig. 2C shows a waveform diagram of a signal with asymmetric amplitude in a sine and cosine feedback signal according to the first embodiment of the present invention;

fig. 2D is a waveform diagram of a signal containing phase asymmetry in a sine and cosine feedback signal according to a first embodiment of the present invention;

FIG. 3 is a flowchart showing DC offset compensation and amplitude asymmetry compensation for sine and cosine feedback signals, respectively, according to a first embodiment of the present invention;

FIG. 4A is a complete flow chart of a first alternative embodiment of DC offset compensation and amplitude asymmetry compensation in accordance with an embodiment of the invention;

FIG. 4B is a complete flow chart of a second alternative embodiment of DC offset compensation and amplitude asymmetry compensation in accordance with the first embodiment of the invention;

FIG. 5A shows a complete flow chart of a first alternative embodiment of phase asymmetry compensation in accordance with embodiment of the invention;

FIG. 5B shows a complete flow chart of a second alternative embodiment of phase asymmetry compensation in accordance with embodiment of the invention;

FIG. 6 is a block diagram of a decoding compensation system for a resolver of an electric motor according to a second embodiment of the present invention;

fig. 7 is a block diagram showing a decoding and compensating apparatus of a resolver for a motor according to a third embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.

Example 1

The decoding compensation method of the motor rotary transformer comprises the steps that the rotary transformer is provided with a demodulation unit and a phase-locked loop unit, the demodulation unit is used for demodulating a rotary signal output by the rotary transformer, and the phase-locked loop unit is used for modulating an input signal of the rotary transformer by a carrier; as shown in fig. 1, the method includes:

S1: the demodulating unit is used for obtaining a sine and cosine feedback signal after demodulation of the rotary transformer;

s2: respectively carrying out direct current bias compensation and amplitude asymmetry compensation on the sine and cosine feedback signals to obtain initial compensation sine and cosine signals;

s3: performing phase asymmetric compensation on the initial compensation sine and cosine signals to obtain target compensation sine and cosine signals;

s4: and carrying out carrier modulation on the target compensation sine and cosine signal by using the phase-locked loop unit, and outputting a target position signal and a target speed signal corresponding to the target compensation sine and cosine signal so as to drive a motor to operate.

Demodulating the rotation signal by using a demodulation unit to obtain a sine and cosine feedback signal without carrier components, respectively carrying out direct current offset compensation and amplitude asymmetry compensation on the sine and cosine feedback signal, and then carrying out phase asymmetry compensation, so that three types of low-frequency errors in the sine and cosine feedback signal, including direct current offset, amplitude asymmetry and phase asymmetry (or phase non-orthogonality), can be overcome, feedback speed fluctuation and feedback position error caused by the low-frequency errors are avoided, and further a more accurate target compensation sine and cosine signal is obtained; and finally, by utilizing the carrier modulation function of the phase-locked loop unit, the signals at the input end and the output end of the phase-locked loop unit can keep carrier synchronization, and accurate target position signals and target speed signals are obtained based on the accurate target compensation sine and cosine signals, so that the decoding compensation of the rotary transformer is realized, and the stable and reliable motor driving system performance is ensured.

Each step of the decoding compensation method of the motor resolver is described in detail below.

In this embodiment S1, the demodulation unit is communicatively connected to the resolver, and receives the carrier signal SC output from the resolver and the sine and cosine signal containing the carrier component (including the sine signal sin containing the carrier componentωt) SC and cosine signal cos with carrier componentωt) SC), demodulating the carrier signal and the sine and cosine signal to obtain a sine and cosine feedback signal (including sine feedback signal sin #)ωt) And cosine feedback signal cosωt)). When the demodulation unit demodulates the signal, the carrier signal SC is multiplied by the sine and cosine signal containing the carrier component, and then the signal is filtered by the low-pass filter, so that signal demodulation can be realized, and a sine and cosine feedback signal without the carrier component is obtained.

When the sine and cosine feedback signal without carrier wave component does not contain low frequency error, the signal waveform diagram is shown in fig. 2A; when the three types of low-frequency errors are included, namely, the direct-current bias, the amplitude asymmetry and the phase asymmetry are included, the signal waveform diagrams are shown in fig. 2B-2D.

Preferably, before S2, the method further comprises:

and performing depth filtering on the sine and cosine feedback signals.

Through depth filtering, a very smooth sine and cosine feedback signal can be obtained, follow-up accurate peak-to-valley value sampling is facilitated, and the precision of the whole compensation process is further improved based on sampling values.

In this embodiment S2, the sine and cosine feedback signals include a sine feedback signal and a cosine feedback signal; the initial compensation sine and cosine signals comprise initial compensation sine signals and initial compensation cosine signals;

as shown in fig. 3, S2 includes:

s21: peak-to-valley sampling is carried out on the sine feedback signal and the cosine feedback signal respectively to obtain a first peak value and a first valley value corresponding to the sine feedback signal and a second peak value and a second valley value corresponding to the cosine feedback signal;

s22: performing direct current bias compensation on the sinusoidal feedback signal based on the first peak value and the first valley value to obtain a first sinusoidal compensation signal; performing direct current offset compensation on the cosine feedback signal according to the second peak value and the second valley value to obtain a first cosine compensation signal;

s23: performing amplitude asymmetric compensation on the sine feedback signal and the cosine feedback signal according to the first peak value, the first valley value, the second peak value and the second valley value to obtain a second sine compensation signal corresponding to the sine feedback signal and a second cosine compensation signal corresponding to the cosine feedback signal;

S24: obtaining the initial compensation sinusoidal signal according to the sinusoidal feedback signal, the first sinusoidal compensation signal and the second sinusoidal compensation signal; and obtaining the initial compensation cosine signal according to the cosine feedback signal, the first cosine compensation signal and the second cosine compensation signal.

As shown in the waveform diagrams of fig. 2B and 2C, when the sine feedback signal (or the cosine feedback signal) has dc bias and asymmetric amplitude, both the peak value and the valley value of the waveform can be directly caused to deviate; therefore, based on the first peak value, the first valley value, the second peak value and the second valley value obtained by peak-valley value sampling, direct current bias compensation and amplitude asymmetry compensation can be respectively realized. When the sine and cosine feedback signals are subjected to direct current bias compensation, corresponding first sine compensation signals and first cosine compensation signals can be obtained; when the sine and cosine feedback signals are subjected to amplitude asymmetric compensation, corresponding second sine compensation signals and second cosine compensation signals can be obtained; finally, a pair of sine and cosine signals (namely initial compensation sine and cosine signals) which finish direct current offset compensation and amplitude asymmetry compensation can be obtained by using the first sine compensation signal, the first cosine compensation signal, the second sine compensation signal and the second cosine compensation signal as well as the sine feedback signal and the cosine feedback signal before uncompensation, so that feedback speed fluctuation and feedback position error caused by direct current offset and amplitude asymmetry are avoided; and the subsequent compensation of the phase asymmetry based on the initial compensation sine and cosine signals can be conveniently realized.

In this embodiment, the order of execution of the step S22 and the step S23 is not limited, that is, the step S22 may be executed first, the step S23 may be executed later, the step S23 may be executed first, the step S22 may be executed later, or the step S22 and the step S23 may be executed simultaneously.

Specifically, S22 includes:

s221: adopting an addition operation method to respectively calculate a first direct current offset value between the first peak value and the first valley value and a second direct current offset value between the second peak value and the second valley value;

s222: pre-establishing a first error regulator and a second error regulator;

s223: taking the first direct current offset value as an input variable of the first error regulator, taking the first sine compensation signal as an output variable of the first error regulator, and obtaining the first sine compensation signal by using the first error regulator;

s224: and taking the second direct current offset value as an input variable of the second error regulator, taking the first cosine compensation signal as an output variable of the second error regulator, and obtaining the first cosine compensation signal by using the second error regulator.

Adding the first peak value and the first valley value to obtain a direct current offset error (namely a first direct current offset value) in the sine feedback signal, inputting the first direct current offset value as an error signal into a first error regulator established by cosine, and obtaining a compensation signal (namely a first sine compensation signal) by utilizing the regulating function of the first error regulator; the process of dc offset compensation of the cosine feedback signal is the same as above, and will not be described here again.

In this embodiment, the first error regulator and the second error regulator may be linear error regulators such as PI regulator and I regulator. The PI regulator forms a control deviation according to a given value and an actual output value, forms a control quantity by linear combination of a proportion (P) and an integral (I) of the deviation, and controls a controlled object. I regulator is an integral regulator, the output of which is proportional to the integral (I) of the deviation, and the output of which is controlled linearly by the integral (I) of the deviation.

Specifically, in the first alternative embodiment, S23 includes:

s23A1: a subtraction method is adopted to respectively calculate a first peak value between the first peak value and the first valley value and a second peak value between the second peak value and the second valley value;

s23A2: calculating a first difference value of the second peak-to-peak value relative to the first peak-to-peak value by using the first peak-to-peak value as a reference and adopting the subtraction method, and taking the first difference value as a first amplitude error signal of the cosine feedback signal relative to the sine feedback signal;

s23A3: pre-constructing a third error regulator;

S23A4: and taking the sine feedback signal as the corresponding second sine compensation signal, taking the first amplitude error signal as the input variable of the third error regulator, taking the second cosine compensation signal as the output variable of the third error regulator, and obtaining the second cosine compensation signal corresponding to the cosine feedback signal by using the third error regulator.

In the first alternative embodiment, the sine feedback signals are used as the reference (i.e. the amplitude of the default sine feedback signals is not biased), and the error adjustment is performed based on the first peak-to-peak value and the second peak-to-peak value by using the cosine feedback signals relative to the first amplitude error signals between the sine feedback signals, so as to further realize the amplitude asymmetry compensation between the sine and cosine feedback signals, and avoid the feedback speed fluctuation and the feedback position error caused by the amplitude asymmetry.

In the first alternative embodiment described above, when the sine feedback signal is used as a reference, the amplitude of the sine feedback signal does not need to be compensated, in which case the first sine feedback signal is directly used as the corresponding second sine compensation signal (i.e. the sine feedback signal remains unchanged during the amplitude asymmetry compensation), and only the cosine feedback signal is amplitude compensated.

Specifically, in a second alternative embodiment, S23 includes:

S23B1: a subtraction method is adopted to respectively calculate a first peak value between the first peak value and the first valley value and a second peak value between the second peak value and the second valley value;

S23B2: calculating a second difference value of the first peak-to-peak value relative to the second peak-to-peak value by using the second peak-to-peak value as a reference and adopting the subtraction method, and taking the second difference value as a second amplitude error signal of the sine feedback signal relative to the cosine feedback signal;

S23B3: pre-constructing a fourth error regulator;

S23B4: and taking the cosine feedback signal as the corresponding second cosine compensation signal, taking the second amplitude error signal as the input variable of the fourth error regulator, taking the second sine compensation signal as the output variable of the fourth error regulator, and obtaining the second sine compensation signal corresponding to the sine feedback signal by using the fourth error regulator.

In the second alternative embodiment, the cosine feedback signals are used as the reference (i.e. the amplitude of the default cosine feedback signals is not biased), and the error adjustment is performed by using the second amplitude error signal between the sine feedback signals and the cosine feedback signals based on the first peak-to-peak value and the second peak-to-peak value, so that the amplitude asymmetry compensation between the sine feedback signals and the cosine feedback signals is realized, and the feedback speed fluctuation and the feedback position error caused by the amplitude asymmetry are avoided.

In the second alternative embodiment, when the cosine feedback signal is taken as a reference, the amplitude of the cosine feedback signal does not need to be compensated, and in this case, the first cosine feedback signal is directly taken as the corresponding second cosine compensation signal (i.e. the cosine feedback signal remains unchanged in the process of amplitude asymmetry compensation), and only the amplitude compensation is performed on the sine feedback signal.

In S23A1 and S23B1, two times of amplitude values can be obtained by using the subtraction operation between the first peak value and the first valley value and the subtraction operation between the second peak value and the second valley value, so that the amplification of the amplitude error is realized, the subsequent compensation of the amplitude asymmetry is facilitated based on the amplified amplitude error, and the accuracy of the compensation is improved.

The third error regulator and the fourth error regulator are similar to the first error regulator and the second error regulator, and are linear error regulators such as PI regulator and I regulator, which are built in advance, and details thereof are not described herein.

The specific process of the amplitude asymmetry compensation described in the two alternative embodiments S23 A1-S23 A4 and S23B 1-S23B 4 can be selected according to the actual situation, and the embodiment is not limited.

Specifically, for the first alternative embodiment, when the sinusoidal feedback signal is taken as the corresponding second sinusoidal compensation signal, the S24 includes:

adding the sinusoidal feedback signal and the first sinusoidal compensation signal to obtain the initial compensation sinusoidal signal; and adding the cosine feedback signal, the first cosine compensation signal and the second cosine compensation signal to obtain the initial compensation cosine signal.

Specifically, for the second alternative embodiment, when the cosine feedback signal is taken as the corresponding second cosine compensation signal, the step S24 includes:

In a first alternative embodiment, when the sinusoidal feedback signal is directly used as the second sinusoidal compensation signal, the sinusoidal feedback signal is used as a reference signal, and the initial compensation sinusoidal signal is obtained by only adding the sinusoidal feedback signal and the first sinusoidal compensation signal, so that two compensation processes of direct current offset compensation and amplitude asymmetry compensation of the sinusoidal feedback signal can be completed; and adding the cosine feedback signal, the first cosine compensation signal and the second cosine compensation signal to finish two compensation processes of DC offset compensation and amplitude asymmetry compensation of the cosine feedback signal, thereby obtaining an initial compensation cosine signal.

In a second alternative embodiment, when the cosine feedback signal is directly used as the second cosine compensation signal, the cosine feedback signal is used as a reference signal, and the amplitude asymmetry compensation is not needed, and only the cosine feedback signal is added with the first cosine compensation signal, so that two compensation processes of direct current bias compensation and amplitude asymmetry compensation of the cosine feedback signal can be completed, and an initial compensation cosine signal is obtained; and adding the sinusoidal feedback signal, the first sinusoidal compensation signal and the second sinusoidal compensation signal to complete two compensation processes of DC offset compensation and amplitude asymmetry compensation of the sinusoidal feedback signal, thereby obtaining an initial compensation sinusoidal signal.

The complete flowchart of S2 in this embodiment is shown in fig. 4A when the sine feedback signal is used as a reference, and the complete flowchart of S2 in this embodiment is shown in fig. 4B when the cosine feedback signal is used as a reference. In FIGS. 4A and 4B, the sinusoidal feedback signal is sin #ωt) After depth filtering and peak-valley value sampling, obtaining a first peak value and a first valley value which are a peak value_s1 and a valley value_s1 respectively; cosine feedback signal is cos @ωt) After depth filtering and peak-valley value sampling, obtaining a second peak value and a second valley value which are a peak value_c1 and a valley value_c1 respectively; the sine feedback signal is sin # - ωt) And cosine feedback signal is cos @ωt) After DC bias compensation and amplitude asymmetry compensation, the obtained initial compensation sine signal and initial compensation cosine signal are sin # -, respectivelyωt) Ch and cosωt)_ch。

It should be understood that, as shown in fig. 4A and fig. 4B, the dc offset compensation and the amplitude asymmetry compensation described in this embodiment are real-time compensation processes, and the initial compensation sinusoidal signal obtained after the previous time t-1 is compensated is input into the depth filter for depth filtration, and then the compensation process of the initial compensation sinusoidal signal at the current time t is continued; and the initial compensation sine signal obtained after the compensation at the current time t is input into a depth filter for depth filtration, the compensation process of the initial compensation sine signal at the next time t+1 is continued, and the like is performed at … ….

Similarly, the initial compensation cosine signal obtained after compensation at the previous time t-1 is input into a depth filter for depth filtration, and then the compensation process of the initial compensation cosine signal at the current time t is continued; and the initial compensated cosine signal obtained after the compensation at the current time t is input into a depth filter for depth filtering, and then the compensation process of the initial compensated cosine signal at the next time t+1 is continued, and the like … ….

In this embodiment S3, the target compensated sine and cosine signals include a target compensated sine signal and a target compensated cosine signal;

s3 comprises the following steps:

s31: multiplying the initial compensation sine signal and the initial compensation cosine signal to obtain a phase error signal between the initial compensation sine signal and the initial compensation cosine signal;

s32: performing peak-to-valley value sampling on the phase error signal to obtain a third peak value and a third valley value corresponding to the phase error signal;

s33: calculating a third direct current offset value between the third peak value and the third valley value by adopting an addition operation method;

s34: based on the third direct current offset value, carrying out phase asymmetric compensation on the initial compensation sine signal by taking the initial compensation cosine signal as a reference to obtain a third sine compensation signal corresponding to the initial compensation sine signal; determining the initial compensation cosine signal as the corresponding target compensation cosine signal, and adding the initial compensation sine signal and the third sine compensation signal to obtain the target compensation sine signal; or, based on the third direct current offset value, carrying out phase asymmetric compensation on the initial compensation cosine signal by taking the initial compensation sine signal as a reference to obtain a third cosine compensation signal corresponding to the initial compensation cosine signal; and determining the initial compensation sine signal as the corresponding target compensation sine signal, and adding the initial compensation cosine signal and the third cosine compensation signal to obtain the target compensation cosine signal.

Multiplying the initial compensation sine signal and the initial compensation cosine signal by using a multiplication operation method to obtain a phase error signal, sampling a peak value and a valley value of the phase error signal to obtain a third peak value and a third amplitude value, and calculating a third direct current offset value between the third peak value and the third valley value by using an addition operation method, so that the relative asymmetric compensation process can be converted into direct current offset (namely a third direct current offset value), and the phase asymmetric compensation can be realized by using a direct current offset compensation similar method conveniently, and the method is simple and effective; similar to the amplitude asymmetry compensation, in the phase asymmetry compensation process, when the initial compensation cosine signal is taken as a reference (i.e. the default initial compensation cosine signal has no phase asymmetry and does not need to be subjected to phase asymmetry compensation), the phase asymmetry compensation of the whole sine and cosine feedback signal can be realized by only carrying out the phase asymmetry compensation on the initial compensation sine signal based on the third direct current offset value, and the feedback speed fluctuation and the feedback position deviation caused by the phase asymmetry are avoided; when the initial compensation sine signal is used as a reference (i.e. the default initial compensation sine signal has no phase asymmetry and does not need to be subjected to phase asymmetry compensation), the phase asymmetry compensation of the whole sine and cosine feedback signal can be realized by only carrying out phase asymmetry compensation on the initial compensation cosine signal based on the third direct current offset value, and the feedback speed fluctuation and the feedback position deviation caused by the phase asymmetry are avoided.

Specifically, in the first alternative embodiment of S34, when the initial compensation cosine signal is taken as a reference, in S34, based on the third dc offset value, the phase asymmetry compensation is performed on the initial compensation sine signal, so as to obtain a third sine compensation signal corresponding to the initial compensation sine signal, which includes:

s34A1: pre-establishing a fifth error regulator;

s34A2: and taking the third direct current offset value as an input variable of the fifth error regulator, taking a third sine compensation signal as an output variable of the fifth error regulator, and obtaining the third sine compensation signal by using the fifth error regulator.

When the initial compensation cosine signal is used as a reference and the phase asymmetry compensation is carried out on the initial compensation sine signal based on the third direct current offset value, the error adjustment of the initial compensation sine signal on the phase can be effectively and accurately realized by utilizing the linear adjustment function of the fifth error adjuster.

Specifically, in the second alternative embodiment of S34, when the initial compensated cosine signal is taken as a reference, in S34, based on the third dc offset value, the phase asymmetry compensation is performed on the initial compensated cosine signal to obtain a third cosine compensation signal corresponding to the initial compensated cosine signal, which includes:

S34B1: pre-establishing a sixth error regulator;

S34B2: and taking the third direct current offset value as an input variable of the sixth error regulator, taking a third cosine compensation signal as an output variable of the sixth error regulator, and obtaining the third cosine compensation signal by using the sixth error regulator.

As in the first alternative embodiment of S34 above, the error adjustment of the initial compensated cosine signal in phase can be efficiently and accurately achieved based on the linear adjustment function of the sixth error adjuster.

The fifth error regulator and the sixth error regulator in this embodiment are linear error regulators such as PI regulator and I regulator, which are built in advance, and detailed details thereof are not described here.

The complete flowchart of the embodiment S3 is shown in FIG. 5BThe complete flow of this embodiment S3 is shown in fig. 5A when the initial compensated sinusoidal signal is taken as a reference. In fig. 5A and 5B, the initial compensation sine signal and the initial compensation cosine signal are sin #, respectivelyωt) Ch and cosωt) The_ch is multiplied by the peak value and the valley value is sampled to obtain a third peak value and a third valley value which are respectively a peak value_s2 and a valley value_s2, and the target compensation sine signal and the target compensation cosine signal which are obtained after error adjustment and phase addition are respectively sin # ωt) C and cosωt)_c。

Similarly, the phase asymmetry compensation described in this embodiment is also a real-time compensation process, and the target compensation sine signal and the target compensation cosine signal obtained after the previous time t-1 is compensated continue to participate in the compensation process of the target compensation sine signal and the target compensation cosine signal at the current time t; and the target compensated sine signal and the target compensated cosine signal obtained after the compensation at the current time t continue to participate in the compensation process of the target compensated sine signal and the target compensated cosine signal at the next time t+1, and so on.

In this embodiment S4, after dc offset compensation, amplitude asymmetry compensation and phase asymmetry compensation, a relatively accurate sine and cosine feedback signal (i.e. a target compensated sine and cosine signal) can be obtained, and by using the carrier modulation function of the phase-locked loop unit, the input signal and the output signal are located at the same carrier frequency (i.e. carrier frequency synchronization is implemented), so that an accurate and smooth target speed signal and a target position signal can be obtained, and a complete decoding compensation process of the rotary transformer is implemented, so as to drive the motor to operate, and ensure the performance of the motor driving system.

The pll unit may be a conventional pll unit, such as a PI-based quadrature pll, and specific functional implementation processes thereof are in the prior art, and details thereof are not described herein.

Example two

A decoding compensation system of a motor rotary transformer, wherein the rotary transformer is provided with a demodulation unit and a phase-locked loop unit, the demodulation unit is used for demodulating a rotary signal output by the rotary transformer, and the phase-locked loop unit is used for modulating an input signal of the rotary transformer by a carrier; in the decoding compensation method applied to the motor resolver according to the first embodiment, as shown in fig. 6, the system includes:

According to the embodiment, the sine and cosine feedback signals without carrier components can be obtained by demodulating the rotation signals through the feedback signal acquisition module by utilizing the demodulation unit, then direct current offset compensation and amplitude asymmetry compensation are respectively carried out on the sine and cosine feedback signals through the first compensation module, and then phase asymmetry compensation is carried out through the second compensation module, so that three types of low-frequency errors in the sine and cosine feedback signals, including direct current offset, amplitude asymmetry and phase asymmetry (or phase non-orthogonality), are overcome, feedback speed fluctuation and feedback position errors caused by the low-frequency errors are avoided, and further more accurate target compensation sine and cosine signals are obtained; and finally, through a target signal output module, the carrier modulation function of the phase-locked loop unit is utilized, so that the signal at the input end of the phase-locked loop unit and the signal at the output end can keep carrier synchronization, an accurate target position signal and a target speed signal are obtained based on the accurate target compensation sine and cosine signal, the decoding compensation of the rotary transformer is realized, and the stable and reliable motor driving system performance is ensured.

The functions of each module of the decoding and compensating system of the motor rotary transformer in this embodiment correspond to the steps of the decoding and compensating method of the motor rotary transformer in the first embodiment, and details of the decoding and compensating method of the motor rotary transformer in this embodiment are not described in detail in the first embodiment and the specific descriptions in fig. 1 to 5B, and are not described here again.

Example III

As shown in fig. 7, a decoding and compensating apparatus of a rotary transformer of a motor, the apparatus comprising:

the decoding compensation system of the motor rotary transformer in the second embodiment is in communication connection with the demodulation unit, and is configured to obtain the sine and cosine feedback signal after the rotary transformer is demodulated by the demodulation unit, and perform dc offset compensation, amplitude asymmetry compensation and phase asymmetry compensation on the sine and cosine feedback signal to obtain a target compensated sine and cosine signal; and

According to the decoding and compensating device of the motor rotary transformer, the decoding and compensating system of the motor rotary transformer of the second embodiment is added between the traditional demodulation unit and the phase-locked loop unit, feedback speed fluctuation and feedback position errors caused by three types of low-frequency errors can be avoided, further accurate target compensation sine and cosine signals are obtained, finally accurate target position signals and target speed signals are obtained based on the accurate target compensation sine and cosine signals, decoding and compensation of the rotary transformer are achieved, and stable and reliable motor driving system performance is ensured.

Similarly, the structure of the decoding and compensating system of the motor rotary transformer in this embodiment is the same as that of the decoding and compensating system of the motor rotary transformer in the second embodiment, and details of the decoding and compensating system of the motor rotary transformer in this embodiment are not described in detail in the first embodiment and the specific descriptions in fig. 1 to 6, and are not described here again.

Example IV

A decoding and compensating device for a motor resolver, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program when executed implements the method steps in the decoding and compensating method for a motor resolver of the first embodiment.

The computer program stored in the memory and running on the processor can avoid feedback speed fluctuation and feedback position error caused by three types of low-frequency errors, further obtain accurate target compensation sine and cosine signals, finally obtain accurate target position signals and target speed signals based on the accurate target compensation sine and cosine signals, realize decoding compensation of the rotary transformer and ensure stable and reliable motor driving system performance.

The processor may be a central processing unit (Central Processing Unit, CPU), other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, the processor being a control center of the computer device, and the various interfaces and lines connecting the various parts of the overall computer device.

The memory may be used to store computer programs and/or models, and the processor implements various functions of the computer device by running or executing the computer programs and/or models stored in the memory, and invoking data stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function (e.g., a sound playing function, an image playing function, etc.); the storage data area may store data (e.g., audio data, video data, etc.) created according to the use of the handset. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as a hard disk, memory, plug-in hard disk, smart Media Card (SMC), secure Digital (SD) Card, flash Card (Flash Card), at least one disk storage device, flash memory device, or other volatile solid-state storage device.

It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer programs. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer programs may also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer programs may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The present embodiment also provides a computer storage medium including: at least one instruction, when executed, implements method steps in the method of decoding compensation of a motor resolver of embodiment one.

By executing the computer storage medium containing at least one instruction, the feedback speed fluctuation and the feedback position error caused by three types of low-frequency errors can be avoided, further, a more accurate target compensation sine and cosine signal is obtained, and finally, an accurate target position signal and a target speed signal are obtained based on the accurate target compensation sine and cosine signal, so that the decoding compensation of the rotary transformer is realized, and the stable and reliable motor driving system performance is ensured.

Similarly, the details of the embodiment are not fully described in detail in the first embodiment, the second embodiment, the third embodiment and fig. 1 to 7, and are not repeated here.

Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations are within the scope of the invention as defined by the appended claims.

Claims

1. The decoding compensation method of the motor rotary transformer comprises the steps that the rotary transformer is provided with a demodulation unit and a phase-locked loop unit, the demodulation unit is used for demodulating a rotary signal output by the rotary transformer, and the phase-locked loop unit is used for modulating an input signal of the rotary transformer by a carrier; characterized in that the method comprises:

the phase-locked loop unit is utilized to carry out carrier modulation on the target compensation sine and cosine signals, and a target position signal and a target speed signal corresponding to the target compensation sine and cosine signals are output so as to drive a motor to operate;

The sine and cosine feedback signals comprise sine feedback signals and cosine feedback signals; the initial compensation sine and cosine signals comprise initial compensation sine signals and initial compensation cosine signals;

Obtaining the initial compensation sinusoidal signal according to the sinusoidal feedback signal, the first sinusoidal compensation signal and the second sinusoidal compensation signal; obtaining the initial compensation cosine signal according to the cosine feedback signal, the first cosine compensation signal and the second cosine compensation signal;

the performing amplitude asymmetric compensation on the sine feedback signal and the cosine feedback signal according to the first peak value, the first valley value, the second peak value and the second valley value to obtain a second sine compensation signal corresponding to the sine feedback signal and a second cosine compensation signal corresponding to the cosine feedback signal, including:

Pre-constructing a third error regulator;

or,

pre-constructing a fourth error regulator;

2. The method of claim 1, wherein the dc offset compensating the sinusoidal feedback signal based on the first peak value and the first valley value results in a first sinusoidal compensation signal; performing dc offset compensation on the cosine feedback signal according to the second peak value and the second valley value to obtain a first cosine compensation signal, including:

pre-establishing a first error regulator and a second error regulator;

3. The method of claim 1, wherein said deriving said initial compensated sinusoidal signal from said sinusoidal feedback signal, said first sinusoidal compensation signal and said second sinusoidal compensation signal when said sinusoidal feedback signal is taken as a corresponding said second sinusoidal compensation signal; obtaining the initial compensated cosine signal according to the cosine feedback signal, the first cosine compensation signal and the second cosine compensation signal, including:

4. The method of claim 1, wherein the target compensated sine signal comprises a target compensated sine signal and a target compensated cosine signal;

5. The method of claim 4, wherein performing phase asymmetry compensation on the initial compensation sine signal based on the third dc offset value with respect to the initial compensation cosine signal to obtain a third sine compensation signal corresponding to the initial compensation sine signal, comprises:

pre-establishing a fifth error regulator;

pre-establishing a sixth error regulator;

6. A decoding compensation system of a motor rotary transformer, wherein the rotary transformer is provided with a demodulation unit and a phase-locked loop unit, the demodulation unit is used for demodulating a rotary signal output by the rotary transformer, and the phase-locked loop unit is used for modulating an input signal of the rotary transformer by a carrier; a decoding and compensation method for a resolver of an electric machine according to any one of claims 1 to 5, said system comprising:

7. A decoding and compensating apparatus for a rotary transformer of an electric machine, comprising:

the decoding compensation system of the rotary transformer of the motor of claim 6, which is in communication connection with the demodulation unit and is used for obtaining the sine and cosine feedback signals demodulated by the demodulation unit of the rotary transformer, and obtaining target compensated sine and cosine signals after direct current offset compensation, amplitude asymmetry compensation and phase asymmetry compensation are carried out on the sine and cosine feedback signals; and

8. A computer storage medium, the computer storage medium comprising: at least one instruction which, when executed, implements the method steps of any of claims 1 to 5.