CN117198374A

CN117198374A - Test method, test equipment and computer storage medium

Info

Publication number: CN117198374A
Application number: CN202210599781.5A
Authority: CN
Inventors: 卢欢; 王鹏
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-05-30
Filing date: 2022-05-30
Publication date: 2023-12-08
Also published as: WO2023231273A1

Abstract

The present disclosure provides a test method, a test apparatus, and a computer storage medium, the method comprising: determining an initial clock signal, and generating a target clock signal based on the initial clock signal; obtaining test data; the test data comprises first test data and second test data; sequentially writing first test data into a target storage area of a chip to be tested according to first type turning moments of a target clock signal, and sequentially writing second test data into the target storage area of the chip to be tested according to second type turning moments of the target clock signal; respectively carrying out data reading sampling on a target storage area of a chip to be tested according to first-class turning moments and second-class turning moments of a target clock signal, and determining first sampling data and second sampling data; and determining a test result based on the comparison result of the first test data and the first sampling data and the comparison result of the second test data and the second sampling data. Thereby, the test of the high-frequency chip can be realized by using the low-frequency test equipment.

Description

Test method, test equipment and computer storage medium

Technical Field

The present disclosure relates to the field of semiconductor testing technology, and in particular, to a testing method, a testing apparatus, and a computer storage medium.

Background

Dynamic random access memory (Dynamic Random Access Memory, DRAM) chips are typically fabricated on wafers, and various performance parameters of the DRAM chips typically need to be tested to ensure that the design of the DRAM chips meets requirements, either before packaging the DRAM chips formed on the wafer or before being put into use.

With the rapid development of semiconductor memory technology, the data speed of the memory is also increased. For example, compared to the fourth generation double rate synchronous dynamic random access memory (Low Power Double Data Rate Fourth Synchronous Dynamic Random Access Memory, DDR4 SDRAM, abbreviated LPDDR 4), the data speed of LPDDR5 is increased to 6400Mbps. In the related art, DRAM high-speed testing relies on the development of high-speed automatic test equipment (Automatic Test Equipment, ATE). However, the high-speed test equipment is expensive, and the test program needs to be re-developed and designed, resulting in excessive test cost for the high-frequency memory.

Disclosure of Invention

The embodiment of the disclosure provides a testing method, testing equipment and a computer storage medium.

In a first aspect, embodiments of the present disclosure provide a test method, the method comprising:

determining an initial clock signal;

generating a target clock signal based on the initial clock signal; wherein the clock frequency of the target clock signal is higher than the clock frequency of the initial clock signal;

obtaining test data; wherein the test data comprises first test data and second test data;

after the first test data are sequentially written into the target storage area of the chip to be tested according to the first type turning moment of the target clock signal, the second test data are sequentially written into the target storage area of the chip to be tested according to the second type turning moment of the target clock signal;

respectively carrying out data reading sampling on a target storage area of the chip to be tested according to first-class turning moments and second-class turning moments of the target clock signal, and determining first sampling data and second sampling data;

determining a test result based on the first test data and the first sample data and the second test data and the second sample data.

In some embodiments, the first type of transition time represents a rising edge time when the target clock signal transitions from low to high, and the second type of transition time represents a falling edge time when the target clock signal transitions from high to low; or,

The first type of flip time represents the falling edge time of the target clock signal from high level to low level, and the second type of flip time represents the falling edge time of the target clock signal from low level to high level.

In some embodiments, the acquiring test data includes:

determining even bit data in the test data as the first test data, and determining odd bit data in the test data as the second test data; or,

and determining odd bit data in the test data as the first test data, and determining even bit data in the test data as the second test data.

In some embodiments, the first type of flip time is a rising edge time of the target clock signal and the second type of flip time is a falling edge time of the target clock signal; and the first test data is even bit data in the test data, and the second test data is odd bit data in the test data,

after the first test data are sequentially written into the target storage area of the tested chip according to the first type of flip time of the target clock signal, the second test data are sequentially written into the target storage area of the tested chip according to the second type of flip time of the target clock signal, including:

Determining a first data mask signal and a second data mask signal, and the first data mask signal and the second data mask signal being opposite in phase;

shielding the odd bit data based on the first data mask signal when performing a first write operation on the chip under test, and sequentially writing the even bit data into a target storage area of the chip under test at a rising edge timing of the target clock signal;

and when the second write operation is executed on the tested chip, carrying out mask processing on the even bit data based on the second data mask signal, and writing the odd bit data into a target storage area of the tested chip in sequence at the second type flip moment of the target clock signal.

In some embodiments, the data reading and sampling are performed on the target storage area of the tested chip according to the first class flip time and the second class flip time of the target clock signal, and determining the first sampling data and the second sampling data includes:

when the first reading operation is executed on the chip to be tested, data is read from a target storage area of the chip to be tested, and the read data is sampled according to the rising edge moment of the target clock signal to obtain the first sampling data;

When the second reading operation is executed on the tested chip, data is read from a target storage area of the tested chip, and the read data is sampled according to the falling edge moment of the target clock signal to obtain second sampling data;

accordingly, the determining a test result based on the first test data and the first sampling data and the second test data and the second sampling data includes:

determining a first comparison result of the even bit data and the first sampling data;

determining a second comparison result of the odd bit data and the second sampling data;

and when the first comparison result indicates that the even bit data is identical to the first sampling data and the second comparison result indicates that the odd bit data is identical to the second sampling data, determining that the test result is test passing.

In some embodiments, after the first test data is sequentially written to the target storage area of the tested chip according to the first type flip time of the target clock signal, the second test data is sequentially written to the target storage area of the tested chip according to the second type flip time of the target clock signal, including:

when the first write operation is executed on the tested chip, masking the second test data based on the first data masking signal, and writing the first test data into a target storage area of the tested chip in sequence at a first type flip time of the target clock signal;

and when the second write operation is executed on the tested chip, masking the first test data based on the second data masking signal, and writing the second test data into the target storage area of the tested chip in sequence at the second type flip time of the target clock signal so as to realize writing the test data into the target storage area of the tested chip.

In some embodiments, when performing a first write operation on the chip under test, the masking the second test data based on the first data mask signal includes: shielding the second test data corresponding to the valid state when the first data mask signal is in the valid state;

Accordingly, when performing a second write operation on the chip under test, the masking the first test data based on the second data mask signal includes: and shielding the first test data corresponding to the valid state when the second data mask signal is in the valid state.

when the first reading operation is executed on the chip to be tested, data is read from a target storage area of the chip to be tested, and the read data is sampled according to the first type turning moment of the target clock signal to obtain first sampled data;

and when the second reading operation is executed on the tested chip, data is read from the target storage area of the tested chip, and the read data is sampled according to the second type turning moment of the target clock signal, so that the second sampled data is obtained.

In some embodiments, the determining a test result based on the first test data and the first sample data and the second test data and the second sample data includes:

Determining a first comparison result of the first test data and the first sampling data;

determining a second comparison result of the second test data and the second sampling data;

and when the first comparison result indicates that the first test data is identical to the first sampling data and the second comparison result indicates that the second test data is identical to the second sampling data, determining that the test result is test passing.

In some embodiments, the method further comprises:

and when the first comparison result indicates that the first test data is different from the first sampling data, and/or the second comparison result indicates that the second test data is different from the second sampling data, determining that the test result is that the test fails.

In some embodiments, the chip under test includes a plurality of memory regions, the target memory region being any one of the plurality of memory regions; the method further comprises the steps of:

if each storage area in the storage areas passes the test, determining that the test result of the tested chip is the test passing;

and if any storage area test in the plurality of storage areas fails, determining that the test result of the tested chip is that the test fails.

In some embodiments, determining the initial clock signal includes: determining a first clock signal and a second clock signal; the phase difference between the first clock signal and the second clock signal is 90 degrees, and the clock frequency of the first clock signal and the clock frequency of the second clock signal are half of the clock frequency of the target clock signal;

the generating a target clock signal based on the initial clock signal includes: and performing exclusive OR operation on the first clock signal and the second clock signal to obtain the target clock signal.

In a second aspect, embodiments of the present disclosure provide a test apparatus, including a determining unit, a generating unit, an acquiring unit, a writing unit, a reading unit, and a comparing unit, wherein,

the determining unit is configured to determine an initial clock signal;

the generating unit is matched to generate a target clock signal based on the initial clock signal; wherein the clock frequency of the target clock signal is higher than the clock frequency of the initial clock signal;

the acquisition unit is configured to acquire test data; wherein the test data comprises first test data and second test data;

The writing unit is configured to sequentially write the first test data into the target storage area of the chip to be tested according to the first type turnover time of the target clock signal and sequentially write the second test data into the target storage area of the chip to be tested according to the second type turnover time of the target clock signal;

the reading unit is configured to respectively read and sample data of a target storage area of the chip to be tested according to first-class turning moments and second-class turning moments of the target clock signal, and determine first sampling data and second sampling data;

the comparing unit is configured to determine a test result based on the first test data and the first sampling data and the second test data and the second sampling data.

In a third aspect, embodiments of the present disclosure provide another test apparatus comprising a memory and a processor, wherein,

the memory is used for storing a computer program capable of running on the processor;

the processor is configured to perform the test method according to any one of the first aspect when the computer program is run.

In a second aspect, embodiments of the present disclosure provide a computer storage medium storing a computer program which, when executed by at least one processor, implements the test method according to any one of the first aspects.

The embodiment of the disclosure provides a test method, test equipment and a computer storage medium, which are characterized in that an initial clock signal is firstly determined, a target clock signal is generated based on the initial clock signal, and the clock frequency of the target clock signal is higher than that of the initial clock signal; acquiring test data, wherein the test data comprises first test data and second test data; sequentially writing first test data into a target storage area of the chip to be tested according to first type turning moments of the target clock signals, and sequentially writing second test data into the target storage area of the chip to be tested according to second type turning moments of the target clock signals; respectively carrying out data reading sampling on a target storage area of the chip to be tested according to first-class turning moments and second-class turning moments of the target clock signal, and determining first sampling data and second sampling data; and finally, determining a test result based on the first test data and the first sampling data and the second test data and the second sampling data. In this way, when the high-frequency test is performed on the tested chip, the test data can be written into the tested chip with higher clock frequency by using the test equipment with lower clock frequency in a twice writing mode; the data can be read from the tested chip by using the test equipment with lower clock frequency in a twice reading and sampling mode; in this way, based on the comparison result of the written first test data and the read first sampling data and the comparison result of the written second test data and the read second sampling data, whether the tested chip passes the test can be determined; that is, compared with the related art relying on high-speed automatic test equipment, the scheme realizes high-frequency test of DRAM chips by using low-frequency test equipment, so that the test complexity is reduced, and the test cost is reduced.

Drawings

Fig. 1 is a schematic flow chart of a test method according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of signal timing corresponding to a write operation according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of signal timing corresponding to a read operation according to an embodiment of the disclosure;

FIG. 4 is a detailed flow chart of a testing method according to an embodiment of the disclosure;

FIG. 5 is a schematic diagram of signal timing corresponding to another read operation according to an embodiment of the disclosure;

fig. 6 is a schematic diagram of a composition structure of a test apparatus according to an embodiment of the present disclosure;

fig. 7 is a schematic diagram of a composition structure of another test apparatus according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to be limiting of the disclosure. It should be further noted that, for convenience of description, only the portions related to the disclosure are shown in the drawings.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing the disclosed embodiments only and is not intended to be limiting of the disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

It should be noted that the term "first\second\third" in relation to the embodiments of the present disclosure is merely to distinguish similar objects and does not represent a particular ordering for the objects, it being understood that the "first\second\third" may be interchanged in a particular order or sequencing where allowed, so that the embodiments of the present disclosure described herein may be implemented in an order other than that illustrated or described herein.

In the related art, DRAM high-speed testing relies on the development of high-speed ATE. Currently, only a small number of manufacturers can support the test requirements of the high-frequency memory (such as DDR5 or LPDDR 5), and the high-speed tester has high cost, and the test program needs to be redeveloped and designed, so that the test of the high-frequency memory is difficult and has high cost.

Based on this, the embodiment of the disclosure provides a test method, by determining an initial clock signal, generating a target clock signal based on the initial clock signal, the clock frequency of the target clock signal being higher than the clock frequency of the initial clock signal; acquiring test data, wherein the test data comprises first test data and second test data; sequentially writing first test data into a target storage area of a chip to be tested according to first type turning moments of a target clock signal, and sequentially writing second test data into the target storage area of the chip to be tested according to second type turning moments of the target clock signal; respectively carrying out data reading sampling on a target storage area of a chip to be tested according to first-class turning moments and second-class turning moments of a target clock signal, and determining first sampling data and second sampling data; a test result is determined based on the first test data and the first sample data and the second test data and the second sample data. In this way, when the high-frequency test is performed on the tested chip, the test data can be written into the tested chip with higher clock frequency by using the test equipment with lower clock frequency in a twice writing mode; the data can be read from the tested chip by using the test equipment with lower clock frequency in a twice reading and sampling mode; in this way, based on the comparison result of the written first test data and the read first sampling data and the comparison result of the written second test data and the read second sampling data, whether the tested chip passes the test can be determined; that is, compared with the related art relying on high-speed automatic test equipment, the scheme realizes high-frequency test of DRAM chips by using low-frequency test equipment, thereby not only reducing the test complexity, but also reducing the test cost.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present disclosure, referring to fig. 1, a schematic flow chart of a testing method provided by an embodiment of the present disclosure is shown. As shown in fig. 1, the method may include:

s101, determining an initial clock signal.

S102, generating a target clock signal based on an initial clock signal; wherein the clock frequency of the target clock signal is higher than the clock frequency of the initial clock signal.

It should be noted that, the test method provided by the embodiment of the present disclosure may be applied to a test device for performing a test of functions such as reading and writing on a tested chip, where the test device may be a chip tester, and the tested chip may be a DRAM chip, for example, a DRAM chip meeting the DDR5 memory specification or the LPDD5 memory specification. In the embodiment of the disclosure, for the clock frequency, the settable range of the test device is smaller than the clock frequency of the tested chip, so that the method can utilize low-cost low-frequency test device (such as test device for LPDDR4 or DDR 4) to realize the test of the high-frequency chip (such as LPDDR5 or DDR 5).

When testing, the chip to be tested needs to be powered on and initialized to enter the testing state. After the tested chip enters a testing state, the tested chip is subjected to read-write testing by the testing equipment so as to determine whether the tested chip passes the testing.

It should also be noted that, in the embodiment of the present disclosure, the target clock signal is generated based on the initial clock signal, and the target clock signal is used as a clock signal for writing or reading data. Here, the clock frequency of the target clock signal is higher than the settable range of the test apparatus, and in addition, the clock frequency of the target clock signal may be equal to the clock frequency of the chip under test. Thus, in the embodiments of the present disclosure, the clock frequency of the initial clock signal is within the settable range of the test apparatus, and the test apparatus may directly generate the initial clock signal, and the clock frequency of the chip under test is higher than the settable range of the test apparatus, that is, the clock frequency of the target clock signal is higher than the settable range of the test apparatus.

Further, for the initial clock signal and the target clock signal, in some embodiments, determining the initial clock signal may include:

determining a first clock signal and a second clock signal; the phase difference between the first clock signal and the second clock signal is 90 degrees, and the clock frequency of the first clock signal and the clock frequency of the second clock signal are half of the clock frequency of the target clock signal.

Accordingly, in some embodiments, generating the target clock signal based on the initial clock signal may include: and performing exclusive OR operation on the first clock signal and the second clock signal to obtain a target clock signal.

It should be noted that the test apparatus itself may generate two clock signals with low frequency (clock frequency is lower than the chip under test): a first clock signal and a second clock signal. In the disclosed embodiments, the clock frequencies of the first clock signal and the second clock signal are within a settable range of the test apparatus, and the first clock signal and the second clock signal may be provided by a pattern generator (Pattern Generator) in the test apparatus. In addition, it should be noted that the test device herein may operate in a variety of frequency modes, but the clock frequency at which it operates does not exceed the highest clock frequency that the test device can achieve.

It should be noted that, after the phase difference between the first clock signal and the second clock signal is 90 degrees and the Exclusive OR (XOR) is performed on the first clock signal and the second clock signal, the low-frequency first clock signal and the low-frequency second clock signal can be converted into the high-frequency target clock signal, and the clock frequency of the target clock signal may be the same as the clock frequency of the chip under test. Wherein the clock frequency of the target clock signal may be twice the clock frequency of the first clock signal (or the second clock signal).

That is, the clock frequencies of the first clock signal and the second clock signal are within the settable range of the test apparatus, and do not exceed the maximum clock frequency that the test apparatus can generate. Accordingly, the clock frequency of the target clock signal does not exceed twice the maximum clock frequency of the test device, since the clock frequency of the target clock signal is twice the clock frequency of the first clock signal (second clock signal).

In the embodiment of the disclosure, the exclusive-or operation on the first clock signal and the second clock signal may be performed in a test board (Loadboard) of the test apparatus. The Loadboard may connect the test device with the chip to be tested, and the Loadboard may include an XOR chip that performs an XOR operation on the first clock signal and the second clock signal to obtain the target clock signal and then transmits the target clock signal to a pin corresponding to the chip to be tested.

In this way, by performing exclusive OR operation on the two low-speed clock signals (the first clock signal and the second clock signal), a multiplied high-speed clock signal (i.e. the target clock signal) can be obtained, so that the test of the low-frequency test equipment on the high-frequency chip can be realized.

S103, acquiring test data; wherein the test data includes first test data and second test data.

It should be noted that, in the embodiment of the present disclosure, the test data is used to test whether the function of the tested chip is normal, for example, the function test of the tested chip is performed by writing and reading. Although the test data may include two contents of the first test data and the second test data, the specific data content of the test data is not limited in this embodiment of the disclosure, and may be random data or user-specified data. For example, the embodiment of the disclosure may divide the test data into two parts of first test data and second test data based on the preset condition, wherein the first test data meets the first preset condition, and the second test data meets the second preset condition.

Further, in some embodiments, acquiring test data may include:

determining even bit data in the test data as first test data, and determining odd bit data in the test data as second test data; or,

and determining odd bit data in the test data as first test data, and determining even bit data in the test data as second test data.

It should be noted that, the first test data conforming to the first preset condition may refer to even bit data in the test data, and the second test data conforming to the second preset condition may refer to odd bit data in the test data.

Illustratively, the test data may include the following bits of data in a sequential order: bit0, bit1, bit2, bit3, bit4, bit5, bit6 and bit7; wherein 0, 2, 4 and 6 are all even numbers, namely bit0, bit2, bit4 and bit6 can be used as even bit data meeting a first preset condition, namely first test data; 1. 3, 5 and 7 are all odd numbers, namely bit1, bit3, bit5 and bit7 can be used as odd bit data meeting a second preset condition, namely second test data.

In addition, the first test data meeting the first preset condition may refer to odd-bit data in the test data, and the second test data meeting the second preset condition may refer to even-bit data in the test data, which is not particularly limited. In the embodiment of the present disclosure, the implementation of the test method will be described in detail mainly by taking the example that the first test data corresponds to even bits and the second test data corresponds to odd bits.

S104, after the first test data are sequentially written into the target storage area of the tested chip according to the first type of turning moment of the target clock signal, the second test data are sequentially written into the target storage area of the tested chip according to the second type of turning moment of the target clock signal.

Note that, in the embodiment of the present disclosure, the flip timing of the target clock signal may refer to a timing when the target clock signal changes from low level to high level (i.e., a rising edge timing), or may refer to a timing when the target clock signal changes from high level to low level (i.e., a falling edge timing).

It should be further noted that, in the embodiment of the present disclosure, when data writing is performed, two writing operations are performed, where the first writing of the first test data is performed sequentially at the first type of flip time in the target storage area of the chip under test, and the second writing of the second test data is performed at the second type of flip time in the target storage area of the chip under test. Therefore, by means of twice writing, the test data can be written into the tested chip with high frequency by using the test equipment with low frequency.

In a specific implementation, the first type of flip time indicates a rising edge time when the target clock signal is flipped from a low level to a high level, and the second type of flip time indicates a falling edge time when the target clock signal is flipped from a high level to a low level.

In another specific implementation, the first type of flip time indicates a falling edge time when the target clock signal is flipped from high to low, and the second type of flip time indicates a falling edge time when the target clock signal is flipped from low to high.

In the embodiment of the present disclosure, the first type of flip time represents a rising edge time and the second type of flip time represents a falling edge time are mainly taken as examples, and the implementation of the test method is described in detail.

Thus, the low-frequency tester can control the high-frequency chip to be tested by means of twice writing. For example: the working frequency of the chip to be tested is 4266Mbps, and one clock period is 0.468 nanoseconds (nS), and then one data is written every 0.234 nS; by means of writing twice, the tested chip still works at the frequency of 4266Mbps, and the test equipment can test the high-frequency tested chip (4266 Mbps) by the low-frequency tester (2133 Mbps) as long as the test equipment works at the frequency of 2133Mbps and 0.468nS is converted into data once.

Further, for the two writing operations, in some embodiments, after sequentially writing the first test data to the target storage area of the tested chip according to the first type flip time of the target clock signal, sequentially writing the second test data to the target storage area of the tested chip according to the second type flip time of the target clock signal may include:

When the first write operation is executed on the tested chip, masking the second test data based on the first data masking signal, and sequentially writing the first test data into a target storage area of the tested chip at the first type flip time of the target clock signal;

when the second writing operation is executed on the tested chip, masking processing is carried out on the first test data based on the second data masking signal, and the second test data are sequentially written into the target storage area of the tested chip at the second type flip time of the target clock signal, so that the test data are written into the target storage area of the tested chip.

It should be noted that, in the embodiment of the present disclosure, the writing of the test data into the target storage area of the tested chip in two times may be implemented by a Mask Write (Mask Write), and the data of a part of bits is masked by the data Mask signal, and only the data that is not masked is written.

Specifically, when the first write operation is performed, only the first test data needs to be written, and at this time, the second test data is masked by masking the second test data through the first data mask signal, so that when the test data is written, the first test data is written only at the first flip time, and the second test data cannot be written. Similarly, when the second writing operation is executed, only the second test data is required to be written, and the first test data is masked by the second data masking signal at this time, so that the second test data is only written at the second type flip time, but not the first test data, when the test data is written.

It should also be noted that in the embodiments of the present disclosure, the phases of the first data mask signal and the second data mask signal are opposite, so that the first mask data signal may implement masking the second test data, and the second data mask signal may implement masking the first test data. Wherein the second data mask signal may be an inverse or delayed version of the first data mask signal.

In some embodiments, when performing the first write operation on the chip under test, masking the second test data based on the first data mask signal may include: when the first data mask signal is in an effective state, shielding second test data corresponding to the effective state;

accordingly, when performing the second write operation on the chip under test, masking the first test data based on the second data mask signal may include: and when the second data mask signal is in an active state, masking the first test data corresponding to the active state.

It should be noted that, the valid state of the data mask signal may be a high level state, where the data mask signal may be a first value of "1", and the non-valid state may be a low level state, where the data mask signal may be a second value of "0".

Thus, for the first write operation, when the first data mask signal is in an active state, the active state corresponds to the second test data, so that the second test data is masked, the inactive state corresponds to the first test data, and the first test data is not masked but is written into the target memory area of the chip under test. For the second write operation, when the second data mask signal is in an active state, the active state corresponds to the first test data, so that the first test data is masked, the inactive state corresponds to the second test data, and the second test data is not masked but is written into the target memory area of the chip under test.

It should be noted that the data mask signal may refer to a first data mask signal or a second data mask signal, where the clock frequency of the data mask signal is the same as the clock frequency of the target clock signal. For the data mask signal, which is similar to the target clock signal, the test equipment cannot directly generate the high frequency data mask signal. The data mask signal may be generated at this time by an exclusive or operation of the two low frequency signals.

In some embodiments, determining the first data mask signal and the second data mask signal may include:

Acquiring a first mask signal and a second mask signal; the phase difference between the first mask signal and the second mask signal is 90 degrees, and the clock frequency of the first mask signal and the second mask signal is equal to the clock frequency of the initial clock signal;

performing exclusive OR operation on the first mask signal and the second mask signal to obtain a first data mask signal;

and performing inversion operation on the first data mask signal to obtain a second data mask signal.

It should be noted that, for the first data mask signal and the second data mask signal, the first data mask signal may be generated in a similar manner to the target clock signal, and then the first data mask signal is inverted to obtain the second data mask signal.

acquiring a third mask signal and a fourth mask signal; the phase difference between the third mask signal and the fourth mask signal is 90 degrees, and the clock frequency of the fourth mask signal and the third mask signal is equal to the clock frequency of the initial clock signal;

performing exclusive OR operation on the third mask signal and the fourth mask signal to obtain a second data mask signal;

And performing inversion operation on the second data mask signal to obtain a first data mask signal.

It should be noted that, for the first data mask signal and the second data mask signal, the disclosed embodiment may also generate the second data mask signal according to the third mask signal and the fourth mask signal, and then invert the second data mask signal to obtain the first data mask signal.

In some embodiments, determining the first data mask signal and the second data mask signal may include: the first mask signal, the second mask signal, the third mask signal and the fourth mask signal are respectively obtained, and exclusive-or operation is carried out on the first mask signal and the second mask signal to obtain a first data mask signal; and performing exclusive or operation on the third mask signal and the fourth mask signal to obtain a second data mask signal, wherein the phase difference between the first mask signal and the third mask signal is 90 degrees, and the phase difference between the second mask signal and the fourth mask signal is 90 degrees.

In this way, a high-speed data mask signal can be obtained by performing exclusive-or operation on the two low-speed signals, so that partial data can be shielded when data is written by using the data mask signal.

Further, for writing test data, the first type of flip time is taken as the rising edge time of the target clock signal, and the second type of flip time is taken as the falling edge time of the target clock signal; and the first test data is even bit data in the test data, and the second test data is odd bit data in the test data, for example, in a specific embodiment, after the first test data is written into the target storage area of the tested chip in sequence according to the first type flip time of the target clock signal, the writing the second test data into the target storage area of the tested chip in sequence according to the second type flip time of the target clock signal may include:

shielding odd bit data based on a first data mask signal when performing a first write operation on a chip under test, and sequentially writing even bit data into a target storage area of the chip under test at a rising edge time of a target clock signal;

and when the second writing operation is executed on the tested chip, carrying out mask processing on the even bit data based on the second data mask signal, and writing the odd bit data into the target storage area of the tested chip in sequence at the second type flip moment of the target clock signal.

It should be noted that even bit data (first test data) in the test data is written into the target memory area of the chip under test at the rising edge time (first type flip time) of the target clock signal, and odd bit data (second test data) is written into the target memory area of the chip under test at the falling edge time (second type flip time) of the target clock signal. Thus, through the operation of twice writing, the data writing of the low-frequency test equipment to the high-frequency tested chip can be realized.

Further, for a specific manner of mask writing, taking an example of writing the data of the odd bits of the test data at the falling edge time of the target clock signal, referring to fig. 2, a signal timing diagram of a writing operation procedure provided by an embodiment of the disclosure is shown. As shown in fig. 2, (a) is a standard for mask writing prescribed by joint electronic device engineering council (Joint Electron Device Engineering Council, JEDEC), and (b) is a timing diagram of each signal when writing data of odd bits is performed.

For example, for LPDDR5, the correspondence between each signal of the chip under test and the Input & Output (IO) signal transmission channel of the test device is shown in table 1.

TABLE 1

Signal pin of chip to be tested	Signal transmission channel of test equipment	Waveform shape
			CK	IO0	NRZ
CS	IO1	NRZ
			CA	IO2	NRZ
	IO3	DNRZ
				IO4	DNRZ
WCK	XOR(IO3,IO4)	-
			DMI	XOR(IO7,IO8)	-
DQ	IO5-20	DNRZ

Referring to table 1 and fig. 2, a reference clock signal (CK) pin is a pin for transmitting the reference clock signal CK in the chip under test, and the waveform of the reference clock signal CK is a non-return-to-zero code (Not Return to Zero, NRZ) and is transmitted through an IO0 channel in the tester; a Chip Select (CS) pin is a pin used for transmitting the CS in the Chip to be tested, the waveform of the CS is NRZ, and the CS is transmitted through an IO1 channel in the tester; the Command signal (CA) pin is a pin used for transmitting the Command signal CA in the chip to be tested, the waveform of the Command signal CA is NRZ, and the Command signal CA is transmitted through an IO2 channel in the tester; the method comprises the steps that a target Clock signal (Write Clock signal, WCK) pin is a pin used for transmitting the target Clock signal WCK in a tested chip, the target Clock signal WCK is obtained by performing exclusive OR operation on a first Clock signal and a second Clock signal, the highest frequency which can be transmitted by an IO channel of test equipment is lower than the frequency of the target Clock signal, the channel of the test equipment cannot directly transmit the target Clock signal WCK, therefore, the first Clock signal is transmitted through an IO3 channel, the second Clock signal is transmitted through an IO4 channel, the waveforms of the first Clock signal and the second Clock signal are double data rate non-return to zero codes (Double Data Rate Not Return to Zero, DNRZ), and after the target Clock signal WCK is obtained by performing exclusive OR operation on the first Clock signal and the second Clock signal, the tested chip receives the target Clock signal WCK at the WCK pin; the data mask inversion (Data Mask or Data Inversion, DMI) pin is a pin used for transmitting a data mask signal DMI in the tested chip, wherein data with odd bits is written, so that a second data mask signal is transmitted, the second data mask signal is obtained by performing exclusive-or operation on a third mask signal and a fourth mask signal, the highest frequency which can be transmitted by an IO channel of the testing device is lower than the frequency of the data mask signal DMI, the channel of the testing device cannot directly transmit the data mask signal DMI, so that the third mask signal is transmitted by the IO7 channel, the fourth mask signal is transmitted by the IO7 channel, the waveforms of the third mask signal and the fourth mask signal are DNRZ, and after the third mask signal and the fourth mask signal are subjected to exclusive-or operation to obtain the second data mask signal, the tested chip receives the second data mask signal at the DMI pin; the DQ pins are pins used for transmitting data signals DQ in the chip to be tested, the waveforms of the data signals DQ are non-return-to-zero codes, and the data signals DQ1 are transmitted through one or more channels IO5-20, and in FIG. 2, the data signals DQ1 are transmitted through the channel IO 5.

As shown in fig. 2, the test apparatus may transmit a write command signal CA to the chip under test and a chip select signal CS to the chip under test when writing data to the chip under test, so that the chip under test responds to the control of the test apparatus. That is, when the chip to be tested receives the chip selection signal, the chip to be tested determines that the chip to be tested is selected, so that each instruction sent by the chip to be tested is responded.

In fig. 2, the command signal CA specifically indicates a Write command signal, and CAs ws_wr, ws_wr=1, mask Write, and Mask Write constitute one Write command. The time Set (TS 1) represents a time Set of test equipment, in which the key parameter is the clock period, and the channel with the highest clock frequency is covered, and in fig. 2, the highest frequencies of the channels IO3 and IO4 are covered. In fig. 2, TS1 represents one clock cycle, and when WCK: ck=2:1, the level state of CK is changed once and the level state of WCK is changed twice in one TS1 as shown in fig. 2; when WCK: ck=4:1, the level state of CK is changed once and the level state of WCK is changed four times within one TS 1.

It should be noted that, for LPDDR5, the operation modes may include three types of WCK: ck=1:1, WCK: ck=2:1, and WCK: ck=4:1. When working in the WCK:CK=1:1 mode, the tester can directly generate clock signals with corresponding frequencies, such as a reference clock signal CK, and the frequency of the target clock signal WCK is the same as the frequency of the reference clock signal CK; when working in the WCK: ck=2:1 mode, the tester can directly generate clock signals with corresponding frequencies, such as a second clock signal transmitted by an IO4 channel, the frequency of the target clock signal WCK is twice that of the reference clock signal CK, the first clock signal is always at a low level, and the exclusive-or operation result of the first clock signal and the second clock signal is still the second clock signal.

When operating in the WCK: ck=4:1 mode, it is necessary to perform a mask write operation twice and generate a high-frequency target clock signal WCK according to the first clock signal and the second clock signal, which is four times the frequency of the reference clock signal CK, and generate a high-frequency second data mask signal according to the third mask signal and the fourth mask signal (specific waveforms of the third mask signal and the fourth mask signal may refer to the first clock signal and the second clock signal) to write the first test data and the second test data at the rising edge time and the falling edge time of the target clock signal, respectively.

It should be noted that, in fig. 2, the connection relationship of the channels is not changed after being fixed, so that the target clock signal WCK is always generated by performing an exclusive or operation on the clock signals transmitted by the IO3 signal and the IO4 channel, whether 4: 1. 2: 1. 1:1, the clock frequency of the target clock signal WCK can be controlled through an IO3 channel and an IO4 channel, and IO3 and IO4 are normal test channels and can transmit any waveform not higher than the highest frequency of the test equipment.

As shown in fig. 2, the measuring and calculating device may send a write command CA to the chip under test through the IO2 channel, generate the target clock signal WCK according to the first clock signal and the second clock signal, and generate the second data mask signal DMI according to the third mask signal and the fourth mask signal, where fig. 2 is writing the odd bit of the test data, so that the second data mask signal is in a high state, that is, in a valid state, in the even bit of the test data.

As shown in fig. 2, DQ represents the test data being written, where 0 represents bit0, and 1 represents bit1 …. At the position corresponding to bit0, the target clock signal WCK is a rising edge, and the second data mask signal is in a high-level state, so that the data of the bit0 position is shielded; and in the position corresponding to the bit1, the target clock signal WCK is in a falling edge, and the second data mask signal is in a low level state, so that the data of the bit1 position is not shielded, the writing of the bit1 data in the falling edge of the target clock signal WCK is realized, and the like until the data of the odd bit is written in the target storage area of the tested chip in sequence.

Specifically, referring to FIG. 2, in DQ, each dashed box contains an odd bit and an even bit. For example, the first dashed box contains bit0 and bit1, and if data of odd bits is to be written, the dashed box holds odd bits for the data corresponding to the clock period of the entire target clock signal WCK, i.e. bit1 in the first dashed box, bit3 in the second dashed box, bit5 in the third dashed box, equivalent to bit0=bit1 and bit2=bit3 … at this time. After this operation, the data rate is reduced to half of the original data rate, so that high-speed data writing can be achieved within the capability of the low-speed test equipment.

For example, the highest clock frequency of the low-frequency test device is 2.25 gigahertz (GHz), the data transmission rate of each IO channel is 4.5 gigabits per second (Gbps) (the clock frequency of the corresponding CK/CA is 2.25 GHz), after performing exclusive-or operation on the first clock signal transmitted by the IO3 channel and the second data signal transmitted by the IO4 channel, a signal with the data transmission rate of up to 9Gbps can be generated, the generated signal is used as the target clock signal WCK, the corresponding clock frequency is 4.5GHz, and the clock frequency of the data mask signal can reach 4.5GHz. That is, in this example, the clock frequency of CK/CS/CA may be up to 2.25GHz, the clock frequency of WCK/DMI may be up to 4.5GHz, and the data transfer rate of DQ may be up to 9Gbps.

And writing even bit data in the test data is similar to writing odd bit data, and at the moment, the second data mask signal can be inverted to obtain a first data mask signal, wherein the first data mask signal is in a high level state at a position corresponding to the odd bit, and the data in the even bit is in a low level state, so that the even bit data of the test data is written in the rising edge of the target clock signal. And finally, writing the test data into the target storage area of the tested chip through two writing operations.

S105, respectively carrying out data reading sampling on a target storage area of the chip to be tested according to the first type turning moment and the second type turning moment of the target clock signal, and determining first sampling data and second sampling data.

It should be noted that, after the test data are all written into the target storage area of the tested chip, the data are read from the target storage area to detect the read-write function of the tested chip. The same is true for the written data, the read data is also performed twice, respectively, a first data read sampling is performed at a first type inversion time of the target clock signal, a first sampling data is determined, and a second data read sampling is performed at a second type inversion time of the target clock signal, and a second sampling data is determined.

It can be understood that, in the case of no error in the read/write function of the tested chip, the first sampling data is identical to the first test data, and the second sampling data is identical to the second test data.

For two times of data reading sampling, in some embodiments, respectively performing data reading sampling on a target storage area of a tested chip according to a first type flip time and a second type flip time of a target clock signal, and determining first sampling data and second sampling data may include:

When a first reading operation is executed on a tested chip, data is read from a target storage area of the tested chip, and the read data is sampled according to a first type of turning moment of a target clock signal to obtain first sampling data;

and when the second reading operation is executed on the tested chip, data is read from the target storage area of the tested chip, and the read data is sampled according to the second type turning moment of the target clock signal, so as to obtain second sampled data.

In the embodiment of the present disclosure, the DRAM chip has a DMI pin for receiving a data mask signal, and when test data is written, the DMI pin may be used by mask writing, but when data is read, such a signal pin is not present. Therefore, when the first reading operation is performed, all data in the target storage area are read out, and then data sampling is performed at the first type inversion time of the target clock signal, so as to obtain first sampling data. And in the second reading operation, the data in the target storage area are read out firstly, and then data sampling is carried out at the second type turning moment of the target clock signal, so that second sampling data are obtained.

Further, taking the first type flip time as the rising edge time of the target clock signal and the second type flip time as the falling edge time of the target clock signal as an example, in a specific embodiment, respectively performing data reading sampling on the target storage area of the tested chip according to the first type flip time and the second type flip time of the target clock signal, and determining the first sampling data and the second sampling data may include:

when a first reading operation is executed on a chip to be tested, data is read from a target storage area of the chip to be tested, and the read data is sampled according to the rising edge moment of a target clock signal to obtain first sampling data;

and when the second reading operation is executed on the tested chip, reading data from the target storage area of the tested chip, and sampling the read data according to the falling edge moment of the target clock signal to obtain second sampling data.

Taking the second reading operation as an example, referring to fig. 3, a schematic signal timing diagram corresponding to the reading operation provided in the embodiment of the disclosure is shown. As shown in fig. 3, (a) is a data reading standard prescribed by JEDEC, and (b) is a timing diagram of each signal when determining the second sample data.

For example, for the correspondence between each signal of the tested chip and the IO channel of the test device, the corresponding relationship is shown in table 2 in detail.

TABLE 2

Table 2 is comparable to Table 1 above, except that the DMI pins and corresponding channels and waveforms are absent, and the remainder are identical and are not repeated here.

As shown in fig. 3, the test device may transmit a read command signal (CA) to the chip under test and transmit a chip select signal (CS) to the chip under test when reading data from the chip, so that the chip under test responds to the control of the test device. When the chip to be tested receives the chip selection signal, the chip to be tested can determine that the chip to be tested is selected, so that each instruction sent by the chip to be tested is responded.

In fig. 3, the command signal CA specifically represents a READ command signal in which read_any, read_bg, READ-16B, and READ-8B constitute one READ command. TS1 represents a clock cycle, as shown in FIG. 3, for LPDDR5, the working modes may include three modes, namely WCK: CK=1:1, WCK: CK=2:1, and WCK: CK=4:1, which are understood with reference to the foregoing description of FIG. 2, and will not be repeated here.

As shown in fig. 3, DQ represents the data being read. Specifically, in fig. 3, each dashed box contains an odd bit and an even bit. For example, the first box contains bit0 and bit1, if odd bits of data are to be sampled at the falling edge of the target clock signal, then the dashed box samples at the falling edge of the WCK throughout the clock period of the target clock signal WCK, and the sampled data all hold the odd bits, i.e. bit1 is held in the first dashed box, bit3 is held in the second dashed box, bit5 is held in the third dashed box, equivalent to bit0=bit1, bit2=bit3 …. By doing so, it is achieved that data is read from the target detection area only at the falling edge timing of the target clock signal, resulting in second sampled data. And for the first sampling data, the data in the target storage area are all read, and then sampling is carried out at the rising edge moment of the target clock signal, so that a first sampling number series is obtained.

S106, determining a test result based on the first test data and the first sampling data and the second test data and the second sampling data.

When determining the test result, the data sampled by reading may be compared with the test data to confirm whether the data is consistent, so as to determine whether the target storage area passes the test.

It should be noted that the above-described writing and reading samples are performed in two steps, and the comparison is divided into two steps. In some embodiments, determining the test result based on the first test data and the first sample data and the second test data and the second sample data may include:

and when the first comparison result indicates that the first test data is identical to the first sampling data and the second comparison result indicates that the second test data is identical to the second sampling data, determining that the test result is the passing of the test.

In the embodiment of the disclosure, since the first test data is written into the chip under test at the first type of flip time of the target clock signal, and the first sampling data is obtained by performing data reading sampling from the chip under test at the first type of flip time of the target clock signal, the first test data and the first sampling data are compared, and the first comparison result can be determined. Similarly, the second test data and the second sampling data are compared, and a second comparison result can be determined.

Specifically, the first comparison result may be that the first sampling data is the same as or different from the first test data, and the second comparison result may be that the second sampling data is the same as or different from the second test data; and determining that the test result of the target storage area passes the test only when the first comparison result and the second comparison result are the same, otherwise, determining that the test result of the target storage area fails the test as long as any one of the first comparison result and the second comparison result is different.

Thus, in some embodiments, the method may further comprise: and when the first comparison result indicates that the first test data is different from the first sampling data and/or the second comparison result indicates that the second test data is different from the second sampling data, determining that the test result is that the test fails.

Taking the first test data as even bit data in the test data and the second test data as odd bit data in the test data as an example, in a specific embodiment, determining the test result based on the first test data and the first sample data and the second test data and the second sample data may include:

and when the first comparison result indicates that the even bit data is identical to the first sampling data and the second comparison result indicates that the odd bit data is identical to the second test data, determining that the test result is test passing.

Further, in this case, the method may further include: and when the first comparison result indicates that the even bit data is different from the first sampling data and/or the second comparison result indicates that the odd bit data is different from the second test data, determining that the test result is that the test fails.

It should be further noted that, in the embodiment of the present disclosure, the chip to be tested may include a plurality of storage areas, and the target storage area is any one of the plurality of storage areas. Thus, for the whole chip under test, in some embodiments, the method may further comprise:

if each storage area in the storage areas passes the test, determining the test result of the tested chip as the test passing;

if any storage area test in the plurality of storage areas fails, determining that the test result of the tested chip is that the test fails.

It should be noted that, in the embodiment of the present disclosure, each storage area in the tested chip may be tested according to the foregoing method, and if each storage area passes the test, it may be determined that the tested chip passes the test, that is, a qualified product; if there is at least one memory area where the test fails, it may be determined that the chip under test fails, i.e., is a reject.

Thus, for the chip under test, the high-frequency test of the chip under test by using the low-frequency test equipment with low cost can be realized through two write operations and two read operations.

The embodiment provides a test method which is applied to test equipment and is used for determining a target clock signal based on an initial clock signal by determining the initial clock signal; wherein the clock frequency of the target clock signal is higher than the clock frequency of the initial clock signal; obtaining test data; the test data comprises first test data and second test data; sequentially writing first test data into a target storage area of a chip to be tested according to first type turnover moments of a target clock signal, and sequentially writing second test data into the target storage area of the chip to be tested according to second type turnover moments of the target clock signal; respectively carrying out data reading sampling on a target storage area of a chip to be tested according to first-class turning moments and second-class turning moments of a target clock signal, and determining first sampling data and second sampling data; a test result is determined based on the first test data and the first sample data and the second test data and the second sample data. In this way, when the high-frequency test is performed on the tested chip, the test data can be written into the tested chip with higher clock frequency by using the test equipment with lower clock frequency in a twice writing mode; the data can be read from the tested chip by using the test equipment with lower clock frequency in a twice reading and sampling mode; in this way, based on the comparison result of the written first test data and the read first sampling data and the comparison result of the written second test data and the read second sampling data, whether the tested chip passes the test can be determined; that is, compared with the related art relying on high-speed automatic test equipment, the scheme realizes high-frequency test of DRAM chips by using low-frequency test equipment, thereby not only reducing the test complexity, but also reducing the test cost.

In another embodiment of the present disclosure, reference is made to fig. 4, which shows a detailed flow schematic of a test method provided by an embodiment of the present disclosure. As shown in fig. 4, the method may include:

s401, powering up and initializing a chip to be tested.

S402, even bit data of the test data are written through mask writing.

S403, writing odd bit data of the test data by mask writing.

S404, only reading the even bit data and comparing the even bit data with the written even bit data.

S405, only the odd bit data is read and compared with the written odd bit data.

It should be noted that, in the embodiment of the present disclosure, when performing a high-frequency test, the chip to be tested is first powered on and initialized, so that the chip to be tested enters a test state.

And then performing two mask writing operations, namely writing even bit data of the test data into the target storage area of the chip to be tested for the first time, and writing odd bit data of the test data into the target storage area of the test data for the second time. The writing of the even bit data may be performed on a rising edge of a target clock signal, and the writing of the odd bit data may be performed on a falling edge of the target clock signal, which may be obtained by exclusive-or operation of two low frequency clock signals.

And then, two times of data reading operation are executed, wherein the first time only reads back the even bit data and compares the even bit data with the written even bit data, the second time only reads back the odd bit data and compares the odd bit data with the written odd bit data, and if the two times of comparison result is the same data, the test is passed. It should be noted that, only reading even bit data, specifically, the data can be completely read first, and then the data sampling is performed on the rising edge of the target clock signal; only the odd bit data is read, specifically, the data is read completely, and then the data sampling is performed on the falling edge of the target clock signal.

It should be further noted that, referring to fig. 5, a schematic signal timing diagram corresponding to a read operation is shown when a test device provided in an embodiment of the disclosure performs test control during the read operation. As shown in fig. 5, the timing sequence is identical to (b) in fig. 3, wherein C1, C2, C3, C4 and C5 are control signals of the test device, and are used for controlling the test device to generate corresponding clock signals; TP is the data value stored in the data register of the test device (i.e., the test data originally written), and strobe TP represents the data read from the DRAM for comparison with the written TP to determine whether the data output by the DRAM is correct, and further to determine whether the DRAM passes the test.

Thus, when the method provided by the embodiment of the present disclosure is used for testing, it is not necessary to modify the time setting group at any time, and one time setting group TS1 can complete all the tests.

Briefly, the present embodiment provides a method for testing a DRAM, and in particular, relates to an over-clocking method, which is described in detail in the foregoing embodiments, and it can be seen that, according to the technical solution of the foregoing embodiments, the method is applied to a DRAM high-frequency test (such as LPDDR5/DDR 5) by using a DRAM mask writing function and a low-frequency test device (such as LPDDR4/DDR 4). By exclusive-or of the two low-speed clocks, a multiplied high-speed clock (target clock signal) can be obtained, and the writing operation is performed twice by using the DRAM mask writing function: the first time only even bit data (clock rising edge of the target clock signal) is written, the second time only odd bit data (clock falling edge of the target clock signal) is written, and the same is done twice during the read operation: the first time only compares even bit data (clock rising edge of target clock signal), the second time only compares odd bit data (clock falling edge of target clock signal), after DRAM receives the read command, it will output the data of corresponding position according to the received address information, the tester will judge whether this data is correct in time at high speed to determine whether the test is passed. Thus, by this test method, the existing LPDDR4 (4.5 Gbps) tester can support high speed testing of LPDDR5 to 6.4Gbps, and based on this method, the skilled artisan can also realize that the existing underlying framework program can be reused for testing of higher frequency chips.

In yet another embodiment of the present disclosure, reference is made to fig. 6, which shows a schematic diagram of the composition and structure of a test apparatus 60 provided by an embodiment of the present disclosure. As shown in fig. 6, the test device 60 may include a determination unit 601, a generation unit 602, an acquisition unit 603, a writing unit 604, a reading unit 605, and a comparison unit 606, wherein,

a determining unit 601 configured to determine an initial clock signal;

a generating unit 602 configured to generate a target clock signal based on the initial clock signal; wherein the clock frequency of the target clock signal is higher than the clock frequency of the initial clock signal;

an acquisition unit 603 configured to acquire test data; the test data comprises first test data and second test data;

the writing unit 604 is configured to sequentially write the first test data into the target storage area of the tested chip according to the first type flip time of the target clock signal, and sequentially write the second test data into the target storage area of the tested chip according to the second type flip time of the target clock signal;

a reading unit 605 configured to perform data reading sampling on the target storage area of the chip to be tested according to the first type flip time and the second type flip time of the target clock signal, and determine first sampling data and second sampling data;

The comparing unit 606 is configured to determine a test result based on the first test data and the first sampling data and the second test data and the second sampling data.

It should be noted that, the test apparatus 60 provided in the embodiment of the present disclosure may implement high-frequency testing of the chip under test. In the case of high-frequency testing, this is achieved by means of two writes and two reads. Specifically, the low-frequency initial clock signal is generated by the determination unit 601, and the high-frequency target clock signal is obtained by the generation unit 602 based on the low-frequency initial clock signal, and then the test data is written and read sampled based on the target clock signal. The writing unit 604 is configured to perform two writing operations, and write the first test data and the second test data into the target storage area of the tested chip respectively; the reading unit 605 is configured to perform two write operations to obtain first sample data and second sample data, respectively; the test result is finally determined by the comparison unit 606 from the two test data and the two sample data.

The first type of flip time indicates a falling edge time when the target clock signal is flipped from a high level to a low level, and the second type of flip time indicates a falling edge time when the target clock signal is flipped from a low level to a high level.

In some embodiments, the first test data is even bit data in the test data and the second test data is odd bit data in the test data; or,

the first test data is odd bit data in the test data, and the second test data is even bit data in the test data.

In some embodiments, the first type of flip time is a rising edge time of the target clock signal and the second type of flip time is a falling edge time of the target clock signal; and the writing unit 604 is further specifically configured to determine the first data mask signal and the second data mask signal, and phases of the first data mask signal and the second data mask signal are opposite when the first test data is even bit data in the test data and the second test data is odd bit data in the test data; when the first write operation is executed on the tested chip, the odd bit data is shielded based on the first data mask signal, and the even bit data is written into the target storage area of the tested chip in sequence at the rising edge moment of the target clock signal; and when the second write operation is executed on the tested chip, carrying out mask processing on the even bit data based on the second data mask signal, and writing the odd bit data into the target storage area of the tested chip in sequence at the second type flip moment of the target clock signal.

In some embodiments, the reading unit 605 is further specifically configured to, when performing a first reading operation on the chip under test, read data from the target storage area of the chip under test, and sample the read data according to the rising edge time of the target clock signal, so as to obtain first sampled data; when the second reading operation is executed on the chip to be tested, data is read from a target storage area of the chip to be tested, and the read data is sampled according to the falling edge moment of the target clock signal to obtain second sampled data;

the comparing unit 606 is further specifically configured to determine a first comparison result of the even bit data and the first sampling data; and determining a second comparison result of the odd bit data and the second sampling data; and determining that the test result is passing when the first comparison result indicates that the even bit data is identical to the first sampling data and the second comparison result indicates that the odd bit data is identical to the second sampling data.

In some embodiments, the writing unit 604 is specifically configured to determine the first data mask signal and the second data mask signal, and the phases of the first data mask signal and the second data mask signal are opposite; when the first write operation is executed on the tested chip, masking the second test data based on the first data masking signal, and writing the first test data into the target storage area of the tested chip in sequence at the first type turning moment of the target clock signal; and when the second write operation is executed on the tested chip, masking the first test data based on the second data masking signal, and writing the second test data into the target storage area of the tested chip in sequence at the second type flip time of the target clock signal so as to realize writing the test data into the target storage area of the tested chip.

In some embodiments, when performing a first write operation on the chip under test, the first data mask signal is used to mask the second test data corresponding to the valid state when in the valid state; when the second write operation is performed on the tested chip, the second data mask signal is used for shielding the first test data corresponding to the valid state when the second write operation is in the valid state.

In some embodiments, the reading unit 605 is specifically configured to, when performing a first reading operation on the chip under test, read data from the target storage area of the chip under test, and sample the read data according to a first type of flip time of the target clock signal, so as to obtain first sampled data; and when the second reading operation is executed on the tested chip, data is read from the target storage area of the tested chip, and the read data is sampled according to the second type turning moment of the target clock signal, so as to obtain second sampled data.

In some embodiments, the comparing unit 606 is specifically configured to determine a first comparison result of the first test data and the first sample data; and determining a second comparison result of the second test data and the second sample data; and determining that the test result is passing when the first comparison result indicates that the first test data is identical to the first sampling data and the second comparison result indicates that the second test data is identical to the second sampling data.

In some embodiments, the comparing unit 606 is further specifically configured to determine that the test result is a test failed when the first comparison result indicates that the first test data is different from the first sampled data and/or the second comparison result indicates that the second test data is different from the second sampled data.

In some embodiments, the chip under test includes a plurality of memory regions, the target memory region being any one of the plurality of memory regions; the comparing unit 606 is further configured to determine that the test result of the tested chip is test passing if each of the plurality of memory areas passes the test; and if the test of any storage area in the storage areas fails, determining that the test result of the tested chip is that the test fails.

In some embodiments, the determining unit 601 is specifically configured to obtain the first clock signal and the second clock signal; the phase difference between the first clock signal and the second clock signal is 90 degrees, and the clock frequency of the first clock signal and the clock frequency of the second clock signal are half of the clock frequency of the target clock signal;

the generating unit 602 is specifically configured to perform an exclusive-or operation on the first clock signal and the second clock signal to obtain a target clock signal.

In some embodiments, the chip under test meets DDR5 memory specifications or LPDDR5 memory specifications.

It will be appreciated that in this embodiment, the "unit" may be a part of a circuit, a part of a processor, a part of a program or software, etc., and may of course be a module, or may be non-modular. Furthermore, the components in the present embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional modules.

The integrated units, if implemented in the form of software functional modules, may be stored in a computer-readable storage medium, if not sold or used as separate products, and based on such understanding, the technical solution of the present embodiment may be embodied essentially or partly in the form of a software product, or all or part of the technical solution, which is stored in a storage medium, and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or processor to perform all or part of the steps of the method described in the present embodiment. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Accordingly, the present embodiment provides a computer storage medium storing a computer program which, when executed by at least one processor, implements the steps of the method of any of the preceding embodiments.

Based on the above-mentioned computer storage medium, referring to fig. 7, a schematic diagram of the composition structure of another test apparatus 60 according to an embodiment of the present disclosure is shown. As shown in fig. 7, may include: a communication interface 501, a memory 502 and a processor 503; the various components are coupled together by a bus system 504. It is to be appreciated that bus system 504 is employed to enable connected communications between these components. The bus system 504 includes a power bus, a control bus, and a status signal bus in addition to the data bus. But for clarity of illustration, the various buses are labeled as bus system 504 in fig. 7. The communication interface 501 is configured to receive and send signals in a process of receiving and sending information with other external network elements;

a memory 502 for storing a computer program capable of running on the processor 503;

a processor 503 for executing, when running the computer program:

Determining an initial clock signal;

obtaining test data; the test data comprises first test data and second test data;

sequentially writing the first test data into a target storage area of the chip to be tested according to the first type of turnover time of the target clock signal, and sequentially writing the second test data into the target storage area of the chip to be tested according to the second type of turnover time of the target clock signal;

respectively carrying out data reading sampling on a target storage area of a chip to be tested according to first-class turning moments and second-class turning moments of a target clock signal, and determining first sampling data and second sampling data;

and determining a test result based on the first test data and the first sampling data and the second test data and the second sampling data.

It is to be appreciated that the memory 502 in embodiments of the present disclosure may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (Random Access Memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), DRAM, synchronous DRAM (SDRAM), double Data Rate SDRAM (ddr SDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), and Direct memory bus RAM (DRRAM). The memory 502 of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

And the processor 503 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuitry of hardware in the processor 503 or by instructions in the form of software. The processor 503 may be a general purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The various methods, steps and logic blocks of the disclosure in the embodiments of the disclosure may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present disclosure may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software modules in a decoded processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in the memory 502, and the processor 503 reads the information in the memory 502, and in combination with its hardware, performs the steps of the above method.

It is to be understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For a hardware implementation, the processing units may be implemented within one or more special purpose integrated circuits (Application Specific Integrated Circuits, ASIC), digital signal processors (Digital Signal Processing, DSP), digital signal processing devices (DSP devices, DSPD), programmable logic devices (Programmable Logic Device, PLD), field programmable gate arrays (Field-Programmable Gate Array, FPGA), general purpose processors, controllers, microcontrollers, microprocessors, other electronic units configured to perform the functions described herein, or a combination thereof.

For a software implementation, the techniques described herein may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. The software codes may be stored in a memory and executed by a processor. The memory may be implemented within the processor or external to the processor.

Optionally, as another embodiment, the processor 503 is further configured to perform the method of any of the previous embodiments when running the computer program.

In the embodiment of the present disclosure, for the electronic device 60, when performing high-frequency test on the chip to be tested, by means of writing and reading the sample twice, and then based on the comparison result of the written test data and the read sample data, it can be determined whether the chip to be tested passes the test; that is, compared with the related art relying on high-speed automatic test equipment, the scheme realizes high-frequency test of DRAM chips by using low-frequency test equipment, thereby not only reducing the test complexity, but also reducing the test cost.

The foregoing description is only of the preferred embodiments of the present disclosure and is not intended to limit the scope of the present disclosure.

It should be noted that in this disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The disclosed features of several product embodiments provided by the present disclosure may be combined arbitrarily without conflict to arrive at a new product embodiment. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method of testing, the method comprising:

determining an initial clock signal;

2. The method of claim 1, wherein the first type of transition time represents a rising edge time at which the target clock signal transitions from low to high, and wherein the second type of transition time represents a falling edge time at which the target clock signal transitions from high to low; or,

3. The method of claim 2, wherein the acquiring test data comprises:

4. A method according to claim 3, wherein the first type of flip time is a rising edge time of the target clock signal and the second type of flip time is a falling edge time of the target clock signal; and the first test data is even bit data in the test data, and the second test data is odd bit data in the test data,

5. The method of claim 4, wherein the performing data read sampling on the target memory area of the chip under test according to the first class flip time and the second class flip time of the target clock signal, respectively, and determining the first sampling data and the second sampling data comprises:

When the second reading operation is executed on the tested chip, data is read from a target storage area of the tested chip, and the read data is sampled according to the falling edge moment of the target clock signal to obtain second sampled data;

6. The method of claim 1, wherein after the first test data is sequentially written to the target memory area of the chip under test according to the first type flip time of the target clock signal, the second test data is sequentially written to the target memory area of the chip under test according to the second type flip time of the target clock signal, comprising:

7. The method of claim 6, wherein the masking the second test data based on the first data mask signal when performing a first write operation on the chip under test comprises: shielding the second test data corresponding to the valid state when the first data mask signal is in the valid state;

8. The method of claim 1, wherein the performing data read sampling on the target memory area of the chip under test according to the first class flip time and the second class flip time of the target clock signal, respectively, and determining the first sampling data and the second sampling data includes:

and when the second reading operation is executed on the tested chip, data is read from a target storage area of the tested chip, and the read data is sampled according to the second type turning moment of the target clock signal, so that the second sampled data is obtained.

9. The method of claim 1, wherein the determining a test result based on the first test data and the first sample data and the second test data and the second sample data comprises:

10. The method according to claim 9, wherein the method further comprises:

11. The method of claim 10, wherein the chip under test comprises a plurality of memory regions, the target memory region being any one of the plurality of memory regions; the method further comprises the steps of:

12. The method of any one of claims 1 to 11, wherein determining the initial clock signal comprises: determining a first clock signal and a second clock signal; the phase difference between the first clock signal and the second clock signal is 90 degrees, and the clock frequency of the first clock signal and the clock frequency of the second clock signal are half of the clock frequency of the target clock signal;

the generating a target clock signal based on the initial clock signal includes: and performing exclusive-or operation on the first clock signal and the second clock signal to obtain the target clock signal.

13. A test apparatus, characterized in that the test apparatus comprises a determination unit, a generation unit, an acquisition unit, a writing unit, a reading unit and a comparison unit, wherein,

the determining unit is configured to determine an initial clock signal;

The generating unit is configured to generate a target clock signal based on the initial clock signal; wherein the clock frequency of the target clock signal is higher than the clock frequency of the initial clock signal;

14. A test apparatus comprising a memory and a processor, wherein,

the processor being adapted to perform the test method according to any of claims 1 to 12 when the computer program is run.

15. A computer storage medium, characterized in that it stores a computer program which, when executed by at least one processor, implements the test method according to any one of claims 1 to 12.