CN117194018A - Processing method and device of system temperature control algorithm in multi-core and multi-chip environment - Google Patents
Processing method and device of system temperature control algorithm in multi-core and multi-chip environment Download PDFInfo
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Abstract
The invention discloses a processing method and a device of a system temperature control algorithm in a multi-core and multi-chip environment, wherein the processing method comprises the following steps: the target chip splits the control Wen Suanfa corresponding to the multi-core multi-chip architecture into a serial algorithm and a parallel algorithm; executing a serial algorithm through a first computing core in the target chip, and executing a parallel algorithm through a second computing core in the target chip; the first computing core is a computing core used for data transmission in the target chip; the second computing core is a computing core used for data computation in the target chip; and the first computing core and the second computing core perform data transmission through a high-speed data transmission bus. The technical scheme of the embodiment of the invention can reduce the execution time consumption of the temperature control algorithm in the multi-core multi-chip architecture and improve the execution efficiency of the temperature control algorithm.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a processing method and a processing device of a system temperature control algorithm in a multi-core and multi-chip environment.
Background
With the development of artificial intelligence (Artificial Intelligence, AI), conventional chip architecture has gradually shifted to a multi-core multi-chip mode, i.e., a chip architecture including a plurality of chips each including a plurality of computing cores.
The existing multi-core multi-chip architecture can design a chip serial temperature control algorithm and a parallel temperature control algorithm which adapt to sparseness change according to the characteristic that the sparseness of a convolution kernel changes along with input according to a neural network algorithm, and then randomly select a computing kernel in each chip to execute the serial temperature control algorithm or the parallel temperature control algorithm, so that the temperature control algorithm is long in execution time and low in efficiency.
Disclosure of Invention
The invention provides a processing method and a processing device for a system temperature control algorithm in a multi-core and multi-chip environment, which can reduce the execution time consumption of the temperature control algorithm in a multi-core and multi-chip architecture and improve the execution efficiency of the temperature control algorithm.
According to an aspect of the present invention, there is provided a method for processing a system temperature control algorithm in a multi-core and multi-chip environment, applied to a target chip in the multi-core and multi-chip environment, the method including:
splitting the control Wen Suanfa corresponding to the multi-core multi-chip architecture into a serial algorithm and a parallel algorithm;
executing a serial algorithm through a first computing core in the target chip, and executing a parallel algorithm through a second computing core in the target chip;
the first computing core is a computing core used for data transmission in the target chip; the second computing core is a computing core used for data computation in the target chip; and the first computing core and the second computing core perform data transmission through a high-speed data transmission bus.
Optionally, before the serial algorithm is executed by the first computing core in the target chip and the parallel algorithm is executed by the second computing core in the target chip, the method further includes:
acquiring all computing cores included in a target chip;
and screening the first computing core and the second computing core from all computing cores according to the transmission performance and the computing performance corresponding to each computing core.
Optionally, executing, by the first computing core in the target chip, a serial algorithm includes:
the kinetic energy components sent by each second computing core in the target chip are accumulated in parallel through the first computing core in the target chip, so that a kinetic energy component accumulated value is obtained;
the kinetic energy component accumulated values are globally broadcast to the first computing cores corresponding to the remaining chips through the first computing cores, and the kinetic energy component accumulated values sent by the first computing cores in the remaining chips are globally accumulated to obtain global kinetic energy values;
processing a serial algorithm of a temperature control algorithm according to the global kinetic energy value through the first computing core to obtain a temperature control computing parameter;
and sending the temperature control calculation parameters to each second calculation core through the first calculation core so as to enable each second calculation core to update the temperature control calculation parameters in parallel.
Optionally, executing, by a second computing core in the target chip, a parallel algorithm, including:
calculating corresponding kinetic energy components through each second calculation core in the target chip, and sending the kinetic energy components to the first calculation core;
and after receiving the temperature control calculation parameters sent by the first calculation core, updating the temperature control calculation parameters in parallel.
The kinetic energy components sent by each second computing core in the target chip are accumulated in parallel through the first computing core in the target chip to obtain a kinetic energy component accumulated value, and the method comprises the following steps:
and after receiving kinetic energy components sent by all second computing cores in the target chip through the first computing cores in the target chip, accumulating all the kinetic energy components in parallel to obtain a kinetic energy component accumulated value.
Optionally, global accumulating the kinetic energy component accumulated values sent by the first computing cores in the remaining chips to obtain global kinetic energy values, including:
and after receiving the kinetic energy component accumulated values sent by the first computing cores in all the remaining chips through the first computing cores in the target chip, carrying out global accumulation on each kinetic energy component accumulated value to obtain a global kinetic energy value.
According to another aspect of the present invention, there is provided a processing apparatus for a system temperature control algorithm in a multi-core and multi-chip environment, applied to a target chip of the multi-core and multi-chip environment, the apparatus comprising:
the algorithm splitting module is used for splitting the control Wen Suanfa corresponding to the multi-core multi-chip architecture into a serial algorithm and a parallel algorithm;
the algorithm execution module is used for executing a serial algorithm through a first computing core in the target chip and executing a parallel algorithm through a second computing core in the target chip;
the first computing core is a computing core used for data transmission in the target chip; the second computing core is a computing core used for data computation in the target chip; and the first computing core and the second computing core perform data transmission through a high-speed data transmission bus.
Optionally, the apparatus further includes:
the computing core acquisition module is used for acquiring all computing cores included in the target chip;
and the computing core screening module is used for screening the first computing core and the second computing core from all the computing cores according to the transmission performance and the computing performance corresponding to each computing core.
According to another aspect of the present invention, there is provided a chip including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor, so that the at least one processor can execute the processing method of the system temperature control algorithm in the multi-core multi-chip environment according to any embodiment of the present invention.
According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to implement a processing method of a system temperature control algorithm in a multi-core and multi-chip environment according to any one of the embodiments of the present invention when executed.
According to the technical scheme provided by the embodiment of the invention, the target chip is used for splitting the control Wen Suanfa corresponding to the multi-core multi-chip architecture into the serial algorithm and the parallel algorithm, the first computing core in the target chip is used for executing the serial algorithm, and the second computing core in the target chip is used for executing the parallel algorithm, so that the execution time consumption of the temperature control algorithm in the multi-core multi-chip architecture can be reduced, and the execution efficiency of the temperature control algorithm can be improved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a processing method of a system temperature control algorithm in a multi-core and multi-chip environment according to an embodiment of the present invention;
FIG. 2 is a flowchart of a processing method of a system temperature control algorithm in a multi-core and multi-chip environment according to another embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a processing device for a system temperature control algorithm in a multi-core and multi-chip environment according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a chip structure for implementing a processing method of a system temperature control algorithm in a multi-core and multi-chip environment according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a flowchart of a processing method of a system temperature control algorithm in a multi-core and multi-chip environment according to a first embodiment of the present invention, where the embodiment is applicable to a case of performing data processing by a multi-core and multi-chip architecture, the method may be performed by a processing device of the system temperature control algorithm in the multi-core and multi-chip environment, the device may be implemented in a hardware and/or software form, and the device may be configured in a target chip with a data processing function. As shown in fig. 1, the method includes:
step 110, splitting the control Wen Suanfa corresponding to the multi-core multi-chip architecture into a serial algorithm and a parallel algorithm.
In this embodiment, the target chip may be any chip in a multi-core multi-chip architecture. The target chip may optionally split the control Wen Suanfa into a serial algorithm and a parallel algorithm according to the computational characteristics of the temperature control algorithm before performing the control Wen Suanfa.
Step 120, executing a serial algorithm through a first computing core in the target chip, and executing a parallel algorithm through a second computing core in the target chip.
In this embodiment, the first computing core is a computing core0 for performing data transmission in the target chip; the second computing core is a computing core1 for performing data computation in the target chip; and the first computing core and the second computing core perform data transmission through a high-speed data transmission bus.
In a specific embodiment, the first computing core in the target chip executes the serial algorithm and simultaneously transmits the corresponding execution result to each second computing core through the high-speed data transmission bus, so that each second computing core completes the parallel algorithm according to the execution result, and transmits the corresponding execution result to the first computing core through the high-speed data transmission bus, thereby realizing the complete execution process of the target chip on the temperature control algorithm.
In this embodiment, by disposing the serial algorithm and the parallel algorithm in the first computing core and the second computing core respectively, performance advantages of the computing cores in the target chip can be fully utilized, data computing efficiency and data transmission efficiency of the target chip can be improved, and execution performance of the target chip on the temperature control algorithm is ensured.
According to the technical scheme provided by the embodiment of the invention, the target chip is used for splitting the control Wen Suanfa corresponding to the multi-core multi-chip architecture into the serial algorithm and the parallel algorithm, the first computing core in the target chip is used for executing the serial algorithm, and the second computing core in the target chip is used for executing the parallel algorithm, so that the execution time consumption of the temperature control algorithm in the multi-core multi-chip architecture can be reduced, and the execution efficiency of the temperature control algorithm can be improved.
Fig. 2 is a flowchart of a processing method of a system temperature control algorithm in a multi-core and multi-chip environment according to a second embodiment of the present invention, where the embodiment is further refined. As shown in fig. 2, the method includes:
step 210, splitting the control Wen Suanfa corresponding to the multi-core multi-chip architecture into a serial algorithm and a parallel algorithm.
220. And acquiring all computing cores included in the target chip, and screening the first computing core and the second computing core from all computing cores according to the transmission performance and the computing performance corresponding to each computing core.
In this embodiment, the performance of different computing cores in the target chip is different. Alternatively, according to the performance priority of each computing core in the target chip, a computing core with a higher priority of transmission data is selected from all computing cores as a first computing core0, and then a computing core with a higher priority of computing performance is selected as a second computing core1.
The first computing core is used for receiving and transmitting data, and the second computing core is used for computing the data.
Step 230, calculating a corresponding kinetic energy component by each second calculation core in the target chip, and sending the kinetic energy component to the first calculation core.
In this embodiment, each second computing core in the target chip may calculate a corresponding kinetic energy component according to a calculation rule of the temperature control algorithm, and then send the kinetic energy component to the first computing core.
And 240, accumulating the kinetic energy components sent by the second computing cores in the target chip in parallel through the first computing cores in the target chip to obtain a kinetic energy component accumulated value.
In one implementation manner of this embodiment, by using the first computing core in the target chip, the kinetic energy components sent by the second computing cores in the target chip are accumulated in parallel to obtain a kinetic energy component accumulated value, which includes: and after receiving kinetic energy components sent by all second computing cores in the target chip through the first computing cores in the target chip, accumulating the kinetic energy components to obtain a kinetic energy component accumulated value.
In a specific embodiment, the first computing core in the target chip accumulates the kinetic energy components only after detecting that all of the second computing cores send the kinetic energy components to the first computing core.
The advantage of this arrangement is that the omission of the kinetic energy component of the second computing core in the first computing core in the target chip can be avoided, and therefore the accuracy of the execution result of the temperature control algorithm can be ensured.
Step 250, globally broadcasting the kinetic energy component accumulated value to the first computing cores corresponding to the remaining chips through the first computing cores in the target chip, and globally accumulating the kinetic energy component accumulated values sent by the first computing cores in the remaining chips to obtain global kinetic energy values.
In one implementation manner of this embodiment, performing global accumulation on the kinetic energy component accumulated values sent by the first computing cores in the remaining chips to obtain global kinetic energy values includes: and after receiving the kinetic energy component accumulated values sent by the first computing cores in all the remaining chips through the first computing cores in the target chip, carrying out global accumulation on each kinetic energy component accumulated value to obtain a global kinetic energy value.
In a specific embodiment, in the multi-core multi-chip architecture, the first computing core of each chip sends the corresponding accumulated kinetic energy component value to the first computing cores of other chips after the accumulated kinetic energy component value is calculated. For a target chip, only the first computing core in the chip is detected, and after the kinetic energy component accumulated values sent by the first computing core of each remaining chip are received, the kinetic energy component accumulated values are subjected to global accumulation.
The advantage of this arrangement is that the omission of the accumulated value of the kinetic energy components of the target chip to other chips can be avoided, and therefore the accuracy of the execution result of the temperature control algorithm can be ensured.
And 260, processing a serial algorithm of the temperature control algorithm according to the global kinetic energy value through the first computing core to obtain a temperature control computing parameter.
Step 270, sending, by the first computing core, the temperature control computing parameter to each second computing core, so that each second computing core performs parallel update on the temperature control computing parameter.
Step 280, after receiving the temperature control calculation parameters sent by the first calculation core through each second calculation core in the target chip, updating the temperature control calculation parameters in parallel.
According to the technical scheme provided by the embodiment of the invention, the target chip is used for splitting the control Wen Suanfa corresponding to the multi-core multi-chip architecture into the serial algorithm and the parallel algorithm, all calculation cores included in the target chip are obtained, the first calculation cores and the second calculation cores are screened in all the calculation cores according to the transmission performance and the calculation performance corresponding to each calculation core, the kinetic energy components corresponding to each second calculation core in the target chip are calculated and sent to the first calculation cores, the kinetic energy components sent by each second calculation core in the target chip are accumulated through the first calculation cores in the target chip to obtain the kinetic energy component accumulated value, the kinetic energy component accumulated value is globally broadcast to the first calculation cores corresponding to the rest chips through the first calculation cores in the target chip, the kinetic energy component accumulated value sent by the first calculation cores in the rest chips is globally accumulated to obtain global kinetic energy values, the serial algorithm of the temperature control algorithm is processed according to the global kinetic energy values to obtain the temperature control calculation parameters, the temperature control calculation parameters are sent to each second calculation core through the first calculation cores, the temperature control parameters are sent to each second calculation core, the temperature control algorithm is updated through the first calculation cores, the temperature control algorithm is carried out in order to reduce the accuracy of the temperature control algorithm, and the performance of the multi-core multi-chip architecture is carried out, and the temperature control algorithm is accurately executed.
Fig. 3 is a schematic structural diagram of a processing device for a system temperature control algorithm in a multi-core and multi-chip environment according to a third embodiment of the present invention, where, as shown in fig. 3, the device includes: an algorithm splitting module 310 and an algorithm executing module 320.
The algorithm splitting module 310 is configured to split a control Wen Suanfa corresponding to the multi-core multi-chip architecture into a serial algorithm and a parallel algorithm;
an algorithm execution module 320, configured to execute a serial algorithm through a first computing core in the target chip and execute a parallel algorithm through a second computing core in the target chip;
the first computing core is a computing core used for data transmission in the target chip; the second computing core is a computing core used for data computation in the target chip; and the first computing core and the second computing core perform data transmission through a high-speed data transmission bus.
According to the technical scheme provided by the embodiment of the invention, the target chip is used for splitting the control Wen Suanfa corresponding to the multi-core multi-chip architecture into the serial algorithm and the parallel algorithm, the first computing core in the target chip is used for executing the serial algorithm, and the second computing core in the target chip is used for executing the parallel algorithm, so that the execution time consumption of the temperature control algorithm in the multi-core multi-chip architecture can be reduced, and the execution efficiency of the temperature control algorithm can be improved.
On the basis of the above embodiment, the apparatus further includes:
the computing core acquisition module is used for acquiring all computing cores included in the target chip;
and the computing core screening module is used for screening the first computing core and the second computing core from all the computing cores according to the transmission performance and the computing performance corresponding to each computing core.
The algorithm execution module 320 includes:
the component accumulation unit is used for accumulating the kinetic energy components sent by each second computing core in the target chip in parallel through the first computing core in the target chip to obtain a kinetic energy component accumulation value;
the global accumulation unit is used for globally broadcasting the kinetic energy component accumulation value to the first computation cores corresponding to the remaining chips through the first computation cores, and globally accumulating the kinetic energy component accumulation values sent by the first computation cores in the remaining chips to obtain global kinetic energy values;
the temperature control parameter determining unit is used for processing a serial algorithm of a temperature control algorithm according to the global kinetic energy value through the first computing core to obtain a temperature control computing parameter;
the temperature control parameter sending unit is used for sending the temperature control calculation parameters to each second calculation core through the first calculation core so as to enable each second calculation core to update the temperature control calculation parameters in parallel;
a component sending unit, configured to calculate a corresponding kinetic energy component through each second computing core in the target chip, and send the kinetic energy component to the first computing core;
the temperature control parameter receiving unit is used for receiving the temperature control calculation parameters sent by the first calculation core through the second calculation core in the target chip and then updating the temperature control calculation parameters in parallel;
the computing core detection unit is used for receiving kinetic energy components sent by all second computing cores in the target chip through the first computing cores in the target chip, and then accumulating all the kinetic energy components in parallel to obtain a kinetic energy component accumulated value;
the chip detection unit is used for receiving the kinetic energy component accumulated values sent by the first computing cores in all the remaining chips through the first computing cores in the target chip, and then carrying out global accumulation on the kinetic energy component accumulated values to obtain global kinetic energy values.
The device can execute the method provided by all the embodiments of the invention, and has the corresponding functional modules and beneficial effects of executing the method. Technical details not described in detail in the embodiments of the present invention can be found in the methods provided in all the foregoing embodiments of the present invention.
Fig. 4 shows a schematic diagram of the structure of a chip 10 that may be used to implement an embodiment of the invention. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.
As shown in fig. 4, the chip 10 includes at least one processor 11, and a memory, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, etc., communicatively connected to the at least one processor 11, in which the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the chip 10 can also be stored. The processor 11, the ROM 12 and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.
The various components in the chip 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, etc.; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the chip 10 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.
The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as the processing of a system temperature control algorithm in a multi-core, multi-chip environment.
In some embodiments, the processing method of the system temperature control algorithm in a multi-core, multi-chip environment may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the chip 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the processing method of the system temperature control algorithm in a multi-core, multi-chip environment described above may be performed. Alternatively, in other embodiments, processor 11 may be configured in any other suitable manner (e.g., by means of firmware) to perform the processing method of the system temperature control algorithm in a multi-core, multi-chip environment.
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), complex Programmable Logic Devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a chip having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or a trackball) through which a user can provide input to the chip. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.
The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. The processing method of the system temperature control algorithm in the multi-core and multi-chip environment is characterized by being applied to a target chip in the multi-core and multi-chip environment, and comprises the following steps:
splitting the control Wen Suanfa corresponding to the multi-core multi-chip architecture into a serial algorithm and a parallel algorithm;
executing a serial algorithm through a first computing core in the target chip, and executing a parallel algorithm through a second computing core in the target chip;
the first computing core is a computing core used for data transmission in the target chip; the second computing core is a computing core used for data computation in the target chip; and the first computing core and the second computing core perform data transmission through a high-speed data transmission bus.
2. The method of claim 1, further comprising, prior to executing the serial algorithm by a first computing core in the target chip and the parallel algorithm by a second computing core in the target chip:
acquiring all computing cores included in a target chip;
and screening the first computing core and the second computing core from all computing cores according to the transmission performance and the computing performance corresponding to each computing core.
3. The method of claim 1, wherein executing, by the first computing core in the target chip, a serial algorithm comprises:
the kinetic energy components sent by each second computing core in the target chip are accumulated in parallel through the first computing core in the target chip, so that a kinetic energy component accumulated value is obtained;
the kinetic energy component accumulated values are globally broadcast to the first computing cores corresponding to the remaining chips through the first computing cores, and the kinetic energy component accumulated values sent by the first computing cores in the remaining chips are globally accumulated to obtain global kinetic energy values;
processing a serial algorithm of a temperature control algorithm according to the global kinetic energy value through the first computing core to obtain a temperature control computing parameter;
and sending the temperature control calculation parameters to each second calculation core through the first calculation core so as to enable each second calculation core to update the temperature control calculation parameters in parallel.
4. A method according to claim 3, wherein executing a parallel algorithm by a second computing core in the target chip comprises:
calculating corresponding kinetic energy components through each second calculation core in the target chip, and sending the kinetic energy components to the first calculation core;
and after receiving the temperature control calculation parameters sent by the first calculation core, updating the temperature control calculation parameters in parallel.
5. The method of claim 3, wherein accumulating, by a first computing core in the target chip, the kinetic energy components sent by each second computing core in the target chip in parallel, to obtain a kinetic energy component accumulated value, comprising:
and after receiving kinetic energy components sent by all second computing cores in the target chip through the first computing cores in the target chip, accumulating all the kinetic energy components in parallel to obtain a kinetic energy component accumulated value.
6. The method of claim 3, wherein globally accumulating the kinetic energy component accumulation values sent by the first computing cores in the remaining chips to obtain global kinetic energy values, comprising:
and after receiving the kinetic energy component accumulated values sent by the first computing cores in all the remaining chips through the first computing cores in the target chip, carrying out global accumulation on each kinetic energy component accumulated value to obtain a global kinetic energy value.
7. A multi-core, multi-chip temperature control apparatus for a target chip of a multi-core, multi-chip, the apparatus comprising:
the algorithm splitting module is used for splitting the control Wen Suanfa corresponding to the multi-core multi-chip architecture into a serial algorithm and a parallel algorithm;
the algorithm execution module is used for executing a serial algorithm through a first computing core in the target chip and executing a parallel algorithm through a second computing core in the target chip;
the first computing core is a computing core used for data transmission in the target chip; the second computing core is a computing core used for data computation in the target chip; and the first computing core and the second computing core perform data transmission through a high-speed data transmission bus.
8. The apparatus of claim 7, wherein the apparatus further comprises:
the computing core acquisition module is used for acquiring all computing cores included in the target chip;
and the computing core screening module is used for screening the first computing core and the second computing core from all the computing cores according to the transmission performance and the computing performance corresponding to each computing core.
9. A chip, the chip comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the method of processing a system temperature control algorithm in a multi-core, multi-chip environment of any one of claims 1-6.
10. A computer readable storage medium, wherein the computer readable storage medium stores computer instructions for causing a processor to execute a processing method for implementing a system temperature control algorithm in a multi-core and multi-chip environment according to any one of claims 1 to 6.
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