CN117192320A - Current detection circuit and method for fully-integrated gallium nitride power chip - Google Patents
Current detection circuit and method for fully-integrated gallium nitride power chip Download PDFInfo
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 169
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 164
- 238000001514 detection method Methods 0.000 title claims abstract description 118
- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000005070 sampling Methods 0.000 claims description 42
- 239000003990 capacitor Substances 0.000 claims description 30
- 239000003381 stabilizer Substances 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 11
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- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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Abstract
The embodiment of the application provides a current detection circuit and a current detection method for a fully integrated gallium nitride power chip, and relates to the technical field of gallium nitride power chips. The on-chip negative pressure is realized by the on-chip voltage stabilizer (U21), the source electrode potential of the gallium nitride detection tube is clamped near the source electrode potential of the gallium nitride power tube by the feedback loop formed by the clamping operational amplifier (U1) and the gallium nitride detection tube, so that accurate current detection is realized, meanwhile, the current flowing through the gallium nitride power tube can be accurately detected on the premise of low power loss, and the problems of high current detection loss and inaccurate detection by the gallium nitride detection tube are solved. In addition, in order to treat the serious mismatch condition possibly existing in the process, an automatic zeroing scheme can be adopted to reduce the offset voltage of the operational amplifier. The circuit structure can be applied to functional modules such as overcurrent protection, peak current control and the like, and provides conditions for carrying more intelligent gallium nitride on-chip functional modules.
Description
Technical Field
The application relates to the technical field of gallium nitride power chips, in particular to a current detection circuit and a method for a fully-integrated gallium nitride power chip.
Background
Gallium nitride power devices are increasingly replacing conventional silicon power devices with their advantages of smaller on-resistance and gate charge in high power density and high frequency applications. Currently, the main gallium nitride power device products in the market are mainly divided into two major types, namely a hybrid scheme and a monolithic integration scheme, and the monolithic integration scheme can be called full integration.
The hybrid scheme is to design a grid driving and controlling circuit on a silicon-based chip aiming at a mature commercial discrete gallium nitride power device, and bond or board-level wiring is carried out between the grid driving and controlling circuit and the silicon-based chip. Loop parasitic inductance caused by bonding or board-level routing can cause serious problems such as radiation electromagnetic interference and reliability. The monolithic integration scheme integrates the driving and control circuit and the power device into one chip, so that the problems in the mixed scheme can be effectively solved.
The existing fully integrated gallium nitride power chip is designed to be relatively simple, and aims to solve the technical difficulties of lack of usable p-channel devices, poor matching performance, higher low-voltage HEMTs threshold voltage and the like. The design of the gallium nitride circuit on the chip is further optimized, a more intelligent on-chip functional module is carried, and the realization of the accurate current detection with low loss on the chip becomes a key problem.
In the prior art, a simpler current detection scheme is to connect an accurate resistor to the source electrode of the off-chip power device to directly detect the current of the power device. This scheme is relatively accurate, but the loss generated is also large due to the large current flowing through the sense resistor. To avoid such losses, a scheme of parallel-connecting proportional sense transistors, i.e., sense HEMTs, to the power transistors to sense the current of the power transistors by sensing the current of the sense HEMTs becomes an alternative. However, if the resistor is connected in series to the source of the sense HEMT to obtain the detection voltage, the sources of the power tube and the detection tube are not completely connected in parallel, so that the detected voltage is distorted, and the detected current of the power device is inaccurate.
Disclosure of Invention
The application introduces a current detection circuit and a current detection method for a fully integrated gallium nitride power chip, wherein the fully integrated gallium nitride power chip is different from a traditional method for bonding a discrete gallium nitride component with a silicon-based driver and an integrated chip designed by using a gallium nitride integrated circuit process. The scheme of the application can accurately detect the current flowing through the power device on the premise of low power loss, and can be applied to the protection and control of gallium nitride integrated circuits.
In a first aspect, an embodiment of the present application provides a current detection circuit of a fully integrated gallium nitride power chip, configured to detect a current of a gallium nitride power tube; the current detection circuit includes: a gallium nitride detection tube and a negative feedback loop;
the gallium nitride power tube and the gallium nitride detection tube have a proportional width-to-length ratio so as to ensure that the gallium nitride detection tube can copy the current of the gallium nitride power tube in proportion;
the negative feedback loop comprises a clamping operational amplifier, a negative feedback switching tube and a sampling unit;
the drain electrode of the gallium nitride detection tube is connected with the drain electrode of the gallium nitride power tube, the grid electrode of the gallium nitride detection tube is connected with the grid electrode of the gallium nitride power tube, the source electrode of the gallium nitride detection tube is connected with the in-phase input end of the clamping operational amplifier, the source electrode of the gallium nitride power tube is connected with the reverse-phase input end of the clamping operational amplifier, the clamping operational amplifier output end is connected with the grid electrode of the negative feedback switch tube, the drain electrode of the negative feedback switch tube is connected with the source electrode of the gallium nitride detection tube, the source electrode of the negative feedback switch tube is connected with the first end of the sampling unit, the second end of the sampling unit is connected with a negative pressure point, and the negative pressure point is used for providing a potential lower than the potential of the source electrode of the gallium nitride power tube so as to conduct the negative feedback loop.
Optionally, the current detection circuit further comprises a negative pressure voltage stabilizer, wherein a positive pressure end of the negative pressure voltage stabilizer is connected with a first power supply, and a reference end of the negative pressure voltage stabilizer is connected with a source electrode of the gallium nitride power tube; the negative voltage terminal of the negative voltage regulator is used for providing a potential lower than the potential of the reference terminal of the negative voltage regulator.
Optionally, the sampling unit includes a sampling resistor;
the source electrode of the negative feedback switch tube is connected with the first end of the sampling resistor, and the second end of the sampling resistor is connected with the negative pressure point;
the first end of the sampling resistor is used as a sampling end to output, and the sampling resistor converts the detected current into the voltage of the sampling end and outputs the voltage.
Optionally, the sampling unit includes a MOS transistor, and a gate of the MOS transistor is connected to a first voltage, where the first voltage is used to make the MOS transistor operate in a linear region;
the source electrode of the negative feedback switch tube is connected with the drain electrode of the MOS tube, the source electrode of the MOS tube is connected with the negative pressure point, the drain electrode of the MOS tube is used as a sampling end, and the MOS tube converts the detected current into the voltage of the sampling end and outputs the voltage.
Optionally, the current detection circuit further comprises an offset voltage storage circuit;
the offset voltage storage circuit includes: the switching device comprises a first switching tube, a second switching tube, a third switching tube, a biasing unit and a capacitor;
the first end of the bias unit is connected with a second power supply, the second end of the bias unit is connected with the non-inverting input end of the clamping operational amplifier and the drain electrode of the first switching tube, the source electrode of the first switching tube is connected with the first end of the capacitor, and the second end of the capacitor is connected with the inverting input end of the clamping operational amplifier;
the source electrode of the gallium nitride power tube is indirectly connected with the inverting input end of the clamping operational amplifier: the source electrode of the second switching tube and the source electrode of the third switching tube are connected with the source electrode of the gallium nitride power tube, and the drain electrode of the third switching tube is connected with the first end of the capacitor; the drain electrode of the second switching tube is connected with the second end of the capacitor and the inverting input end of the clamping operational amplifier;
the grid electrode of the first switching tube and the grid electrode of the second switching tube are both connected with signals in phase with the control signals of the gallium nitride power tube;
and the grid electrode of the third switching tube is connected with a signal which is opposite to the control signal of the gallium nitride power tube.
Optionally, the bias unit comprises a fourth switching tube and a bias resistor;
the drain electrode of the fourth switching tube is connected with a second power supply, the source electrode of the fourth switching tube is connected with the first end of the bias resistor, and the second end of the bias resistor is connected with the non-inverting input end of the clamping operational amplifier and the drain electrode of the first switching tube;
and the grid electrode of the first switching tube, the grid electrode of the fourth switching tube and the grid electrode of the second switching tube are all connected with signals which are in phase with the control signals of the gallium nitride power tube.
Optionally, the first switching tube, the second switching tube, the third switching tube, the fourth switching tube and the negative feedback switching tube are all enhanced NMOS tubes.
In a second aspect, an embodiment of the present application provides a current detection method of a fully integrated gallium nitride power chip, which is applied to a current detection circuit of the fully integrated gallium nitride power chip in the first aspect, and the current detection method includes:
applying the same control signal to the grid electrode of the gallium nitride power tube and the grid electrode of the gallium nitride detection tube;
and determining the current of the gallium nitride power tube according to the voltages at the two ends of the sampling unit.
Optionally, the current detection circuit further comprises an offset voltage storage circuit;
the offset voltage storage circuit includes: the switching device comprises a first switching tube, a second switching tube, a third switching tube, a biasing unit and a capacitor;
the first end of the bias unit is connected with a second power supply, the second end of the bias unit is connected with the non-inverting input end of the clamping operational amplifier and the drain electrode of the first switching tube, the source electrode of the first switching tube is connected with the first end of the capacitor, and the second end of the capacitor is connected with the inverting input end of the clamping operational amplifier;
the source electrode of the gallium nitride power tube is indirectly connected with the inverting input end of the clamping operational amplifier: the source electrode of the second switching tube and the source electrode of the third switching tube are connected with the source electrode of the gallium nitride power tube, and the drain electrode of the third switching tube is connected with the first end of the capacitor; the drain electrode of the second switching tube is connected with the second end of the capacitor and the inverting input end of the clamping operational amplifier;
the current detection method further comprises the following steps:
when the control signal is at a low level, a high level is applied to the grid electrode of the first switching tube and the grid electrode of the second switching tube, and a low level is applied to the grid electrode of the third switching tube, so that the capacitor stores offset voltages of two input ends of the clamping operational amplifier;
when the control signal is at a high level, a low level is applied to the grid electrode of the first switching tube and the grid electrode of the second switching tube, and a high level is applied to the grid electrode of the third switching tube, so that the capacitor adds stored voltage to the inverting input end of the clamping operational amplifier when the gallium nitride power tube is conducted.
In a third aspect, an embodiment of the present application provides a fully integrated gallium nitride power chip, including the current detection circuit of the first aspect.
Compared with the prior art, the application has the following beneficial effects:
in the current detection circuit for the fully integrated gallium nitride power chip provided by the embodiment of the application, the grid electrodes and the drain electrodes of the gallium nitride power tube and the gallium nitride detection tube are connected with the same potential node, and the negative feedback loop clamps the source electrode potential of the gallium nitride detection tube near the potential of the gallium nitride power tube, namely, the grid electrodes, the source electrode and the drain electrode of the gallium nitride detection tube and the gallium nitride power tube are all kept at the same potential, so that the detection tube can accurately copy the current of the power tube in proportion to realize the accurate detection of the current.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a current detection circuit of a fully integrated gallium nitride power chip according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a current detection circuit in which the sampling resistor in FIG. 1 is replaced with a MOS transistor operating in a linear region;
FIG. 3 is a schematic diagram of a current detection circuit with offset voltage storage circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of the node signal timing in FIG. 3;
FIG. 5 is a schematic diagram illustrating a step of storing offset voltages in FIG. 3;
FIG. 6 is a schematic diagram illustrating the step of discharging the offset voltage in FIG. 3;
FIG. 7 is a schematic diagram of the bias cell of FIG. 3 with the resistor omitted;
FIG. 8 is a schematic diagram of the bias unit of FIG. 3 with transistors omitted;
fig. 9 is a schematic diagram of an overcurrent protection circuit according to an embodiment of the present application;
FIG. 10 is a schematic diagram of a loop cycle-by-cycle peak current control circuit according to an embodiment of the present application;
fig. 11 is a timing diagram of fig. 10 in BCM mode.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application. The following embodiments and features of the embodiments may be combined with each other without conflict.
In the description of the present application, it should be noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The term "coupled" is to be interpreted broadly, as being a fixed connection, a removable connection, or an integral connection, for example; can be directly connected or indirectly connected through an intermediate medium.
The sources of the existing detection tube and power tube are not completely connected in parallel, and the problem of distortion of the detected voltage exists. And the design of the fully integrated gallium nitride power chip is mostly relatively simple, and a scheme of on-chip low-loss accurate current detection is lacked.
In order to realize on-chip accurate detection of current flowing through a gallium nitride power tube, referring to fig. 1, an embodiment of the present application provides a current detection circuit for a fully integrated gallium nitride power chip (a fully integrated gallium nitride power chip may also be referred to as a fully integrated gallium nitride power driving chip), where the current detection circuit is integrated on the fully integrated gallium nitride power chip through a fully integrated gallium nitride process (All-GaN process), and the current detection circuit includes: gallium nitride detection tube Sense HEMT and negative feedback loop. The Power HEMT of the gallium nitride Power tube and the Sense HEMT of the gallium nitride detection tube have proportional width-to-length ratios so as to ensure that the Sense HEMT of the gallium nitride detection tube can copy the current of the Power HEMT of the gallium nitride Power tube in proportion (1/n I in the figure) D Merely to the scale of illustration). The negative feedback loop comprises a clamping operational amplifier U1, a negative feedback switching tube M0, a sampling unit U22 and a negative voltage stabilizer U21. Has the following connection relation:
the drain electrode of the gallium nitride detection tube sensor HEMT is connected with the drain electrode of the gallium nitride Power tube Power HEMT, the grid electrode of the gallium nitride detection tube sensor HEMT is connected with the grid electrode of the gallium nitride Power tube Power HEMT, the source electrode of the gallium nitride detection tube sensor HEMT is connected with the in-phase input end of the clamping operational amplifier U1, the source electrode of the gallium nitride Power tube Power HEMT is connected with the anti-phase input end of the clamping operational amplifier U1, the output end of the clamping operational amplifier U1 is connected with the grid electrode of the negative feedback switch tube M0, the drain electrode of the negative feedback switch tube M0 is connected with the source electrode of the gallium nitride detection tube sensor HEMT, the source electrode of the negative feedback switch tube M0 is connected with the first end of the sampling unit U22, the second end of the sampling unit U22 is connected with the negative pressure end of the negative pressure regulator U21, the positive pressure end of the negative pressure regulator U21 is connected with the first Power VCC, and the reference end of the negative pressure regulator U21 is connected with the source electrode of the gallium nitride Power tube Power HEMT.
The grey framed area in the figure may be provided on a gallium nitride integrated chip, which refers to a monolithic chip based on a GaN-on-SOI process or other gallium nitride integrated process. Box X (VCC, S, D, V) in the figure SENSE Box X) beside the isocode indicates a PAD (interface) that can be connected off-chip as an external port of the chip.
The device of the gray area in the figure may also be partly set up on another chip and then the bond connection, for example the gray area in the figure also comprises a power drive circuit U0, the power drive circuit U0 may also be set up on another chip.
Next, taking fig. 1 as an example, the working principle of the current detection circuit will be described:
1. the power driving circuit U0 is used for driving the power driving circuit according to the signal source V PWM And outputting a control signal to the grid electrode of the Power HEMT of the gallium nitride Power tube and the grid electrode of the Sense HEMT of the gallium nitride detection tube, wherein the control signal has enough driving current to enable the Power HEMT of the gallium nitride Power tube to be rapidly turned on or turned off. The grid electrode and the drain electrode of the Power HEMT of the gallium nitride Power tube and the grid electrode of the Sense HEMT of the gallium nitride detection tube are connected with the same potential node and have proportional width-to-length ratio so as to ensure that the detection tube can copy the current of the Power tube in proportion. The clamping operational amplifier U1 controls the on-off of the negative feedback switch tube M0 according to the voltage difference between the source electrode (X node) of the gallium nitride detection tube Sense HEMT and the source electrode (S node) of the gallium nitride Power tube Power HEMT, so as to form a negative feedback loop: when the source voltage of the gallium nitride detection tube Sense HEMT is too high, the negative feedback switch tube M0 is turned on to reduce the source voltage of the gallium nitride detection tube Sense HEMT. The S node to the X node form a unity gain feedback, the X node potential being clamped around the S node potential.
2. According to the conditions, the grid electrode, the source electrode and the drain electrode of the Power HEMT of the gallium nitride Power tube and the grid electrode, the source electrode and the drain electrode of the sensor HEMT of the gallium nitride detection tube are all kept at the same potential, so that the detection tube can accurately copy the current of the Power tube in proportion, and accurate detection of the current is realized.
3. In fig. 1, the voltage in brackets is a relative potential using the negative voltage end of the negative voltage regulator U21 as a 0V reference potential, and the voltage marked outside brackets is a relative potential when the S node is used as the 0V reference potential, that is, the source electrode of the gallium nitride Power tube Power HEMT is used as the 0V reference potential, and the S node is grounded. The negative voltage stabilizer U21 converts external positive voltage into on-chip equivalent negative voltage by utilizing the isolation characteristic of the GaN-on-SOI process so as to ensure the normal operation of the negative feedback switch tube M0 and enable the negative feedback switch tube M to pass through the sampling resistor R SENSE The current flowing through the detection tube is subjected to current-voltage conversion.
Fig. 1 illustrates an example in which the sampling unit U11 includes a sampling resistor R SENSE . FIG. 2 shows an alternative embodiment in which the sampling unit U22 comprises a MOS transistor having a gate connected to a first voltage V b The first voltage V b For operating the MOS transistor in a linear region. Similar to the sampling resistor R SENSE The source electrode of the negative feedback switch tube M0 is connected with the source electrode of the MOS tube, the drain electrode of the MOS tube is connected with the negative pressure point, and the source electrode of the MOS tube is used as a sampling end and used for providing voltage to detect the current of the Power HEMT of the gallium nitride Power tube.
Fig. 1 illustrates an example in which the negative voltage terminal of the negative voltage regulator U21 provides a potential lower than the source potential of the Power HEMT of the gallium nitride Power tube to turn on the negative feedback loop. In an alternative way, the negative pressure regulator U21 may be removed, and a negative pressure external port is disposed on the fully integrated gallium nitride power chip, and the second end of the sampling unit U22 is connected to the negative pressure external port.
In the embodiments shown in fig. 1 and 2, due to the defects of the fully integrated gallium nitride process, a problem of offset of the clamping operational amplifier may occur, and the offset of the clamping operational amplifier may cause the gate-source voltage of the gallium nitride detection tube to deviate from the desired gate-source voltage of the gallium nitride power tube, so that the accuracy of current detection is reduced. FIG. 3Embodiments for solving the clamping operational amplifier offset problem are shown, and the current detection circuit further comprises an offset voltage storage circuit U30. Specifically, offset voltage storage circuit U30 may include: first switch tube M 1 Second switch tube M 2 Third switch tube M 3 Fourth switching tube M dummy Bias resistor R dummy And capacitor C AZ 。
First switch tube M 1 Second switch tube M 2 Third switch tube M 3 Fourth switching tube M dummy And the negative feedback switching transistor M0 may be an enhanced NMOS transistor. One of the innovation points of the circuit is that the current circuit is designed under the condition of no PMOS, and the circuit is suitable for the fully integrated gallium nitride technology.
According to fig. 3, there is the following connection relationship:
fourth switching tube M dummy The drain electrode of the fourth switch tube M is connected with the second power supply VDD dummy Is connected with a bias resistor R dummy Is a first end of a bias resistor R dummy The second end of the (C) is connected with the non-inverting input end of the clamping operational amplifier U1 and the first switching tube M 1 Drain electrode of the first switch tube M 1 Source connection capacitor C of (2) AZ Capacitor C AZ The second end of the clamping operational amplifier U1 is connected with the inverting input end of the clamping operational amplifier U;
third switch tube M 3 Drain electrode connection capacitor C AZ A third switch tube M 3 The source electrode of the Power HEMT of the gallium nitride Power tube is connected with the source electrode of the Power HEMT of the gallium nitride Power tube;
second switch tube M 2 Drain electrode connection capacitor C AZ A second switch tube M 2 Is connected with the source of the Power HEMT of the gallium nitride Power tube (in the scheme of FIG. 3, the source of the Power HEMT of the gallium nitride Power tube is connected with the source of the Power HEMT of the gallium nitride Power tube through a second switch tube M 2 Indirectly connected to the inverting input of the clamp op-amp U1) rather than directly connected).
First switch tube M 1 Gate of (d), fourth switching tube M dummy Gate of (2) and second switching tube M 2 The grid electrodes of the Power HEMT are connected with a signal V which is in phase with the control signal of the Power HEMT of the gallium nitride AZ ；
Third switch tube M 3 A signal V which is opposite to the control signal of the Power HEMT of the gallium nitride Power tube is connected with the grid electrode SEN 。
Next, the operation principle of the offset voltage storage circuit will be described with reference to fig. 4 to 6. Fig. 4 shows the driving voltage V of the gan power tube G Signal V AZ Signal V SEN Clamping voltage V at X node CLAMP Current I of GaN power tube D Resistance R SENSE First end voltage V SENSE Is a timing chart of (a):
1. driving voltage V of GaN power tube G When the voltage is low, no large current flows in the gallium nitride power tube, V AZ At high level, V SEN At low level, the circuit is in auto-zero state, as shown in FIG. 5, M dummy ，M 1 And M 2 Conduction, M 3 The offset voltage between the two input ends of the operational amplifier is stored in the capacitor C AZ (as indicated by the dashed arrow).
2. Driving voltage V of GaN power tube G When the voltage jumps to a high level, the gallium nitride detection tube and the gallium nitride power tube are both conducted, V AZ At low level, V SEN At a high level, the circuit enters a current sense state, as shown in FIG. 6, M dummy ，M 1 And M 2 Shut off, M 3 Turned on, the offset voltage stored in the previous state is reversely added to the op-amp input (as indicated by the dashed arrow) and the clamping voltage V at the X node CLAMP Is reduced to about 0V, which is the potential of the S node, to offset the offset of the op-amp itself.
That is, the present solution utilizes the on-chip capacitance C AZ The possible offset voltage is stored and corrected to solve the operational amplifier offset problem, and the gallium nitride detection tube can accurately copy the gallium nitride power tube current I in proportion D Accurate detection of current is achieved.
As can be further seen from fig. 1 and 3, the voltages of the first power source VCC and the second power source VDD may be different, and VDD may be 5-6V to supply power to the power driving circuit. According to the reference end 0V of the negative voltage stabilizer, the negative voltage stabilizer can stabilize VCC at 16V, and VCC can supply power for the simultaneous clamping operational amplifier.
In the example of FIG. 3, a fourth switching tube M dummy And bias resistor R dummy Acting to provide operating voltage, the fourth switching tube M dummy And bias resistor R dummy A bias unit U31 is formed. The biasing unit U31 may also be implemented by other embodiments, such as:
1. the bias unit U31 may have only one transistor, e.g. only the fourth switching transistor M dummy And bias resistor R dummy Omitted, as in fig. 7, it may be necessary to make the transistor have a sufficient withstand voltage by an appropriate process at this time;
2. the bias unit U31 can have only one bias resistor R dummy Fourth switch tube M dummy Omitted as in fig. 8.
Based on the current detection circuit, the embodiment of the application also provides a current detection method of the fully integrated gallium nitride power chip, which is applied to the current detection circuit and comprises the following steps:
applying the same control signal to the grid electrode of the Power HEMT of the gallium nitride Power tube and the grid electrode of the Sense HEMT of the gallium nitride detection tube;
according to the sampling resistance R SENSE And the voltage at two ends determines the current of the Power HEMT of the gallium nitride Power tube.
Further, in the case where the current detection circuit includes an offset voltage storage circuit, the same control signal is applied to the gate of the switching transistor in the offset voltage storage circuit while the same control signal is applied to the gate of the gallium nitride Power transistor Power HEMT and the gate of the gallium nitride detection transistor Sense HEMT:
when the control signal is at low level, the first switch tube M 1 Gate of (d), fourth switching tube M dummy Gate of (2) and second switching tube M 2 Applying a high level to the gate of the third switch tube M 3 Applying a low level to the gate of (2) to cause a capacitance C AZ Storing offset voltages of two input ends of the clamping operational amplifier U1;
when the control signal is at high level, the first switch tube M 1 Gate electrode of (iv)Switch tube M dummy Gate of (2) and second switching tube M 2 Applying a low level to the gate of the third switch tube M 3 Applying a high level to the gate of (2) to cause the capacitance C to AZ And when the Power HEMT of the gallium nitride Power tube is conducted, the stored voltage is added to the inverting input end of the clamping operational amplifier U1.
Fig. 9 shows an embodiment of applying the above-mentioned current detection circuit to an overcurrent protection circuit, in which a blanking circuit U40, a comparator U50, a logic control module U60, and a power driving circuit U0 are connected in this order, which may be integrated with the current detection circuit in a single chip. The working principle is as follows:
using R in a current sense circuit SENSE Obtaining a current detection voltage V SENSE After deburring by the blanking circuit U40, the voltage is compared with the on-chip reference voltage V REF The comparison is performed by a comparator U50. When V is SENSE Exceeding V REF When the Power HEMT current of the gallium nitride Power tube exceeds the preset value, the comparator U50 outputs an enabling signal, and the logic module U40 controls the Power driving circuit U0 to enable the Power driving circuit U0 to output to be in a low level, so that the gallium nitride Power tube stops working. When V is SENSE Normally, i.e. not exceeding V REF When the circuit is in a normal working state.
Fig. 10 shows an embodiment of the above-described current detection circuit applied to a loop cycle-by-cycle peak current control circuit, in which there are a blanking circuit U40, a comparator U50, a latch U60, and a power driving circuit U0, which may be integrated with the current detection circuit in a single chip, connected in this order. The working principle is as follows:
the acquired voltage V SENSE After deburring by the blanking circuit U40, the reference voltage V is obtained by the comparator U50 REF Comparing, the output voltage of the blanking circuit is greater than V REF At this time, the comparator U50 outputs a falling edge of the trigger latch output terminal Q, thereby adjusting the pulse width. The rising edge of the latch output Q is provided by a fixed clock CLK, as shown in fig. 11. Voltage V output by latch output terminal Q Q Is used as a PWM signal and provided to a Power driving circuit U0 to finally determine a gallium nitride Power tube Power HEThe on time of MT in each cycle. In the embodiment, the ratio of the width to length ratio of the gallium nitride power tube to the gallium nitride detection tube and R are arranged in the chip SENSE The peak inductor current is limited to a fixed value by the resistance value and the off-chip set reference voltage. In particular, when the BUCK topology is operating in BCM (Boundary Conduction Mode ) mode, the output current I LOAD Equal to half the peak inductor current.
Based on the current detection circuit, the embodiment of the application also provides a fully-integrated gallium nitride power chip, which can comprise any one of the current detection circuit, the overcurrent protection circuit or the loop cycle-by-cycle peak current control circuit.
In general, the application provides a current detection circuit for a fully integrated gallium nitride power chip, which utilizes an on-chip negative voltage regulator to realize negative voltage in the chip and utilizes the on-chip negative voltage regulator to supply power for a clamping operational amplifier, and utilizes a feedback loop formed by the clamping operational amplifier and a gallium nitride detection tube to clamp the source electrode potential of the gallium nitride detection tube near the source electrode potential of the gallium nitride power tube, thereby realizing accurate current detection, simultaneously accurately detecting the current flowing through the gallium nitride power tube on the premise of low power loss, and solving the problems of high current detection loss and inaccurate detection by utilizing the gallium nitride detection tube. In addition, for the possible serious mismatch condition of the processing technology, an automatic zeroing scheme is adopted to reduce the offset voltage of the operational amplifier. The circuit structure can be applied to various power chip circuit modules requiring current detection, such as over-current protection, peak current control and other functional modules, and provides conditions for carrying more intelligent gallium nitride on-chip functional modules.
The above-described embodiments of the apparatus and system are merely illustrative, and some or all of the modules may be selected according to actual needs to achieve the objectives of the present embodiment. Those of ordinary skill in the art will understand and implement the present application without undue burden.
The foregoing is only a preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the technical scope of the present application should be covered by the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims (10)
1. A current detection circuit of a fully integrated gallium nitride Power chip, which is used for detecting the current of a gallium nitride Power tube (Power HEMT); the current detection circuit is integrated on a fully-integrated gallium nitride power chip through a fully-integrated gallium nitride process, and comprises: a gallium nitride Sense tube (Sense HEMT) and a negative feedback loop;
the gallium nitride Power tube (Power HEMT) and the gallium nitride detection tube (Sense HEMT) have proportional width-to-length ratios so as to ensure that the gallium nitride detection tube (Sense HEMT) can copy the current of the gallium nitride Power tube (Power HEMT) in proportion;
the negative feedback loop comprises a clamping operational amplifier (U1), a negative feedback switching tube (M0) and a sampling unit (U22);
the drain electrode of the gallium nitride detection tube (Sense HEMT) is connected with the drain electrode of the gallium nitride Power tube (Power HEMT), the grid electrode of the gallium nitride detection tube (Sense HEMT) is connected with the grid electrode of the gallium nitride Power tube (Power HEMT), the source electrode of the gallium nitride detection tube (Sense HEMT) is connected with the in-phase input end of the clamping operational amplifier (U1), the source electrode of the gallium nitride Power tube (Power HEMT) is connected with the inverting input end of the clamping operational amplifier (U1), the output end of the clamping operational amplifier (U1) is connected with the grid electrode of the negative feedback switch tube (M0), the drain electrode of the negative feedback switch tube (M0) is connected with the source electrode of the gallium nitride detection tube (Sense HEMT), the source electrode of the negative feedback switch tube (M0) is connected with the first end of the sampling unit (U22), and the second end of the sampling unit (U22) is connected with a negative pressure point which is used for providing a negative return voltage lower than the potential of the gallium nitride Power tube (Power HEMT) to conduct the negative feedback path.
2. The current detection circuit according to claim 1, further comprising a negative voltage regulator (U21), wherein a positive voltage terminal of the negative voltage regulator (U21) is connected to a first Power supply (VCC), and a reference terminal of the negative voltage regulator (U21) is connected to a source of the gallium nitride Power tube (Power HEMT); the negative voltage terminal of the negative voltage regulator (U21) is used for providing a potential lower than the potential of the reference terminal of the negative voltage regulator (U21).
3. A current detection circuit according to claim 1, wherein the sampling unit (U22) comprises a sampling resistor (R SENSE )；
The source electrode of the negative feedback switch tube (M0) is connected with the sampling resistor (R SENSE ) Is arranged at the first end of the sampling resistor (R SENSE ) The second end of the first electrode is connected with the negative pressure point;
the sampling resistor (R SENSE ) As a sampling end, the sampling resistor (R SENSE ) And converting the detected current into the voltage of the sampling end and outputting the voltage.
4. A current detection circuit according to claim 1, wherein the sampling unit (U22) comprises a MOS transistor having a gate connected to a first voltage (V b ) The first voltage is used for enabling the MOS tube to work in a linear region;
the source electrode of the negative feedback switch tube (M0) is connected with the drain electrode of the MOS tube, the source electrode of the MOS tube is connected with the negative pressure point, the drain electrode of the MOS tube is used as a sampling end, and the MOS tube converts the detected current into the voltage of the sampling end and outputs the voltage.
5. The current detection circuit according to claim 1, further comprising an offset voltage storage circuit (U30);
the offset voltage storage circuit (U30) includes: first switch tube (M) 1 ) Second switch tube (M) 2 ) Third switch tube (M) 3 ) A bias unit (U31) and a capacitor (C) AZ )；
The first end of the bias unit (U31) is connected with a second power supply (VDD), and the second end of the bias unit (U31) is connected withIs connected to the non-inverting input of the clamping operational amplifier (U1) and the first switching tube (M) 1 ) Is connected with the drain electrode of the first switch tube (M 1 ) Is connected to the source of the capacitor (C AZ ) Is arranged between the first end of the capacitor (C AZ ) The second end of the clamping operational amplifier (U1) is connected with the inverting input end of the clamping operational amplifier;
the source electrode of the gallium nitride Power tube (Power HEMT) is indirectly connected with the inverting input end of the clamping operational amplifier (U1): the second switching tube (M 2 ) And the source of the third switching tube (M 3 ) Is connected to the source of the gallium nitride Power tube (Power HEMT), the third switching tube (M 3 ) Is connected to the drain of the capacitor (C AZ ) Is a first end of (2); the second switching tube (M 2 ) Is connected to the drain of the capacitor (C AZ ) And an inverting input of the clamping op-amp (U1);
the first switching tube (M 1 ) And the gate of the second switching tube (M 2 ) The gates of the Power HEMT are connected with signals in phase with control signals of the gallium nitride Power tube (Power HEMT);
the third switching tube (M 3 ) Is connected with a signal which is opposite to the control signal of the gallium nitride Power tube (Power HEMT).
6. A current detection circuit according to claim 5, wherein the biasing unit (U31) comprises a fourth switching tube (M dummy ) And bias resistor (R) dummy )；
The fourth switching tube (M dummy ) Is connected to the second power supply (VDD), the fourth switching tube (M dummy ) Is connected to the source of the bias resistor (R dummy ) Is arranged at the first end of the bias resistor (R dummy ) Is connected to the non-inverting input of the clamping operational amplifier (U1) and the first switching tube (M) 1 ) A drain electrode of (2);
the first switching tube (M 1 ) Is connected to the gate of the fourth switching tube (M dummy ) And the gate of the second switching tube (M 2 ) The gates of the Power transistors are connected with signals which are in phase with the control signals of the gallium nitride Power transistors (Power HEMTs).
7. The current detection circuit according to claim 6, wherein the first switching tube (M 1 ) Said second switching tube (M 2 ) Said third switching tube (M 3 ) Said fourth switching tube (M dummy ) And the negative feedback switch tube (M0) is an enhanced NMOS tube.
8. A current detection method of a fully integrated gallium nitride power chip, characterized by being applied to the current detection circuit of a fully integrated gallium nitride power chip according to any one of claims 1 to 7, the current detection method comprising:
applying the same control signal to the grid electrode of the gallium nitride Power tube (Power HEMT) and the grid electrode of the gallium nitride detection tube (Sense HEMT);
and determining the current of the gallium nitride Power tube (Power HEMT) according to the voltage of the two ends of the sampling unit (U22).
9. The current detection method according to claim 8, wherein the current detection circuit further comprises an offset voltage storage circuit (U30);
the offset voltage storage circuit (U30) includes: first switch tube (M) 1 ) Second switch tube (M) 2 ) Third switch tube (M) 3 ) A bias unit (U31) and a capacitor (C) AZ )；
A first end of the bias unit (U31) is connected with a second power supply (VDD), a second end of the bias unit (U31) is connected with a non-inverting input end of the clamping operational amplifier (U1) and the first switch tube (M) 1 ) Is connected with the drain electrode of the first switch tube (M 1 ) Is connected to the source of the capacitor (C AZ ) Is arranged between the first end of the capacitor (C AZ ) The second end of the clamping operational amplifier (U1) is connected with the inverting input end of the clamping operational amplifier;
the source electrode of the gallium nitride Power tube (Power HEMT) is indirectly connected with the inverting input end of the clamping operational amplifier (U1): the second switching tube (M 2 ) And the source of the third switching tube (M 3 ) Is connected to the source of the GaN power tube (Power HEMT), the third switching tube (M 3 ) Is connected to the drain of the capacitor (C AZ ) Is a first end of (2); the second switching tube (M 2 ) Is connected to the drain of the capacitor (C AZ ) And an inverting input of the clamping op-amp (U1);
the current detection method further comprises the following steps:
when the control signal is low, the control signal is applied to the first switching tube (M 1 ) And the gate of the second switching tube (M 2 ) Is applied with a high level at the gate of the third switching tube (M 3 ) Is applied low to the gate of the capacitor (C AZ ) Storing offset voltages of two input ends of the clamping operational amplifier (U1);
when the control signal is high, the control signal is applied to the first switching tube (M 1 ) And the gate of the second switching tube (M 2 ) Is applied low at the gate of the third switching tube (M 3 ) Is applied high to the gate of the capacitor (C AZ ) And adding the stored voltage to the inverting input end of the clamping operational amplifier (U1) when the gallium nitride Power tube (Power HEMT) is conducted.
10. A fully integrated gallium nitride power chip comprising the current detection circuit of any one of claims 1-7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311169822.8A CN117192320A (en) | 2023-09-08 | 2023-09-08 | Current detection circuit and method for fully-integrated gallium nitride power chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311169822.8A CN117192320A (en) | 2023-09-08 | 2023-09-08 | Current detection circuit and method for fully-integrated gallium nitride power chip |
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| CN (1) | CN117192320A (en) |
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