CN117178253A

CN117178253A - Floating point number calculating circuit and floating point number calculating method

Info

Publication number: CN117178253A
Application number: CN202180096895.1A
Authority: CN
Inventors: 毛伟; 余浩; 谢环; 董镇江
Original assignee: Huawei Technologies Co Ltd; Southwest University of Science and Technology
Current assignee: Huawei Technologies Co Ltd; Southwest University of Science and Technology
Priority date: 2021-08-31
Filing date: 2021-08-31
Publication date: 2023-12-05
Also published as: WO2023028884A1

Abstract

A floating point number calculating circuit, a floating point number calculating method and a calculating device are provided, wherein the calculating circuit in the floating point number calculating circuit can select and output partial data in a plurality of first operation results to obtain a plurality of first addition data and a plurality of second addition data. The computing circuit splits a plurality of first operation results with higher digits into a plurality of first addition data with lower digits and a plurality of second addition data with lower digits by selecting part of data in the first operation results, and further sums the plurality of first addition data with lower digits, the plurality of second addition data and the plurality of first operation results through an adder with smaller digits to obtain the product of the first mantissa and the second mantissa. The bit width of the adder adopted when the product of the mantissa parts of the first floating point number and the second floating point number is calculated is small, the hardware design cost is low, and the technical popularization is facilitated.

Description

Floating point number calculating circuit and floating point number calculating method

Technical Field

The embodiment of the application relates to the field of computers, in particular to an artificial intelligence (artificial intelligence, AI) technology application in the field of computers, and particularly relates to a floating point number calculation circuit and a floating point number calculation method.

Background

Artificial intelligence (Artificial Intelligence, AI) is the theory, method, technique and application system that uses a digital computer or a machine controlled by a digital computer to simulate, extend and extend human intelligence, sense the environment, acquire knowledge and use the knowledge to obtain optimal results. In other words, artificial intelligence is a branch of computer science that attempts to understand the essence of intelligence and to produce a new intelligent machine that can react in a similar manner to human intelligence. Artificial intelligence, i.e. research on design principles and implementation methods of various intelligent machines, enables the machines to have functions of sensing, reasoning and decision. Research in the field of artificial intelligence includes robotics, natural language processing, computer vision, decision and reasoning, man-machine interaction, recommendation and search, AI-based theory, and the like.

Convolutional neural networks (convolution neural network, CNN) are currently widely used in various types of image processing applications, and when a model is trained by using Floating Point (FP) 16 data, the FP16 data has insufficient precision, which can cause the network training to be not converged or have low convergence speed, so that the FP32 data with higher precision needs to be used to ensure the network training effect. Furthermore, in the supercomputing application, it is necessary to use FP64 data of higher accuracy for numerical calculation.

In the existing data calculation scheme, a multiplier with a smaller bit number can be used for calculating a floating point number with a larger bit number. For example, FP64 type floating point data may be calculated by a multiplier for calculating FP32 data. The network equipment divides the floating point data of the FP64 type into floating point numbers with smaller digits and then performs multiplication operation, and then adds the result after the multiplication operation through an adder to obtain the product of the floating point data of the FP64 type. In the traditional calculation mode, the number of bits of the adder required for adding the multiplication results is large, the hardware design cost is high, and the technical popularization is not facilitated.

Disclosure of Invention

The embodiment of the application provides a floating point number calculating circuit and a floating point number calculating method, wherein the floating point number calculating circuit can split a floating point number with a larger bit number into a floating point number with a smaller bit number, so that the floating point number calculating circuit has short time sequence cost and low hardware design cost, and reasonably utilizes the calculating performance of a multiplier.

The first aspect of the present application provides a floating point number calculation circuit for calculating a product of a first floating point number including a first exponent and a first mantissa and a second floating point number including a second exponent and a second mantissa, the floating point number calculation circuit comprising: an exponent processing circuit and a calculation circuit; the output end of the index processing circuit is electrically connected with the input end of the calculating circuit; the exponent processing circuit is configured to obtain a first shift number according to the first exponent and the second exponent, where the first shift number is used to represent a shift number of a product between a first split mantissa and a second split mantissa, the first split mantissa is obtained by splitting the first mantissa, and the second split mantissa is obtained by splitting the second mantissa; the computing circuit is used for selectively outputting partial data in a plurality of first operation results to obtain a plurality of first addition data and a plurality of second addition data, obtaining products of the first mantissas and the second mantissas according to the plurality of first addition data, the plurality of second addition data and the plurality of first operation results, and the first operation results are used for representing the data obtained after the products of the first split mantissas and the second split mantissas are shifted according to the first shift number.

In the application, the calculation circuit in the floating point number calculation circuit can select and output partial data in a plurality of first operation results to obtain a plurality of first addition data and a plurality of second addition data. The computing circuit splits a plurality of first operation results with higher digits into a plurality of first addition data with lower digits and a plurality of second addition data with lower digits by selecting part of data in the first operation results, and further sums the plurality of first addition data with lower digits, the plurality of second addition data and the plurality of first operation results through an adder with smaller digits to obtain the product of the first mantissa and the second mantissa. The bit width of the adder adopted when the product of the mantissa parts of the first floating point number and the second floating point number is calculated is small, the hardware design cost is low, and the technical popularization is facilitated.

In a possible implementation manner of the first aspect, the computing circuit includes a multiplying circuit, an adding circuit, and a first selecting circuit; the output end of the exponent processing circuit is electrically connected with the input end of the multiplying circuit; the input end of the first selection circuit is electrically connected with the output end of the multiplication circuit, and the output end of the first selection circuit is electrically connected with the input end of the addition circuit; the first selection circuit is used for selecting and outputting low-order data in a plurality of first operation results to obtain a plurality of first addition data, and selecting and outputting high-order data in a plurality of first operation results to obtain a plurality of second addition data; the addition circuit is configured to add the plurality of first addition data and the plurality of first operation results to obtain a low-order addition result and carry data, add the plurality of carry data, the plurality of second addition data and the plurality of first operation results to obtain a high-order addition result, and add the high-order addition result and the low-order addition result to obtain a product of the first mantissa and the second mantissa.

In this possible implementation manner, after the multiplication circuit outputs the plurality of first operation results, the first selection circuit may select to output low-order data in the plurality of first operation results to obtain a plurality of first addition data, and select to output high-order data in the plurality of first operation results to obtain a plurality of second addition data. The first selection circuit may split the first operation result with a larger number of bits into first addition data and second addition data with a smaller number of bits. And further, the first addition data and the second addition data are respectively summed with the corresponding first operation result to obtain a low-order addition result and a high-order addition result. Because the bit width of the low-order addition result and the high-order addition result is smaller, the bit width of an adder used for calculating the low-order addition result and the high-order addition result is smaller, and the construction cost of a calculation circuit is reduced.

In a possible implementation manner of the first aspect, the adding circuit includes a first adder and an accumulator; the input end of the first adder is electrically connected with the output end of the first selection circuit, and the output end of the first adder is electrically connected with the input end of the accumulator; the first adder is configured to add the plurality of first addition data and the plurality of first operation results in a first calculation cycle to obtain the lower addition result and the carry data, and add the plurality of carry data, the plurality of second addition data and the plurality of first operation results in a second calculation cycle to obtain the higher addition result; and the accumulator is used for accumulating the low-order addition result and the high-order addition result to obtain the product of the first mantissa and the second mantissa.

In this possible implementation, the mantissa portion length is 53 bits due to the floating point number of FP64 type. Thus, the total length number of mantissa portions obtained after calculation of a_mantissa is 106 bits. If the calculation of the mantissa portion of a pair of FP64 type floating point numbers is to be directly completed in one calculation unit (PE unit), the order (first adder) needs to be expanded into an adder supporting data calculation with a length of 106 bits, and the area cost and the time sequence cost of the order after the order is expanded are too high. Therefore, the multiplication of mantissa of the pair FP64 may be split into two parts (part 1 and part 2) by the first selection circuit, the first adder calculating part1 in the first calculation period to obtain the low-order addition result, and calculating part2 in the second period to obtain the high-order addition result. The accumulator accumulates the results obtained in the two calculation periods to obtain the product of the first mantissa and the second mantissa. Because the bit width of the low-order addition result and the high-order addition result is smaller, the bit width of an adder used for calculating the low-order addition result and the high-order addition result is smaller, and the construction cost of the floating point number calculation circuit is reduced.

In a possible implementation manner of the first aspect, the floating point number calculation circuit further includes a splitting circuit; the output end of the splitting circuit is electrically connected with the input end of the exponent processing circuit and the input end of the multiplying circuit; the splitting circuit is configured to split the first mantissa into the first split mantissa, the first split mantissa includes a first high-order mantissa and a first low-order mantissa, split the second mantissa into the second split mantissa, the second split mantissa includes a second high-order mantissa and a second low-order mantissa, and the first shift number is used to indicate a shift difference value between a highest position of each high-order mantissa and a highest position of each low-order mantissa.

In the possible implementation manner, the floating point number calculation circuit provided by the application can split the mantissa part with larger number of the first floating point number into the first high-order mantissa with smaller number of bits and the first low-order mantissa, and split the mantissa part with larger number of the second floating point number into the second high-order mantissa with smaller number of bits and the second low-order mantissa, so that the product of each mantissa part after the split is calculated by adopting the multiplier with smaller number of bits, the design cost of hardware is reduced, and the calculation performance of the multiplier is reasonably utilized.

In a possible implementation manner of the first aspect, the first high-order mantissa includes a third mantissa, the first low-order mantissa includes a fourth mantissa, a fifth mantissa, a sixth mantissa, and a seventh mantissa, the second high-order mantissa includes an eighth mantissa, and the second low-order mantissa includes a ninth mantissa, a tenth mantissa, an eleventh mantissa, and a twelfth mantissa.

In this possible implementation manner, a specific splitting manner is provided for the first mantissa and the second mantissa, after the mantissa portion of the FP64 type floating point number is split by using this splitting manner, the calculation may be performed by using the FP32 type multiplier, and after the mantissa portion of the FP128 type floating point number is split by using this splitting manner, the calculation may be performed by using the FP64 type multiplier. The splitting mode can realize that a multiplier with a smaller bit number is adopted to calculate the product of the first mantissa and the second mantissa. The construction cost of the floating point number calculation circuit is reduced, and the technology popularization is facilitated.

In a possible implementation manner of the first aspect, the floating point number calculation circuit further includes a storage circuit; the output end of the splitting circuit is electrically connected with the input end of the storage circuit; the input end of the index processing circuit is electrically connected with the first output end of the storage circuit; the input end of the computing circuit is electrically connected with the second output end of the storage circuit; the storage circuit is configured to store the first split mantissa, the second split mantissa, the first exponent, the second exponent, a third shift number and a fourth shift number, where the third shift number is used to represent the shift number of the first split mantissa, and the fourth shift number is used to represent the shift number of the second split mantissa.

The possible implementation manner provides a specific implementation manner for storing temporary data in the floating point number computing circuit, so that the feasibility of the scheme is improved.

In a possible implementation manner of the first aspect, the exponent processing circuit includes a second adder, a second selection circuit, and a third adder; the input end of the second adder is electrically connected with the first output end of the storage circuit, and the output end of the second adder is electrically connected with the first input end of the third adder; the second input end of the third adder is electrically connected with the output end of the second selection circuit, and the output end of the third adder is electrically connected with the first input end of the calculation circuit; the second adder is configured to add the first exponent, the second exponent, the third shift count, and the fourth shift count to obtain a plurality of second operation results; the second selection circuit is used for selecting the maximum value in a plurality of second operation results; and the third adder is used for subtracting the maximum value in the plurality of second operation results from each second operation result to obtain the first shift number.

The possible implementation mode provides a specific implementation mode of the exponent processing circuit, and the feasibility of the scheme is improved.

In a possible implementation manner of the first aspect, the multiplication circuit includes a multiplier and a shift register; the input end of the multiplier is electrically connected with the second output end of the storage circuit, and the output end of the multiplier is electrically connected with the first input end of the shift register; the second input end of the shift register is electrically connected with the output end of the third adder; the output end of the shift register is electrically connected with the input end of the first adder; the multiplier is used for multiplying the first split mantissa and the second split mantissa to obtain a plurality of third operation results; the shift register is used for carrying out shift processing on the third operation results according to the first shift numbers to obtain the first operation results.

This possible implementation provides a specific implementation form of the multiplication circuit, which improves the feasibility of the scheme.

In a possible implementation manner of the first aspect, the floating point number computing circuit further includes a memory controller; the output end of the memory controller is electrically connected with the input end of the splitting circuit; the memory controller is configured to obtain the first floating point number and the second floating point number, and send the first floating point number and the second floating point number to the splitting circuit.

The possible implementation manner provides a specific implementation manner of a hardware structure capable of acquiring the first floating point number and the second floating point number, and the feasibility of the scheme is improved.

In a possible implementation manner of the first aspect, the first floating point number further includes a first sign bit, and the second floating point number further includes a second sign bit.

The second aspect of the present application provides a floating point number calculation method for calculating a product of a first floating point number and a second floating point number, the first floating point number including a first exponent and a first mantissa, the second floating point number including a second exponent and a second mantissa, the method comprising: obtaining a first shift number according to the first exponent and the second exponent, wherein the first shift number is used for representing the shift number of the product between a first split mantissa and a second split mantissa, the first split mantissa is obtained by splitting the first mantissa, and the second split mantissa is obtained by splitting the second mantissa; and selecting and outputting partial data in a plurality of first operation results to obtain a plurality of first addition data and a plurality of second addition data, acquiring products of the first mantissas and the second mantissas according to the plurality of first addition data, the plurality of second addition data and the plurality of first operation results, wherein the first operation results are used for representing the data obtained by shifting the products of the first split mantissas and the second split mantissas according to the first shift number.

In the floating point number calculation method provided by the application, partial data in a plurality of first operation results can be selectively output to obtain a plurality of first addition data and a plurality of second addition data. The method includes that a plurality of first operation results with higher bit numbers are split into a plurality of first addition data with lower bit numbers and a plurality of second addition data by selecting part of data in the first operation results, and then the plurality of first addition data with lower bit numbers, the plurality of second addition data and the plurality of first operation results are summed through an adder with smaller bit width, so that the product of a first mantissa and a second mantissa can be obtained. The bit width of the adder adopted when the product of the mantissa parts of the first floating point number and the second floating point number is calculated is small, the hardware design cost is low, and the technical popularization is facilitated.

In the application, when the product of the first mantissa and the second mantissa is calculated, part of data in a plurality of first operation results can be selected and output to obtain a plurality of first addition data and a plurality of second addition data. The method includes that a plurality of first operation results with higher bit numbers are split into a plurality of first addition data with lower bit numbers and a plurality of second addition data by selecting part of data in the first operation results, and then the plurality of first addition data with lower bit numbers, the plurality of second addition data and the plurality of first operation results can be summed through an adder with smaller bit width, so that the product of a first mantissa and a second mantissa can be obtained. The bit width of the adder adopted when the product of the mantissa parts of the first floating point number and the second floating point number is calculated is small, the hardware design cost is low, and the technical popularization is facilitated.

In a possible implementation manner of the second aspect, the selecting to output the partial data in the plurality of first operation results to obtain the plurality of first addition data and the plurality of second addition data, and obtaining the product of the first mantissa and the second mantissa according to the plurality of first addition data, the plurality of second addition data and the plurality of first operation results includes: selecting and outputting low-order data in a plurality of first operation results to obtain a plurality of first addition data, and selecting and outputting high-order data in a plurality of first operation results to obtain a plurality of second addition data; and adding the plurality of first addition data and the plurality of first operation results to obtain a low-order addition result and carry data, adding the plurality of carry data, the plurality of second addition data and the plurality of first operation results to obtain a high-order addition result, and adding the high-order addition result and the low-order addition result to obtain the product of the first mantissa and the second mantissa.

In this possible implementation manner, after the plurality of first operation results are obtained, the low-order data in the plurality of first operation results may be selectively output to obtain a plurality of first addition data, and the high-order data in the plurality of first operation results may be selectively output to obtain a plurality of second addition data. Namely, the first operation result with larger bit number is split into first addition data and second addition data with smaller bit number. And further, the first addition data and the second addition data are respectively summed with the corresponding first operation result to obtain a low-order addition result and a high-order addition result. Because the bit width of the low-order addition result and the high-order addition result is smaller, the bit width of an adder used for calculating the low-order addition result and the high-order addition result is smaller, and the construction cost of a calculation circuit is reduced.

In a possible implementation manner of the second aspect, the adding the plurality of first addition data and the plurality of first operation results to obtain a low-order addition result and carry data, adding the carry data, the plurality of second addition data and the plurality of first operation results to obtain a high-order addition result, adding the high-order addition result and the low-order addition result to obtain a product of the first mantissa and the second mantissa, includes: adding the plurality of first addition data and the plurality of first operation results in a first calculation period to obtain the low-order addition result and the carry data, and adding the carry data, the plurality of second addition data and the plurality of first operation results in a second calculation period to obtain the high-order addition result; and accumulating the low-order addition result and the high-order addition result to obtain the product of the first mantissa and the second mantissa.

In this possible implementation, if the first floating point number and the second floating point number are both FP64 type floating point numbers. The mantissa portion length due to the FP64 type floating point number is 53 bits. Thus, the total length number of mantissa portions obtained after calculation of a_mantissa is 106 bits. If the calculation of the mantissa portion of a pair of FP64 type floating point numbers is to be directly completed in one calculation unit (PE unit), the adder (first adder) needs to be expanded into an adder supporting data calculation with a length of 106 bits, and the area cost and the time sequence cost of the adder after the completion of the expansion are too high. Therefore, the multiplication of mantissa of a pair of FP64 may be selectively split into two parts (part 1 and part 2), with part1 being calculated to obtain a low order addition result in the first calculation cycle and part2 being calculated to obtain a high order addition result in the second cycle. Then, the product of the first mantissa and the second mantissa is obtained by accumulating the results obtained in the two calculation periods. Because the bit width of the low-order addition result and the high-order addition result is smaller, the bit width of an adder used for calculating the low-order addition result and the high-order addition result is smaller, and the construction cost of the floating point number calculation circuit is reduced.

In a possible implementation manner of the second aspect, the method further includes: the first mantissa is split into the first split mantissa, the first split mantissa comprises a first high-order mantissa and a first low-order mantissa, the second mantissa is split into the second split mantissa, the second split mantissa comprises a second high-order mantissa and a second low-order mantissa, and the first shift number is used for indicating a shift difference value between the highest position of each high-order mantissa and the highest position of each low-order mantissa.

In the possible implementation manner, the mantissa part with larger number of first floating point numbers can be split into the first high-order mantissa and the first low-order mantissa with smaller number of bits, and the mantissa part with larger number of second floating point numbers can be split into the second high-order mantissa and the second low-order mantissa with smaller number of bits, so that the product of each split mantissa part is calculated by adopting the multiplier with smaller number of bits, the design cost of hardware is reduced, and the calculation performance of the multiplier is reasonably utilized.

In a possible implementation manner of the second aspect, the first high-order mantissa includes a third mantissa, the first low-order mantissa includes a fourth mantissa, a fifth mantissa, a sixth mantissa, and a seventh mantissa, the second high-order mantissa includes an eighth mantissa, and the second low-order mantissa includes a ninth mantissa, a tenth mantissa, an eleventh mantissa, and a twelfth mantissa.

In a possible implementation manner of the second aspect, the method further includes: storing the first split mantissa, the second split mantissa, the first exponent, the second exponent, a third number of shifts used to represent the number of shifts of the first split mantissa, and a fourth number of shifts used to represent the number of shifts of the second split mantissa.

The possible implementation manner provides a specific implementation manner for storing temporary data in the floating point number calculation method, and the feasibility of the scheme is improved.

In a possible implementation manner of the second aspect, the obtaining a first shift number according to the first exponent and the second exponent includes: selecting a maximum value of a plurality of second operation results; and subtracting the maximum value in the plurality of second operation results from each second operation result to obtain the first shift number.

The possible implementation manner provides a specific implementation manner for acquiring the first shift number, and the feasibility of the scheme is improved.

In a possible implementation manner of the second aspect, the method further includes: multiplying the first split mantissa and the second split mantissa to obtain a plurality of third operation results; and performing shift processing on the third operation results according to the first shift numbers to obtain the first operation results.

The possible implementation manner provides a specific implementation manner for obtaining the first operation result, and the feasibility of the scheme is improved.

In a possible implementation manner of the second aspect, the method further includes: and acquiring the first floating point number and the second floating point number.

In a possible implementation manner of the second aspect, the first floating point number further includes a first sign bit, and the second floating point number further includes a second sign bit.

A third aspect of the present application provides a floating point number calculation circuit comprising: an exponent processing circuit and a calculation circuit including a first multiplication circuit, a first selector, and an addition circuit; the output end of the exponent processing circuit is electrically connected with the input end of the first multiplication circuit; the output end of the first multiplication circuit is electrically connected with the input end of the first selector; the output end of the first selector is electrically connected with the input end of the adding circuit.

In the application, in the process that a calculation circuit in a floating point number calculation circuit calculates the product of mantissa parts of two floating points, a first multiplication circuit outputs a plurality of operation results, a first selector can split the operation result with larger digits in the plurality of operation results into first addition data and second addition data with smaller digits, and further, the addition circuit can sum the plurality of first addition data, the plurality of second addition data and the plurality of first operation results with lower digits through an adder with smaller digits to obtain the product of the first mantissa and the second mantissa. The bit width of the adder adopted when the product of the mantissa parts of the first floating point number and the second floating point number is calculated is small, the hardware design cost is low, and the technical popularization is facilitated.

In a possible implementation manner of the third aspect, the floating point number calculation circuit is configured to calculate a product of a first floating point number and a second floating point number, where the first floating point number includes a first exponent, a first mantissa, and a first sign bit, and the second floating point number includes a second exponent, a second mantissa, and a second sign bit; the input end of the exponent processing circuit is used for receiving the first exponent and the second exponent; the input of the computing circuit is for receiving the first mantissa and the second mantissa.

In the possible implementation manner, the specific format of the floating point number input during the operation of the floating point number calculation circuit is described, and the feasibility of the scheme is improved.

In a possible implementation manner of the third aspect, the adding circuit includes a first adder and an accumulator; the input end of the first adder is electrically connected with the output end of the first selector, and the output end of the first adder is electrically connected with the input end of the accumulator.

In this possible implementation manner, after the first selector splits the operation result into the first addition data and the second addition data with lower bit numbers, the first adder may obtain a low-order addition result according to the first addition data and the plurality of non-split operation results, and obtain a high-order addition result according to the second addition data and the plurality of split operation results. The accumulator sums the lower addition result and the higher addition result to obtain the product of the first mantissa and the second mantissa. Because the bit width of the low-order addition result and the high-order addition result is smaller, the bit width of the first adder used for calculating the low-order addition result and the high-order addition result is smaller, and the construction cost of the calculation circuit is reduced.

In a possible implementation manner of the third aspect, the first multiplication circuit includes a first multiplier and a first shift register; the first input end of the first shift register is electrically connected with the output end of the exponent processing circuit, the second input end of the first shift register is electrically connected with the output end of the first multiplier, and the output end of the first shift register is electrically connected with the input end of the first selector.

In this possible implementation manner, the first multiplier may calculate a product between the split first mantissa and the split second mantissa, and the first shift register may shift a result output by the first multiplier according to a shift number output by the exponent processing circuit, and output an operation result after the shift. The possible implementation mode provides a specific implementation mode of the multiplication circuit, and the feasibility of the scheme is improved.

In a possible implementation manner of the third aspect, the exponent processing circuit includes a second adder, a second selector, and a third adder; the output end of the second adder is electrically connected with the first input end of the third adder; the second input end of the third adder is electrically connected with the output end of the second selector, and the output end of the third adder is electrically connected with the first input end of the first shift register.

In a possible implementation manner of the third aspect, the computing circuit further includes a second multiplication circuit, where the second multiplication circuit includes a second multiplier and a second shift register; the first input end of the second shift register is electrically connected with the output end of the exponent processing circuit, the second input end of the second shift register is electrically connected with the output end of the second multiplier, and the output end of the second shift register is electrically connected with the input end of the first adder.

In this possible implementation manner, the second multiplier in the second multiplication circuit multiplies the split first mantissa and the split second mantissa, and the second shift register shifts the result output by the second multiplier according to the shift number output by the exponent processing circuit to obtain a plurality of operation results. The second shift register directly inputs a plurality of operation results to the first adder, so that the first adder can sum the first addition result and the second addition result output by the first multiplication circuit with the plurality of operation results output by the second shift register to obtain the product of the first mantissa and the second mantissa.

In a possible implementation manner of the third aspect, the floating point number computing circuit further includes a memory controller, a third selector, and a register; the input end of the third selector is electrically connected with the output end of the memory controller, and the output end of the third selector is electrically connected with the input end of the register; the first output end of the register is electrically connected with the input end of the exponent processing circuit, and the second output end of the register is electrically connected with the input end of the calculating circuit.

In this possible manner, the memory controller transmits the first floating point number and the second floating point number acquired at the memory to the third selector, and the third selector splits the first mantissa and the second mantissa and then inputs the split first mantissa and the split second mantissa into the register for storage. This possible implementation promotes the feasibility of the solution.

A third aspect of an embodiment of the present application provides a computing device, including a control circuit and a floating point number computing circuit. The floating point number calculation circuit calculates data under the control of the control circuit, the floating point number calculation circuit being as described in the first aspect or any one of the possible implementations of the first aspect, or the floating point number calculation circuit being as described in the third aspect or any one of the possible implementations of the third aspect.

Drawings

FIG. 1 is a schematic diagram of a convolutional neural network provided by the present application;

FIG. 2 is a schematic diagram of the composition of a FP32 type floating point provided by an embodiment of the application;

FIG. 3 is a schematic diagram of a floating point number computing circuit according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a computing circuit according to an embodiment of the present application;

FIG. 5 is a schematic diagram of another configuration of a computing circuit according to an embodiment of the present application;

FIG. 6 is a schematic diagram of another configuration of a computing circuit according to an embodiment of the present application;

FIG. 7 is a schematic diagram of mantissa portions of first and second floating point numbers provided in the present application;

FIG. 8 is a schematic diagram of a computing circuit according to the present application;

FIG. 9 is a schematic diagram illustrating an operation process of a computing circuit according to the present application;

FIG. 10 is a schematic diagram of a floating point number computing circuit according to an embodiment of the present application;

FIG. 11 is a schematic diagram of another embodiment of a floating point number calculation circuit according to an embodiment of the present application;

FIG. 12 is a schematic diagram of another embodiment of a floating point number calculation circuit according to an embodiment of the present application;

fig. 13 is a schematic diagram of a split circuit according to the present application;

FIG. 14 is a schematic diagram of a first mantissa and a second mantissa according to the present application;

FIG. 15 is a schematic diagram of a memory circuit according to the present application;

FIG. 16 is a schematic diagram illustrating a connection relationship between a memory controller and a memory according to the present application;

FIG. 17 is a schematic diagram of an exponential processing circuit according to the present application;

FIG. 18 is a schematic diagram of another embodiment of a floating point number calculation circuit according to an embodiment of the present application;

FIG. 19 is a schematic diagram of another embodiment of a floating point number calculation circuit according to an embodiment of the present application;

FIG. 20 is a schematic diagram of another embodiment of a floating point number calculation circuit according to an embodiment of the present application;

FIG. 21 is a schematic diagram of another embodiment of a floating point number calculation circuit according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. As a person skilled in the art can know, with the appearance of a new application scenario, the technical scheme provided by the embodiment of the application is also applicable to similar technical problems.

The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or modules is not necessarily limited to those steps or modules that are expressly listed or inherent to such process, method, article, or apparatus. The naming or numbering of the steps in the present application does not mean that the steps in the method flow must be executed according to the time/logic sequence indicated by the naming or numbering, and the execution sequence of the steps in the flow that are named or numbered may be changed according to the technical purpose to be achieved, so long as the same or similar technical effects can be achieved.

Fig. 1 is a schematic diagram of a convolutional neural network according to the present application.

The convolutional neural network CNN has wide application prospects in the fields of image, voice recognition and the like. As shown in fig. 1, the convolutional neural network requires a convolutional operation on a plurality of convolutional kernels and one or more feature maps. Specifically, for each convolution kernel, it is moved from the first pixel of the feature map, the row direction is shifted from pixel to pixel, when the end of the row is reached, one pixel is shifted down in the column direction, the row direction is returned to the start, and the row direction shifting process is repeated until all pixels of the feature map are traversed. In the moving process of the convolution kernel, the data of the corresponding positions in the parameter and the feature image in the convolution kernel are used as two parts of convolution operation to be input, convolution operation is carried out (multiplication is carried out in pairs, and products are accumulated one by one), and the convolution result is output after the convolution result is obtained.

Convolutional neural networks (convolution neural network, CNN) are widely used in various image processing applications, and when performing network training on a model by using Floating Point (FP) 16 type data, the FP16 type data has insufficient precision, which may cause the network training to be not converged or have slow convergence speed, so that the FP32 type data with higher precision needs to be used to ensure the network training effect. Furthermore, in some applications, it is desirable to use higher accuracy FP64 type data as well as FP128 type data for model training.

It should be noted that the floating point number computing circuit according to the present invention may be applied to the field of data signal processing, such as an image processing system, a radar system, and a communication system, in addition to the field of artificial intelligence. The circuit and method may optimize the performance of digital signal processing (digital signal processing, DSP) or other digital devices. Such as digital devices in current communication systems, such as long term evolution (long term evolution, LTE), universal mobile telecommunications system (universal mobile telecommunications system, UMTS), global system for mobile communications (global system for mobile communications, GSM), etc.

In the existing data calculation scheme, a multiplier with a smaller bit number can be used for calculating a floating point number with a larger bit number. For example, FP64 type floating point data may be calculated by a multiplier for calculating FP32 data. The network equipment divides the floating point data of the FP64 type into floating point numbers with smaller digits and then performs multiplication operation, and then adds the result after the multiplication operation through an adder to obtain the product of the floating point data of the FP64 type. In the traditional calculation mode, the bit width of the adder required by adding the multiplication results is larger, the hardware design cost is high, and the technical popularization is not facilitated.

Aiming at the problems of the existing data calculation scheme, the embodiment of the application provides a floating point number calculation circuit, a floating point number calculation method and a calculation device. The bit width of the adder adopted when the product of the mantissa parts of the first floating point number and the second floating point number is calculated is small, the hardware design cost is low, and the technical popularization is facilitated.

Before describing the floating point number calculation circuit, the floating point number calculation method and the calculation device provided by the application, the format of the floating point number and the calculation mode of the floating point number are described by the following examples.

At present, floating point numbers with four formats, namely FP16, FP32, FP64 and FP128, are common. Wherein each floating point number consists of three parts, namely sign bit (sign), exponent bit (exp) and mantissa bit (mantissa). The actual value of a floating point number is equal to sign 2 ^exp *mantissa。

FIG. 2 is a schematic diagram of the composition of a floating point number of the FP32 type according to an embodiment of the present application.

As shown in FIG. 2, the FP32 type floating point number has 1bit sign,8bit exp and 24bit mantis, showing a total of 32 bits stored. Wherein the most significant bits of mantissa are implicitly stored (the hide bit is 1 if exp is not 0, otherwise the hide bit is 0), and the total of three parts is 32 bits.

When the floating point number A is calculated, the calculation process of the exponent part is A_exp+B_exp, and the calculation process of the mantissa part is A_mantissa a B_mantissa. The new exp and mantissa are then used to generate new floating point numbers according to the format in the standard.

When calculating floating point number A+B, the larger one of A_exp and B_exp is first obtained. Let a_exp be n larger than b_exp. Then, when mantissa is added, B_mantissa is required to be shifted to the right by n bits, then the B_mantissa is added with A_mantissa to obtain new mantissa, and then a new floating point number is generated according to the standard. When a plurality of floating point numbers are calculated to be added together, the largest exp is obtained, then the mantissa is correspondingly shifted according to the difference value between the largest exp and the exp of each floating point number, and then the shifted mantissa is added.

The floating point number calculating circuit, the floating point number calculating method and the calculating device provided by the application will be described in detail with reference to the accompanying drawings, and the floating point number calculating circuit provided by the application will be described first.

FIG. 3 is a schematic diagram of a floating point number computing circuit according to an embodiment of the present application.

Referring to fig. 3, the floating point number calculation circuit provided by the present application at least includes an exponent processing circuit 101 and a calculation circuit 102.

Wherein the output of the exponent processing circuit 101 is electrically connected to the input of the calculation circuit 102.

In the application, the floating point number calculation circuit is used for calculating the product of the first floating point number and the second floating point number. Wherein the first floating point number includes a first exponent and a first mantissa and the second floating point number includes a second exponent and a second mantissa. Exponent processing circuit 101 and calculation circuit 102 may calculate a product of the first floating point number and the second floating point number mantissa portion from the first floating point number and the second floating point number. This calculation process will be described below.

In the present application, the exponent processing circuit 101 may obtain the first shift number according to the first exponent and the second exponent. The first shift number is used for representing the shift number of the product between the first split mantissa and the second split mantissa, the first split mantissa is obtained by splitting the first mantissa, and the second split mantissa is obtained by splitting the second mantissa.

In the present application, the computing circuit 102 may selectively output part of data in the plurality of first operation results to obtain a plurality of first addition data and a plurality of second addition data, obtain a product of the first mantissa and the second mantissa according to the plurality of first addition data, the plurality of second addition data and the plurality of first operation results, where the first operation result is used to represent data obtained by shifting the product of the first split mantissa and the second split mantissa according to the first shift number.

The following examples will describe in detail the detailed process of calculating the floating point mantissa partial product in the present application in the instruction processing circuit 101 and the calculation circuit 102.

A specific implementation of the computing circuit 102 and an operation procedure of the computing circuit 102 will be described first.

Fig. 4 is a schematic diagram of a configuration of a computing circuit 102 according to an embodiment of the present application.

Referring to fig. 4, in the present application, optionally, the calculating circuit 102 may include a multiplying circuit 201, a first selecting circuit 202 and an adding circuit 203.

In the present application, the output of the exponent processing circuit 101 is electrically connected to the input of the multiplication circuit 201. An input terminal of the first selection circuit 202 is electrically connected to an output terminal of the multiplication circuit 201, and an output terminal of the first selection circuit 202 is electrically connected to an input terminal of the addition circuit 203.

The first selection circuit 202 may select and output low-order data in the plurality of first operation results to obtain a plurality of first addition data, and select and output high-order data in the plurality of first operation results to obtain a plurality of second addition data.

The adder 203 may add the plurality of first addition data and the plurality of first operation results to obtain a lower addition result and carry data, add the plurality of second addition data and the plurality of first operation results to obtain an upper addition result, and add the upper addition result and the lower addition result to obtain a product of the first mantissa and the second mantissa.

In the present application, the number of multiplication circuits 201, first selection circuits 202 and addition circuits 203 shown in fig. 4 is merely illustrative, and more multiplication circuits 201, more addition circuits 203 and/or more first selection circuits 202 may be included in the calculation circuit 102, which is not limited herein.

In the present application, the adder 203 has a specific implementation, and a specific implementation of the adder 203 provided in the present application will be described below by taking fig. 5 as an example.

Fig. 5 is a schematic diagram of another configuration of a computing circuit according to an embodiment of the present application.

Alternatively, the addition circuit 203 may include a first adder 301 and an accumulator 302.

Wherein, the input terminal of the first adder 301 is electrically connected to the output terminal of the first selection circuit 202, and the output terminal of the first adder 301 is electrically connected to the input terminal of the accumulator 302.

The first adder 301 may add the plurality of first addition data and the plurality of first operation results to obtain a lower addition result and carry data in a first calculation cycle, and add the plurality of second addition data and the plurality of first operation results to obtain a higher addition result in a second calculation cycle.

Accumulator 302 may accumulate the lower addition result and the higher addition result to obtain a product of the first mantissa and the second mantissa.

In the present application, the number of the first adder 301 and the accumulator 302 included in the addition circuit 203 shown in fig. 5 is optionally only exemplified. The adder 203 may include more first adders 301 and/or more accumulators 302, which are not limited herein.

In the present application, the multiplication circuit 201 has a specific implementation, and a specific implementation of the multiplication circuit 201 provided in the present application will be described below by taking fig. 6 as an example.

Fig. 6 is a schematic diagram of another configuration of a computing circuit according to an embodiment of the present application.

Referring to fig. 6, the multiplication circuit 201 includes a multiplier 303 and a shift register 304;

an input of the multiplier 303 is electrically connected to an output of the exponent processing circuit 101, and an output of the multiplier 303 is electrically connected to an input of the shift register 304.

The multiplier 303 may multiply the first split mantissa and the second split mantissa to obtain a plurality of third operation results.

The shift register 304 may perform shift processing on the third operation results according to the first shift numbers to obtain first operation results.

The operation of the calculation circuit 102 in the present application is described below with a specific calculation example.

Before describing the operation of the calculation circuit 102, the format of the mantissa portions of the first floating point number and the second floating point number will be described first.

FIG. 7 is a schematic diagram of mantissa portions of first and second floating point numbers provided in the present application.

For example, assume that a first floating point number a and a second floating point number B are stored in a memory, where the first floating point number a and the second floating point number B are FP64 type floating point numbers. In processing the calculation of FP64 type floating point numbers, as in fig. 7, the calculation circuit may split the mantissa portion (first mantissa) of the first floating point number a into five portions a0, a1, a2, a3, a 4. The mantissa portion (second mantissa) of the second floating point number B is split into five portions B0, B1, B2, B3, B4. Wherein a0, a1, a2, a3, a4 are the first split mantissas and b0, b1, b2, b3, b4 are the second split mantissas. The numbers of bits of a1, a2, a3, a4, b1, b2, b3, b4 are all 12 bits, and the numbers of bits of a0, b0 are 5 bits.

After obtaining the first split mantissa and the second split mantissa, when the calculation circuit 102 performs an operation, multiplication of the mantissa portion of the first floating point number a and the mantissa portion of the second floating point number B may be expressed as formula 1.

Equation 1:

A _mantissa *B _mantissa

＝(a0＜＜48bit+a1＜＜36bit+a2＜＜24bit+a3＜＜12bit+a4)*

(a0＜＜48bit+a1＜＜36bit+a2＜＜24bit+a3＜＜12bit+a4)

＝Part1[Low_12bit(a0*b4+a4*b0+a1*b3+a3*b1+a2*b2)＜＜48bit

+(a1*b4+b1*a4+a2*b3+a3*b2)＜＜32bit

+(a2*b4+a4*b2+a3*b3)＜＜24bit

+(a3*b4+a4*b3)＜＜12bit

+(a4*b4)]

+Part2[(a0*b0))96bit

+(a0*b1+a1*b0)＜＜84bit

+(a0*b2+a2*b0+a1*b1)＜＜72bit

+(a0*b3+a3*b0+a1*b2+a2*b1)＜＜60bit

+High_12bit(a0*b4+a4*b0+a1*b3+a3*b1+a2*b2)＜＜48bit]

in the application, the mantissa part length of the floating point number of the FP64 type is 53 bits. Thus, the total length number of mantissa portions obtained after calculation of a_mantissa is 106 bits. If the calculation of the mantissa portion of a pair of FP64 type floating point numbers is to be directly completed in one calculation unit (PE unit), the adder (first adder) needs to be expanded into an adder supporting data calculation with a length of 106 bits, and the area cost and the time sequence cost of the adder after the completion of the expansion are too high. Thus, the multiplication of mantissa for a pair of FP64 may be chosen to split into two parts, with a first part (part 1) of the above formula being calculated in a first calculation cycle and a second part (part 2) being calculated in a second calculation cycle.

The operation procedures of the multiplication circuit 201, the first selection circuit 202, and the addition circuit 203 are described below with reference to the drawings and the above formula 1, respectively.

(1) And the operation process of the multiplication circuit.

Fig. 8 is a schematic diagram of a computing circuit according to the present application.

First, the operation procedure of the multiplication circuit is described with reference to fig. 8 and the above-described formulas.

Referring to fig. 8, in the present application, it is assumed that the hardware portion of the computing circuit 102 is divided into a plurality of computing modules. The multiple multipliers in each calculation module calculate products between the first split mantissa and the second split mantissa, such as a0×b4, a4×b0, a1×b3, a3×b1, a2×b2, etc., where the products between the first split mantissa and the second split mantissa are all calculated by the multipliers in the specific calculation process for illustration, and 25 third calculation results are obtained by the products between the 5 first split mantissas and the 5 second split mantissas.

The shift register shifts the 25 third operation results according to the first shift numbers output by the exponent processing circuit, so as to obtain the first operation result. In the above formula, the exemplary value of (a0+a4+b0+a1+b3+a3+a1+a2+a2) < 48 bits, 48 bits is the first shift number of the following third calculation results a0+b4, a4+b0, a1+b3, a3+b1, a2. The shift registers can shift the third operation results according to the first shift number.

The third operation result and the corresponding 48bit shift number described in the above example are only exemplary, and in the actual calculation process, the shift register may perform shift processing on a plurality of third operation results according to other first shift numbers, where the first shift numbers may also be other shift numbers, and the present application is not limited thereto.

(2) The first selection circuit and the addition circuit.

The operation of the first selection circuit and the addition circuit is described below with reference to fig. 8 and the above-described formulas.

In the present application, the first selection circuit in the first calculation module and the second calculation module receives a2×b2, a1×b3, a3×b1, a0×b4, and a4×b0 (first operation result) after the shift processing. Since the lengths of the shift results of a 2b 2, a1 b3, a3 b1, a0 b4 and a 4b 0 are 24 bits, the first selection circuit may output the low-order 12 bits (first addition data) in the first calculation period, and the low-order 12 bits and the shift-processed a1 b4, a 4b 1, a 2b 3, a3 b2, a3 b3, a 2b 4, a 4b 2, a3 b4, a 4b 3, a 4b 4 (first calculation result) may be added by a plurality of 52-bit adders (first adders), so as to obtain the low-order addition result and carry data, where the carry data refers to the data generated by the carry after the calculation of the plurality of addition results.

Similarly, the first selection circuit in the first calculation module and the second calculation module receives a2×b2, a1×b3, a3×b1, a0×b4, and a4×b0 (the first operation result) after the shift processing. Since the lengths of the shift results of a 2b 2, a1 b3, a3 b1, a0 b4 and a 4b 0 are 24 bits, the first selection circuit can output the 12 bits (second addition data) of the high bits in the second calculation period, and the high-bit 12 bits are added to the shift results of a0 b0, a0 b1, a1 b0, a0 b2, a 2b 0, a1 b1, a0 b3, a3 b0, a1 b2 and a 2b 1 (first calculation result) and carry data by a plurality of 52-bit adders (first adders), so as to obtain the high-bit addition result.

The accumulator accumulates the low order addition result and the high order addition result to obtain the product of the first mantissa and the second mantissa.

The above example describes the operation procedure of the calculation circuit 102 in conjunction with the specific hardware configuration in fig. 8, and the following describes the procedure of the calculation circuit 102 obtaining the lower addition result from the first addition data and the first operation result in the first calculation period, and the procedure of the calculation circuit 102 obtaining the higher addition result from the second addition data, the carry data, and the first operation result in the second calculation period, respectively, in conjunction with fig. 9.

Fig. 9 is a schematic diagram illustrating an operation process of a computing circuit according to the present application.

Referring to fig. 9, PP1 to PP25 respectively represent a plurality of first operation results, wherein a2×b2, a1×b3, a3×b1, a0×b4 and a4×b0 respectively correspond to PP11 to PP15 in the figure. The sum of the lower mantissa parts of PP11 to PP15 and other first operation results is calculated in the first calculation period, and the sum of the upper mantissa parts of carry data PP00, PP11 to PP15 and other first operation results is calculated in the second calculation period.

In the application, the first calculation cycle calculates the sum of 15 groups of parts of low-order bits, takes the low-order 12 bits of PP1 as [11:0] bits of the final 106-bit result, and takes the high-order 12 bits of PP1 as the input of the low-order 12 bits of the addition tree. Taking the lower 12 bits of PP11 to PP15 as the upper 12 bits of the 48-bit addition tree, and taking the shifted [59:12] bits as the addition tree input as shown in the figure, wherein 15 groups of partial products of the lower bits are calculated and accumulated in the first calculation period to obtain a 52-bit result, the 48-bit result of [47:0] is the [59:12] bit of the final 106-bit result, and the 4-bit result of the upper bit is [51:48] as carry data. In the second calculation period, the high 12 bits of PP11 to PP15 are taken as the low 12 bits in the input 48-bit addition tree, the low 12 bits of PP25 are taken as the high 12 bits in the input 48-bit addition tree, the width of PP25 is only 10 bits, so that the high 12 bits of PP25, namely [23:12], can be omitted, PP16 to PP24 are taken as the input of the addition tree after the shift, and the carry signal of the first calculation period is added, so that a 52-bit result can be obtained. Since 53 bits are also maximally only 106 bits of final result, the highest 6 bits of the 52 bits of result calculated by the 2 nd period addition tree, i.e., [51:46], must be 0, while the remaining 46 bits are [105:60] bits of the final result.

In the application, optionally, for the high 4bit [51:48] (carry data PP 0) brought by carry in the first calculation period, an additional register can be added for saving, and the bit width of the addition tree can be 48 bits. The carry can also be completely covered with the addition tree, where the bit width of the addition tree needs 52 bits. The specific examples are not limited herein.

FIG. 10 is a schematic diagram of another embodiment of a floating point number calculation circuit according to an embodiment of the present application.

As shown in fig. 10, the first calculation results obtained by calculating the parts of part1 and part2 are corresponding positions in the addition tree. As can be seen from fig. 10, the 60bit addition tree can cover the computation of part 1. The addition tree for calculating the low order addition result (Part 1) needs 52 bits wide, and the addition tree can completely cover the 4bit carry of the Part 1. The addition tree for calculating the higher addition result (Part 2) requires 48 bits wide. Thus, for each Part, the adder tree requires at most 52 bits to enable multiplication between the first mantissa and the second mantissa.

FIG. 11 is a schematic diagram of another embodiment of a floating point number calculation circuit according to an embodiment of the present application.

As shown in fig. 11, black parts in the drawing are positions in the addition tree corresponding to the respective first calculation results in part 1. Wherein the lower 12 bits of a 2b 2, a1 b3, a3 b1, a 0b 4 and a 4b 0 shifted according to the first shift number are located in 48 bits to 60 bits. The shifted a1 b4, a 4b 1, a 2b 3, a3 b2 are located at 36bit-60bit. The shifted a3 b3, a 2b 4, a 4b 2 are located at 24bit-48bit. The shifted a3 b4, a 4b 3 are located at 12bit-36bit. The shifted a 4b 4 is located between 0bit and 24bit.

FIG. 12 is a schematic diagram of another embodiment of a floating point number calculation circuit according to an embodiment of the present application.

As shown in fig. 12, the black parts in the drawing are positions in the addition tree corresponding to the first calculation results in part2, respectively.

Wherein the high order 12 bits of a0 x b4 and a4 x b0 shifted according to the first shift number are located in 60-72 bits. The high order 12 bits of the first shift bit shifted a2×b2, a1×b3, a3×b1 are located in 60-72 bits. The a 0b 3 and a3 b0 after shifting according to the first shift number are located in 60bit-77 bit. The a 1b 2 and a 2b 1 shifted according to the first shift number are located in 60-84 bit positions. The a 0b 2 and a 2b 0 after the shift according to the first shift number are located in 72bit-89 bit. The a 1b 1 shifted according to the first shift number is located in 72bit-96 bit. The a 0b 1 and a 1b 0 shifted according to the first shift number are located in 84-101 bit positions. The a 0b 0 shifted according to the first shift number is located in 96-106 bit.

In the present application, in the examples shown in fig. 11 and 12, it is noted that in both Part1 and Part2, a2×b2, a1×b3, a3×b1, a0×b4, a4×b0 are repeatedly calculated. But Part1 is the 12bit with the low order and Part2 is the 12bit with the high order, which can be achieved by adding a first selection circuit in the calculation circuit, the overhead of fixed shift is small, and the increase of area and power consumption is also small. And partial repeated operation does not increase the area, and the power consumption influence is small.

In the present application, the floating point number calculation circuit may also include a splitting circuit.

Fig. 13 is a schematic diagram of a split circuit according to the present application.

Referring to fig. 13, the output end of the splitting circuit is electrically connected to the input end of the exponent processing circuit and the input end of the multiplying circuit. Optionally, the splitting circuit may include a first selector and a register, where an output terminal of the first selector is electrically connected to an input terminal of the register. The first selector inputs the first floating point number and the second floating point number, and the first selector stores a result obtained after the first floating point number and the second floating point number are split in a corresponding register.

Fig. 14 is a schematic diagram of a first mantissa and a second mantissa according to the present application.

As shown in fig. 14, specifically, the plurality of first selectors in the splitting circuit may split the first mantissa into a first split mantissa, where the first split mantissa includes a first high-order mantissa and a first low-order mantissa, split the second mantissa into a second split mantissa, where the second split mantissa includes a second high-order mantissa and a second low-order mantissa, and the first shift number is used to indicate a shift difference between a highest bit of each high-order mantissa and a highest bit of each low-order mantissa.

Optionally, the first high mantissa includes a third mantissa, the first low mantissa includes a fourth mantissa, a fifth mantissa, a sixth mantissa, and a seventh mantissa, the second high mantissa includes an eighth mantissa, and the second low mantissa includes a ninth mantissa, a tenth mantissa, an eleventh mantissa, and a twelfth mantissa. After the splitting circuit in fig. 13 inputs the first floating point number and the second floating point number, the plurality of first selectors in the splitting circuit may split the first mantissa of the first floating point number into a third mantissa, a fourth mantissa, a fifth mantissa, a sixth mantissa, and a seventh mantissa. The first selector may split the second mantissa of the second floating-point number into an eighth mantissa, a ninth mantissa, a tenth mantissa, an eleventh mantissa, and a twelfth mantissa.

The process of splitting the mantissa portion of a floating point number by a splitting circuit is described below in a specific example.

For example, if the first floating point number is a FP64 type floating point number. It is assumed that the splitting circuit can split the mantissa portion of the first floating point number into a third mantissa 10001 of length 5 bits, a fourth mantissa 100000000001 of length 12 bits, a fifth mantissa 100000000011 of length 12 bits, a sixth mantissa 100000000111 of length 12 bits, and a seventh mantissa 100000001111 of length 12 bits.

In this embodiment, the third mantissa belongs to the first high mantissa, and the fourth mantissa, the fifth mantissa, the sixth mantissa, and the seventh mantissa belong to the first low mantissa. The first shift number is used for indicating a shift difference between the highest bit of the high-order mantissa and the highest bit of each low-order mantissa, namely, the shift number of the first mantissa is 0, the first shift number of the fourth mantissa is 5 bits of the shift difference between the first bit of the fourth mantissa and the first bit of the third mantissa, and the shift number is the same as the bit number of the third mantissa, so that the first shift number of the fourth mantissa is 5 bits shifted right. The first shift number of the fifth mantissa is 17 bits of the shift difference between the first bit of the fifth mantissa and the first bit of the third mantissa, which is the same as the sum of the shift numbers of the third mantissa and the fourth mantissa, so the first shift number of the fifth mantissa is 17 bits shifted right. The first shift number of the sixth mantissa is 29 bits of the shift difference between the first bit of the sixth mantissa and the first bit of the third mantissa, which is the same as the sum of the shift numbers of the third mantissa, the fourth mantissa, and the fifth mantissa, so the first shift number of the sixth mantissa is 29 bits shifted right. The first shift count of the seventh mantissa is 41 bits of the shift difference between the first bit of the seventh mantissa and the first bit of the third mantissa, which is the same as the sum of the shift counts of the third mantissa, the fourth mantissa, the fifth mantissa, and the sixth mantissa, so the first shift count of the seventh mantissa is 41 bits to the right.

In this embodiment, the first high-order mantissa and the second high-order mantissa may have other different splitting manners, for example, the first bit length is 9 bits, and the second mantissa, the third mantissa, the fourth mantissa and the fifth mantissa are all 11 bits, which is not limited herein.

In this embodiment, the second high-order mantissa is similar to the first high-order mantissa in terms of splitting, and the second low-order mantissa is similar to the first low-order mantissa in terms of splitting, which will not be described in detail herein.

The splitting manner is only used for illustration, alternatively, the first floating point number may be a FP32 type floating point number, the first floating point number may also be a FP64 type floating point number, and the first floating point number may also be a FP128 type floating point number, which is not limited herein. Optionally, the mantissa portion of the first floating point number may be split into two portions or may be split into multiple portions, which is not limited herein. The number of bits of each of the mantissa portions after splitting may be equal, or the number of bits of each of the mantissa portions after splitting may be unequal, which is not limited herein.

In the present application, the floating point number calculation circuit may optionally further include a storage circuit.

The output end of the splitting circuit is electrically connected with the input end of the storage circuit, and the input end of the index processing circuit is electrically connected with the first output end of the storage circuit. The input end of the computing circuit is electrically connected with the second output end of the storage circuit.

Fig. 15 is a schematic diagram of a structure of a memory circuit according to the present application.

Referring to fig. 15, the memory circuit includes a plurality of registers for storing a first split mantissa, a second split mantissa, a first exponent, a second exponent, a third shift number for indicating a shift number of the first split mantissa, and a fourth shift number for indicating a shift number of the second split mantissa.

It will be appreciated that the number of registers included in the memory circuit of fig. 15 is merely illustrative. Alternatively, more registers than those shown in fig. 15 may be included in the memory circuit, and fewer registers than those shown in fig. 15 may be included in the memory circuit, which is not limited herein.

In the present application, the floating point number calculation circuit may also include a memory controller.

Fig. 16 is a schematic diagram of a connection relationship between a memory controller and a memory according to the present application.

As shown in fig. 16, the input end of the memory controller is connected to the output end of the memory, and the output end of the memory controller is electrically connected to the input end of the splitting circuit.

In the application, the first floating point number and the second floating point number are stored in the memory, the memory controller can acquire the first floating point number and the second floating point number and send the first floating point number and the second floating point number to the splitting circuit. Alternatively, the memory may be a Double Data Rate (DDR) memory, or may be other memories, which is not limited herein. The memory controller may be a DDR controller or other types of memory controllers, and is not limited herein.

In the present application, the exponent processing circuit 101 has a specific implementation manner, and the exponent processing circuit 101 may obtain the first shift number according to the first exponent and the second exponent, which also has a specific calculation manner, and a specific implementation manner of the exponent processing circuit 101 and an operation process of the exponent processing circuit 101 are described below with reference to fig. 17.

Fig. 17 is a schematic diagram of an exponent processing circuit according to the present application.

Referring to fig. 17, the exponent processing circuit 101 includes at least a second adder 401, a second selecting circuit 402, and a third adder 403.

Wherein an input of the second adder 401 is electrically connected to a first output of the memory circuit, and an output of the second adder 401 is electrically connected to a first input of the third adder 403. A second input of the third adder 403 is electrically connected to the output of the second selection circuit, and an output of the third adder 403 is electrically connected to the first input of the calculation circuit 102.

In the present application, the second adder 401 may add the first exponent, the second exponent, the third shift count and the fourth shift count to obtain a plurality of second operation results. The second selection circuit 402 may select a maximum value among the plurality of second operation results. The third adder 403 subtracts each of the second operation results from the maximum value of the plurality of second operation results to obtain the first shift number.

The present application also provides a floating point number calculation method, and a specific implementation manner of the floating point number calculation method can be understood by referring to the floating point number calculation circuits described in fig. 3 to 17, and detailed descriptions thereof are omitted herein.

The application also provides another floating point number calculation circuit, and similarly, the specific implementation manner of the floating point number calculation method can be understood by referring to the floating point number calculation circuit described in fig. 3 to 17, and detailed description is omitted here.

FIG. 18 is a schematic diagram of another embodiment of a floating point number calculation circuit according to an embodiment of the present application.

Step one: referring to fig. 18, the second floating point number B is the data in the filter matrix. The DDR controller (memory controller) reads a plurality of first floating point numbers a and second floating point numbers B from the DDR (memory), splits the mantissa part of the first floating point number a into two parts of MSB and LSB by a high-low bit splitting logic (splitting circuit) and stores the two parts into a data RAM (storing circuit), contents included in I, II, … X in fig. 10 are a_msb and a_lsb obtained by the mantissa splitting of each first floating point number a, an exponent part EXP corresponding to each a_msb and a_lsb, and the mantissa part of the second floating point number B is divided into two parts of MSB and LSB and stores the two parts into a weight RAM (storing circuit), and contents included in 1, 2, N in fig. 18 are b_msb and b_lsb obtained by the mantssa splitting of each second floating point number B, and an exponent part EXP corresponding to each b_msb and b_lsb.

FIG. 19 is a schematic diagram of another embodiment of a floating point number calculation circuit according to an embodiment of the present application.

Step two: referring to fig. 19, mantissa after splitting in the weight RAM is preloaded into the convolution calculation unit, and EXP (exponent portion corresponding to each mantissa portion after splitting) is also preloaded into the convolution calculation unit after being processed by EXP offset (second adder).

FIG. 20 is a schematic diagram of another embodiment of a floating point number calculation circuit according to an embodiment of the present application.

Step three: referring to fig. 20, the first segment mantissa data (part I) is extracted from the data RAM, and the EXP part is also first processed by EXP offset, and then placed into a convolution calculation unit, and calculated with the preloaded parameter (part 1) and the result is obtained.

Step four: referring to fig. 21, the convolution processing unit 1 forwards the first piece of data (part I) to the computing unit 2, and acquires the second piece of data (part II) from the data RAM. The calculation unit 1 after acquiring the part II data, and the calculation unit 2 after acquiring the part I data complete the operation generation result. After that, each clock, the computing units 2 to N forward the data processed by the previous clock to the next computing unit, and the computing unit 1 acquires new data from the data RAM each time.

Step five: repeating the fourth step until all the data are operated to generate a result.

The floating point number calculation circuit and the floating point number calculation method provided by the embodiment of the application are described in detail, and specific examples are applied to illustrate the principle and implementation of the application, and the description of the above embodiments is only used for helping to understand the method and core ideas of the application. Meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims

A floating point number calculation circuit for calculating a product of a first floating point number and a second floating point number, the first floating point number including a first exponent and a first mantissa, the second floating point number including a second exponent and a second mantissa, the floating point number calculation circuit comprising: an exponent processing circuit and a calculation circuit;

the output end of the index processing circuit is electrically connected with the input end of the calculating circuit;

the exponent processing circuit is configured to obtain a first shift number according to the first exponent and the second exponent, where the first shift number is used to represent a shift number of a product between a first split mantissa and a second split mantissa, the first split mantissa is obtained by splitting the first mantissa, and the second split mantissa is obtained by splitting the second mantissa;

The computing circuit is used for selectively outputting partial data in a plurality of first operation results to obtain a plurality of first addition data and a plurality of second addition data, obtaining products of the first mantissas and the second mantissas according to the plurality of first addition data, the plurality of second addition data and the plurality of first operation results, and the first operation results are used for representing the data obtained after the products of the first split mantissas and the second split mantissas are shifted according to the first shift number.
The floating point number calculation circuit of claim 1, wherein the calculation circuit comprises a multiplication circuit, an addition circuit, and a first selection circuit;

the output end of the exponent processing circuit is electrically connected with the input end of the multiplying circuit;

the input end of the first selection circuit is electrically connected with the output end of the multiplication circuit, and the output end of the first selection circuit is electrically connected with the input end of the addition circuit;

the first selection circuit is used for selecting and outputting low-order data in a plurality of first operation results to obtain a plurality of first addition data, and selecting and outputting high-order data in a plurality of first operation results to obtain a plurality of second addition data;

The addition circuit is configured to add the plurality of first addition data and the plurality of first operation results to obtain a low-order addition result and carry data, add the plurality of carry data, the plurality of second addition data and the plurality of first operation results to obtain a high-order addition result, and add the high-order addition result and the low-order addition result to obtain a product of the first mantissa and the second mantissa.
The floating point number calculation circuit of claim 2 wherein said adding circuit comprises a first adder and an accumulator;

the input end of the first adder is electrically connected with the output end of the first selection circuit, and the output end of the first adder is electrically connected with the input end of the accumulator;

the first adder is configured to add the plurality of first addition data and the plurality of first operation results in a first calculation cycle to obtain the lower addition result and the carry data, and add the plurality of carry data, the plurality of second addition data and the plurality of first operation results in a second calculation cycle to obtain the higher addition result;

and the accumulator is used for accumulating the low-order addition result and the high-order addition result to obtain the product of the first mantissa and the second mantissa.
A floating point number calculation circuit as claimed in claim 2 or claim 3, wherein the floating point number calculation circuit further comprises a splitting circuit;

the output end of the splitting circuit is electrically connected with the input end of the exponent processing circuit and the input end of the multiplying circuit;

the splitting circuit is configured to split the first mantissa into the first split mantissa, the first split mantissa includes a first high-order mantissa and a first low-order mantissa, split the second mantissa into the second split mantissa, the second split mantissa includes a second high-order mantissa and a second low-order mantissa, and the first shift number is used to indicate a shift difference value between a highest position of each high-order mantissa and a highest position of each low-order mantissa.
The floating point number computing circuit of claim 4 wherein,

the first high-order mantissa includes a third mantissa, the first low-order mantissa includes a fourth mantissa, a fifth mantissa, a sixth mantissa, and a seventh mantissa, the second high-order mantissa includes an eighth mantissa, and the second low-order mantissa includes a ninth mantissa, a tenth mantissa, an eleventh mantissa, and a twelfth mantissa.
The floating point number calculation circuit according to any one of claims 1 to 5, characterized in that the floating point number calculation circuit further comprises a storage circuit;

The output end of the splitting circuit is electrically connected with the input end of the storage circuit;

the input end of the index processing circuit is electrically connected with the first output end of the storage circuit;

the input end of the computing circuit is electrically connected with the second output end of the storage circuit;

the storage circuit is configured to store the first split mantissa, the second split mantissa, the first exponent, the second exponent, a third shift number and a fourth shift number, where the third shift number is used to represent the shift number of the first split mantissa, and the fourth shift number is used to represent the shift number of the second split mantissa.
The floating point number computing circuit of claim 6, wherein,

the exponent processing circuit comprises a second adder, a second selection circuit and a third adder;

the input end of the second adder is electrically connected with the first output end of the storage circuit, and the output end of the second adder is electrically connected with the first input end of the third adder;

the second input end of the third adder is electrically connected with the output end of the second selection circuit, and the output end of the third adder is electrically connected with the first input end of the calculation circuit;

The second adder is configured to add the first exponent, the second exponent, the third shift count, and the fourth shift count to obtain a plurality of second operation results;

the second selection circuit is used for selecting the maximum value in a plurality of second operation results;

and the third adder is used for subtracting the maximum value in the plurality of second operation results from each second operation result to obtain the first shift number.
The floating point number calculation circuit of any one of claims 6 or 7, wherein the multiplication circuit includes a multiplier and a shift register;

the input end of the multiplier is electrically connected with the second output end of the storage circuit, and the output end of the multiplier is electrically connected with the first input end of the shift register;

the second input end of the shift register is electrically connected with the output end of the third adder;

the output end of the shift register is electrically connected with the input end of the first adder;

the multiplier is used for multiplying the first split mantissa and the second split mantissa to obtain a plurality of third operation results;

the shift register is used for carrying out shift processing on the third operation results according to the first shift numbers to obtain the first operation results.
The floating point number computing circuit of any one of claims 6 to 8, further comprising a memory controller;

the output end of the memory controller is electrically connected with the input end of the splitting circuit;

the memory controller is configured to obtain the first floating point number and the second floating point number, and send the first floating point number and the second floating point number to the splitting circuit.
The floating point number calculation circuit of any one of claims 1 to 9 wherein the first floating point number further comprises a first sign bit and the second floating point number further comprises a second sign bit.
A floating point number calculation method for calculating a product of a first floating point number and a second floating point number, the first floating point number including a first exponent and a first mantissa, the second floating point number including a second exponent and a second mantissa, the method comprising:

obtaining a first shift number according to the first exponent and the second exponent, wherein the first shift number is used for representing the shift number of the product between a first split mantissa and a second split mantissa, the first split mantissa is obtained by splitting the first mantissa, and the second split mantissa is obtained by splitting the second mantissa;

And selecting and outputting partial data in a plurality of first operation results to obtain a plurality of first addition data and a plurality of second addition data, acquiring products of the first mantissas and the second mantissas according to the plurality of first addition data, the plurality of second addition data and the plurality of first operation results, wherein the first operation results are used for representing the data obtained by shifting the products of the first split mantissas and the second split mantissas according to the first shift number.
The floating point number computing method of claim 11 wherein the selecting to output the partial data in the plurality of first operation results in a plurality of first addition data and a plurality of second addition data, and obtaining the product of the first mantissa and the second mantissa based on the plurality of first addition data, the plurality of second addition data, and the plurality of first operation results comprises:

selecting and outputting low-order data in a plurality of first operation results to obtain a plurality of first addition data, and selecting and outputting high-order data in a plurality of first operation results to obtain a plurality of second addition data;

and adding the plurality of first addition data and the plurality of first operation results to obtain a low-order addition result and carry data, adding the plurality of carry data, the plurality of second addition data and the plurality of first operation results to obtain a high-order addition result, and adding the high-order addition result and the low-order addition result to obtain the product of the first mantissa and the second mantissa.
The floating point number calculation method as set forth in claim 12, wherein said adding said plurality of said first addition data and said plurality of said first operation results to obtain a lower addition result and a carry data, adding said carry data, said plurality of said second addition data and said plurality of said first operation results to obtain an upper addition result, and adding said upper addition result and said lower addition result to obtain a product of said first mantissa and said second mantissa, comprises:

adding the plurality of first addition data and the plurality of first operation results in a first calculation period to obtain the low-order addition result and the carry data, and adding the carry data, the plurality of second addition data and the plurality of first operation results in a second calculation period to obtain the high-order addition result;

and accumulating the low-order addition result and the high-order addition result to obtain the product of the first mantissa and the second mantissa.
The floating point number calculation method of claim 12 or 13, further comprising:

the first mantissa is split into the first split mantissa, the first split mantissa comprises a first high-order mantissa and a first low-order mantissa, the second mantissa is split into the second split mantissa, the second split mantissa comprises a second high-order mantissa and a second low-order mantissa, and the first shift number is used for indicating a shift difference value between the highest position of each high-order mantissa and the highest position of each low-order mantissa.
The method of floating point number calculation of claim 14 wherein,

the first high-order mantissa includes a third mantissa, the first low-order mantissa includes a fourth mantissa, a fifth mantissa, a sixth mantissa, and a seventh mantissa, the second high-order mantissa includes an eighth mantissa, and the second low-order mantissa includes a ninth mantissa, a tenth mantissa, an eleventh mantissa, and a twelfth mantissa.
The floating point number calculation method according to any one of claims 11 to 13, characterized in that the method further comprises:

storing the first split mantissa, the second split mantissa, the first exponent, the second exponent, a third number of shifts used to represent the number of shifts of the first split mantissa, and a fourth number of shifts used to represent the number of shifts of the second split mantissa.
The floating point number computing method of claim 16 wherein the obtaining a first shift number from the first exponent and the second exponent comprises:

selecting a maximum value of a plurality of second operation results;

and subtracting the maximum value in the plurality of second operation results from each second operation result to obtain the first shift number.
The floating point number calculation method as claimed in any one of claims 16 or 17, further comprising:

multiplying the first split mantissa and the second split mantissa to obtain a plurality of third operation results;

and performing shift processing on the third operation results according to the first shift numbers to obtain the first operation results.
The floating point number calculation method as claimed in any one of claims 12 to 18, further comprising:

and acquiring the first floating point number and the second floating point number.
The floating point number calculation method of any one of claims 11 to 19 wherein the first floating point number further comprises a first sign bit and the second floating point number further comprises a second sign bit.
A floating point number calculation circuit, the floating point number calculation circuit comprising: an exponent processing circuit and a calculation circuit including a first multiplication circuit, a first selector, and an addition circuit;

the output end of the exponent processing circuit is electrically connected with the input end of the first multiplication circuit;

the output end of the first multiplication circuit is electrically connected with the input end of the first selector;

The output end of the first selector is electrically connected with the input end of the adding circuit.
The floating point number computing circuit of claim 21, wherein the floating point number computing circuit is configured to compute a product of a first floating point number comprising a first exponent, a first mantissa, and a first sign bit and a second floating point number comprising a second exponent, a second mantissa, and a second sign bit;

the input end of the exponent processing circuit is used for receiving the first exponent and the second exponent;

the input of the computing circuit is for receiving the first mantissa and the second mantissa.
The floating point number computing circuit of claim 22, wherein the adding circuit comprises a first adder and an accumulator;

the input end of the first adder is electrically connected with the output end of the first selector, and the output end of the first adder is electrically connected with the input end of the accumulator.
The floating point number calculation circuit of claim 22 or 23, wherein the first multiplication circuit comprises a first multiplier and a first shift register;

the first input end of the first shift register is electrically connected with the output end of the exponent processing circuit, the second input end of the first shift register is electrically connected with the output end of the first multiplier, and the output end of the first shift register is electrically connected with the input end of the first selector.
The floating point number calculation circuit of any one of claims 22 to 24 wherein the exponent processing circuit includes a second adder, a second selector and a third adder;

the output end of the second adder is electrically connected with the first input end of the third adder;

the second input end of the third adder is electrically connected with the output end of the second selector, and the output end of the third adder is electrically connected with the first input end of the first shift register.
The floating point number calculation circuit of any one of claims 22 to 25, further comprising a second multiplication circuit comprising a second multiplier and a second shift register;

the first input end of the second shift register is electrically connected with the output end of the exponent processing circuit, the second input end of the second shift register is electrically connected with the output end of the second multiplier, and the output end of the second shift register is electrically connected with the input end of the first adder.
The floating point number computing circuit of any one of claims 22 to 25, further comprising a memory controller, a third selector, and a register;

The input end of the third selector is electrically connected with the output end of the memory controller, and the output end of the third selector is electrically connected with the input end of the register;

the first output end of the register is electrically connected with the input end of the exponent processing circuit, and the second output end of the register is electrically connected with the input end of the calculating circuit.
A computing device, comprising a control circuit and a floating point number computing circuit;

the floating point number calculation circuit calculates data under the control of the control circuit, the floating point number calculation circuit being the floating point number calculation circuit as claimed in any one of claims 1 to 10, or the floating point number calculation circuit being the floating point number calculation circuit as claimed in any one of claims 21 to 27.