CN117175665B

CN117175665B - Wave-transmitting synchronous system, method and related equipment for PCS (process control system) multi-machine parallel connection

Info

Publication number: CN117175665B
Application number: CN202311447176.7A
Authority: CN
Inventors: 黄英雄
Original assignee: Shenzhen Haichen Energy Storage Technology Co ltd; Xiamen Hithium Energy Storage Technology Co Ltd
Current assignee: Shenzhen Haichen Energy Storage Technology Co ltd; Xiamen Hithium Energy Storage Technology Co Ltd
Priority date: 2023-11-02
Filing date: 2023-11-02
Publication date: 2024-01-26
Anticipated expiration: 2043-11-02
Also published as: CN117175665A

Abstract

The application provides a wave-transmitting synchronization system, a method and related equipment for multi-machine parallel connection of PCS (process control systems), wherein a main PCS (process control system) in the system can report a signal to a slave PCS sending parameter; the method comprises the steps that a parameter report signal is received from a PCS, and the frequency of an output current signal of a local phase-locked loop frequency synthesizer, the frequency division coefficient of a local frequency divider and a power frequency signal within a certain time are reported to a main PCS; the master PCS obtains carrier synchronization signals based on the frequency and the frequency division coefficient of the output current signals of the local phase-locked loop frequency synthesizers of the slave PCS; based on the power frequency signals and the carrier synchronization signals of each slave PCS, obtaining the power frequency synchronization signals, and transmitting the carrier synchronization signals and the power frequency synchronization signals to each slave PCS; each slave PCS carries out local adjustment based on the carrier synchronous signal and the power frequency synchronous signal so as to realize the wave-transmitting synchronization of the PCS. The embodiment of the application is beneficial to inhibiting the circulation among PCS and ensuring the stability of the PCS parallel system.

Description

Wave-transmitting synchronous system, method and related equipment for PCS (process control system) multi-machine parallel connection

Technical Field

The application relates to the technical field of energy storage converters in new energy storage, in particular to a wave-transmitting synchronization system, a wave-transmitting synchronization method and relevant equipment for PCS multi-machine parallel connection.

Background

Household energy storage is also called a household energy storage system, and is usually installed in combination with a household photovoltaic system to provide electric energy for household users. The energy storage converter (Power Conversion System, PCS) is a device connected between a battery and a power grid in an electrochemical energy storage system and used for realizing the bidirectional conversion of electric energy, and the function of the device is mainly that direct current of the battery is inverted into alternating current and is transmitted to the power grid or used for an alternating current load; or rectifying the alternating current of the power grid into direct current to charge the battery. PCS is an indispensable component in household energy storage, and under the working condition of multi-machine parallel connection, the PCS off-grid operation can cause problems of circulation, power unequal division and the like, and how to inhibit circulation among PCS so as to ensure the stability of a parallel system is a problem to be solved currently.

Disclosure of Invention

Aiming at the problems, the application provides a wave-transmitting synchronization system, a wave-transmitting synchronization method and related equipment for PCS multi-machine parallel connection, which can realize wave-transmitting synchronization under the PCS multi-machine parallel connection working condition through a carrier synchronization signal and a power frequency synchronization signal, thereby inhibiting circulation among PCS and ensuring the stability of the PCS parallel connection system.

In order to achieve the above objective, a first aspect of the present application provides a wave-transmitting synchronization system with multiple parallel PCS, where the system includes multiple battery clusters, multiple PCS corresponding to the multiple battery clusters one to one, and the multiple battery clusters are connected to the dc sides of the corresponding PCS through power lines respectively; the off-grid output ends of the PCS are connected with a distribution board through power lines, and the distribution board is electrically connected with a household load; the PCS comprises a master PCS, and PCS except the master PCS is a slave PCS; the master PCS and each slave PCS are communicated through signal lines;

The main PCS is used for sending parameter reporting signals to the auxiliary PCS when detecting that each PCS is in the off-network working condition;

each slave PCS is used for reporting the frequency of an output current signal of the local phase-locked loop frequency synthesizer, the frequency division coefficient of a frequency divider in the local phase-locked loop frequency synthesizer and a power frequency signal in a preset time period to the master PCS under the condition of receiving the parameter reporting signal;

the master PCS is also used for obtaining carrier synchronization signals based on the frequency of the output current signals of the local phase-locked loop frequency synthesizers of the slave PCS and the frequency division coefficient; and obtaining a power frequency synchronous signal based on the power frequency signal and the carrier synchronous signal of each slave PCS;

the master PCS is also used for transmitting the carrier synchronous signal and the power frequency synchronous signal to each slave PCS;

each slave PCS is also used for carrying out local adjustment based on the carrier synchronous signal and the power frequency synchronous signal so as to realize the wave transmission synchronization of a plurality of PCS.

With reference to the first aspect, in a possible implementation manner, each slave PCS further includes a phase detector in a local phase-locked loop frequency synthesizer; under the condition that each slave PCS receives the parameter report signal, the phase difference output by the phase discriminator is also reported to the master PCS;

The main PCS is specifically used for:

obtaining the frequency range of the input current reference signal of the local phase-locked loop frequency synthesizer of each slave PCS based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of each slave PCS and the frequency division coefficient;

determining a carrier frequency based on a frequency range of an input current reference signal of each local phase-locked loop frequency synthesizer of the slave PCS;

determining a carrier phase based on the phase difference output by the phase detector;

a carrier synchronization signal is generated based on the carrier frequency and the carrier phase.

With reference to the first aspect, in one possible implementation manner, each slave PCS further reports a circuit structure of the local phase-locked loop frequency synthesizer to the master PCS when receiving the parameter report signal;

the main PCS is specifically used for:

inquiring and obtaining frequency operation expressions corresponding to the circuit structures of the local phase-locked loop frequency synthesizers of the slave PCS based on the circuit structures of the local phase-locked loop frequency synthesizers of the slave PCS; the frequency operation expression is constructed by taking the frequency of an input current reference signal, the frequency of an output current signal and the frequency division coefficient of each slave PCS local phase-locked loop frequency synthesizer as parameters;

The frequency range of the input current reference signal of each slave PCS local phase-locked loop frequency synthesizer is obtained based on the frequency of the output current signal of each slave PCS local phase-locked loop frequency synthesizer, the frequency division coefficient and the corresponding frequency operation expression.

With reference to the first aspect, in one possible implementation manner, the frequency divider in the local phase-locked loop frequency synthesizer of each slave PCS includes a frequency divider a;

the main PCS is specifically used for:

for a first slave PCS in each slave PCS, calculating based on the frequency of an output current signal of a local phase-locked loop frequency synthesizer of the first slave PCS, the frequency division coefficient of a frequency divider A in the local phase-locked loop frequency synthesizer of the first slave PCS and a corresponding frequency calculation expression to obtain the minimum frequency of an input current reference signal of the local phase-locked loop frequency synthesizer of the first slave PCS; the first slave PCS is a slave PCS with the frequency division coefficient of the frequency divider A being larger than 1;

based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of the first slave PCS, the reciprocal of the frequency division coefficient of the frequency divider A in the local phase-locked loop frequency synthesizer of the first slave PCS and the corresponding frequency operation expression, calculating to obtain the maximum frequency of the input current reference signal of the local phase-locked loop frequency synthesizer of the first slave PCS;

The frequency range of the input current reference signal of the local phase-locked loop frequency synthesizer of the first slave PCS is determined based on the maximum frequency and the minimum frequency of the input current reference signal of the local phase-locked loop frequency synthesizer of the first slave PCS.

With reference to the first aspect, in one possible implementation manner, the main PCS is specifically configured to:

for a second slave PCS in each slave PCS, calculating based on the frequency of an output current signal of a local phase-locked loop frequency synthesizer of the second slave PCS, the frequency division coefficient of a frequency divider A in the local phase-locked loop frequency synthesizer of the second slave PCS and a corresponding frequency calculation expression to obtain the maximum frequency of an input current reference signal of the local phase-locked loop frequency synthesizer of the second slave PCS; the second slave PCS is a slave PCS with the frequency division coefficient of the frequency divider A being more than 0 and less than 1;

based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of the second slave PCS, the reciprocal of the frequency division coefficient of the frequency divider A in the local phase-locked loop frequency synthesizer of the second slave PCS and the corresponding frequency operation expression, calculating to obtain the minimum frequency of the input current reference signal of the local phase-locked loop frequency synthesizer of the second slave PCS;

the frequency range of the input current reference signal of the local phase-locked loop frequency synthesizer of the second slave PCS is determined based on the maximum frequency and the minimum frequency of the input current reference signal of the local phase-locked loop frequency synthesizer of the second slave PCS.

obtaining at least two candidate frequencies based on the frequency range of the input current reference signal of each slave PCS local phase-locked loop frequency synthesizer;

based on at least two candidate frequencies, a carrier frequency is obtained.

calculating the average value of the phase difference output by the phase discriminator to obtain a phase difference reference value;

the frequency of an input current reference signal of a local phase-locked loop frequency synthesizer is adjusted to be carrier frequency, the phase of the input current reference signal of the local phase-locked loop frequency synthesizer is modulated, and the phase difference output by a phase discriminator in the local phase-locked loop frequency synthesizer after each phase modulation is captured;

and when the difference value between the captured target phase difference and the phase difference reference value is smaller than a preset threshold value, determining the phase of the input current reference signal corresponding to the obtained target phase difference as the carrier phase.

carrying out frequency estimation on each power frequency signal of the slave PCS by adopting a sampling counting method to obtain a corresponding frequency estimation value;

Based on the frequency estimation value corresponding to the power frequency signal of each slave PCS, carrying out phase estimation on the power frequency signal of each slave PCS by adopting a Levenberg-Marquardt algorithm to obtain a corresponding phase estimation value;

determining a power frequency phase based on a carrier phase of the carrier synchronization signal for phase estimation values corresponding to the power frequency signals of each slave PCS;

and generating a power frequency synchronous signal based on the power frequency phase.

A second aspect of the present application provides a method for synchronizing wave transmissions of a PCS multi-machine parallel connection, which is applied to the system as described in the first aspect, and the method includes:

when the main PCS detects that each PCS is in an off-network working condition, the main PCS sends a parameter reporting signal to the auxiliary PCS;

under the condition that each slave PCS receives the parameter reporting signal, reporting the frequency of an output current signal of the local phase-locked loop frequency synthesizer, the frequency division coefficient of a frequency divider in the local phase-locked loop frequency synthesizer and a power frequency signal in a preset time period to the master PCS;

the master PCS obtains carrier synchronization signals based on the frequency of the output current signals of the local phase-locked loop frequency synthesizers of the slave PCS and the frequency division coefficient; and obtaining a power frequency synchronous signal based on the power frequency signal and the carrier synchronous signal of each slave PCS;

The master PCS transmits a carrier synchronization signal and a power frequency synchronization signal to each slave PCS;

each slave PCS carries out local adjustment based on the carrier synchronization signal and the power frequency synchronization signal so as to realize the wave transmission synchronization of a plurality of PCS.

With reference to the second aspect, in one possible implementation manner, each slave PCS further includes a phase detector in a local phase-locked loop frequency synthesizer; under the condition that each slave PCS receives the parameter report signal, the phase difference output by the phase discriminator is also reported to the master PCS; the master PCS obtains a carrier synchronization signal based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of each slave PCS and the frequency division coefficient, and the method comprises the following steps:

With reference to the second aspect, in one possible implementation manner, each slave PCS further reports the circuit structure of the local phase-locked loop frequency synthesizer to the master PCS when receiving the parameter report signal; the master PCS obtains the frequency range of the input current reference signal of the local phase-locked loop frequency synthesizer of each slave PCS based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of each slave PCS and the frequency division coefficient, and the method comprises the following steps:

With reference to the second aspect, in one possible implementation manner, the frequency divider in the local phase-locked loop frequency synthesizer of each slave PCS includes a frequency divider a; the master PCS obtains a frequency range of an input current reference signal of the local phase-locked loop frequency synthesizer of each slave PCS based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of each slave PCS, the frequency division coefficient and the corresponding frequency operation expression, and the method comprises the following steps:

With reference to the second aspect, in one possible implementation manner, the master PCS obtains a frequency range of an input current reference signal of a local phase-locked loop frequency synthesizer of each slave PCS based on a frequency of an output current signal of the local phase-locked loop frequency synthesizer of each slave PCS, the frequency division coefficient and a corresponding frequency operation expression, and further includes:

With reference to the second aspect, in one possible implementation manner, the determining, by the master PCS, a carrier frequency based on a frequency range of an input current reference signal of a local phase-locked loop frequency synthesizer of each slave PCS includes:

based on at least two candidate frequencies, a carrier frequency is obtained.

With reference to the second aspect, in one possible implementation manner, the determining, by the master PCS, a carrier phase based on a phase difference output by the phase detector includes:

With reference to the second aspect, in one possible implementation manner, the master PCS obtains a power frequency synchronization signal based on a power frequency signal and a carrier synchronization signal of each slave PCS, and includes:

It can be understood that, since the method embodiment and the system embodiment are different presentation forms of the same technical concept, the content of the first aspect of the embodiment of the present application should be synchronously adapted to the second aspect of the embodiment of the present application, and the same or similar beneficial effects can be achieved, which is not described herein.

A third aspect of the present application provides a PCS comprising a memory storing a computer program and a processor implementing the steps of the method as in any one of the embodiments of the second aspect described above when the computer program is executed.

A fourth aspect of the present application provides a computer readable storage medium storing a computer program for execution by a device, the computer program when executed implementing a method according to any one of the embodiments of the second aspect.

The scheme of the application at least comprises the following beneficial effects:

in the embodiment of the application, in a multi-machine parallel wave-transmitting synchronous system of PCS, a main PCS generates carrier synchronous signals based on the frequency of an output current signal of a local phase-locked loop frequency synthesizer of each auxiliary PCS and the frequency division coefficient of a frequency divider; and generating a power frequency synchronization signal based on the power frequency signal and the carrier synchronization signal of each slave PCS. The main PCS transmits the carrier synchronization signal and the power frequency synchronization signal to each auxiliary PCS through signal wires connected with each auxiliary PCS, each auxiliary PCS captures information carried by the carrier synchronization signal and the power frequency synchronization signal to adjust local frequency and phase, thereby realizing wave transmission synchronization, further being beneficial to inhibiting circulation among PCS and ensuring the stability of the PCS multi-machine parallel system.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a wave-transmitting synchronization system with parallel PCS multiple units provided in an embodiment of the present application;

fig. 2 is a schematic diagram of a pll frequency synthesizer according to an embodiment of the present application;

fig. 3 is a schematic flow chart of a method for synchronizing parallel wave transmission of PCS multiple units according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a PCS according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a household energy storage system according to an embodiment of the present application.

Reference numerals: 1. an energy storage device; 2. an electric energy conversion device; 3. a first user load; 4. a second user load; 401. a processor; 402. a memory; 403. a communication interface; 404. a bus.

Detailed Description

In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.

The terms "comprising" and "having" and any variations thereof, as used in the specification, claims and drawings, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may optionally further include other steps or elements not listed or inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," and "third," etc. are used for distinguishing between different objects and not for describing a particular sequential order.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

Because of the strong timeliness and space properties of energy required by people, in order to reasonably utilize the energy and improve the utilization rate of the energy, one energy form needs to be stored by one medium or equipment and then converted into another energy form, and the energy is released in a specific energy form based on future application. At present, the main way of generating green electric energy is to develop green energy sources such as photovoltaic, wind power and the like to replace fossil energy sources,

At present, the generation of green electric energy generally depends on photovoltaic, wind power, water potential and the like, but wind energy, solar energy and the like generally have the problems of strong intermittence and large fluctuation, which can cause unstable power grid, insufficient peak electricity consumption, too much electricity consumption and unstable voltage can cause damage to the electric power, so that the problem of 'wind abandoning and light abandoning' possibly occurs due to insufficient electricity consumption requirement or insufficient power grid acceptance, and the problem needs to be solved by relying on energy storage. The energy is converted into other forms of energy through physical or chemical means and is stored, the energy is converted into electric energy when needed and released, in short, the energy storage is similar to a large-scale 'charge pal', the electric energy is stored when the photovoltaic and wind energy are sufficient, and the stored electric power is released when needed.

Taking electrochemical energy storage as an example, the scheme provides an energy storage device, wherein a group of chemical batteries are arranged in the energy storage device, chemical elements in the batteries are mainly used as energy storage media, and the charge and discharge process is accompanied with chemical reaction or change of the energy storage media.

The present energy storage (i.e. energy storage) application scenario is comparatively extensive, including aspects such as power generation side energy storage, electric wire netting side energy storage and power consumption side energy storage, and the kind of corresponding energy storage device includes:

(1) The large energy storage power station applied to the wind power and photovoltaic power station side can assist renewable energy sources to generate electricity to meet grid-connected requirements, and meanwhile, the utilization rate of the renewable energy sources is improved; the energy storage power station is used as a high-quality active/reactive power regulating power supply in a power supply side, so that the load matching of electric energy in time and space is realized, the capacity of absorbing renewable energy sources is enhanced, the instantaneous power change is reduced, the impact on a power grid is reduced, the problem of generating and absorbing new energy sources is solved, and the energy storage power station has great significance in the aspects of standby of a power grid system, relieving peak load power supply pressure and peak regulation and frequency modulation;

(2) The energy storage container applied to the power grid side has the functions of mainly peak regulation, frequency modulation and power grid blocking and peak regulation relieving, and can realize peak clipping and valley filling of the power consumption load, namely the energy storage battery is charged when the power consumption load is low, and the stored electric quantity is released in the peak period of the power consumption load, so that the balance between power production and power consumption is realized;

(3) The small energy storage cabinet applied to the electricity utilization side has the main functions of spontaneous electricity utilization, peak Gu Jiacha arbitrage, capacity cost management and power supply reliability improvement. According to the different application scenes, the electricity-side energy storage can be divided into an industrial and commercial energy storage cabinet, a household energy storage device, an energy storage charging pile and the like, and is generally matched with the distributed photovoltaic. The energy storage can be used by industrial and commercial users for valley peak price difference arbitrage and capacity cost management. In the electric power market implementing peak-valley electricity price, the energy storage system is charged when the electricity price is low, and the energy storage system is discharged when the electricity price is high, so that peak-valley electricity price difference arbitrage is realized, and the electricity cost is reduced. In addition, the energy storage system is suitable for two industrial enterprises with electricity price, can store energy when electricity is used in low valley and discharge the energy when the electricity is used in peak load, so that peak power and the declared maximum demand are reduced, and the purpose of reducing the capacity electricity fee is achieved. The household photovoltaic distribution and storage can improve the spontaneous self-use level of the electric power. Due to high electricity prices and poor power supply stability, the photovoltaic installation requirements of users are pulled. Considering that the photovoltaic power generation is performed in daytime, and the load of a user is generally higher at night, the photovoltaic power can be better utilized through configuration of energy storage, the spontaneous self-use level is improved, and meanwhile the power consumption cost is reduced. In addition, the fields of communication base stations, data centers and the like need to be configured with energy storage for standby power.

In order to overcome the defects or shortcomings in the related art, the embodiment of the application provides a wave-transmitting synchronization system with a plurality of PCS machines connected in parallel. Referring to fig. 1, fig. 1 is a schematic structural diagram of a parallel wave-transmitting synchronization system of a PCS, provided in an embodiment of the present application, where, as shown in fig. 1, the system includes a plurality of battery clusters, and a plurality of PCS corresponding to the plurality of battery clusters one by one, where the plurality of battery clusters are connected with dc sides of the corresponding PCS respectively through power lines, a battery switch is provided between each battery cluster and the corresponding PCS, one end of the battery switch is connected with the battery cluster, and the other end is connected with the dc side of the PCS. The off-grid outputs (BACK-UP) of the individual PCS are connected via power lines to the switchboard 1, which switchboard 1 is connected to the household loads. An ac breaker is provided between each PCS and the switchboard 1, which can be used to protect lines and equipment on the lines, and in case of emergency, the connection between the PCS and the switchboard 1 can be cut off. The GRID-connected output terminals (ON-GRID) of the PCS are connected to the switchboard 2 through power lines, the switchboard 2 is connected to the GRID through other devices or apparatuses, and an ac breaker is also arranged between each PCS and the switchboard 2. The direct current side of each PCS is also connected with the photovoltaic module through a power line, and the electric energy output by the photovoltaic module side can be stored into a battery module in a battery cluster by the PCS or is transmitted to a power grid after being converted by the PCS under a grid-connected working condition. Among the plurality of PCS, one master PCS is included, and the PCS other than the master PCS is a slave PCS, and the master PCS and each slave PCS communicate through a signal line, which may be a communication line based on a positive acknowledgement protocol (Positive Acknowledgement with Retransmission, PAR) supporting retransmission, for example. By way of example, the master PCS may be the most powerful PCS of the plurality of PCS, which communicates with the battery cluster connection via another signal line, which may be a battery management system (Battery Management System, BMS) harness.

In the multi-machine parallel architecture of the PCS shown in fig. 1, the master PCS may be configured to obtain voltages of the grid-connected points of each PCS, and when the voltage drops or rises above a threshold value at a plurality of sampling points, that is, the power grid is considered to be disconnected from the micro-grid or the power grid fails, the master PCS controls each PCS to execute the off-grid operation, and when each PCS is in the off-grid working condition, the master PCS sends a parameter reporting signal to each slave PCS through a signal line. Wherein each PCS includes a master PCS and each slave PCS.

Each slave PCS is used for reporting the frequency of the output current signal of the local phase-locked loop frequency synthesizer, the frequency division coefficient of the frequency divider in the local phase-locked loop frequency synthesizer and the power frequency signal in a preset time period to the master PCS under the condition of receiving the parameter reporting signal sent by the master PCS. Wherein the circuit structure of the local phase-locked loop frequency synthesizer of each slave PCS is different, such as: there may be only 1 divider in the local pll frequency synthesizer of slave PCS1, 2 or more dividers in the local pll frequency synthesizer of slave PCS2, and the frequency division coefficients of the frequency dividers may be different between the different slave PCS, and the frequency division coefficients of the individual frequency dividers of one slave PCS may also be different. Exemplary, circuit configurations of a phase-locked loop frequency synthesizer including 1 divider, 2 dividers, and 3 dividers are shown in fig. 2 (a), (b), and (c), respectively. It should be noted that the phase detector, the loop filter, and the voltage-controlled oscillator are basic components of the phase-locked loop frequency synthesizer, and the functional roles thereof can be referred to the description of the related documents. Based on (a), (b) and (c) in fig. 2, in the application scenario of multi-machine parallel connection of the PCS in the application, each local pll frequency synthesizer of the PCS includes a frequency divider a, an input end of the frequency divider a is directly or indirectly connected to an output end of the voltage-controlled oscillator, and an output end of the frequency divider a is directly or indirectly connected to an input end of the phase discriminator.

Illustratively, each slave PCS is provided with a power frequency signal generator for outputting a power frequency signal corresponding to the PCS. When the parameter report signal is received, each slave PCS reports the power frequency signal of t milliseconds before and after the time of receiving the parameter report signal to the master PCS.

A master PCS for obtaining a carrier synchronization signal based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of each slave PCS and the frequency division coefficient of the frequency divider in the local phase-locked loop frequency synthesizer of each slave PCS; and obtaining the power frequency synchronous signal based on the power frequency signal and the carrier synchronous signal of each slave PCS.

Illustratively, each slave PCS also reports the phase difference output by the phase detector in the local pll frequency synthesizer to the master PCS when receiving the parameter report signal. In terms of obtaining a carrier synchronization signal based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of each slave PCS and the frequency division coefficient, the master PCS is specifically configured to:

1. and obtaining the frequency range of the input current reference signal of the local phase-locked loop frequency synthesizer of each slave PCS based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of each slave PCS and the frequency division coefficient.

In an exemplary embodiment, each slave PCS further reports the circuit structure of the local pll frequency synthesizer to the master PCS when receiving the parameter reporting signal, where the master PCS stores frequency operation expressions corresponding to the pll frequency synthesizers with different circuit structures, and the frequency operation expressions are constructed by using the frequency of the input current reference signal, the frequency of the output current signal, and the frequency division coefficient of each local pll frequency synthesizer of the slave PCS as parameters. The master PCS calculates the frequency range of the input current reference signal of the local phase-locked loop frequency synthesizer of each slave PCS based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of each slave PCS, the frequency division coefficient and the corresponding frequency operation expression. In short, the main PCS can calculate the frequency range of the corresponding input current reference signal using the frequency operation expression, knowing the frequency of the output signal and the division coefficient of the divider.

Illustratively, each slave PCS includes a first PCS having a frequency division factor greater than 1 for divider a in the local phase-locked loop frequency synthesizer. For the first PCS, the master PCS calculates based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of the first slave PCS, the frequency division coefficient of the frequency divider A in the local phase-locked loop frequency synthesizer of the first slave PCS and the corresponding frequency operation expression, and obtains the minimum frequency of the input current reference signal of the local phase-locked loop frequency synthesizer of the first slave PCS. Exemplary, a pll frequency synthesizer having a circuit structure as shown in fig. 2 (a) may have the following frequency operation expression:

Wherein,representing the frequency of the input current reference signal, +.>Representing the frequency of the output current signal, < >>Representing the division factor of divider A, based on which the master PCS can calculate the minimum frequency +.>。

Exemplary, a pll frequency synthesizer having a circuit structure as shown in fig. 2 (b) may have the following frequency operation expression:

wherein,representing the division factor of divider B, based on which the master PCS can likewise calculate the minimum frequency +.>. It should be understood that the pll frequency synthesizer of the circuit structure shown in fig. 2 (c) corresponds to a different frequency operation expression as described above, and of course, in the case of more slave PCS, there will be a different frequency operation expression, which is not exemplified here.

The master PCS carries out operation based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of the first slave PCS, the reciprocal of the frequency dividing coefficient of the frequency divider A in the local phase-locked loop frequency synthesizer of the first slave PCS and a corresponding frequency operation expression, and the maximum frequency of the input current reference signal of the local phase-locked loop frequency synthesizer of the first slave PCS is obtained. Taking the reciprocal of the division factor of the frequency divider a as an example, the phase-locked loop frequency synthesizer with the circuit structure shown in fig. 2 (a) may have a corresponding frequency operation expression modified as follows:

Based on this, the main PCS can calculate the maximum frequency of the corresponding input current reference signal. Similarly, the phase-locked loop frequency synthesizer with the circuit structure as shown in fig. 2 (b) has a corresponding frequency operation expression that can be modified as follows:

based on this, the main PCS can also calculate the maximum frequency of the corresponding input current reference signal。

The frequency range of the input current reference signal of the local phase-locked loop frequency synthesizer of the first slave PCS may then be expressed as:。

illustratively, each slave PCS includes a second PCS having a frequency division factor greater than 0 and less than 1 for divider a in the local phase-locked loop frequency synthesizer. And for the second slave PCS, calculating based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of the second slave PCS, the frequency division coefficient of the frequency divider A in the local phase-locked loop frequency synthesizer of the second slave PCS and the corresponding frequency calculation expression to obtain the maximum frequency of the input current reference signal of the local phase-locked loop frequency synthesizer of the second slave PCS. Exemplary, a PLL frequency synthesizer having a circuit configuration as shown in FIG. 2 (a) and (b) can calculate the maximum frequency of the input current reference signal using its corresponding frequency operation expression . The master PCS calculates based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of the second slave PCS, the reciprocal of the frequency division coefficient of the frequency divider A in the local phase-locked loop frequency synthesizer of the second slave PCS and the corresponding frequency calculation expression, and obtains the minimum frequency of the input current reference signal of the local phase-locked loop frequency synthesizer of the second slave PCS. Exemplary, the pll frequency synthesizer with the circuit structure shown in fig. 2 (a) and (b) is to take the reciprocal of the division coefficient of the divider a to deform the frequency operation expression, and the deformed expression is used to calculate the minimum frequency of the input current reference signal>. The frequency range of the input current reference signal of the local phase-locked loop frequency synthesizer of the second slave PCS can also be expressed as: />。

2. The carrier frequency is determined based on the frequency range of the input current reference signal of the respective slave PCS local phase locked loop frequency synthesizer.

Illustratively, the master PCS is specifically configured to: obtaining at least two candidate frequencies based on the frequency range of the input current reference signal of each slave PCS local phase-locked loop frequency synthesizer; based on at least two candidate frequencies, a carrier frequency is obtained. The master PCS takes the intermediate value of the frequency range of the input current reference signal of the local pll frequency synthesizer of each slave PCS to obtain at least two candidate frequencies, and calculates the average value of the at least two candidate frequencies to obtain the carrier frequency of the PCS power supply, and the calculation formula is as follows:

Wherein,represents the number of slave PCS>Indicate->Personal slave PCS->Indicate->Minimum frequency of input current reference signal of local phase-locked loop frequency synthesizer of slave PCS,/>Indicate->The maximum frequency of the input current reference signal from the local phase locked loop frequency synthesizer of the PCS.

For example, the primary PCS may further perform weighted averaging on at least two candidate frequencies based on preset weights of the at least two candidate frequencies to obtain a carrier frequency; or the intermediate value is obtained after weighted summation, so as to obtain the carrier frequency.

Illustratively, the primary PCS may further obtain a frequency range of an input current reference signal of the local pll frequency synthesizer of the primary PCS based on the frequency of the output current signal of the local pll frequency synthesizer, the frequency division coefficient, and a corresponding frequency operational expression. The master PCS obtains at least two candidate frequencies based on the frequency range of the input current reference signal of the local phase-locked loop frequency synthesizer and the frequency ranges of the input current reference signals of the local phase-locked loop frequency synthesizers of the slave PCS, and then obtains carrier frequencies based on the at least two candidate frequencies.

In the implementation manner, the master PCS further determines the carrier frequency of carrier synchronization based on the frequency range of the solved input current reference signals of the local phase-locked loop frequency synthesizers of the slave PCS, comprehensively references the current input current reference signals of the slave PCS, and is beneficial to ensuring that the master PCS and the slave PCS carry out frequency adjustment with smaller reference values, so that the PCS system can carry out wave transmission synchronization in a smooth and stable mode.

3. Determining a carrier phase based on the phase difference output from each phase detector in the local phase locked loop frequency synthesizer of the PCS;

the master PCS calculates an average value of phase differences output by phase detectors in local phase-locked loop frequency synthesizers of each slave PCS to obtain a phase difference reference value, then performs local adjustment, adjusts the frequency of an input current reference signal of the local phase-locked loop frequency synthesizers to carrier frequency, modulates the phase of the input current reference signal of the local phase-locked loop frequency synthesizers, captures the phase difference output by the phase detectors in the local phase-locked loop frequency synthesizers after each phase modulation, and determines the phase of the input current reference signal corresponding to the obtained target phase difference as the carrier phase when the difference between the captured target phase difference and the phase difference reference value is smaller than a preset threshold value. Such as: the calculated phase difference reference value is calculated asWhen the main PCS captures a phase difference +.>And->Or->Less than a preset threshold->Then->For the target phase difference, the primary PCS determines the phase of the corresponding input current reference signal after the secondary phase modulation as the carrier phase of each PCS power supply. Exemplary, - >0 may be taken.

4. A carrier synchronization signal is generated based on the carrier frequency and the carrier phase.

Illustratively, in terms of obtaining a power frequency synchronization signal based on the power frequency signal and the carrier synchronization signal of each slave PCS, the master PCS is specifically configured to:

1. and carrying out frequency estimation on each power frequency signal of the slave PCS by adopting a sampling counting method to obtain a corresponding frequency estimation value.

In the detection of the zero crossing time of the power frequency signals, the main PCS is connected with the sampling circuit for continuous sampling, judges each sampling value in real time, and outputs the zero crossing time when detecting that the sampling value is in zero crossing jump from negative to positive (or from positive to negative). The main PCS counts the peak value of the stored sampling value and carries out frequency estimation through the peak value number, the sampling frequency and the sampling period.

2. Based on the frequency estimation value corresponding to the power frequency signal of each slave PCS, carrying out phase estimation on the power frequency signal of each slave PCS by adopting a Levenberg-Marquardt algorithm to obtain a corresponding phase estimation value.

Under the condition of determining the frequency estimation value, carrying out iteration by adopting a Levenberg-Marquardt (LM) algorithm and carrying out frequency estimation value, so as to obtain the phase estimation value corresponding to each power frequency signal of the PCS.

3. And determining the power frequency phase based on the carrier phase of the carrier synchronous signal for the phase estimation value corresponding to the power frequency signal of each slave PCS.

The master PCS determines whether a unique mode exists in the phase estimation values corresponding to the power frequency signals of the slave PCS, and if so, the unique mode is used as a power frequency phase; if the phase difference value does not exist, the carrier phase corresponding to the carrier synchronous signal is taken as the power frequency phase, or the difference value between the phase estimation value corresponding to the power frequency signal of each slave PCS and the carrier phase corresponding to the carrier synchronous signal is calculated, and the phase estimation value with the smallest difference value is taken as the power frequency phase.

In the implementation manner, when the unique mode exists in the phase estimation value, the unique mode is used as the power frequency phase, when the unique mode does not exist in the phase estimation value, the carrier phase corresponding to the carrier synchronous signal is used as the power frequency phase or one phase estimation value with the smallest difference value of the carrier phases corresponding to the carrier synchronous signal is used as the power frequency phase, so that on one hand, the complexity of determining the power frequency phase is reduced, and on the other hand, the power frequency phase of each slave PCS is close to the carrier phase as much as possible, and the carrier synchronization and the power frequency synchronization are combined.

4. And generating a power frequency synchronous signal based on the power frequency phase.

The master PCS is also used for transmitting the carrier synchronous signal and the power frequency synchronous signal to each slave PCS; each slave PCS is further configured to perform local adjustment based on the carrier synchronization signal and the power frequency synchronization signal, for example: the carrier frequency and carrier phase of the carrier synchronous signal are locked, and the power frequency phase of the power frequency synchronous signal is locked, so that the wave-transmitting synchronization of a plurality of PCS is realized.

It can be seen that, in the embodiment of the present application, in the wave-transmitting synchronization system with multiple parallel PCS, the master PCS generates the carrier synchronization signal based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of each slave PCS and the frequency division coefficient of the frequency divider; and generating a power frequency synchronization signal based on the power frequency signal and the carrier synchronization signal of each slave PCS. The main PCS transmits the carrier synchronization signal and the power frequency synchronization signal to each auxiliary PCS through signal wires connected with each auxiliary PCS, each auxiliary PCS captures information carried by the carrier synchronization signal and the power frequency synchronization signal to adjust local frequency and phase, thereby realizing wave transmission synchronization, further being beneficial to inhibiting circulation among PCS and ensuring the stability of the PCS multi-machine parallel system.

Based on the description of the embodiment of the parallel-connected wave-transmitting synchronization system of the PCS, the application also provides a parallel-connected wave-transmitting synchronization method of the PCS, and the method can be applied to the system shown in fig. 1. Referring to fig. 3, fig. 3 is a flow chart of a method for synchronizing parallel transmission waves of a PCS according to an embodiment of the present application, and as shown in fig. 3, the method may include steps 301 to 305:

301: when the main PCS detects that each PCS is in an off-network working condition, the main PCS sends a parameter reporting signal to the auxiliary PCS;

302: under the condition that each slave PCS receives the parameter reporting signal, reporting the frequency of an output current signal of the local phase-locked loop frequency synthesizer, the frequency division coefficient of a frequency divider in the local phase-locked loop frequency synthesizer and a power frequency signal in a preset time period to the master PCS;

303: the master PCS obtains carrier synchronization signals based on the frequency of the output current signals of the local phase-locked loop frequency synthesizers of the slave PCS and the frequency division coefficient; and obtaining a power frequency synchronous signal based on the power frequency signal and the carrier synchronous signal of each slave PCS;

304: the master PCS transmits a carrier synchronization signal and a power frequency synchronization signal to each slave PCS;

305: each slave PCS carries out local adjustment based on the carrier synchronization signal and the power frequency synchronization signal so as to realize the wave transmission synchronization of a plurality of PCS.

It can be seen that, in the embodiment of the present application, the master PCS generates the carrier synchronization signal based on the frequency of the output current signal of the local pll frequency synthesizer of each slave PCS and the frequency division coefficient of the frequency divider; and generating a power frequency synchronization signal based on the power frequency signal and the carrier synchronization signal of each slave PCS. The main PCS transmits the carrier synchronization signal and the power frequency synchronization signal to each auxiliary PCS through signal wires connected with each auxiliary PCS, each auxiliary PCS captures information carried by the carrier synchronization signal and the power frequency synchronization signal to adjust local frequency and phase, thereby realizing wave transmission synchronization, further being beneficial to inhibiting circulation among PCS and ensuring the stability of the PCS multi-machine parallel system.

Wherein each slave PCS local phase-locked loop frequency synthesizer also comprises a phase discriminator; under the condition that each slave PCS receives the parameter report signal, the phase difference output by the phase discriminator is also reported to the master PCS; the master PCS obtains a carrier synchronization signal based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of each slave PCS and the frequency division coefficient, and the method comprises the following steps:

Under the condition that each slave PCS receives the parameter reporting signal, the circuit structure of the local phase-locked loop frequency synthesizer is also reported to the master PCS; the master PCS obtains the frequency range of the input current reference signal of the local phase-locked loop frequency synthesizer of each slave PCS based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of each slave PCS and the frequency division coefficient, and the method comprises the following steps:

Wherein the frequency divider in each slave PCS local phase-locked loop frequency synthesizer comprises frequency divider a; the master PCS obtains a frequency range of an input current reference signal of the local phase-locked loop frequency synthesizer of each slave PCS based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of each slave PCS, the frequency division coefficient and the corresponding frequency operation expression, and the method comprises the following steps:

The master PCS obtains a frequency range of an input current reference signal of the local phase-locked loop frequency synthesizer of each slave PCS based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of each slave PCS, the frequency division coefficient and the corresponding frequency operation expression, and the master PCS further comprises:

Wherein the master PCS determines a carrier frequency based on a frequency range of an input current reference signal of a local phase-locked loop frequency synthesizer of each slave PCS, comprising:

based on at least two candidate frequencies, a carrier frequency is obtained.

Wherein the main PCS determines a carrier phase based on the phase difference output from the phase detector, including:

The main PCS obtains power frequency synchronous signals based on the power frequency signals and carrier synchronous signals of all the auxiliary PCS, and the method comprises the following steps:

It should be noted that, since the method embodiment and the system embodiment are different presentation forms of the same technical concept, the specific implementation manner of the embodiment shown in fig. 3 may correspond to the related description in the system shown in fig. 1.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a PCS according to an embodiment of the present application. The PCS includes a processor 401, a memory 402, and a communication interface 403, which are interconnected by a bus 404. Wherein in some scenarios the processor 401 may also be referred to as a PCS controller.

Memory 402 includes, but is not limited to, random access memory (random access memory, RAM), read-only memory (ROM), erasable programmable read-only memory (erasable programmable read only memory, EPROM), or portable read-only memory (compact disc read-only memory, CD-ROM), with memory 402 for associated computer programs and data. The communication interface 403 is used to receive and transmit data.

The processor 401 may be one or more central processing units (central processing unit, CPU), and in the case where the processor 401 is one CPU, the CPU may be a single-core CPU or a multi-core CPU.

The PCS may be a master PCS or a slave PCS in the system shown in fig. 1, where, in the case that the PCS is the master PCS, the processor 401 in the PCS is configured to read the computer program code stored in the memory 402, and perform the following operations:

when detecting that each PCS is in an off-network working condition, sending a parameter reporting signal to the slave PCS; based on the frequency of the output current signal of each local phase-locked loop frequency synthesizer reported from PCS and the frequency division coefficient of the frequency divider, obtaining a carrier synchronization signal; and obtaining a power frequency synchronous signal based on the power frequency signal and the carrier synchronous signal reported from the PCS; transmitting the carrier synchronization signal and the power frequency synchronization signal to each slave PCS;

Wherein, in case the PCS is a slave PCS, the processor 401 in the PCS is configured to read the computer program code stored in the memory 402, and execute the following operations:

under the condition of receiving the parameter reporting signal, reporting the frequency of an output current signal of the local phase-locked loop frequency synthesizer, the frequency division coefficient of a frequency divider in the local phase-locked loop frequency synthesizer and a power frequency signal within a preset time period to a main PCS; and carrying out local adjustment based on the carrier synchronization signal and the power frequency synchronization signal so as to realize wave transmission synchronization of a plurality of PCS.

It should be noted that the implementation of the respective operations may also correspond to the respective description with reference to the system embodiment shown in fig. 1 or the method embodiment shown in fig. 3. It should be understood that the PCS provided in the embodiments of the present application may further include an Insulated Gate Bipolar Transistor (IGBT), a soft starter, a filter, etc., and fig. 4 is only an example and does not limit the PCS in any way.

The embodiments also provide a computer-readable storage medium (Memory) that is a Memory device in an information processing apparatus or an information transmitting apparatus or an information receiving apparatus, for storing programs and data. It will be appreciated that the computer readable storage medium herein may include a built-in storage medium in the PCS, or may include an extended storage medium supported by the PCS, or may include a storage medium used with the processor 401. Also stored in this memory space are one or more instructions, which may be one or more computer programs (including program code), adapted to be loaded and executed by processor 401. It should be noted that, the computer readable storage medium may be a random access memory (random access memory, RAM), a double rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR), etc., or may be a non-volatile memory (non-volatile memory), such as at least one disk memory; alternatively, it may be at least one computer-readable storage medium located remotely from the aforementioned processor 401. In one embodiment, one or more instructions stored in a computer-readable storage medium may be loaded and executed by the PCS to implement the method of PCS multi-machine parallel transmit synchronization shown in FIG. 3.

Embodiments of the present application also provide a computer program product, wherein the computer program product comprises a non-transitory computer readable storage medium storing a computer program operable to cause an apparatus to perform the method of PCS multi-machine parallel transmission synchronization shown in fig. 3. The computer program product may be a software installation package.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a household energy storage system according to an embodiment of the present application. As shown in fig. 5, the household energy storage system comprises an electric energy conversion device 2 (photovoltaic panel), a first user load 3 (street lamp), a second user load 4 (for example, household appliances such as an air conditioner) and the like, and an energy storage device 1, wherein the energy storage device 1 is a small energy storage box and can be installed on an outdoor wall in a wall-hanging manner. In particular, the photovoltaic panel can convert solar energy into electric energy during the low electricity price period, and the energy storage device 1 is used for storing the electric energy and supplying the electric energy to street lamps and household appliances for use during the electricity price peak or supplying power during the power failure/power outage of the power grid. It should be understood that the embodiment of fig. 5 of the present application is described by taking a household energy storage scenario in a user side energy storage as an example, and the drawing is an application diagram in a household energy storage scenario, and it should be understood that the energy storage device 1 in the present application is not limited to the household energy storage scenario.

The foregoing has outlined rather broadly the more detailed description of embodiments of the present application, wherein specific examples are provided herein to illustrate the principles and embodiments of the present application, the above examples being provided solely to assist in the understanding of the methods of the present application and the core ideas thereof; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims

1. The system is characterized by comprising a plurality of battery clusters and a plurality of PCSs corresponding to the battery clusters one by one, wherein the battery clusters are respectively connected with the direct current sides of the corresponding PCSs through power lines; the off-grid output ends of the PCS are connected with a distribution board through power lines, and the distribution board is electrically connected with a household load; the PCS comprises a master PCS, and PCS except the master PCS is a slave PCS; the master PCS and each slave PCS are communicated through a signal line;

the main PCS is used for sending parameter reporting signals to the auxiliary PCS when detecting that each PCS is in an off-network working condition;

each slave PCS is used for reporting the frequency of an output current signal of the local phase-locked loop frequency synthesizer, the frequency division coefficient of a frequency divider in the local phase-locked loop frequency synthesizer and a power frequency signal in a preset time period to the master PCS under the condition that the parameter reporting signal is received;

The master PCS is further configured to obtain a carrier synchronization signal based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of each slave PCS and the frequency division coefficient; and obtaining a power frequency synchronizing signal based on the power frequency signal of each slave PCS and the carrier synchronizing signal;

the master PCS is further configured to send the carrier synchronization signal and the power frequency synchronization signal to each slave PCS;

and each slave PCS is further used for carrying out local adjustment based on the carrier synchronization signal and the power frequency synchronization signal so as to realize the wave transmission synchronization of the PCS.

2. The system of claim 1 wherein each of said slave PCS local phase-locked loop frequency synthesizers further comprises a phase detector; each slave PCS also reports the phase difference output by the phase discriminator to the master PCS under the condition of receiving the parameter reporting signal;

the main PCS is specifically configured to:

obtaining the frequency range of the input current reference signal of each local phase-locked loop frequency synthesizer of the slave PCS based on the frequency of the output current signal of each local phase-locked loop frequency synthesizer of the slave PCS and the frequency division coefficient;

Determining a carrier frequency based on the frequency range of the input current reference signal of each of the slave PCS local phase-locked loop frequency synthesizers;

the carrier synchronization signal is generated based on the carrier frequency and the carrier phase.

3. The system of claim 2 wherein each of said slave PCS further reports the circuit structure of the local phase-locked loop frequency synthesizer to said master PCS upon receipt of said parameter report signal;

the main PCS is specifically configured to:

inquiring and obtaining frequency operation expressions corresponding to the circuit structures of the local phase-locked loop frequency synthesizers of the slave PCS based on the circuit structures of the local phase-locked loop frequency synthesizers of the slave PCS; the frequency operation expression is constructed by taking the frequency of an input current reference signal, the frequency of an output current signal and the frequency division coefficient of each local phase-locked loop frequency synthesizer of the slave PCS as parameters;

and obtaining the frequency range of the input current reference signal of each slave PCS local phase-locked loop frequency synthesizer based on the frequency of the output current signal of each slave PCS local phase-locked loop frequency synthesizer, the frequency division coefficient and the corresponding frequency operation expression.

4. The system of claim 3 wherein the divider in each of said slave PCS's local phase-locked loop frequency synthesizers comprises divider a;

the main PCS is specifically configured to:

for a first slave PCS in each slave PCS, calculating based on the frequency of an output current signal of a local phase-locked loop frequency synthesizer of the first slave PCS, a frequency division coefficient of a frequency divider A in the local phase-locked loop frequency synthesizer of the first slave PCS and a corresponding frequency calculation expression to obtain the minimum frequency of an input current reference signal of the local phase-locked loop frequency synthesizer of the first slave PCS; the first slave PCS is a slave PCS with the frequency division coefficient of the frequency divider A being larger than 1;

calculating based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of the first slave PCS, the reciprocal of the frequency dividing coefficient of the frequency divider A in the local phase-locked loop frequency synthesizer of the first slave PCS and a corresponding frequency calculation expression to obtain the maximum frequency of the input current reference signal of the local phase-locked loop frequency synthesizer of the first slave PCS;

5. The system of claim 4, wherein the master PCS is configured to:

for a second slave PCS in each slave PCS, calculating based on the frequency of an output current signal of a local phase-locked loop frequency synthesizer of the second slave PCS, a frequency division coefficient of a frequency divider A in the local phase-locked loop frequency synthesizer of the second slave PCS and a corresponding frequency calculation expression to obtain the maximum frequency of an input current reference signal of the local phase-locked loop frequency synthesizer of the second slave PCS; the second slave PCS is a slave PCS with the frequency division coefficient of the frequency divider A being more than 0 and less than 1;

calculating based on the frequency of the output current signal of the local phase-locked loop frequency synthesizer of the second slave PCS, the reciprocal of the frequency dividing coefficient of the frequency divider A in the local phase-locked loop frequency synthesizer of the second slave PCS and a corresponding frequency calculation expression to obtain the minimum frequency of the input current reference signal of the local phase-locked loop frequency synthesizer of the second slave PCS;

6. The system according to claim 2, wherein the master PCS is specifically configured to:

obtaining at least two candidate frequencies based on the frequency ranges of the input current reference signals of the local phase-locked loop frequency synthesizers of the slave PCS;

and obtaining the carrier frequency based on the at least two candidate frequencies.

7. The system according to claim 2, wherein the master PCS is specifically configured to:

the frequency of an input current reference signal of a local phase-locked loop frequency synthesizer is adjusted to be the carrier frequency, the phase of the input current reference signal of the local phase-locked loop frequency synthesizer is modulated, and the phase difference output by a phase discriminator in the local phase-locked loop frequency synthesizer after each phase modulation is captured;

8. The system according to claim 2, wherein the master PCS is specifically configured to:

determining a power frequency phase based on the phase estimation value corresponding to the power frequency signal of each slave PCS by the carrier phase of the carrier synchronous signal;

9. A method for synchronizing wave transmission of a plurality of PCS in parallel, which is applied to the system as claimed in any one of claims 1 to 8; the method comprises the following steps:

under the condition that each slave PCS receives the parameter reporting signal, reporting the frequency of an output current signal of a local phase-locked loop frequency synthesizer, a frequency division coefficient of a frequency divider in the local phase-locked loop frequency synthesizer and a power frequency signal within a preset time period to the master PCS;

the master PCS obtains carrier synchronization signals based on the frequency of the output current signals of the local phase-locked loop frequency synthesizers of the slave PCS and the frequency division coefficients; and obtaining a power frequency synchronizing signal based on the power frequency signal of each slave PCS and the carrier synchronizing signal;

The master PCS transmits the carrier synchronization signal and the power frequency synchronization signal to each slave PCS;

and each slave PCS carries out local adjustment based on the carrier synchronization signal and the power frequency synchronization signal so as to realize the wave transmission synchronization of the PCS.

10. A PCS comprising a memory storing a computer program and a processor, wherein the processor implements the steps of the method of claim 9 when executing the computer program.

11. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program for device execution, which computer program, when executed, implements the method as claimed in claim 9.