CN117153956A - Flip Micro-LED chip and preparation method thereof - Google Patents
Flip Micro-LED chip and preparation method thereof Download PDFInfo
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- CN117153956A CN117153956A CN202310877958.8A CN202310877958A CN117153956A CN 117153956 A CN117153956 A CN 117153956A CN 202310877958 A CN202310877958 A CN 202310877958A CN 117153956 A CN117153956 A CN 117153956A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 54
- 239000010980 sapphire Substances 0.000 claims abstract description 54
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 108
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000004205 dimethyl polysiloxane Substances 0.000 claims description 13
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000011148 porous material Substances 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 239000012790 adhesive layer Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 239000007772 electrode material Substances 0.000 claims description 5
- 239000012298 atmosphere Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- -1 polydimethylsiloxane Polymers 0.000 claims description 2
- 238000002310 reflectometry Methods 0.000 abstract description 4
- 238000000605 extraction Methods 0.000 abstract description 3
- 230000000052 comparative effect Effects 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 230000037303 wrinkles Effects 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/405—Reflective materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
Abstract
The invention discloses a flip-chip Micro-LED chip and a preparation method thereof, wherein the preparation method comprises the steps of sequentially growing an n-type AlGaN layer, a multiple quantum well active region layer, a p-type AlGaN layer and a p-type GaN layer on the surface of a sapphire unit; the inside of the sapphire unit is provided with orderly arranged air holes; and then etching the p-type GaN layer, the p-type AlGaN layer, the multiple quantum well active region layer and the n-type AlGaN layer, wherein the etched n-type AlGaN layer comprises a lower bottom, a shoulder and an upper bulge for a mesa structure, an n-type electrode is prepared on the shoulder of the etched n-type AlGaN layer, a p-type electrode is prepared on the surface of the etched p-type GaN layer, and a fold pattern is formed on the other surface of the sapphire unit after the n-type electrode and the p-type electrode are conducted by using a bonding pad, so that the flip-chip Micro-LED chip is obtained. The invention uses the high-reflectivity low-resistance Ni/Rh/Ni/Au electrode to form good ohmic contact with p-type GaN, and prepares the orderly arranged air holes and the fold patterns. The voltage of the flip-chip Micro-LED chip is reduced, the light extraction efficiency is enhanced, and the high-efficiency flip-chip Micro-LED chip is obtained.
Description
Technical Field
The invention relates to the technical field of semiconductor light-emitting devices, in particular to a flip-chip Micro-LED chip and a preparation method thereof.
Background
The flip Micro-LED adopts the reflection p electrode to reflect the emergent light of the active region to the emergent light of the sapphire surface, and compared with a horizontal structure, the emergent light efficiency of the chip can be effectively improved. However, the outgoing light generated from the active region of the flip-chip Micro-LED chip, after entering the sapphire substrate, is totally reflected at the sapphire-air interface until being absorbed by the chip and converted into heat energy, which also greatly limits the front-side light-emitting of the flip-chip Micro-LED chip. In addition, the p-type electrode of the traditional flip-chip Micro-LED chip has a strong light absorption effect, and the light emitting efficiency of the chip is further reduced.
Therefore, there is a need to improve the structure of flip-chip Micro-LEDs, increasing their light extraction efficiency.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a preparation method of a flip-chip Micro-LED chip, which comprises the following steps,
dividing a sapphire substrate into a plurality of identical sapphire units, and growing an epitaxial layer on the surface of each sapphire unit, wherein the epitaxial layer sequentially comprises an n-type AlGaN layer, a multiple quantum well active region layer, a p-type AlGaN layer and a p-type GaN layer from bottom to top;
etching the p-type GaN layer, the p-type AlGaN layer, the multiple quantum well active region layer and the n-type AlGaN layer, wherein the etched n-type AlGaN layer is of a mesa structure and comprises a lower bottom, a shoulder and an upper bulge, and the upper bulge is the same as the bottom area of the etched p-type GaN layer, the p-type AlGaN layer and the multiple quantum well active region layer;
step three, preparing an n-type electrode at the shoulder of the etched n-type AlGaN layer;
step four, preparing a p-type electrode on the surface of the etched p-type GaN layer;
depositing a silicon dioxide insulating layer on the shoulder of the etched n-type AlGaN layer and the surface of the etched p-type GaN layer, and then etching the silicon dioxide insulating layer to form an n-type through hole and a p-type through hole, so that the n-type electrode and the p-type electrode are communicated with the outside;
step six, respectively depositing an n-type bonding pad and a p-type bonding pad in the n-type through hole and the p-type through hole, and conducting an n-type electrode and a p-type electrode;
wherein, in the first step, the inside of the sapphire unit is provided with orderly arranged air holes,
or etching the inside of the sapphire unit in any one of the first step to the sixth step to form orderly arranged air holes;
the p-type electrode material comprises Ni/Rh/Ni/Au, and the thickness is respectively 2-10 nm, 20-200 nm, 10-100 nm and 50-200 nm. Wherein the deposition sequence is Ni, rh, ni, au.
Further, splitting each sapphire unit is further included after the sixth step.
Further, in the first step, the thicknesses of the sapphire unit, the n-type AlGaN layer, the multiple quantum well active region layer, the p-type AlGaN layer and the p-type GaN layer are respectively 100-500 mu m, 1-3 mu m, 100-500 nm, 10-100 nm and 10-500 nm;
in the second step, the shoulder height of the n-type AlGaN layer is 0.2-0.8 μm, and the bottom surface of the upper bump is rectangular with the length of 1-100 μm and the width of 1-100 μm.
In some embodiments of the present invention the sapphire substrate initially selected has an ordered array of pores within it.
In other embodiments of the present invention, the sapphire substrate initially selected does not have pores in an ordered arrangement, and then the sapphire unit may be etched in any one of the first to sixth steps to generate pores in an ordered arrangement.
Further, the spacing and diameter of the air holes are 4-6 μm and 1-3 μm, respectively.
Further, etching the inside of the sapphire unit by using laser hidden cutting equipment to form orderly arranged air holes;
laser parameters: the wavelength is 300-400 nm, the power is 0.1-0.6W, the repetition rate is 100kHz, the pulse duration is 20ps, and the focusing height is 50-80 mu m.
Further, in the first step, a rough surface is formed on the other surface of the epitaxial layer grown by the sapphire units with orderly arranged air holes,
or etching the inside of the sapphire unit in any one of the first step to the sixth step to form orderly arranged air holes, and forming a rough surface on the other surface of the epitaxial layer grown by the sapphire unit with orderly arranged air holes. The rough surface of the sapphire can scatter laser, so that the laser is focused in the sapphire, and the operation of etching the inside of the sapphire unit by utilizing the laser hidden cutting equipment to form orderly arranged air holes is required to be performed before the rough surface is prepared.
Further, forming a rough surface on the other side of the epitaxial layer grown by the sapphire unit with the orderly arranged air holes specifically comprises,
spin-coating an imprinting adhesive layer on the other surface of the epitaxial layer grown by the sapphire units with orderly arranged air holes, imprinting and curing by adopting a Polydimethylsiloxane (PDMS) stamp with a fold pattern to obtain the imprinting adhesive layer with the fold pattern;
etching the imprinting adhesive layer with the fold patterns, and forming the fold patterns on the surface of the other side of the epitaxial layer grown by the sapphire units with the orderly arranged air holes.
Further, the step three further comprises the step of after the n-type electrode is prepared on the shoulder part of the n-type AlGaN layer,
and performing first annealing in a protective gas atmosphere to enable the n-type electrode and the n-type AlGaN layer to form good ohmic contact. The protective gas can be nitrogen, the first annealing is carried out at 300-1000 ℃ for 30-200 s, the n-type electrode material comprises Ti/Al/Ti/Au, and the thickness is respectively 10-100 nm, 100-500 nm, 10-100 nm and 500-2000 nm. Wherein the deposition sequence is Ti, al, ti, au.
Further, the preparing the p-type electrode at the upper end of the p-type GaN layer in the fourth step further comprises,
performing second annealing in an oxygen atmosphere to enable the p-type electrode and the p-type GaN layer to form good ohmic contact;
the second annealing is kept at 300-700 ℃ for 30-100 s.
The invention also provides a flip-chip Micro-LED chip, which is obtained by using the preparation method.
Compared with the prior art, the invention has the following beneficial effects:
the invention uses the high-reflectivity low-resistance Ni/Rh/Ni/Au electrode to form good ohmic contact with p-type GaN, and prepares orderly arranged air holes and fold patterns in the sapphire substrate and on the surface by utilizing laser hidden cutting equipment and nano imprinting technology respectively. The voltage of the flip-chip Micro-LED chip is reduced, the light extraction efficiency is enhanced, and the high-efficiency flip-chip Micro-LED chip is obtained.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 shows a flow chart of a method of fabricating a flip-chip Micro-LED chip according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the structure of an epitaxial layer in an embodiment of the present invention;
fig. 3 (a) shows a schematic structural diagram of an etched epitaxial layer in the embodiment of the present invention, and fig. 3 (b) shows a schematic structural diagram of an etched n-type AlGaN layer;
FIG. 4 shows a side view of an n-type electrode in an embodiment of the invention;
FIG. 5 shows a top view of an n-type electrode in an embodiment of the invention;
FIG. 6 shows a side view of a p-type electrode in an embodiment of the invention;
FIG. 7 shows a top view of a p-type electrode in an embodiment of the invention;
FIG. 8 shows a side view of a p-type via and an n-type via in an embodiment of the invention;
FIG. 9 shows a top view of a p-type via and an n-type via in an embodiment of the invention;
FIG. 10 illustrates a side view of a p-type pad and an n-type pad in an embodiment of the invention;
FIG. 11 shows a top view of a p-type pad and an n-type pad in an embodiment of the invention;
FIG. 12 shows a side view of the distribution of air holes in an embodiment of the invention;
FIG. 13 shows a top view of the distribution of air holes in an embodiment of the invention;
FIG. 14 shows a microscopic view of the distribution of air holes in an embodiment of the invention;
FIG. 15 illustrates a side view of an embossed bond line in an embodiment of the invention;
FIG. 16 shows a schematic diagram of imprinting a PDMS stamp with a fold pattern in an embodiment of the present invention;
FIG. 17 is a schematic diagram of a PDMS stamp with a fold pattern removed after curing in an embodiment of the present invention;
FIG. 18 is a schematic diagram of a flip-chip Micro-LED chip according to an embodiment of the present invention;
FIG. 19 is a graph showing comparison of the results of the optical output power tests of the examples of the present invention and the comparative examples;
FIG. 20 shows the results of current voltage testing of flip-chip Micro-LED chips prepared in examples of the present invention and comparative example 6;
reference numerals illustrate:
201. a sapphire unit; 202', n-type AlGaN layers; 202. an etched n-type AlGaN layer; 2021. a lower bottom; 2022. a shoulder; 2023. an upper protrusion; 203', a multiple quantum well active region layer; 203. the etched multi-quantum well active region layer; 204', p-type AlGaN layers; 204. the etched p-type AlGaN layer; 205', p-type GaN layer; 205. the etched p-type GaN layer; 206. Ti/Al/Ti/Au n-type electrode; 207. Ni/Rh/Ni/Au p-type electrode; 208. a silicon dioxide insulating layer; 209. an n-type via; 210. a p-type via; 211. an n-type bonding pad; 212. a p-type bonding pad; 213. air holes; 214. stamping the adhesive layer; 215. an imprinting glue layer with a fold pattern; 216. PDMS stamp with fold pattern; 217. sapphire cells with a corrugated pattern.
Detailed Description
The endpoints of the ranges and any values disclosed in the present invention are not limited to the precise range or value, and the range or value should be understood to include values close to the range or value. For numerical ranges, one or more new numerical ranges may be obtained in combination with each other between the endpoints of each range, between the endpoint of each range and the individual point value, and between the individual point values, and are to be considered as specifically disclosed in the present invention.
The following description of specific embodiments of the present invention and the accompanying drawings will provide a clear and complete description of the technical solutions of embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The preparation method of the PDMS stamp with the fold pattern used in the embodiment comprises the following steps: the mixture of PDMS and a curing agent was spin-coated on a clean glass substrate, and then the glass substrate spin-coated with the mixture of PDMS and a curing agent was baked in a vacuum oven at 70 ℃ for 2 hours. And evaporating an aluminum film on the glass substrate by adopting a thermal evaporation technology to obtain the aluminum film with wrinkles. The liquid PDMS was poured onto the surface of the pleated aluminum film and placed in a vacuum box for 10 hours. Finally, heating at 80 ℃ for 1 hour in vacuum to obtain the PDMS stamp with the fold pattern.
Examples
As shown in fig. 1, a preparation method of a flip Micro-LED chip comprises the following steps:
s101, dividing a sapphire substrate with the thickness of 300 mu m into a plurality of identical sapphire units, and sequentially epitaxially growing n-type AlGaN layers 202', 300nm multiple quantum well active region layers 203', 50nm p-type AlGaN layers 204', 300nm p-type GaN layers 205' which have the same area as the sapphire units 201 and the thickness of 2 mu m respectively on the surface of the sapphire units 201 by utilizing a metal organic chemical vapor deposition technology to form epitaxial layers, wherein the epitaxial layers are shown in FIG. 2;
s102, etching the p-type GaN layer 205', the p-type AlGaN layer 204', the multiple quantum well active region layer 203' and the n-type AlGaN layer 202' of the epitaxial layer by utilizing an inductively coupled plasma etching technology until the n-type AlGaN layer 202' is exposed to form a mesa structure, as shown in fig. 2 and 3 (a); referring to fig. 3 (b), the etched n-type AlGaN layer 202 has a mesa structure including a lower bottom 2021, a shoulder 2022 and an upper bump 2023, wherein the area of the lower bottom 2021 is the same as that of the sapphire unit 201, the height of the shoulder 2022 is 0.5 μm, and the bottom area of the upper bump 2023 is the same as that of the etched p-type GaN layer 205, the etched p-type AlGaN layer 204 and the etched multiple quantum well active region layer 203, and is a rectangle with a length of 60 μm and a width of 50 μm;
s103, sputtering a cylindrical Ti/Al/Ti/Au n-type electrode 206 on the shoulder 2022 of the etched n-type AlGaN layer 202 by photoetching and magnetron sputtering technology, wherein the thicknesses of the cylindrical Ti/Al/Ti/Au n-type electrode 206 are respectively 50nm, 300nm, 50nm and 1000nm, as shown in FIG. 4 and FIG. 5, and annealing at a high temperature for 90S in a nitrogen environment at 900 ℃ so that the shoulder 2022 and the Ti/Al/Ti/Au n-type electrode 206 form good ohmic contact;
s104, sputtering a cylindrical Ni/Rh/Ni/Au p-type electrode 207 on the surface of the etched p-type GaN layer 205 by photoetching and magnetron sputtering technology, wherein the thicknesses of the Ni/Rh/Ni/Au p-type electrode 207 are 5nm, 100nm, 50nm and 100nm respectively, and annealing at high temperature for 60S in an oxygen environment at 600 ℃ as shown in FIG. 6 and FIG. 7, so that good ohmic contact is formed between the etched p-type GaN layer 205 and the Ni/Rh/Ni/Au p-type electrode 207;
s105, depositing a silicon dioxide insulating layer 208 with the same area as that of the sapphire unit 201 on the surface of the shoulder 2022 and the etched p-type GaN layer 205 by a plasma enhanced chemical vapor deposition technology, wherein the top of the silicon dioxide insulating layer 208 is higher than the Ni/Rh/Ni/Au p-type electrode 207, then etching the silicon dioxide insulating layer 208 to form an n-type through hole 209 and a p-type through hole 210 to open the Ti/Al/Ti/Au n-type electrode 206 and the Ni/Rh/Ni/Au p-type electrode 207 to the outside, and referring to FIGS. 8 and 9, the n-type through hole 209 presents a cylinder shape, and the p-type through hole 210 presents a cylinder shape;
s106, an n-type pad 211 and a p-type pad 212 are respectively deposited in an n-type through hole 209 and a p-type through hole 210 through a photoetching process and an electron beam evaporation process, and referring to FIG. 10 and FIG. 11, the p-type pad 212 is communicated with a Ni/Rh/Ni/Au p-type electrode 207 through the p-type through hole 210, and the n-type pad 211 is communicated with an n-electrode 206 through the n-type through hole 209;
s107, adopting laser hidden cutting equipment to focus and ablate orderly arranged air holes 213 in the sapphire unit, and laser parameters: the wavelength is 300nm, the power is 0.5W, the repetition rate is 100kHz, the pulse duration is 20ps, the focusing height is 50 μm, the pitch and diameter of the air holes 213 are 5 μm and 2 μm respectively, referring to FIGS. 12 and 13, the air holes 213 are spheres with a diameter of 2 μm, and FIG. 14 also shows a microscopic image of the orderly arranged air holes 213 in the sapphire cell;
s108, spin-coating a laminated glue layer 214 on the other surface of the epitaxial layer grown by the sapphire units 201 with the orderly arranged air holes 213, imprinting and curing by adopting the PDMS stamp 216 with the fold pattern, removing the PDMS stamp 216 with the fold pattern after curing to obtain the imprinted glue layer 215 with the fold pattern, wherein the imprinting process can refer to figures 15-17;
and S109, etching the structure obtained in the step S108 by adopting an inductively coupled plasma etching technology until the sapphire units 201 with the orderly arranged air holes 213 grow on the other surface of the epitaxial layer to form a fold pattern, and finally splitting each sapphire unit to obtain the flip-chip Micro-LED chip as shown in fig. 18.
Comparative example 1
Substantially the same as in example 1, except that: without step S107 and step S108, the prepared flip-chip Micro-LED chip has no air holes and no wrinkle pattern.
Comparative example 2
Substantially the same as in example 1, except that: without step S107, the prepared flip-chip Micro-LED chip has no air holes.
Comparative example 3
Substantially the same as in example 1, except that: without step S108, the prepared flip-chip Micro-LED chip has no wrinkle pattern.
Comparative example 4
Substantially the same as in example 1, except that: the pores obtained in step S107 had a pitch of 5 μm and a diameter of 5. Mu.m.
Comparative example 5
Substantially the same as in example 1, except that: the pores obtained in step S107 had a pitch of 3 μm and a diameter of 2. Mu.m
Comparative example 6
Substantially the same as in example 1, except that: sputtering in step S104 to obtain Ni/Au p-type electrode
The flip-chip Micro-LED chips prepared in examples and comparative examples 1 to 6 were subjected to an output power test, and the results are shown in fig. 19. It can be seen that the light output power of the Micro-LED of this example is significantly improved compared to comparative examples 1 to 5 due to the high reflectivity and low resistance Ni/Rh/Ni/Au p-type electrode, pores inside the sapphire unit, and the corrugated pattern of the surface.
The flip-chip Micro-LED chips prepared in examples and comparative example 6 were subjected to a current-voltage test, and the results are shown in fig. 20. It can be seen that the voltage of the Micro-LED of the example is reduced compared to comparative example 6 thanks to the high reflectivity low resistance Ni/Rh/Ni/Au p-type electrode.
Finally, it should be noted that: the foregoing description is only illustrative of the preferred embodiments of the present invention, and although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described, or equivalents may be substituted for elements thereof, and any modifications, equivalents, improvements or changes may be made without departing from the spirit and principles of the present invention.
Claims (9)
1. A preparation method of a flip Micro-LED chip is characterized by comprising the following steps,
dividing a sapphire substrate into a plurality of identical sapphire units, and growing an epitaxial layer on the surface of each sapphire unit, wherein the epitaxial layer sequentially comprises an n-type AlGaN layer, a multiple quantum well active region layer, a p-type AlGaN layer and a p-type GaN layer from bottom to top;
etching the p-type GaN layer, the p-type AlGaN layer, the multiple quantum well active region layer and the n-type AlGaN layer, wherein the etched n-type AlGaN layer is of a mesa structure and comprises a lower bottom, a shoulder and an upper bulge, and the upper bulge is the same as the bottom area of the etched p-type GaN layer, the p-type AlGaN layer and the multiple quantum well active region layer;
step three, preparing an n-type electrode at the shoulder of the etched n-type AlGaN layer;
step four, preparing a p-type electrode on the surface of the etched p-type GaN layer;
depositing a silicon dioxide insulating layer on the shoulder of the etched n-type AlGaN layer and the surface of the etched p-type GaN layer, and then etching the silicon dioxide insulating layer to form an n-type through hole and a p-type through hole, so that the n-type electrode and the p-type electrode are communicated with the outside;
step six, respectively depositing an n-type bonding pad and a p-type bonding pad in the n-type through hole and the p-type through hole, and conducting an n-type electrode and a p-type electrode;
wherein, in the first step, the inside of the sapphire unit is provided with orderly arranged air holes,
or etching the inside of the sapphire unit in any one of the first step to the sixth step to form orderly arranged air holes;
in the first step, a rough surface is formed on the other surface of the epitaxial layer grown by the sapphire units with orderly arranged air holes,
or etching the inside of the sapphire unit in any one of the first to sixth steps to form ordered pores, and forming a rough surface on the other surface of the epitaxial layer grown on the sapphire unit with ordered pores
The p-type electrode material comprises Ni/Rh/Ni/Au, and the thickness is respectively 2-10 nm, 20-200 nm, 10-100 nm and 50-200 nm.
2. The method of manufacturing a flip-chip Micro-LED chip according to claim 1, wherein the pitch and diameter of the air holes are 4 to 6 μm and 1 to 3 μm, respectively.
3. The method for manufacturing the flip-chip Micro-LED chip according to claim 1, wherein the inside of the sapphire unit is etched by using a laser dicing apparatus to form orderly arranged air holes;
laser parameters: the wavelength is 300-400 nm, the power is 0.1-0.6W, the repetition rate is 100kHz, the pulse duration is 20ps, and the focusing height is 50-80 mu m.
4. The method of fabricating a flip-chip Micro-LED chip according to claim 1, wherein the forming a rough surface on the other surface of the epitaxial layer grown with the porous sapphire cells in an ordered arrangement comprises,
spin-coating an imprinting adhesive layer on the other surface of the epitaxial layer grown by the sapphire units with orderly arranged air holes, imprinting and curing by adopting a polydimethylsiloxane seal with fold patterns to obtain the imprinting adhesive layer with the fold patterns;
etching the imprinting adhesive layer with the fold patterns, and forming the fold patterns on the surface of the other side of the epitaxial layer grown by the sapphire units with the orderly arranged air holes.
5. The method of fabricating a flip-chip Micro-LED chip according to claim 1, further comprising, after the n-type electrode is fabricated on the shoulder of the n-type AlGaN layer in step three,
performing first annealing in a protective gas atmosphere to enable the n-type electrode and the n-type AlGaN layer to form good ohmic contact;
the n-type electrode material comprises Ti/Al/Ti/Au, and the thickness of the n-type electrode material is respectively 10-100 nm, 100-500 nm, 10-100 nm and 500-2000 nm;
the first annealing is kept at 300-1000 ℃ for 30-200 s.
6. The method of fabricating a flip-chip Micro-LED chip according to claim 1, wherein fabricating a p-type electrode on the upper end of the p-type GaN layer in the fourth step further comprises,
performing second annealing in an oxygen atmosphere to enable the p-type electrode and the p-type GaN layer to form good ohmic contact;
the second annealing is kept at 300-700 ℃ for 30-200 s.
7. The method of fabricating a flip-chip Micro-LED chip according to claim 1, wherein the thicknesses of the sapphire unit, the n-type AlGaN layer, the multiple quantum well active region layer, the p-type AlGaN layer and the p-type GaN layer in the first step are 100 to 500 μm, 1 to 3 μm, 100 to 500nm, 10 to 100nm and 10 to 500nm, respectively;
in the second step, the shoulder height of the n-type AlGaN layer is 0.2-0.8 μm, and the bottom surface of the upper bump is rectangular with the length of 1-100 μm and the width of 1-100 μm.
8. The method of manufacturing a flip-chip Micro-LED chip according to any one of claims 1 to 7, further comprising splitting each sapphire unit after step six.
9. A flip-chip Micro-LED chip, characterized in that it is obtained using the manufacturing method according to any one of claims 1 to 8.
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| CN202310877958.8A CN117153956A (en) | 2023-07-17 | 2023-07-17 | Flip Micro-LED chip and preparation method thereof |
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