CN117153886A - Graphene ohmic contact diamond planar gate VDMOS device and preparation method thereof - Google Patents
Graphene ohmic contact diamond planar gate VDMOS device and preparation method thereof Download PDFInfo
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- CN117153886A CN117153886A CN202311298225.5A CN202311298225A CN117153886A CN 117153886 A CN117153886 A CN 117153886A CN 202311298225 A CN202311298225 A CN 202311298225A CN 117153886 A CN117153886 A CN 117153886A
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 80
- 229910021389 graphene Inorganic materials 0.000 title claims abstract description 80
- 229910003460 diamond Inorganic materials 0.000 title claims abstract description 40
- 239000010432 diamond Substances 0.000 title claims abstract description 40
- 238000002360 preparation method Methods 0.000 title abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims abstract description 46
- 238000009413 insulation Methods 0.000 claims abstract description 13
- 229910002804 graphite Inorganic materials 0.000 claims abstract description 6
- 239000010439 graphite Substances 0.000 claims abstract description 6
- -1 graphite alkene Chemical class 0.000 claims abstract description 6
- 238000013461 design Methods 0.000 claims abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 66
- 230000000903 blocking effect Effects 0.000 claims description 53
- 230000003197 catalytic effect Effects 0.000 claims description 24
- 238000000151 deposition Methods 0.000 claims description 23
- 238000005229 chemical vapour deposition Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 8
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses a graphene ohmic contact diamond planar gate VDMOS device and a preparation method thereof, and relates to the technical field of semiconductors.A drain metal layer is arranged at the bottommost end of the device, a graphene layer and an N-buffer zone are arranged above the drain metal layer, the top of the N-buffer zone is in a convex design, a P-type base region is arranged at the outer side of the top of the N-buffer zone, and the P-type base region also covers the upper surface of the N-buffer zone; the upper surface outside of P type base region also is provided with the graphite alkene layer, the top of graphite alkene layer is provided with source metal layer and high K gate insulation layer, the upper surface of high K gate insulation layer is provided with the gate metal layer. The invention has the advantages of low contact resistance and source region resistance, can reduce the on-resistance of the device, is manufactured based on diamond materials, and has the advantages of small volume, strong severe environment resistance, good high-frequency characteristic and small on-resistance.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a graphene ohmic contact diamond planar gate VDMOS device and a preparation method thereof.
Background
Diamond in a diamond planar gate VDMOS (metal-oxide-semiconductor field effect transistor) device is used as an ultra-wide band gap semiconductor, and its excellent electrical performance, voltage withstanding property, and heat conduction property are widely paid attention to and studied. The current diamond research is mainly focused on the device structure and working mechanism which are the same as the traditional power device, and the problem of larger ohmic contact resistance exists due to the limitation of the development stage of the process.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a graphene ohmic contact diamond planar gate VDMOS device and a preparation method thereof, so as to solve the problems in the background art.
In order to achieve the above purpose, the present invention provides the following technical solutions: the diamond planar gate VDMOS device comprises a graphene ohmic contact, wherein a drain metal layer is arranged at the bottommost end of the device, a graphene layer is arranged above the drain metal layer, an N-buffer region is arranged above the graphene layer, the top of the N-buffer region is of a convex design, a P-type base region is arranged outside the top of the N-buffer region, and the P-type base region also covers the upper surface of the N-buffer region;
the upper surface outside of P type base region also is provided with the graphite alkene layer, the top of graphite alkene layer is provided with source metal layer, the top of N-buffer district and P type base region is provided with high K gate insulation layer, the upper surface of high K gate insulation layer is provided with the gate metal layer.
According to the technical scheme, the graphene layer positioned on the outer side of the upper surface of the P-type base region is flush with the heights of the P-type base region and the N-buffer region.
According to the technical scheme, the device is designed longitudinally, and ohmic contacts of a source metal layer and a drain metal layer of the device are constructed through contact of metal and a graphene layer.
According to the technical scheme, the graphene layer is an active region of the device, and the graphene layer and the P-type base region form a heterojunction for switching off a conductive channel of the device.
Further optimizing the technical scheme, the gate insulating medium of the high-K gate insulating layer adopts silicon dioxide.
The preparation method of the graphene ohmic contact diamond planar gate VDMOS device comprises the following specific steps of:
s1, depositing a graphene catalytic layer below an N-buffer area, annealing the graphene catalytic layer at 1100 ℃ for 3 minutes to catalyze a drain electrode to form graphene, removing the catalytic layer, and forming a drain electrode metal layer through deposition after the graphene layer is formed;
s2, a blocking layer is deposited on the upper portion of the N-buffer area through chemical vapor deposition, photoresist is smeared on the blocking layer, the photoresist at the exposed position is removed by using a photoresist solution through exposing the through hole of the photoresist, the blocking layer is further etched, a P-type base region through hole is formed, and P-type ion implantation is carried out at the through hole;
s3, a blocking layer is deposited on the upper portion of the N-buffer area through chemical vapor deposition, photoresist is smeared on the blocking layer, the photoresist at the exposed position is removed through a photoresist solution by exposing the through hole of the photoresist, the blocking layer is etched, a graphene layer through hole is formed, a graphene catalytic layer is deposited, and the graphene catalytic layer is annealed for 3 minutes at 1100 ℃;
s4, removing the catalytic layer, the blocking layer and the photoresist, depositing the blocking layer on the N-buffer area by chemical vapor deposition, smearing the photoresist on the blocking layer, exposing the through hole part of the photoresist, removing the photoresist at the exposed part by using a photoetching solution to etch the blocking layer, forming a source metal through hole, and depositing a source metal layer on the through hole;
s5, removing the blocking layer and the photoresist, depositing the blocking layer by chemical vapor deposition above the N-buffer region, smearing the photoresist on the blocking layer, exposing the through hole part of the photoresist, removing the photoresist at the exposed part by using a photoresist solution to etch the blocking layer, forming a high-K gate insulating layer through hole, and depositing silicon dioxide above the high-K gate insulating layer through hole;
s6, removing the blocking layer and the photoresist, depositing the blocking layer by chemical vapor deposition above the N-buffer area, smearing the photoresist on the blocking layer, exposing the through hole part of the photoresist, removing the photoresist at the exposed part by using a photoresist solution to further etch the blocking layer, forming a gate metal through hole, and depositing a gate metal layer above the gate insulation layer through hole.
Further optimizing the technical scheme, in the step S2, when the P-type ions are implanted, the ions are boron, and the formed ion concentration is 2 x 10 16 cm -3 -6*10 16 cm -3 。
Further optimizing the technical scheme, in the steps S1 and S3, the graphene catalytic layer is nickel or copper.
Compared with the prior art, the invention provides a graphene ohmic contact diamond planar gate VDMOS device and a preparation method thereof, and the graphene ohmic contact diamond planar gate VDMOS device has the following beneficial effects:
according to the diamond planar gate VDMOS device with the graphene ohmic contact and the preparation method, a planar gate VDMOS structure is adopted, the ohmic contacts of the source electrode and the drain electrode are made of graphene and metal, the advantages of low contact resistance and source region resistance are achieved, the on-resistance of the device can be reduced, and the diamond planar gate VDMOS device is manufactured based on diamond materials and has the advantages of being small in size, strong in severe environment resistance, good in high-frequency characteristic and small in on-resistance.
Drawings
Fig. 1 is a schematic device cross-section diagram of a graphene ohmic contact diamond planar gate VDMOS device according to the present invention;
fig. 2 is a schematic cross-sectional view of a device in step S1 in a method for manufacturing a graphene ohmic contact diamond planar gate VDMOS device according to the present invention;
fig. 3 is a schematic cross-sectional view of a device in step S2 in the method for manufacturing a graphene ohmic contact diamond planar gate VDMOS device according to the present invention;
fig. 4 is a schematic cross-sectional view of a device in step S3 in the method for manufacturing a graphene ohmic contact diamond planar gate VDMOS device according to the present invention;
fig. 5 is a schematic cross-sectional view of a device in step S4 in the method for manufacturing a graphene ohmic contact diamond planar gate VDMOS device according to the present invention;
fig. 6 is a schematic cross-sectional view of a device in step S5 in a method for manufacturing a graphene ohmic contact diamond planar gate VDMOS device according to the present invention;
fig. 7 is a schematic cross-sectional view of a device in step S6 in a method for manufacturing a graphene ohmic contact diamond planar gate VDMOS device according to the present invention.
In the figure: 1. a drain metal layer; 2. a graphene layer; 3. an N-buffer area; 4. a P-type base region; 5. a source metal layer; 6. a high-K gate insulating layer; 7. a gate metal layer; 8. and a graphene catalytic layer.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Embodiment one:
referring to fig. 1, a diamond planar gate VDMOS device with graphene ohmic contact is disclosed, the device is designed longitudinally, ohmic contacts of a source metal layer 5 and a drain metal layer 1 of the device are both formed by contact of metal and a graphene layer 2, the bottom end of the device is provided with the drain metal layer 1, the graphene layer 2 is arranged above the drain metal layer 1, the preparation process is compatible with diamond materials, the electron mobility is high, the resistance is small, an N-buffer zone 3 is arranged above the graphene layer 2, the top of the N-buffer zone 3 is designed in a convex manner, a P-type base region 4 is arranged outside the top of the N-buffer zone 3, and the P-type base region 4 also covers the upper surface of the N-buffer zone 3.
The graphene layer 2 is an active region of the device, and the graphene layer 2 and the P-type base region 4 form a heterojunction for switching off a conductive channel of the device.
The upper surface outside of P type base region 4 also is provided with graphene layer 2, the top of graphene layer 2 is provided with source metal layer 5, the top of N-buffer district 3 and P type base region 4 is provided with high K gate insulation layer 6, the gate insulation medium of high K gate insulation layer 6 adopts silica, and is close with traditional silicon technology, and the manufacturing degree of difficulty is low, the upper surface of high K gate insulation layer 6 is provided with gate metal layer 7.
The graphene layer 2 positioned on the outer side of the upper surface of the P-type base region 4 is flush with the heights of the P-type base region 4 and the N-buffer region 3.
In conclusion, the device adopts a planar gate VDMOS structure, ohmic contacts of a source electrode and a drain electrode are both graphene and metal contacts, the advantages of low contact resistance and source region resistance are achieved, the on-resistance of the device can be reduced, and the device has the advantages of small size, strong severe environment resistance, good high-frequency characteristics and small on-resistance based on diamond material manufacturing.
Embodiment two:
the preparation method of the graphene ohmic contact diamond planar gate VDMOS device is based on the graphene ohmic contact diamond planar gate VDMOS device in the first embodiment, and comprises the following specific steps:
s1, as shown in FIG. 2, a graphene catalytic layer 8 is deposited below an N-buffer area 3, the graphene catalytic layer 8 is nickel or copper, material damage is reduced through catalytic preparation without means such as ion implantation, device quality is improved, the graphene catalytic layer 8 is annealed for 3 minutes at 1100 ℃, a drain electrode is catalyzed to form graphene, the catalytic layer is removed, and a drain electrode metal layer 1 is formed through deposition after the graphene layer 2 is formed;
s2, as shown in FIG. 3, a chemical vapor deposition blocking layer is coated on the upper part of the N-buffer region 3, photoresist is partially exposed through the through hole of the photoresist, the photoresist at the exposed part is removed by using a photoresist solution, then the blocking layer is etched, a P-type base region 4 through hole is formed, P-type ion implantation is carried out at the through hole, the ion is boron, and the formed ion concentration is 2 x 10 16 cm -3 -6*10 16 cm -3 ；
S3, as shown in FIG. 4, a blocking layer is deposited on the upper side of the N-buffer area 3 by chemical vapor deposition, photoresist is smeared on the blocking layer, the photoresist at the exposed part is removed by using a photoetching solution through exposing the through hole part of the photoresist, then the blocking layer is etched, a through hole of the graphene layer 2 is formed, a graphene catalytic layer 8 is deposited, the graphene catalytic layer 8 is nickel or copper, and the graphene catalytic layer is annealed for 3 minutes at 1100 ℃;
s4, as shown in FIG. 5, removing the catalytic layer, the blocking layer and the photoresist, depositing the blocking layer by chemical vapor deposition above the N-buffer area 3, smearing the photoresist on the blocking layer, exposing the through hole part of the photoresist, removing the photoresist at the exposed part by using a photoresist solution to etch the blocking layer, forming a source metal through hole, and depositing a source metal layer 5 above the through hole;
s5, as shown in FIG. 6, removing the blocking layer and the photoresist, depositing the blocking layer by chemical vapor deposition above the N-buffer region 3, smearing the photoresist on the blocking layer, exposing the through hole part of the photoresist, removing the photoresist at the exposed part by using a photoresist solution to etch the blocking layer, forming a through hole of the high-K gate insulating layer 6, and depositing silicon dioxide above the through hole of the high-K gate insulating layer 6;
s6, as shown in FIG. 7, removing the blocking layer and the photoresist, depositing the blocking layer by chemical vapor deposition above the N-buffer area 3, smearing the photoresist on the blocking layer, exposing the through hole part of the photoresist, removing the photoresist at the exposed part by using a photoresist solution to further etch the blocking layer, forming a gate metal through hole, and depositing a gate metal layer 7 above the gate insulation layer through hole.
The beneficial effects of the invention are as follows:
according to the diamond planar gate VDMOS device with the graphene ohmic contact and the preparation method, a planar gate VDMOS structure is adopted, the ohmic contacts of the source electrode and the drain electrode are made of graphene and metal, the advantages of low contact resistance and source region resistance are achieved, the on-resistance of the device can be reduced, and the diamond planar gate VDMOS device is manufactured based on diamond materials and has the advantages of being small in size, strong in severe environment resistance, good in high-frequency characteristic and small in on-resistance.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. The diamond planar gate VDMOS device is characterized in that a drain electrode metal layer is arranged at the bottommost end of the device, a graphene layer is arranged above the drain electrode metal layer, an N-buffer area is arranged above the graphene layer, the top of the N-buffer area is of a convex design, a P-type base area is arranged on the outer side of the top of the N-buffer area, and the P-type base area also covers the upper surface of the N-buffer area;
the upper surface outside of P type base region also is provided with the graphite alkene layer, the top of graphite alkene layer is provided with source metal layer, the top of N-buffer district and P type base region is provided with high K gate insulation layer, the upper surface of high K gate insulation layer is provided with the gate metal layer.
2. The graphene ohmic contact diamond planar gate VDMOS device of claim 1, wherein the graphene layer outside the upper surface of the P-type base region is level with the heights of the P-type base region and the N-buffer region.
3. The graphene ohmic contact diamond planar gate VDMOS device of claim 1 wherein the device is of a vertical design, and the ohmic contacts of the source metal layer and the drain metal layer of the device are both made by contact of metal and graphene layers.
4. The graphene ohmic contact diamond planar gate VDMOS device of claim 1, wherein the graphene layer is an active region of the device, and the graphene layer and the P-type base region form a heterojunction for turning off a conductive channel of the device.
5. The graphene ohmic contact diamond planar gate VDMOS device of claim 1, wherein the gate insulating medium of the high K gate insulating layer is silicon dioxide.
6. A method for preparing a graphene ohmic contact diamond planar gate VDMOS device, which is prepared based on the graphene ohmic contact diamond planar gate VDMOS device according to any one of claims 1 to 5, and is characterized by comprising the following specific steps:
s1, depositing a graphene catalytic layer below an N-buffer area, annealing the graphene catalytic layer at 1100 ℃ for 3 minutes to catalyze a drain electrode to form graphene, removing the catalytic layer, and forming a drain electrode metal layer through deposition after the graphene layer is formed;
s2, a blocking layer is deposited on the upper portion of the N-buffer area through chemical vapor deposition, photoresist is smeared on the blocking layer, the photoresist at the exposed position is removed by using a photoresist solution through exposing the through hole of the photoresist, the blocking layer is further etched, a P-type base region through hole is formed, and P-type ion implantation is carried out at the through hole;
s3, a blocking layer is deposited on the upper portion of the N-buffer area through chemical vapor deposition, photoresist is smeared on the blocking layer, the photoresist at the exposed position is removed through a photoresist solution by exposing the through hole of the photoresist, the blocking layer is etched, a graphene layer through hole is formed, a graphene catalytic layer is deposited, and the graphene catalytic layer is annealed for 3 minutes at 1100 ℃;
s4, removing the catalytic layer, the blocking layer and the photoresist, depositing the blocking layer on the N-buffer area by chemical vapor deposition, smearing the photoresist on the blocking layer, exposing the through hole part of the photoresist, removing the photoresist at the exposed part by using a photoetching solution to etch the blocking layer, forming a source metal through hole, and depositing a source metal layer on the through hole;
s5, removing the blocking layer and the photoresist, depositing the blocking layer by chemical vapor deposition above the N-buffer region, smearing the photoresist on the blocking layer, exposing the through hole part of the photoresist, removing the photoresist at the exposed part by using a photoresist solution to etch the blocking layer, forming a high-K gate insulating layer through hole, and depositing silicon dioxide above the high-K gate insulating layer through hole;
s6, removing the blocking layer and the photoresist, depositing the blocking layer by chemical vapor deposition above the N-buffer area, smearing the photoresist on the blocking layer, exposing the through hole part of the photoresist, removing the photoresist at the exposed part by using a photoresist solution to further etch the blocking layer, forming a gate metal through hole, and depositing a gate metal layer above the gate insulation layer through hole.
7. The method for preparing a graphene ohmic contact diamond planar gate VDMOS device as defined in claim 6, wherein in step S2, the ions are boron and the concentration of the ions is 2×10 during P-type ion implantation 16 cm -3 -6*10 16 cm -3 。
8. The method for manufacturing a graphene ohmic contact diamond planar gate VDMOS device according to claim 6, wherein in the steps S1 and S3, the graphene catalytic layer is nickel or copper.
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| JP2012033731A (en) * | 2010-07-30 | 2012-02-16 | Mitsubishi Electric Corp | Power semiconductor device |
| CN109273354A (en) * | 2018-09-07 | 2019-01-25 | 中国电子科技集团公司第十三研究所 | Diamond device and preparation method thereof |
| CN115244651A (en) * | 2020-03-17 | 2022-10-25 | 日立能源瑞士股份公司 | Insulated gate structure, wide band gap material power device with insulated gate structure and manufacturing method thereof |
| CN115312389A (en) * | 2022-06-30 | 2022-11-08 | 北京清芯昇能半导体有限公司 | Method for manufacturing semiconductor device having vertical structure and semiconductor device |
| CN115632031A (en) * | 2022-12-21 | 2023-01-20 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of planar gate silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) integrated with gate protection mechanism |
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2023
- 2023-10-09 CN CN202311298225.5A patent/CN117153886A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012033731A (en) * | 2010-07-30 | 2012-02-16 | Mitsubishi Electric Corp | Power semiconductor device |
| CN109273354A (en) * | 2018-09-07 | 2019-01-25 | 中国电子科技集团公司第十三研究所 | Diamond device and preparation method thereof |
| CN115244651A (en) * | 2020-03-17 | 2022-10-25 | 日立能源瑞士股份公司 | Insulated gate structure, wide band gap material power device with insulated gate structure and manufacturing method thereof |
| CN115312389A (en) * | 2022-06-30 | 2022-11-08 | 北京清芯昇能半导体有限公司 | Method for manufacturing semiconductor device having vertical structure and semiconductor device |
| CN115632031A (en) * | 2022-12-21 | 2023-01-20 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of planar gate silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) integrated with gate protection mechanism |
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