CN117149425A - Domain controller, domain control method, domain control device, and storage medium - Google Patents

Domain controller, domain control method, domain control device, and storage medium Download PDF

Info

Publication number
CN117149425A
CN117149425A CN202311122912.1A CN202311122912A CN117149425A CN 117149425 A CN117149425 A CN 117149425A CN 202311122912 A CN202311122912 A CN 202311122912A CN 117149425 A CN117149425 A CN 117149425A
Authority
CN
China
Prior art keywords
processor
path
switcher
output port
target device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311122912.1A
Other languages
Chinese (zh)
Inventor
周晓飞
许剑斌
胡斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avatr Technology Chongqing Co Ltd
Original Assignee
Avatr Technology Chongqing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Avatr Technology Chongqing Co Ltd filed Critical Avatr Technology Chongqing Co Ltd
Priority to CN202311122912.1A priority Critical patent/CN117149425A/en
Publication of CN117149425A publication Critical patent/CN117149425A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Hardware Redundancy (AREA)

Abstract

The application discloses a domain controller, a method, equipment and a storage medium, wherein the domain controller comprises a first processor, a second processor, a switcher, a microprocessor MCU and an output port; wherein the MCU is connected with the switcher; the output port is respectively connected with the first processor and the second processor through the switcher so as to form a first passage and a second passage; the output port is used for accessing the target equipment; the MCU is used for: and under the condition that the target equipment is accessed, controlling the switcher to sequentially conduct the first path and the second path so as to realize data processing between the first processor and the target equipment and between the second processor and the target equipment. The domain controller improves the data transmission efficiency and the accuracy of the data transmission.

Description

Domain controller, domain control method, domain control device, and storage medium
Technical Field
The present application relates to the field of vehicle technology, and relates to, but is not limited to, domain controllers, methods, devices, and storage media.
Background
With the continuous development of vehicle technology, more and more data need to be processed by the cabin controller. In order to increase the processing efficiency of the cabin domain controller, load balancing is typically achieved by two processors.
For data transmission between the output port of the cabin domain controller and the two processors, in the related art, generally all data is transmitted to the main processor through the output port, and the main processor retransmits the data belonging to the sub-processor.
It can be seen that, in the related art, when data is transmitted, data belonging to sub-processing needs to be transmitted to the main processor and then transmitted to the sub-processor by the main processor, so that all transmission efficiency is low; and in the process of transmitting the main processor to the sub-processor, there is possibility of data transmission errors, so the accuracy is low.
Disclosure of Invention
The application provides a domain controller, a method, equipment and a storage medium, which improve the data transmission efficiency and the accuracy of data transmission.
The technical scheme of the application is realized as follows:
in a first aspect, the present application provides a domain controller, where the domain controller includes a first processor, a second processor, a switcher, a microprocessor MCU, and an output port;
wherein the MCU is connected with the switcher; the output port is respectively connected with the first processor and the second processor through the switcher so as to form a first passage and a second passage;
the output port is used for accessing the target equipment;
the MCU is used for: and under the condition that the target equipment is accessed, controlling the switcher to sequentially conduct the first path and the second path so as to realize data processing between the first processor and the target equipment and between the second processor and the target equipment.
In a second aspect, the present application provides a data processing method applied to a domain controller of a vehicle device, the domain controller including a first processor, a second processor, a switch, and an output port; the output port is respectively connected with the first processor and the second processor through the switcher to form a first passage and a second passage; the method comprises the following steps:
when detecting that the target equipment is connected to the output port of the domain processor, controlling the switcher to conduct a first passage; the first path is used for data transmission between the first processor and target equipment; controlling the switcher to conduct the second path under the condition that the first condition is met; the second path is for data transfer between the second processor and the target device.
In a third aspect, the present application also provides a vehicle device comprising the domain controller provided in the first aspect.
In a fourth aspect, the present application also provides a storage medium, on which a computer program is stored, which when executed implements any one of the data processing methods provided by the present application.
The application provides a domain controller, a method, equipment and a storage medium, wherein the domain controller comprises a first processor, a second processor, a switcher, a microprocessor MCU and an output port; wherein the MCU is connected with the switcher; the output port is respectively connected with the first processor and the second processor through the switcher so as to form a first passage and a second passage; the output port is used for accessing the target equipment; the MCU is used for: and under the condition that the target equipment is accessed, controlling the switcher to sequentially conduct the first path and the second path so as to realize data processing between the first processor and the target equipment and between the second processor and the target equipment.
In the scheme of the application, a switcher is added in the domain controller to form a first passage and a second passage, and the first passage and the second passage are controlled to be sequentially conducted through the MCU, so that data processing between the first processor and the target equipment and between the second processor and the target equipment is automatically realized through the two passages. It can be seen that when data processing is performed between the first processor and the target device and between the second processor and the target device, the data processing can be realized based on respective paths, so that the situation that the data is transmitted to the first processor and then transmitted to the second processor by the first processor is avoided, and the data transmission efficiency and the data transmission accuracy are improved.
Drawings
FIG. 1 is a schematic diagram of an alternative architecture of a domain controller according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an alternative domain controller according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an alternative configuration of a domain controller according to an embodiment of the present application;
FIG. 4A is a schematic flow chart of an alternative method for processing data according to an embodiment of the present application;
FIG. 4B is a schematic flow chart of another alternative data processing method according to an embodiment of the present application;
FIG. 5 is a schematic diagram of an alternative configuration of a domain controller according to an embodiment of the present application;
fig. 6 is a schematic flow chart of a first alternative upgrade process according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application more clear, the specific technical solutions of the application will be described in further detail below with reference to the accompanying drawings in the embodiments of the present application. The following examples are illustrative of the application and are not intended to limit the scope of the application.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
In the following description, the term "first\second\third" is merely used for example to distinguish different objects, and does not represent a specific ordering for the objects, and does not have a limitation of precedence order. It is to be understood that the "first-/second-/third-" may interchange specific orders or precedence when allowed to enable embodiments of the application described herein to be implemented in other than those illustrated or described herein.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the application only and is not intended to be limiting of the application.
Embodiments of the present application provide a domain controller, a method, an apparatus, and a storage medium.
In a first aspect, the present embodiment provides a domain controller, referring to the content shown in fig. 1, the domain controller 10 may include: a first processor 101, a second processor 102, a switch 103, a microprocessor (Microcontroller Unit, MCU) 104, an output port 105.
The MCU104 is connected with the switcher 103; the output port 105 is connected with the first processor 101 and the second processor 102 through the switcher 103 respectively to form a first path and a second path;
the output port 105 is used for accessing the target device 20;
the MCU104 is configured to: in the case of the target device 20 being accessed, the control switch 103 sequentially turns on the first path and the second path to realize data processing between the first processor 101 and the target device 20, and between the second processor 102 and the target device 20.
Wherein:
domain controller 10 refers to a controller having related functions. By way of example, the domain controller 10 may be a cabin domain controller in a vehicle device.
Illustratively, the first processor 101 may be a main processor and the second processor 102 may be a sub-processor; alternatively, the first processor 101 may be a sub-processor and the second processor 102 may be a main processor.
The main processor refers to a processor which must exist in the domain controller. The embodiment of the application does not limit the information such as the type of the main processor, and can be configured according to actual conditions.
Sub-processors, which may or may not be processors in the domain controller. The embodiment of the application does not limit the information such as the type of the sub-processor, and can be configured according to actual conditions.
For the switcher 103, switching of the paths is performed. The specific type of the switch 103 in the embodiment of the present application is not limited, and may be configured according to actual situations. Illustratively, the switch 103 may be a multiple-way switch.
For the MCU104, it is used to assist in implementing related control functions implemented by non-processors within the domain controller. The embodiment of the application does not limit the specific type of the MCU104, and can be configured according to actual situations.
For the output port 105, for accessing the target device. The embodiment of the present application does not limit the specific type of the output port 105, and may be configured according to actual situations. By way of example, the output port 105 may be a universal serial bus (Universal Serial Bus, USB) port.
For the target device 20, for accessing the cabin controller 10 through the output port 105. The target device has a port corresponding to the output port 105. By way of example, the target device may be an electronic device having a USB port. By way of example, the target device 20 may include, but is not limited to, any of the following: USB flash disk, tablet, etc.
A path refers to a channel that may be made up of multiple devices for transmitting a data link. The first path and the second path refer to paths which are respectively conducted when the switcher corresponds to two switching states respectively.
For the connection relationship between the devices in the domain controller 10, the MCU104 is connected to the switch 103. Here, the MCU104 is connected to the switch 103 through a control line so that the MCU104 can transmit a control signal to the switch 103.
The output port 105 is connected to the second processor 102 and the first processor 101 via the switch 103, respectively, to form a first path and a second path.
Specifically, the first path may include, connected in order: an output port 105, a switch 103, and a first processor 101; alternatively, the first processor 101, the switch 103, and the output port 105.
The second path may include, connected in sequence: an output port 105, a switch 103, and a second processor 102; or the second processor 102, the switch 103 and the output port 105.
The MCU104 is configured to: in the case of the target device 20 being accessed, the control switch 103 sequentially turns on the first path and the second path to achieve data processing between the first processor 101 and the target device 20 and between the second processor 102 and the target device 20.
Here, the order of conduction of the first and second passages is not particularly limited. For example, the first passage may be conducted and the second passage may be conducted; alternatively, the second passage may be connected by a pilot, and the first passage may be connected by a pilot.
The data processing here may include output transmission, as well as processing of data.
It should be noted that, the specific number of the processors included in the domain controller is not limited only in the embodiment of the present application, and may be configured according to practical situations. If the number of processors is greater than two, the number of switches of the switch 103 is adjusted accordingly. When data is actually transmitted, a transmission path of one processor is led to transmit the data, and then the transmission path of the other processor is led to transmit the data, so that all the processors are traversed in the same way to transmit the data.
The domain controller provided by the embodiment of the application comprises a first processor, a second processor, a switcher, a microprocessor MCU and an output port; wherein the MCU is connected with the switcher; the output port is respectively connected with the first processor and the second processor through the switcher so as to form a first passage and a second passage; the output port is used for accessing the target equipment; the MCU is used for: and under the condition that the target equipment is accessed, controlling the switcher to sequentially conduct the first path and the second path so as to realize data processing between the first processor and the target equipment and between the second processor and the target equipment.
In the scheme of the application, a switcher is added in the domain controller to form a first passage and a second passage, and the first passage and the second passage are controlled to be sequentially conducted through the MCU, so that data processing between the first processor and the target equipment and between the second processor and the target equipment is automatically realized through the two passages. It can be seen that when data processing is performed between the first processor and the target device and between the second processor and the target device, the data processing can be realized based on respective paths, so that the situation that the data is transmitted to the first processor and then transmitted to the second processor by the first processor is avoided, and the data transmission efficiency and the data transmission accuracy are improved.
Next, a description will be given of how the MCU104 sequentially turns on the first path and the second path.
The process will be described with the first processor as a sub-processor and the second processor as a main processor.
Specifically, but not limited to, case 1 or case 2 described below.
In the case 1, the MCU controls to conduct the transmission channel of the sub-processor firstly and then conduct the transmission channel of the main processor so as to conduct data transmission;
and 2, the MCU controls the transmission path of the main processor to be conducted firstly, and then the transmission path of the sub-processor to be conducted so as to conduct data transmission.
Next, the MCU control in case 1 turns on the transmission path of the sub-processor first and then turns on the transmission path of the main processor to perform data transmission.
In the case that the target device 20 is accessed, the MCU controls the switch 103 to turn on the first path, so as to realize data transmission between the target device 20 and the sub-processor 101A based on the first path.
The first passage includes: the target device, the output port, the switch, the sub-processor.
Reference is made to what is shown in fig. 2, wherein the bold line identifies the conductive path.
In a possible implementation, in case that the target device 20 is detected to be connected to the domain controller 10 through the output port 105, the MCU controls the switch 103 to switch to the first switch on state to turn on the first path of the sub-processor, so that the target device 20 transmits data to the sub-processor 101A through the first path (target device 20-output port 105-switch 103-sub-processor 101A).
In another possible implementation, in case that the target device 20 is detected to be connected to the domain controller 10 through the output port 105, the MCU controls the switch 103 to switch to the first switch on state to turn on the first path of the sub-processor, so that the sub-processor 101A transmits data to the target device 20 through the first path (sub-processor 101A-output port 105-switch 103-target device 20).
In case the first condition is met, the MCU controls the switch 103 to turn on the second path to enable data transfer between the target device 20 and the main processor 102A based on the second path.
Illustratively, the first condition may include: the data transfer between the target device 20 and the sub-processor 101A is completed.
The second passage sequentially comprises: the target device, the output port, the switch, the host processor.
Since the output port 105 can only transmit serial data, it is necessary to switch the channel after completing one transmission and then perform the second transmission.
Reference is made to what is shown in fig. 3, wherein the bold line identifies the conductive path.
In a possible implementation, when it is detected that the data transmission between the target device 20 and the sub-processor 101A is completed, the MCU controls the switch 103 to switch to the second switch on state to turn on the second path of the main processor 102A, so that the target device 20 transmits data to the main processor 102A through the second path (the target device 20-output port 105-the switch 103-the main processor 102A).
In another possible implementation, the MCU controls the switch 103 to switch to the second switch on state to turn on the second path of the main processor 102A to cause the main processor 102A to transmit data to the target device 20 via the second path (main processor 102A-output port 105-switch 103-target device 20) upon detecting that the first condition is met.
Next, a process of conducting the transmission path of the main processor and then conducting the transmission path of the sub-processor by the MCU control in case 2 to perform data transmission will be described.
In the case where the target device 20 is accessed, the control switch 103 turns on the second path to realize data transmission between the target device 20 and the main processor 102A based on the second path.
In the case that the second condition is satisfied, the switch 103 is controlled to turn on the first path to realize data transfer between the target device 20 and the sub-processor 101A based on the first path.
The second condition may include: the data transfer between the target device 20 and the host processor 102A is complete.
Case 2 differs from case 1 in that the order in which the first passage and the second passage are turned on is different. The specific implementation of case 2 may refer to the detailed description in case 1, and will not be described in detail here.
Compared with the case 1, the case 2 leads to the transmission path of the main processor, so that the data transmission effect of the main processor can be ensured to the greatest extent. Compared with the case 2, the case 1 performs data transmission of the sub-processor first, and finally performs data transmission of the main processor. In this way, the last state of the switch can be set on the transmission link of the main processor, and the output port can be used further after the data transmission is completed. For example, the main processor integrates the multimedia application, so after the data transmission is completed, the access of the multimedia application can still be performed through the output port, and the use of the output port can be ensured to the greatest extent.
In order to maximize the use of the output port 105, if the MCU adopts the transmission scheme in case 2, the MCU may further switch to the transmission path of the main processor after completing the data transmission of the sub-processor, so as to ensure the use of the output port 105.
Next, a control method of the MCU104 will be described.
In one possible implementation, the MCU104 sends a first level signal to the switch 103 to turn on the first path; the MCU104 transmits a second level signal to the switch 103 to turn on the second path.
The embodiment of the application does not limit the first level signal and the second level signal in particular, and can be configured according to actual conditions. For example, the first level information signal may be a high level signal and the second level signal may be a low level signal. Alternatively, the first level information signal may be a low level signal and the second level signal may be a high level signal.
For the case of a plurality of sub-processors 101A, at least 3 level signals are required here. Illustratively, it may be specifically configured as 001, 010, 100, etc. Wherein, 1 corresponds to high level and 0 corresponds to low level.
Next, the output port 105 will be described.
In one possible implementation, the output port 105 may be a universal serial bus, USB, port.
In another possible implementation, output port 105 may be a TYP-C port.
In yet another possible implementation, the output port 105 may be a lightning (lightning) port.
It will be appreciated that the output port 105 may also be other data transmission ports, which are not listed here.
In a second aspect, the present embodiment provides a data processing method applied to a domain controller of a vehicle device.
In one possible implementation, the domain controller includes a first processor, a second processor, a switch, and an output port; the output port is connected with the first processor and the second processor through the switcher respectively to form a first passage and a second passage.
The following describes a data processing method provided in the embodiment of the present application.
Referring to what is shown in fig. 4A, the process may include, but is not limited to, S401A and S402A described below.
S401A, when detecting that the target device is connected to the output port of the domain processor, controlling the switcher to conduct the first path.
The first path is for data transmission between the first processor and a target device.
When the target device is accessed to the output port, the output port is triggered to send a corresponding notification message to indicate that a new device is input.
In one possible implementation, the MCU controls the switch to be in a first switching state to turn on the first path.
In another possible embodiment, the first processor controls the switch to be in the first switching state to turn on the first path.
In yet another possible embodiment, the second processor controls the switch to be in the first switching state to turn on the first path.
It will be appreciated that controlling the switch to conduct the first path may be accomplished by electronics having associated capabilities, such as a first processor, a second processor, an MCU, or a switch having control capabilities, etc.
The specific implementation process may refer to the detailed description about the MCU function, and will not be described in detail here.
S402A, when a first condition is satisfied, controlling the switch to turn on the second path.
The second path is for data transfer between the second processor and the target device.
The specific implementation may refer to the detailed description of the MCU function side, and will not be described in detail herein.
Similar to the switching on of the first path, here the control switch to switch on the second path may be implemented by electronics with associated capabilities, e.g. a first processor, a second processor, an MCU or a switch with control capabilities, etc.
The data processing method provided by the embodiment of the application comprises the following steps: when detecting that the target equipment is connected to the output port of the domain processor, controlling the switcher to conduct a first passage; the first path is used for data transmission between the first processor and target equipment; controlling the switcher to conduct the second path under the condition that the first condition is met; the second path is for data transfer between the second processor and the target device.
In the scheme of the application, a switcher is added in the domain controller to form a first path and a second path, and the first path and the second path are controlled to be conducted in sequence, so that data processing between the first processor and the target equipment and between the second processor and the target equipment is automatically realized through the two paths. It can be seen that when data processing is performed between the first processor and the target device and between the second processor and the target device, the data processing can be realized based on respective paths, so that the situation that the data is transmitted to the first processor and then transmitted to the second processor by the first processor is avoided, and the data transmission efficiency and the data transmission accuracy are improved.
In another possible implementation, the domain controller includes a first processor, a second processor, a switch, a microprocessor MCU, an output port; wherein the MCU is connected with the switcher; the output port is respectively connected with the first processor and the second processor through the switcher so as to form a first passage and a second passage;
the following describes a data processing method provided by an embodiment of the present application.
Fig. 4B is a flowchart of a data processing method according to an embodiment of the application.
Referring to the content shown in fig. 4B, the data processing method may include, but is not limited to, S401B to S404B shown in fig. 4B.
S401B, when detecting that the target device is accessed to the output port of the domain processor, the MCU controls the switcher to conduct the first channel.
When the target device is accessed to the output port, the output port is triggered to send a corresponding notification message to indicate that a new device is input.
Here, the MCU controls the switch to be in the first switching state to turn on the first path.
The specific implementation process may refer to the detailed description about the MCU function, and will not be described in detail here.
S402B, based on the first path, data transmission is carried out between the first processor and the target equipment.
The first processor herein may be a main processor; alternatively, the first processor may also be a sub-processor.
The implementation of S402B may refer to detailed description of the MCU function side, and will not be described herein.
S403B, when the first condition is satisfied, the MCU controls the switcher to turn on the second path.
The specific implementation of S403B may refer to the detailed description of the MCU function side, and will not be described herein.
S404B, based on the second path, the second processor performs data transmission with the target device.
The second processor is different from the first processor, and is a sub-processor in the case that the first processor is a main processor, and is a main processor in the case that the first processor is a sub-processor.
The specific implementation of S404B may refer to the detailed description of the MCU function side, and will not be described herein.
The data processing method provided by the embodiment of the application comprises the following steps: when detecting that target equipment is connected to an output port of the cabin processor, the MCU controls the switcher to conduct a first passage; based on the first path, data transmission is carried out between the first processor and target equipment; the MCU controls the switcher to conduct the second path under the condition that the first condition is met; based on the second path, data is transferred between the second processor and the target device.
In the scheme of the application, a switcher is added in the domain controller to form a first passage and a second passage, and the first passage and the second passage are controlled to be sequentially conducted through the MCU, so that data processing between the first processor and the target equipment and between the second processor and the target equipment is automatically realized through the two passages. It can be seen that when data processing is performed between the first processor and the target device and between the second processor and the target device, the data processing can be realized based on respective paths, so that the situation that the data is transmitted to the first processor and then transmitted to the second processor by the first processor is avoided, and the data transmission efficiency and the data transmission accuracy are improved.
The data processing method provided by the embodiment of the application can further comprise the step of carrying out data transmission based on the second path of the first path. The process may also correspond to the process of transmitting data between the first processor and the target device based on the first path in S402B, and the process of transmitting data between the second processor and the target device based on the second path in S404B.
The process may include, but is not limited to, any of cases a to C described below.
The method comprises the steps that A, an upgrade package is transmitted based on a first path and a second path;
the case B, based on the first path and the second path, transmitting the test program;
case C, log information is transmitted based on the first path and the second path.
Next, a procedure of transmitting an upgrade package based on the first path and the second path in case a will be described.
In case a, based on the first path, the first processor receives a first upgrade packet sent by the target device, and the first processor performs upgrade based on the first upgrade packet.
The first upgrade package is an upgrade package of the first processor.
After the first upgrade package is sent to the first processor, an upgrade program of the first processor may be automatically started for installation. Or after the upgrade packages of the two processors are sent, the upgrade program is started for installation.
Specifically, if the installation is successful, the upgrade is successful, and if the installation is failed, the version is automatically reset to the version before the upgrade.
In case a, based on the second path, the second processor receives a second upgrade packet sent by the target device, and the second processor upgrades based on the second upgrade packet.
The second upgrade package is an upgrade package of the second processor.
After the second upgrade package is sent to the second processor, the upgrade program of the second processor may be automatically started for installation. Alternatively, the upgrade packages of both processors may be installed at other times (e.g., a preset time).
Specifically, if the installation is successful, the upgrade is successful, and if the installation is failed, the version is automatically reset to the version before the upgrade.
In case B, based on the first path, the first processor receives a first test program sent by the target device, and the first processor performs a test based on the first test program. .
The first test program herein refers to a test program of the first processor.
After the first test program is sent to the first processor, the first test program can be automatically started to test the first processor. Or, after the test programs of the two processors are all sent, the test program is started again for testing.
In case B, based on the second path, the second processor receives a second test program sent by the target device, and the second processor performs a test based on the second test program.
The second test program herein refers to a test program of the second processor.
After the second test program is sent to the second processor, the second test program can be automatically started to test the second processor. Or, after the test programs of the two processors are all sent, the test program is started again for testing.
In case C, based on the first path, the first processor receives first log information sent by the target device.
The first log information refers to log information of the first processor.
In case C, based on the second path, the first processor receives second log information sent by the target device.
The second log information refers to log information of the second processor.
The embodiment of the application does not limit the specific content of the log information and the specific application of the log information, and can be determined according to actual conditions.
Next, the first processor, the second processor, the first path, and the second path will be described.
In one possible implementation, in case the first processor comprises a sub-processor; the first passage includes: the target device, the output port, the switch, and the sub-processor.
Briefly, the first passageway comprises: target device-output port-switcher-sub-processor; or, a sub-processor-output port-switcher-target device.
In the case where the second processor includes a main processor, the second path includes: the target device, the output port, the switch, and the host processor.
Briefly, the second path includes: target device-output port-switcher-main processor; or, a host processor-output port-switcher-target device.
Therefore, the data of the first path is transmitted first, which is equivalent to the data of the sub-processor, so that the data of the main processor is transmitted last, and the data is in the transmission state of the second path when the transmission is completed.
In a further possible embodiment of the present application,
the first processor includes a main processor; the first passage sequentially comprises: the target device, the output port, the switch, and the host processor;
the second processor includes a sub-processor; the second passage sequentially comprises: the target device, the output port, the switch, and the sub-processor.
Therefore, the data of the first path is transmitted first, which is equivalent to the data of the main processor, and then the data of the sub-processor is transmitted last, so that the data transmission of the main processor can be ensured to the greatest extent, and the reliability is higher.
Next, a process of controlling the switch to turn on the first path in S401A and a process of controlling the switch to turn on the second path in S402A will be described.
In one possible implementation of the method according to the application,
controlling the switcher to conduct the first path comprises the following steps: a first level signal is sent to the switch to turn on the first path based on the first level signal.
The specific reference may be made to the description of the control manner of the MCU104 in the domain controller, which is not described herein.
Controlling the switch to conduct the second path includes: a second level signal is sent to the switch to turn on the second path based on the second level signal.
The specific reference may be made to the description of the control manner of the MCU104 in the domain controller, which is not described herein.
Here, for transmitting a first level signal to the switcher to turn on the first path based on the first level signal; alternatively, the process of sending the second level signal to the switch to turn on the second path based on the second level signal may be performed (completed) by the MCU, or may be performed by the first processor, the second processor, or the switch with related processing capability.
In the following, an upgrade procedure is taken as an example, and a domain controller and a data processing method provided by the present application are described by a detailed embodiment.
Referring to the content shown in fig. 5, the domain controller includes: a-core processor 501 (corresponding to the first processor or the main processor), B-core processor 502 (corresponding to the second processor or the sub-processor), USB switch503, USB interface 504 (corresponding to the output port), and MCU505.
The a-core processor 501 and the B-core processor 502 are respectively connected to a USB switch (switch) 503, and the USB switch (switch) 503 is also respectively connected to a USB interface 504 and an MCU505.
The MCU505 is used to control the USB switch503 to switch to implement a connection with the A-core processor 501 or with the B-core processor 502.
In practice, the components in fig. 5 except for USB are disposed in the vehicle, and the USB is disposed and outside the vehicle for accessing external devices.
The function of the USB switch is to allow the USB to establish a connection with the A core/B core to transfer the system upgrade package (or program package) of the A core/B core stored in the USB.
Next, the upgrading process will be described. Specifically, the process may include, but is not limited to, steps 1 to 6 described below.
And step 1, inserting USB equipment, and controlling the USB SWITCH to be switched to the B core by the MCU so that the B core is connected with the USB.
And 2, transmitting an upgrade package corresponding to the B core through the USB equipment, and installing the upgrade package to the B core to finish the upgrade.
And step 3, if the B core fails to upgrade, rolling back to the state before upgrading.
And 4, if the upgrading of the core B is successful, the MCU controls the USB SWITCH to be switched to the core A, so that the core A is connected with the USB.
And 5, transmitting an upgrade package corresponding to the A core through the USB equipment, and installing the upgrade package by the A core to finish the upgrade.
And step 6, if the upgrading of the core A fails, rolling back to the state before upgrading.
In addition, for the switching time of "the MCU controls the USB SWITCH to SWITCH to the A core" in the step 4, besides the success of the B core upgrade, the USB can also transmit the B core upgrade packet to the B core.
Briefly, referring to what is shown in fig. 6, the upgrade process may include, but is not limited to, S601 to S605 described below.
S601, inserting a U disk, and preparing for upgrading;
s602, the MCU controls the USB switch to be firstly switched to the core B;
s603, upgrading the core B until success;
s604, the MCU controls the USB switch to be switched to the core A;
s605, core a upgrades until successful.
It should be noted that, upgrade B first, upgrade A, can guarantee on A of USB mount last, on the one hand, the application of the multimedia is on A, can guarantee the usability of the multimedia application; on the other hand, after the main control is pulled out or fails from the core A, the core B can be ensured to be normally used based on the USB interface.
In a third aspect, the present application also provides a vehicle apparatus comprising any one of the domain controllers described above.
In a fourth aspect, the present application further provides a storage medium, where a computer program is stored, where any one of the data processing methods provided by the embodiments of the present application is implemented when the computer program on the storage medium is executed.
It should be noted that, regarding the description of the storage medium, similar to the description of the data processing method described above, the description of the beneficial effects similar to the data processing method is not repeated. In addition, for technical details not disclosed in the device embodiments of the present application, please refer to the description of the data processing method embodiments.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.
The units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing module, or each unit may be separately used as one unit, or two or more units may be integrated in one unit; the integrated units may be implemented in hardware or in hardware plus software functional units. Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware associated with program instructions, where the foregoing program may be stored in a computer readable storage medium, and when executed, the program performs steps including the above method embodiments; and the aforementioned storage medium includes: a mobile storage device, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk or an optical disk, or the like, which can store program codes.
The methods disclosed in the method embodiments provided by the application can be arbitrarily combined under the condition of no conflict to obtain a new method embodiment.
The features disclosed in the several product embodiments provided by the application can be combined arbitrarily under the condition of no conflict to obtain new product embodiments.
The features disclosed in the embodiments of the method or the apparatus provided by the application can be arbitrarily combined without conflict to obtain new embodiments of the method or the apparatus.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. The domain controller is characterized by comprising a first processor, a second processor, a switcher, a microprocessor MCU and an output port;
wherein the MCU is connected with the switcher; the output port is respectively connected with the first processor and the second processor through the switcher so as to form a first passage and a second passage;
the output port is used for accessing the target equipment;
the MCU is used for: and under the condition that the target equipment is accessed, controlling the switcher to sequentially conduct the first path and the second path so as to realize data processing between the first processor and the target equipment and between the second processor and the target equipment.
2. The domain controller of claim 1, wherein, in the case where the first processor is a sub-processor and the second processor is a main processor,
under the condition that the target equipment is accessed, the MCU controls the switcher to conduct the first passage so as to realize data transmission between the target equipment and the sub-processor based on the first passage; the first passage includes: the target device, the output port, the switcher, the sub-processor;
in the case that a first condition is met, the MCU controls the switcher to conduct the second path so as to realize data transmission between the target equipment and the main processor based on the second path; the second passage includes: the target device, the output port, the switch, the host processor.
3. The domain controller of claim 2, wherein the domain controller comprises,
the MCU sends a first level signal to the switcher to conduct the first channel;
the MCU sends a second level signal to the switcher to turn on the second path.
4. A domain controller according to any of claims 1-3, wherein the output port comprises a universal serial bus USB port.
5. A data processing method, wherein the method is applied to a domain controller of a vehicle device, and the domain controller comprises a first processor, a second processor, a switcher and an output port; the output port is respectively connected with the first processor and the second processor through the switcher to form a first passage and a second passage; the method comprises the following steps:
when detecting that the target equipment is connected to the output port of the domain processor, controlling the switcher to conduct a first passage; the first path is used for data transmission between the first processor and target equipment;
controlling the switcher to conduct the second path under the condition that the first condition is met; the second path is for data transfer between the second processor and the target device.
6. The method of claim 5, wherein the method further comprises:
based on the first path, the first processor receives a first upgrade packet sent by the target device, and the first processor upgrades based on the first upgrade packet;
based on the second path, the second processor receives a second upgrade packet sent by the target device, and the second processor upgrades based on the second upgrade packet;
or,
based on the first path, the first processor receives a first test program sent by the target device, and the first processor performs a test based on the first test program;
based on the second path, the second processor receives a second test program sent by the target device, and the second processor performs a test based on the second test program;
or,
based on the first path, the first processor receives first log information sent by the target device;
based on the second path, the first processor receives second log information sent by the target device.
7. The method according to claim 5 or 6, wherein,
in the case where the first processor includes a sub-processor; the first passage includes: the target device, the output port, the switch, and the sub-processor;
in the case where the second processor comprises a main processor; the second passage includes: the target device, the output port, the switch, and the host processor.
8. The method according to claim 5 or 6, wherein,
controlling the switcher to conduct the first path comprises the following steps: transmitting a first level signal to the switch to turn on the first path based on the first level signal;
controlling the switch to conduct the second path includes: a second level signal is sent to the switch to turn on the second path based on the second level signal.
9. A vehicle device comprising the domain controller of any one of claims 1 to 4.
10. A computer readable storage medium having a computer program stored thereon, which when executed, implements the data processing method of any of claims 5 to 8.
CN202311122912.1A 2023-08-31 2023-08-31 Domain controller, domain control method, domain control device, and storage medium Pending CN117149425A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311122912.1A CN117149425A (en) 2023-08-31 2023-08-31 Domain controller, domain control method, domain control device, and storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311122912.1A CN117149425A (en) 2023-08-31 2023-08-31 Domain controller, domain control method, domain control device, and storage medium

Publications (1)

Publication Number Publication Date
CN117149425A true CN117149425A (en) 2023-12-01

Family

ID=88911435

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311122912.1A Pending CN117149425A (en) 2023-08-31 2023-08-31 Domain controller, domain control method, domain control device, and storage medium

Country Status (1)

Country Link
CN (1) CN117149425A (en)

Similar Documents

Publication Publication Date Title
US8521929B2 (en) Virtual serial port management system and method
US7139861B2 (en) Input/output unit access switching system and method
US4684885A (en) Arrangement for on-line diagnostic testing of an off-line standby processor in a duplicated processor configuration
CN106557446B (en) Bus system
US20110179211A1 (en) Bios architecture
US20070285394A1 (en) Kvm switch system capable of transmitting keyboard-mouse data and receiving video data through single cable
US20100082846A1 (en) Usb device and method for connecting the usb device with usb host
CN101727430B (en) Method and device for hot plug of card
CN107391419B (en) Support general sequence busbar concentrator of many host computers and automobile-used host computer
US20120093203A1 (en) Data communication method, communication device, and communication system
US20140149617A1 (en) I2c bus structure and device availability query method
CN112015689B (en) Method, system and device for switching serial port output paths and switch
CN111813599A (en) Solid-state storage device, server mainboard and control method
CN107111568A (en) System and method for driver installation file to be presented when enabling USB equipment
CN108920962A (en) Firmware downloads sign test method, firmware dissemination method, mobile terminal and server
CN117149425A (en) Domain controller, domain control method, domain control device, and storage medium
CN103793180A (en) Disk collocation method and server rack system
US20070204088A1 (en) Modularized circuit board bus connection control method and system
CN108268210B (en) Information processing method, computing node and storage node
CN115361432A (en) Communication control method and device between master device and slave device, vehicle and storage medium
US9246848B2 (en) Relay apparatus, storage system, and method of controlling relay apparatus
JP2000040040A (en) Data communication device and storage medium storing program
CN107274589B (en) Access method and system of financial self-service terminal hardware equipment and terminal equipment
CN109343387B (en) Data communication method, device, equipment and air conditioner
US8378998B2 (en) Electronic device, control method thereof and electronic control system including the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination