CN117135994B - Method for manufacturing semiconductor device and semiconductor device - Google Patents
Method for manufacturing semiconductor device and semiconductor device Download PDFInfo
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- CN117135994B CN117135994B CN202311386718.4A CN202311386718A CN117135994B CN 117135994 B CN117135994 B CN 117135994B CN 202311386718 A CN202311386718 A CN 202311386718A CN 117135994 B CN117135994 B CN 117135994B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims description 29
- 238000005530 etching Methods 0.000 claims abstract description 59
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 21
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 224
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 230000005641 tunneling Effects 0.000 claims description 13
- 238000010884 ion-beam technique Methods 0.000 claims description 9
- 238000001020 plasma etching Methods 0.000 claims description 9
- 239000002356 single layer Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 abstract description 36
- 238000011065 in-situ storage Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 description 12
- 230000000694 effects Effects 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005265 energy consumption Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 230000005415 magnetization Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000005355 Hall effect Effects 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/80—Constructional details
Abstract
The invention provides a manufacturing method of a semiconductor device and the semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: etching the photoresist layer, the hard mask film layer and the magnetic tunnel junction film layer to form a Magnetic Tunnel Junction (MTJ), and forming a focusing structure at the bottom of the MTJ; depositing a dielectric layer, wherein the dielectric layer wraps the hard mask film layer and the Magnetic Tunnel Junction (MTJ) and covers the bottom electrode layer and the top of the Footing structure; and etching the dielectric layer, removing the hard mask film layer, the bottom electrode layer and the dielectric layer at the top of the patterning structure, and etching a groove around the bottom side wall of the Magnetic Tunnel Junction (MTJ) to cut off the patterning structure. After patterning the Magnetic Tunnel Junction (MTJ) to form a patterning structure, a dielectric layer is deposited firstly to perform in-situ protection on the side wall and the bottom electrode layer of the Magnetic Tunnel Junction (MTJ) and the patterning structure, then the dielectric layer in the horizontal direction is etched, a groove is formed around the Magnetic Tunnel Junction (MTJ), and the patterning structure is cut off, so that the influence of the patterning is solved.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.
Background
A non-volatile magnetic memory SOT-MRAM (Spin-orbit torque magnetic random access memory) for storing information by utilizing magnetic resistance characteristics is expected to replace an existing memory with excellent performances such as high read-write speed, high stability, non-volatility and the like. The working principle of the SOT-MRAM is to read and write information by utilizing the magnetic resistance difference of the magnetic tunnel junction (magnetic tunnel junction, MTJ) in different states. The magnetic tunnel junction MTJ comprises a sandwich structure of a free layer, an oxide tunneling layer, and a fixed layer, wherein the magnetization direction of the fixed layer is constant and can be changed by a current flowing through a heavy metal layer with spin hall effect. When the magnetization directions of the fixed layer and the free layer are the same, the magnetic tunnel junction MTJ exhibits a low resistance, for example, to the outside, and a high resistance, for example, to the outside. The two states of high and low resistance can represent 0 and 1 in the memory of the computer for information storage.
When the magnetic tunnel junction MTJ is etched, a foot (writing) structure is formed that causes the write current Ic to increase and the coercive field Hc to decrease, so that the writing efficiency decreases. The reasons for the formation of Footing include: 1) Shadow effect during ion beam etching (Ions Beam Etching, IBE), i.e. when using IBE to pattern the magnetic tunnel junction MTJ, in order to avoid sidewall redeposition, the carrier on which the wafer is typically placed will be at a certain angle to the ion beam, and shadow effect makes the bottom etching amount of the magnetic tunnel junction MTJ pillar smaller, forming a patterning structure; 2) The etching is stopped on the bottom electrode, namely, in order to avoid etching the bottom electrode and causing the sidewall redeposition to cause the short circuit failure of the device, the etching is stopped on the bottom electrode below the tunneling layer, and a Footing structure is formed on the bottom electrode. The Footing structure brings a plurality of adverse effects, on one hand, the existence of Footing can lead write current to generate shunt, the shunt in Footing has no SOT effect, current efficiency is reduced, working current is increased, and energy consumption of the Magnetic Tunnel Junction (MTJ) for storing information is increased; on the other hand, the existence of the Footing structure can reduce the tunneling magneto-resistance effect (Tunneling Magnetoresistance Effect, TMR) and the coercive field Hc, and increase the read-write error rate of the SOT-MRAM. The existing method for solving the problem of the Footing is to use IBE to carry out secondary etching on the Footing structure, however, the method cannot fundamentally solve the problem of the Footing due to the existence of shadows.
Disclosure of Invention
An object of an embodiment of the present invention is to provide a method of manufacturing a semiconductor device capable of fundamentally solving a problem of patterning.
In order to achieve the above object, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including: depositing a bottom electrode layer, a magnetic tunnel junction film layer, a hard mask film layer and a photoresist layer on a semiconductor substrate; etching the photoresist layer, the hard mask film layer and the magnetic tunnel junction film layer to form a Magnetic Tunnel Junction (MTJ), and forming a focusing structure at the bottom of the MTJ; depositing a first dielectric layer, wherein the first dielectric layer wraps the etched hard mask film layer and the Magnetic Tunnel Junction (MTJ) and covers the bottom electrode layer and the top of the focusing structure; and etching the first dielectric layer, removing the hard mask film layer, the bottom electrode layer and the first dielectric layer at the top of the patterning structure, and etching a groove around the bottom side wall of the Magnetic Tunnel Junction (MTJ) to cut off the patterning structure.
Optionally, the magnetic tunnel junction film layer includes a free layer, a tunneling layer, and a fixed layer deposited on the bottom electrode layer.
Optionally, after etching a trench around the bottom sidewall of the MTJ, the first dielectric layer wraps the hard mask film layer, the tunneling layer, and the sidewall of the fixed layer, and wraps a portion of the sidewall of the free layer.
Optionally, the hard mask layer is a metal hard mask layer or a stack layer formed by the metal hard mask layer and the dielectric hard mask layer.
Optionally, the metal hard mask layer is a single-layer metal hard mask or a stack layer formed by multiple layers of different metal hard masks, and the dielectric hard mask layer is a single-layer dielectric hard mask or a stack layer formed by multiple layers of different dielectric hard masks.
Optionally, the etching the photoresist layer, the hard mask film layer and the magnetic tunnel junction film layer to form a magnetic tunnel junction MTJ includes: forming a Magnetic Tunnel Junction (MTJ) pattern on the photoresist layer; etching the hard mask film layer by taking the photoresist layer as a mask based on the Magnetic Tunnel Junction (MTJ) pattern; and etching the magnetic tunnel junction film layer by taking the etched hard mask film layer as a mask to form the Magnetic Tunnel Junction (MTJ).
Optionally, the hard mask film layer is etched by reactive ion etching or ion beam etching, and the magnetic tunnel junction film layer is etched by ion beam etching.
Optionally, a trench is etched around the bottom sidewall of the magnetic tunnel junction MTJ by setting an etching parameter of the reactive ion etching.
Optionally, the method for manufacturing a semiconductor device further includes: and depositing a second dielectric layer, wherein the second dielectric layer wraps the hard mask film layer, the Magnetic Tunnel Junction (MTJ), the groove and the cut-off focusing structure and covers the top of the bottom electrode layer.
The embodiment of the invention also provides a semiconductor device which is manufactured by the manufacturing method of the semiconductor device.
Through the technical scheme, after the magnetic tunnel junction MTJ is patterned to form the patterning structure, the first dielectric layer is deposited, the side wall and the bottom electrode layer of the magnetic tunnel junction MTJ and the patterning structure are protected in situ, and then the dielectric layer in the horizontal direction, namely, the bottom electrode layer and the dielectric layer above the patterning structure are etched. In the process of etching the first dielectric layer, a groove is formed around the magnetic tunnel junction MTJ, and a forming structure is cut off by utilizing the etching formed Trench, so that the influence of forming is further solved, the write current Ic can be reduced, the coercive field Hc is increased, the writing efficiency of a semiconductor device (for example, SOT-MRAM) is improved, and the energy consumption is reduced. Further, a second dielectric layer may be further deposited to encapsulate the magnetic tunnel junction MTJ to protect the magnetic tunnel junction MTJ.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain, without limitation, the embodiments of the invention. In the drawings:
fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view illustrating deposition of various film layers;
FIG. 3 is a schematic cross-sectional view illustrating the layers after sequentially patterning a photoresist layer and a hard mask layer;
FIG. 4 is a schematic cross-sectional view of the layers after exemplary patterning of the MTJ film layers;
FIG. 5 is a schematic cross-sectional view of the layers after exemplary deposition of a dielectric layer;
FIG. 6 is a schematic cross-sectional view of an example magnetic tunnel junction MTJ formed trench cut-off patterning structure after etching a dielectric layer; and
FIG. 7 is a schematic cross-sectional view of an example etched trench formed followed by a deposited dielectric layer surrounding the magnetic tunnel junction MTJ.
Description of the reference numerals
101 a photoresist layer; 102 hard mask film layer; 103 a fixed layer; 104 tunneling layer;
105 free layer; 106 a bottom electrode layer; 107Footing structures; 108 a first dielectric layer;
109 grooves; 110 a second dielectric layer.
Detailed Description
The following describes the detailed implementation of the embodiments of the present invention with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
Spatially relative terms, such as "under …," "under …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Furthermore, in subsequent manufacturing processes, there may be one or more additional operations among/between the operations described, and the order of the operations may be changed. In this disclosure, the phrase "one of A, B and C" refers to "A, B and/or C" (A, B, C, a and B, a and C, B and C, or A, B and C), unless otherwise indicated, does not denote one element from a, one element from B, and one element from C. Materials, configurations, dimensions, processes and/or operations described with respect to one embodiment may be employed in other embodiments and detailed descriptions thereof may be omitted.
The manufacturing method provided by the embodiment of the present invention will be described below by taking the manufacturing process of the SOT-MRAM as an example, but it should be noted that the manufacturing method of the semiconductor device provided by the embodiment of the present invention has universality, and is not only applicable to the manufacturing of the SOT-MRAM, but also applicable to the manufacturing of other semiconductor devices having similar structures.
In order to avoid using ion beam etching (Ions Beam Etching, IBE) when etching the magnetic tunnel junction (magnetic tunnel junction, MTJ), etching to the bottom electrode layer under the magnetic tunnel junction (Magnetic Tunnel Junction, MTJ) film causes bottom electrode metal to sputter to the side wall of the magnetic tunnel junction MTJ, shorting the magnetic tunnel junction MTJ, disabling the semiconductor device, and presenting an angle between IBE and the magnetic tunnel junction film to be etched when etching the magnetic tunnel junction film. However, the bottom of the Magnetic Tunnel Junction (MTJ) column is shaded, and the corresponding etching amount is small, so that a Footing structure is formed. The formed writing structure causes the write current Ic to increase and the coercive field Hc to decrease, so that the writing efficiency decreases. The existing method for solving the problem of the Footing is to use IBE to carry out secondary etching on the Footing structure, however, the method cannot fundamentally solve the Footing problem due to the existence of shadows.
Fig. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, referring to fig. 1, the method for manufacturing a semiconductor device may include the following steps:
step S110: a bottom electrode layer 106, a magnetic tunnel junction film layer, a hard mask film layer 102, and a photoresist layer 101 are deposited on a semiconductor substrate.
The magnetic tunnel junction film layer preferred in the embodiments of the present invention includes a free layer 105, a tunneling layer 104, and a fixed layer 103 deposited on the bottom electrode layer.
Referring to fig. 2, a bottom electrode layer 106, a magnetic tunnel junction film layer, a hard mask film layer 102, and a photoresist layer 101 are sequentially deposited on a semiconductor substrate. Wherein the bottom electrode layer 106 may be a conductive layer having a strong spin-orbit coupling effect. The material of the bottom electrode layer 106 may be a positive spin hall angle material, such as Pt, pd, hf, au, auPt, ptHf, ptCr, ptMn, feMn, niMn, etc.; may also be a negative spin hall angle material, e.g. Ta, W, hf, ir, irMn, W, WO x WN, W (O, N), taN, taB, etc.; may also be a topological insulator material, e.g. WTE 2 、Bi x Se 1-x 、Bi x Sb 1-x 、(Bi，Sb) 2 Te 3 Etc.; also, a multilayer film structure may be used, for example, comprising two or more of the above materials. The magnetic tunnel junction film layer may include a free layer 105, a tunneling layer 104, and a fixed layer 103, i.e., a sandwich structure.
The hard mask layer 102 may be a metal hard mask layer or a stack of a metal hard mask layer and a dielectric hard mask layer.
The metal hard mask layer is preferably a single-layer metal hard mask or a lamination composed of multiple layers of different metal hard masks, and the dielectric hard mask layer is preferably a single-layer dielectric hard mask or a lamination composed of multiple layers of different dielectric hard masks.
Materials for the metal hard mask layer include, but are not limited to, the following: ta, co, ru, taN, ti, tiN, W, etc.; materials for the dielectric hard mask layer include, but are not limited to, the following: siO, si 3 N 4 SiC, siON, etc.
Step S120: and etching the photoresist layer 101, the hard mask film layer 102 and the magnetic tunnel junction film layer to form a Magnetic Tunnel Junction (MTJ), and forming a patterning structure 107 at the bottom of the Magnetic Tunnel Junction (MTJ).
Preferably, step S120 may include: forming a Magnetic Tunnel Junction (MTJ) pattern on the photoresist layer 101; etching the hard mask film layer 102 by taking the photoresist layer 101 as a mask based on the Magnetic Tunnel Junction (MTJ) pattern; and etching the magnetic tunnel junction film layer by taking the etched hard mask film layer 102 as a mask to form the magnetic tunnel junction MTJ.
Illustratively, the photoresist layer 101 is patterned to form a magnetic tunnel junction MTJ pattern, and the hard mask layer 102 is etched using the photoresist layer 101 as a mask to form the structure shown in fig. 3. After removing the photoresist, etching the MTJ film layer by using the hard mask film layer 102 as a mask, forming the magnetic tunnel junction MTJ, and forming a patterning structure 107 at the bottom of the magnetic tunnel junction MTJ, thereby forming the structure shown in fig. 4.
Preferably, the hard mask film layer is etched by reactive ion etching or ion beam etching, and the magnetic tunnel junction film layer is etched by ion beam etching.
Illustratively, the hard mask film 102 is patterned using reactive ion etching (Reactive Ions Etching, RIE) or IBE. Using IBE, the magnetic tunnel junction film layer is patterned. When the magnetic tunnel junction film layer is patterned, a patterning structure 107 is formed at the bottom of the magnetic tunnel junction MTJ, thereby affecting the performance of the semiconductor device. As described above, the reasons include: IBE etches the magnetic tunnel junction film layer at a certain angle, and shadow formed by the magnetic tunnel junction MTJ (pillar) forms a focusing structure 107 at the bottom of the magnetic tunnel junction MTJ; to avoid etching the bottom electrode layer 106 and then redeposition sputtered metal on the sidewalls of the magnetic tunnel junction MTJ, resulting in failure of the semiconductor device, the formation of the patterning structure 107 to etch the film layer stopping on top of the bottom electrode layer 106 results in a free layer size that is larger than the magnetic tunnel junction MTJ junction, as shown in fig. 4, reducing the coercive field Hc of the semiconductor device.
Step S130: a first dielectric layer 108 is deposited, and the first dielectric layer 108 wraps the etched hard mask film layer 102 and the magnetic tunnel junction MTJ, and covers the bottom electrode layer 106 and the top of the patterning structure 107.
Referring to FIG. 5, to illustrate, a first dielectric layer 108 is deposited over the etched magnetic tunnel junction MTJ, the materials of the first dielectric layer 108 include, but are not limited to, the following: siO (SiO) 2 、Si 3 N 4 SiC, siOC, etc. With a first mediumThe material of the mass layer 108 is SiO 2 For example, the SiO 2 Layer 108 wraps around the magnetic tunnel junction MTJ, the sidewalls of the hard mask film layer 102, and the top of the hard mask film layer 102, covering the top of the patterning structure 107 and the bottom electrode layer 106. The first dielectric layer 108 may serve as a mask for etching in step S140, and may further protect the side wall of the magnetic tunnel junction MTJ in situ, so as to avoid metal back-splash deposited on the side wall during etching, and cause short circuit of the semiconductor device.
Step S140: and etching the first dielectric layer 108, removing the hard mask film layer 102, the bottom electrode layer 106 and the first dielectric layer 108 on the top of the patterning structure 107, and etching a trench109 around the bottom side wall of the magnetic tunnel junction MTJ to cut off the patterning structure 107.
Preferably, a trench109 is etched around the bottom sidewall of the magnetic tunnel junction MTJ by setting an etching parameter of the reactive ion etching.
Referring to fig. 6, the first dielectric layer 108 is etched to remove the first dielectric layer 108 on top of the magnetic tunnel junction MTJ, the bottom electrode layer 106, and the patterning structure 107 by way of example. In the RIE etching process, a Trench (Trench) 109 may be etched around the bottom sidewall of the magnetic tunnel junction MTJ by setting an appropriate etching parameter (the parameter may be obtained through a lot of experiments), where the Trench109 may cut off the patterning structure 107, thereby solving the influence caused by the patterning structure 107.
Preferably, after the trench109 is etched around the bottom sidewall of the magnetic tunnel junction MTJ, the first dielectric layer 108 wraps around the hard mask layer 102, the tunneling layer 104, and the sidewalls of the fixed layer 103, and wraps around a portion of the sidewalls of the free layer 105.
With continued reference to fig. 6, the material of the first dielectric layer 108 is SiO 2 For example, for the SiO 2 The layer 108 is etched to remove the top of the hard mask layer 102 and the portion covering the top of the patterning structure 107 and the bottom electrode layer 106, so that the first dielectric layer 108 wraps the hard mask layer 102, the tunneling layer 104 and the side wall of the fixed layer 103, and wraps a portion of the side wall of the free layer 105. In the process, by setting etching parameters, the method canSo that a Trench109 is formed around the bottom of the magnetic tunnel junction MTJ, the presence of the Trench109 cuts off the patterning structure 107, thereby eliminating the adverse effects of the patterning structure 107.
Preferably, the method for manufacturing a semiconductor device further includes: a second dielectric layer 110 is deposited, where the second dielectric layer 110 wraps the hard mask film 102, the MTJ, the trench109, and the cut-off patterning structure 107, and covers the top of the bottom electrode layer 106.
Further preferably, the second dielectric layer 110 is deposited by chemical vapor deposition.
Referring to fig. 7, the material of the first dielectric layer 108 is SiO 2 After forming the trench109 around the magnetic tunnel junction MTJ, a second dielectric layer 110 may also be deposited by chemical vapor deposition (Chemical Vapor Deposition, CVD) to encapsulate the magnetic tunnel junction MTJ to protect the magnetic tunnel junction MTJ.
Accordingly, in the embodiment of the invention, after patterning the magnetic tunnel junction MTJ to form the patterning structure 107, the first dielectric layer 108 is deposited first to protect the sidewall and the bottom electrode layer 106 of the magnetic tunnel junction MTJ and the patterning structure 107 in situ, and then the first dielectric layer 108 in the horizontal direction, that is, the bottom electrode layer 106 and the first dielectric layer 108 on the patterning structure 107 are etched. In the etching process of the first dielectric layer 108, by controlling etching parameters, a groove 109 is formed around the magnetic tunnel junction MTJ, the imaging structure 107 is cut off by using the etched groove 109, so that the influence of imaging is solved, the writing current Ic can be reduced, the coercive field Hc can be increased, the writing efficiency of a semiconductor device (for example, SOT-MRAM) is improved, and the energy consumption is reduced. Further, a second dielectric layer 110 may be further deposited to encapsulate the magnetic tunnel junction MTJ to protect the magnetic tunnel junction MTJ.
The embodiment of the invention also provides a semiconductor device which is manufactured by the manufacturing method of the semiconductor device.
The embodiment of the invention also provides electronic equipment, which comprises a processor and the semiconductor device coupled with the processor.
Technical details and effects of the semiconductor device and the electronic device provided by the embodiments of the present invention are similar to those of the method for manufacturing a semiconductor device provided by the embodiments of the present invention, and reference may be made to the above, and details are not repeated here.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises an element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and changes may be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. which are within the spirit and principles of the present application are intended to be included within the scope of the claims of the present application.
Claims (10)
1. A method of manufacturing a semiconductor device, the method comprising:
depositing a bottom electrode layer, a magnetic tunnel junction film layer, a hard mask film layer and a photoresist layer on a semiconductor substrate;
etching the photoresist layer, the hard mask film layer and the magnetic tunnel junction film layer to form a Magnetic Tunnel Junction (MTJ), and forming a focusing structure at the bottom of the MTJ;
depositing a first dielectric layer, wherein the first dielectric layer wraps the etched hard mask film layer and the Magnetic Tunnel Junction (MTJ) and covers the bottom electrode layer and the top of the focusing structure; and
and etching the first dielectric layer, removing the hard mask film layer, the bottom electrode layer and the first dielectric layer at the top of the Footing structure, and etching a groove around the side wall at the bottom of the Magnetic Tunnel Junction (MTJ) to cut off the Footing structure.
2. The method of manufacturing a semiconductor device of claim 1, wherein the magnetic tunnel junction film layer comprises a free layer, a tunneling layer, and a fixed layer deposited on the bottom electrode layer.
3. The method of manufacturing a semiconductor device of claim 2, wherein after etching a trench around a bottom sidewall of the magnetic tunnel junction MTJ, the first dielectric layer wraps around sidewalls of the hard mask film layer, the tunneling layer, and the fixed layer, wrapping around a portion of sidewalls of the free layer.
4. The method of manufacturing a semiconductor device according to claim 1, wherein the hard mask layer is a metal hard mask layer, or
And a stack of a metal hard mask layer and a dielectric hard mask layer.
5. The method of manufacturing a semiconductor device according to claim 4, wherein the metal hard mask layer is a single metal hard mask or a stack of a plurality of different metal hard masks,
the dielectric hard mask layer is a single-layer dielectric hard mask or a lamination layer formed by multiple layers of different dielectric hard masks.
6. The method of manufacturing a semiconductor device according to claim 1, wherein the etching the photoresist layer, the hard mask layer, and the magnetic tunnel junction film layer to form a magnetic tunnel junction MTJ comprises:
forming a Magnetic Tunnel Junction (MTJ) pattern on the photoresist layer;
etching the hard mask film layer by taking the photoresist layer as a mask based on the Magnetic Tunnel Junction (MTJ) pattern; and
and etching the magnetic tunnel junction film layer by taking the etched hard mask film layer as a mask to form the Magnetic Tunnel Junction (MTJ).
7. The method of manufacturing a semiconductor device according to claim 6, wherein the hard mask layer is etched by reactive ion etching or ion beam etching, and
and etching the magnetic tunnel junction film layer by ion beam etching.
8. The method of manufacturing a semiconductor device according to claim 1, wherein a trench is etched around a bottom sidewall of the magnetic tunnel junction MTJ by setting an etching parameter of reactive ion etching.
9. The method for manufacturing a semiconductor device according to claim 1, wherein the method for manufacturing a semiconductor device further comprises:
and depositing a second dielectric layer, wherein the second dielectric layer wraps the hard mask film layer, the Magnetic Tunnel Junction (MTJ), the groove and the cut-off focusing structure and covers the top of the bottom electrode layer.
10. A semiconductor device manufactured by the manufacturing method of the semiconductor device according to any one of claims 1 to 9.
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