CN117134718A - Power protection loop for amplifier chain element - Google Patents

Abstract

A power protection loop for an amplifier chain element is disclosed. In one aspect, an amplifier chain may have a power detection circuit to detect power within the amplifier chain. When the power exceeds a threshold, a control circuit limits the amplification provided by the amplifier elements within the amplifier chain to suppress or reduce the power level within the amplifier chain, thereby protecting the elements within the amplifier chain. In this way, not only the amplifier element but also the acoustic filter element can be protected. The threshold for suppressing or reducing the power level may be based on one or more of: supply voltage, sensed temperature, and mode (e.g., 2G, 3G, 4G, 5G). By protecting these components, they can withstand power surges without failing.

Description

Power protection loop for amplifier chain element

Priority application

The present application claims priority from U.S. provisional patent application No. 63/381,419 entitled "power protection loop for amplifier chain element (POWER PROTECTION LOOP FOR AMPLIFIER CHAIN ELEMENTS)" filed on 10/28 of 2022, the contents of which are incorporated herein by reference in its entirety.

The present application claims priority from U.S. provisional patent application No. 63/346,118 entitled "ADJUSTABLE POWER limiting loop with per mode threshold for fused 2G/3G/4G/5G PA and acoustic filter protection" (ADJUSTABLE POWER-LIMITING LOOP WITH PER-MODE THRESHOLD FOR CONVERGED 2G/3G/4G/5G PAs AND ACOUSTIC FILTER PROTECTION) "filed on month 26 of 2022, the contents of which are incorporated herein by reference in their entirety.

Technical Field

The technology of the present disclosure relates generally to protecting elements in a power amplifier chain from high power conditions that may damage the elements. Specifically, the amplifier and the acoustic filter are protected from over-power conditions.

Background

In modern society, computing devices are of all kinds, and more particularly mobile communication devices are becoming more and more common. The popularity of these mobile communication devices is driven in part by the many functions that are currently enabled on such devices. The increase in processing power in such devices means that mobile communication devices evolve from pure communication tools to complex mobile entertainment centers, enabling enhanced user experience. With the advent of the variety of functions available for such devices, there is increasing pressure to find ways to improve data transfer between elements. This pressure has prompted the forward evolution of cellular standards that rely on higher frequencies and has increased the need for accurate control of power at these frequencies. Such requirements require that the power amplifier chain be able to withstand power surges outside of the parameters of the cellular standard. Providing such a power amplifier chain provides an innovative opportunity.

Disclosure of Invention

Aspects disclosed in the detailed description include a power protection loop for an amplifier chain element. An amplifier chain may have a power detection circuit to detect power within the amplifier chain. When the power exceeds a threshold, a control circuit limits the amplification provided by the amplifier elements within the amplifier chain to suppress or reduce the power level within the amplifier chain, thereby protecting the elements within the amplifier chain. In this way, not only the amplifier element but also the acoustic filter element can be protected. The threshold for suppressing or reducing the power level may be based on one or more of: supply voltage, sensed temperature, and mode (e.g., 2G, 3G, 4G, 5G). By protecting these components, they can withstand power surges without failing.

In this regard, in one aspect, an amplifier chain is disclosed. The amplifier chain includes an amplifier. The amplifier chain also includes a power detector associated with the amplifier. The amplifier chain also includes a comparison circuit coupled to the amplifier and configured to compare a signal from the power detector to a threshold. The amplifier chain also includes a control circuit coupled to the comparison circuit and configured to modify the behavior of the amplifier when the signal from the power detector exceeds a threshold.

Drawings

FIG. 1 is a block diagram of an exemplary amplifier chain having a power protection loop for protecting elements of the amplifier chain from over-power conditions;

FIG. 2 is a block diagram of an exemplary amplifier chain having a power protection loop as in FIG. 1 but having additional voltage clamps, over Voltage Protection (OVP) and Over Current Protection (OCP) loops to protect elements of the amplifier chain from over power conditions;

FIG. 3 is a block diagram of an exemplary amplifier chain in which the control circuit that adjusts the power level in response to the power protection loop is a regulator;

FIG. 4 is a block diagram of an exemplary amplifier chain in which the control circuit that adjusts the power level in response to the power protection loop is a bias circuit;

figures 5A-5D are block diagrams of an amplifier chain showing possible power detection points and possible parallel OVP loop options;

FIG. 6 is a block diagram of an amplifier chain with an exemplary power detection circuit at the output stage output;

fig. 7 is a block diagram of a transceiver having an amplifier chain therein according to the present disclosure;

8A-8C are circuit diagrams of possible detector circuits that may be used as the power detector of the present disclosure;

FIG. 8D shows the detector circuit of FIG. 8B with an amplifier chain;

FIG. 9 is a circuit diagram of a detector circuit, a comparison circuit, and a reference circuit that may be used to instantiate aspects of the present disclosure; and

fig. 10 is a block diagram of a mobile terminal that may include the transceiver and associated amplifier chain of fig. 7 in accordance with the present disclosure.

Detailed Description

The embodiments set forth below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "over" another element, it can be directly on the other element or extend directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly on" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Relative terms, such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Aspects disclosed in the detailed description include a power protection loop for an amplifier chain element. An amplifier chain may have a power detection circuit to detect power within the amplifier chain. When the power exceeds a threshold, a control circuit limits the amplification provided by the amplifier elements within the amplifier chain to suppress or reduce the power level within the amplifier chain, thereby protecting the elements within the amplifier chain. In this way, not only the amplifier element but also the acoustic filter element can be protected. The threshold for suppressing or reducing the power level may be based on one or more of: supply voltage, sensed temperature, and mode (e.g., 2G, 3G, 4G, 5G). By protecting these components, they can withstand power surges without failing.

Before discussing exemplary aspects of the present disclosure, an overview of existing protection schemes is provided. More specifically, most amplifier chains are used in transceivers as part of a wireless transmission scheme according to cellular standards or modes, such as second generation (2G), third generation (3G), fourth generation (4G), fifth generation (5G), some arrangement of these cellular standards or modes, or some new cellular standards in the future. These amplifier chains contain components such as amplifiers and acoustic filters that are sensitive to power levels. That is, if these elements are exposed to an over-power condition, the elements may fail, resulting in failure of the amplifier chain, transceiver, and, for most purposes, the mobile computing device that includes the transceiver. One way to protect such elements is by means of a voltage clamp formed by a stack of one or more diodes. These clamps are relatively inflexible (particularly when switching between modes) and provide an upper voltage limit of a fixed value that may not coincide with the desired value. While the owners of the present disclosure propose various over-power protection loops, such loops may protect the amplifier while leaving the acoustic filter still vulnerable. While many amplifier chains may protect the amplifier chain during normal operation, some designers have proposed new stress tests that place additional performance burden on the amplifier chain. Meeting these new stress tests and use cases to excite such stress tests presents challenges to existing clamp and over-power protection loop solutions.

Exemplary aspects of the present disclosure contemplate improving existing amplifier chain protection solutions by adding another over-power loop that detects the power level within the amplifier chain. Such detected power level may be compared to a threshold. The threshold is set based on the supply voltage, the temperature in the die containing the amplifier chain, and the mode indication. When the threshold is exceeded (indicating a power condition high enough to potentially damage elements of the amplifier chain), the control circuit adjusts operation of the amplifiers within the amplifier chain to reduce the power level to a sustainable level.

In this regard, fig. 1 is a block diagram of an amplifier chain 100 with vulnerable elements including a driver amplifier 102, an output amplifier 104, and a filter 106. It should be appreciated that the amplifiers 102 and 104 may be formed of multiple transistors. The filter 106 may be an acoustic filter, and more specifically, may be a Surface Acoustic Wave (SAW) filter, a Bulk Acoustic Wave (BAW) filter, a High Frequency SAW (HFSAW), or the like. Similarly, there may be additional amplifier stages (not shown), such as, for example, front driver stages, intermediate stages, and the like. Further, while shown generally as single ended elements, it should be appreciated that the elements may be differential, quadrature, doherty (Doherty) amplifiers, and the like, without departing from the disclosure.

The amplifier chain 100 may detect the power level (directly or indirectly, as explained in more detail below) at a detection node, such as an input node 108 before the driver amplifier 102, at an intermediate node 110 between the driver amplifier 102 and the output amplifier 104, or at an output node 112 after the output amplifier 104. If there are other amplifier stages, there may be additional detection nodes. Detection circuit 114 is coupled to the detection node and indicates a power level to comparison circuit 116, which compares the power level (or a proxy indicator of the power level) to a threshold value and provides an indication to control circuit 118 of whether the threshold value is exceeded. The control circuit 118 adjusts the operation of the amplifier 102 or 104 (or other amplifier if present in the amplifier chain 100) to reduce the power level and protect the vulnerable components.

In addition, the temperature sensor 120 may provide a temperature detection signal 122 to a threshold setting control circuit 124. While it may be preferable to have the temperature sensor 120 in or in close proximity to the filter 106, such placement may be difficult to design. Thus, the temperature sensor 120 may be in or near circuitry (e.g., transistors) forming the output amplifier 104.

The threshold setting control circuit 124 may further receive information regarding the power supply voltage (Vcc 126) being used. Additionally, an indication of the mode used (e.g., 2G/3G/4G/5G) may be provided from a digital Radio Frequency Front End (RFFE) element 128 (or something similar to a baseband processor). The patterns used may be cross-referenced in a look-up table (LUT) 130 or other memory element to provide adjustments to the threshold setting control circuit 124. It should be noted that LUT 130 may be integrated into threshold setting control circuit 124. Based on the received values, the threshold setting control circuit 124 may set a dynamically adjustable threshold for use by the comparison circuit 116. The threshold may change if the mode, temperature, or supply voltage changes.

It should be noted that the use of the protection loop of the present disclosure does not preclude the use of other protection options. Fig. 2 illustrates how aspects of the present disclosure may be used with other protection options. Specifically, the amplifier chain 200 may include an amplifier element 202 and an acoustic filter 204. In this regard, the power protection loop of the present disclosure utilizes a power detector 208 to detect power at the input node 206 for use by the comparison circuit 210. Additionally, the power level at the input node 206 may be clamped by the input clamp 212. The input clamp 212 may appear superfluous, but since the input clamp 212 is acting faster than the power protection loop, the input clamp 212 may be set at a higher threshold and correspondingly rarely used, while remaining present to prevent fast transients from occurring. It should be noted that other clamps (not shown) may be present, such as an inter-stage clamp or an output clamp. In addition, an over-current protection (OCP) loop 214 and/or an over-voltage protection (OVP) loop 216 may be present and provide signals to a control circuit 218.

The control circuit 118 of fig. 1 or the control circuit 218 of fig. 2 may be implemented in various ways. In a first exemplary aspect, the control circuit may be a regulator. In a second exemplary aspect, the control circuit may be a bias circuit (as better shown in fig. 4). In yet another exemplary aspect, the control circuit may be a regulator for one stage and a bias circuit for another stage (as better shown in fig. 3).

In this regard, fig. 3 shows an amplifier chain 300 having a driver amplifier 302 and an output amplifier 304. Driver amplifier 302 has an associated driver bias circuit 306 and output amplifier 304 has an associated output bias circuit 308. The power protection loop of the present disclosure may utilize a power detector 310 to detect power at a node 312, 314, or 316. The comparison circuit 318 compares the power indication to a threshold and provides a signal to the control circuit 320. The control circuit 320 includes a regulator 322 to limit the power and voltage of the driver amplifier 302. Thus, the regulator 322 provides fine control and relatively fast control of the driver amplifier 302. In addition, the control circuit 320 may include an output bias circuit 308. The output amplifier has few regulators and thus control by the output bias circuit 308 may be the best way to provide additional power protection. It should be noted that the inclusion of the output bias circuit 308 in the control circuit 320 is optional.

In contrast, fig. 4 shows an amplifier chain 400 with a driver amplifier 402 and an output amplifier 404. Driver amplifier 402 has an associated driver bias circuit 406 and output amplifier 404 has an associated output bias circuit 408. The power protection loop of the present disclosure may utilize a power detector 410 to detect power at a node 412, 414, or 416. The comparison circuit 418 compares the power indication to a threshold and provides a signal to the control circuit 420. The control circuit 420 includes a driver bias circuit 406. In addition, the control circuit 420 may include an output bias circuit 408. Such additional associated bias circuitry may optionally be included in control circuitry 420 if there are other amplifier stages (also not shown) with associated bias circuitry (not shown).

As noted above, the power detection circuit may be coupled to various nodes in the amplifier chain. Similarly, the OVP loop may vary. Fig. 5A-5D illustrate various configurations, and it should be understood that other variations are within the scope of the present disclosure. For example, fig. 5A shows an amplifier chain 500A with a driver amplifier 502 and an output amplifier 504. An input clamp 506 and a power detector 508 are provided at an input node 510. The driver OVP loop 512 is tapped at an inter-stage node 514 at the output of the driver amplifier 502. A control circuit (not explicitly shown) may control the bias circuits 516, 518 or a regulator (not shown) as previously described.

Fig. 5B is similar, but in amplifier chain 500B, power detector 508 moves to an inter-stage node 514.

Fig. 5C is similar, but amplifier chain 500C adds an OVP loop 520 coupled to output node 522 instead of driver OVP loop 512. Both the power protection loop and the OVP loop 520 of the present disclosure control the bias circuit 518.

Fig. 5D is similar, but amplifier chain 500D also moves power detector 508 to output node 522, and both the power protection loop and OVP loop 520 of the present disclosure control bias circuit 518.

An even more complex amplifier chain with two power protection loops is shown in fig. 6, showing an amplifier chain 600 with a driver amplifier 602 and an output amplifier 604. The driver amplifier 602 has an associated driver bias circuit 606, while the output amplifier 604 has an associated output bias circuit 608. The power protection loop of the present disclosure may include two sub-loops 609A, 609B and may utilize a power detector 610 at an input node 612 and a power detector 614 at an output node 616 to detect power. An input clamp 618 is also present at the input node 612. An inter-stage clamp 620 is present at an inter-stage node 622. A driver OVP loop 624 is also coupled to the interstage node 622. The driver bias circuit 606 is controlled by a driver OVP loop 624 and a power protection sub-loop 609A. An output OVP loop 626 is also coupled to the output node 616. The output bias circuit 608 is controlled by an output OVP loop 626 and a power protection sub-loop 609B. An output clamp 628 may also be present at the output node 616. Collectively, clamps 618, 620, and 628, along with OVP loops 624, 626 and over-power loops (including sub-loops 609A, 609B), help protect amplifiers 602, 604 and filter 630 from damage.

At nodes 612 and 622, the impedance is controlled relatively well (e.g., fifty ohms (50Ω)). Thus, the current can be readily derived using voltage measurements, and the power can be readily determined from voltage measurements coupled to known resistors (p=v ² R). Thus, the power detector 610 may be a simple voltage detector. In contrast, at the output node 616, the impedance may substantially fluctuate with a relative volatile Voltage Standing Wave Ratio (VSWR) from the antenna (not shown) and the filter 630. Thus, measuring only the voltage at output node 616 may not give a reliable power measurement because R may not be reliably known. The power detector 614 may include a current detector 632 and a voltage detector 634. Multiplication may be difficult to implement in a die structured to provide an amplifier, but summing current and voltage may be a reasonable proxy for detected power for the present disclosure, and summing circuit 636 may sum values from detectors 632, 634 to control output bias circuit 608.

To aid in understanding the context of the present disclosure, a block diagram of a transceiver 700 is provided in fig. 7. Transceiver 700 includes a baseband processor (BBP) 702 that provides signals to be sent to intermediate frequency circuitry 704, which may up-convert the signals to intermediate frequency and/or radio frequency for transmission. The BBP 702 can also provide a mode indication to a control circuit (not shown) for consideration of LUTs and the like. According to the present disclosure, IF circuit 704 is coupled to amplifier chain 706. The amplifier chain 706 is coupled to a switch 708. Switch 708 is coupled to antenna 710 and a receive path. Signals may be transmitted from the amplifier chain 706 to the antenna 710 through the switch 708. Similarly, signals received at antenna 710 may be passed through switch 708 to a Low Noise Amplifier (LNA) 712, and then down-converted by another IF circuit 714 before processing by BBP 702. Other transceiver structures may also benefit from the teachings of the present disclosure.

Fig. 8A-8C illustrate different types of voltage detectors that may be used in the power detectors of the present disclosure. Specifically, fig. 8A shows a single Field Effect Transistor (FET) 800 that turns on when the voltage at gate 800G exceeds the threshold of FET 800. Such relatively small input detections may result in large threshold variability and are not perfect solutions. Fig. 8B shows a set of stacked and parallel FETs 802 (1) -802 (4) with less variability in threshold and higher on threshold. Fig. 8C shows a large set of stacked and parallel FETs 804 (1) -804 (8) with low threshold variability, but beginning to occupy more space and may consume power beyond design preferences. Thus, the structure of FIG. 8B may be the best compromise for some designers.

The detector of fig. 8A-8C may have a nonlinear capacitance modeled by the variable capacitance 806 in fig. 8D, which may negatively impact operation when coupled to a node for voltage detection. Thus, the varactor 808 may be coupled to the detector 810 to provide an approximate inverse of the variable capacitance 806, resulting in a constant total input impedance of the amplifier 812 of the amplifier chain 814.

Although the comparison circuit for comparing signals from the power detectors described above may be a comparator, it is more likely to be a subtractive comparison circuit, as shown by power protection loop 900 of fig. 9. The detector 810 may provide the signal 901 to a comparison circuit 902 that is proportional to the voltage of the RFin signal. The comparison circuit 902 also receives a threshold signal 903 from a reference circuit 904. The value of the threshold signal 903 is set by the number of FETs 905 (1) -905 (N) in the reference circuit 904 that are modified by the variable resistor network 906. The calibrated bandgap voltage is applied to a variable resistor network 906 that turns on and off a desired number of FETs 905 within the reference circuit 904. The temperature, supply voltage, and mode signals set the values of the variable resistor network 906. The comparison circuit 902 subtracts the signal 903 from the signal 901 and generates output signals 908 and 910 when the signal 901 exceeds the signal 903 (i.e., the signal 901 minus the signal 903> 0). Signal 908 may generate an alarm and/or be used to activate a control circuit. Similarly, signal 910 may be used to unbiase an amplifier using a corresponding bias circuit (not shown in fig. 9).

Node 912 within the compare circuit 902 is shown as a floating node, but is actually held at a known voltage. FET 914 remains biased on reference circuit 902 and thus can act relatively quickly when signal 901 arrives. Otherwise, the signal 901 may have to "turn on" the various FETs within the comparison circuit 902, slowing down responsiveness. Other comparison circuits may also be used.

It should also be noted that the materials used in the amplifier chain may assist in design. For example, the amplifier chain may be a hybrid structure with driver stages formed in a Complementary Metal Oxide Semiconductor (CMOS) structure and output stages formed in a bipolar structure (e.g., gallium arsenide (GaAs)). CMOS structures allow some digital control through the use of digital-to-analog converters (DACs) and the like. The present disclosure is not limited to such hybrid structures.

An amplifier chain with power protection according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples include, but are not limited to, set top boxes, entertainment units, navigation devices, communications devices, fixed location data units, mobile location data units, global Positioning System (GPS) devices, mobile phones, cellular phones, smart phones, session Initiation Protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, eyeglasses, etc.), desktop computers, personal Digital Assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, digital Video Disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, unmanned aerial vehicles, and multi-rotor aircraft.

In this regard, fig. 10 is a system level block diagram of an exemplary mobile terminal 1000, such as a smartphone, mobile computing device, tablet, or the like. The mobile terminal 1000 includes an application processor 1004 (sometimes referred to as a host) that communicates with a mass storage element 1006 over a Universal Flash Storage (UFS) bus 1008. The application processor 1004 may additionally be connected to a display 1010 through a Display Serial Interface (DSI) bus 1012 and to a camera 1014 through a Camera Serial Interface (CSI) bus 1016. Various audio elements, such as a microphone 1018, a speaker 1020, and an audio codec 1022, may be coupled to the application processor 1004 through a serial low power inter-chip multimedia bus (SLIMbus) 1024. In addition, the audio elements may communicate with each other over a SOUNDWIRE bus 1026. The modem 1028 may also be coupled to the SLIMbus 1024 and/or SOUNDWIRE bus 1026. Modem 1028 may additionally be connected to application processor 1004 via a Peripheral Component Interconnect (PCI) or PCI express (PCIe) bus 1030 and/or a System Power Management Interface (SPMI) bus 1032.

With continued reference to fig. 10, the spmi bus 1032 may also be coupled to a local area network (LAN or WLAN) IC (LAN or WLAN IC) 1034, a Power Management Integrated Circuit (PMIC) 1036, a companion IC (sometimes referred to as a bridge chip) 1038, and a Radio Frequency IC (RFIC) 1040. It should be appreciated that separate PCI buses 1042 and 1044 may also couple application processor 1004 to companion IC 1038 and WLAN IC 1034. The application processor 1004 may additionally be connected to a sensor 1046 through a sensor bus 1048. Modem 1028 and RFIC 1040 may communicate using bus 1050.

With continued reference to fig. 10, the rfic 1040 may be coupled to one or more Radio Frequency Front End (RFFE) elements, such as an antenna tuner 1052, a switch 1054, and a power amplifier 1056, via an RFFE bus 1058. In addition, the RFIC 1040 may be coupled to an Envelope Tracking Power Supply (ETPS) 1060 via a bus 1062, and the ETPS 1060 may be in communication with a power amplifier 1056. The power amplifier 1056 may include an amplifier chain with the power protection loop of the present disclosure. Generally, RFFE elements that comprise RFIC 1040 may be considered as RFFE system 1064. It should be appreciated that RFFE bus 1058 may be formed from clock lines and data lines (not shown).

It should also be noted that the operational steps described in any of the exemplary aspects herein are described for purposes of providing examples and discussion. The described operations may be performed in a number of different orders than that illustrated. Furthermore, operations described in a single operational step may actually be performed in many different steps. Additionally, one or more of the operational steps discussed in the exemplary aspects may be combined. It will be appreciated that the operational steps shown in the flow diagrams may be susceptible to many different modifications as will be readily apparent to those of skill in the art. Those of skill in the art would also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (18)

1. An amplifier chain, comprising:

an amplifier;

a power detector associated with the amplifier;

a comparison circuit coupled to the amplifier and configured to compare a signal from the power detector to a threshold; and

a control circuit is coupled to the comparison circuit and configured to modify the behavior of the amplifier when the signal from the power detector exceeds the threshold.

2. The amplifier chain of claim 1, wherein the amplifier comprises a driver amplifier.

3. The amplifier chain of claim 2, wherein the control circuit comprises a regulator.

4. The amplifier chain of claim 1, wherein the control circuit comprises a bias circuit.

5. The amplifier chain of claim 2, wherein the amplifier further comprises an output amplifier serially coupled to the driver amplifier.

6. The amplifier chain of claim 5, wherein the power detector is coupled to an output node at an output of the output amplifier.

7. The amplifier chain of claim 5, wherein the power detector is coupled to an inter-stage node between the driver amplifier and the output amplifier.

8. The amplifier chain of claim 2, wherein the power detector is coupled to an input node of the driver amplifier.

9. The amplifier chain of claim 1, wherein the power detector comprises a voltage detector.

10. The amplifier chain of claim 1, wherein the power detector comprises a voltage detector and a current detector.

11. The amplifier chain of claim 1, further comprising a temperature sensor, and wherein the threshold is based at least in part on a temperature signal from the temperature sensor.

12. The amplifier chain of claim 1, wherein the threshold is based at least in part on a mode signal.

13. The amplifier chain of claim 1, wherein the threshold is based at least in part on a supply voltage.

14. The amplifier chain of claim 1, further comprising a clamp associated with the amplifier and configured to clamp a voltage of the amplifier at a second threshold that is higher than the threshold.

15. The amplifier chain of claim 1, further comprising an Over Voltage Protection (OVP) loop associated with the amplifier.

16. The amplifier chain of claim 1, further comprising a filter coupled to the amplifier.

17. The amplifier chain of claim 16, wherein the threshold is set to be lower than a voltage that damages the filter.

18. The amplifier chain of claim 16, wherein the filter comprises an acoustic filter.