CN117116911A - Semiconductor structure preparation method and semiconductor structure - Google Patents
Semiconductor structure preparation method and semiconductor structure Download PDFInfo
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- CN117116911A CN117116911A CN202311030053.3A CN202311030053A CN117116911A CN 117116911 A CN117116911 A CN 117116911A CN 202311030053 A CN202311030053 A CN 202311030053A CN 117116911 A CN117116911 A CN 117116911A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 141
- 238000002360 preparation method Methods 0.000 title abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 71
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 57
- 239000000758 substrate Substances 0.000 claims description 44
- 230000008569 process Effects 0.000 claims description 42
- 229910052710 silicon Inorganic materials 0.000 claims description 41
- 239000010703 silicon Substances 0.000 claims description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 40
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 33
- 238000004519 manufacturing process Methods 0.000 claims description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 25
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 239000002210 silicon-based material Substances 0.000 claims description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 238000004299 exfoliation Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 2
- 239000013078 crystal Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 230
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- 230000000694 effects Effects 0.000 description 19
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- 239000000126 substance Substances 0.000 description 6
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- 230000015572 biosynthetic process Effects 0.000 description 5
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- 230000008054 signal transmission Effects 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 230000008570 general process Effects 0.000 description 2
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000000678 plasma activation Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/98—Methods for disconnecting semiconductor or solid-state bodies
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- General Physics & Mathematics (AREA)
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Abstract
The embodiment of the application relates to the technical field of semiconductors, in particular to a semiconductor structure preparation method and a semiconductor structure, wherein the semiconductor structure preparation method comprises the following steps: marking through holes are formed in the surface of the first initial wafer; wherein the marking through hole extends to the peeling layer of the first wafer; preparing a preceding device unit in a first initial wafer based on the marking position of the marking through hole to obtain a target first wafer; bonding the target first wafer and the second wafer to obtain an intermediate semiconductor structure; stripping the intermediate semiconductor along the stripping layer to obtain a target semiconductor structure; and preparing a subsequent device unit corresponding to the previous device unit position at a target position of the target semiconductor surface corresponding to the mark position. The semiconductor structure prepared by the method for preparing the semiconductor structure provided by the embodiment of the application still has the marked through holes exposed on the surface of the crystal after bonding and stripping, and the accuracy and the product yield of a subsequent device unit formed based on the marked through holes are higher, so that the preparation method has wider application range.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor structure preparation method and a semiconductor structure.
Background
In wafer fabrication, which may involve alignment between levels or between level devices, current marking methods typically mark the corresponding locations in the fabrication of the prior devices by patterning or the like, and then use that mark as a reference in subsequent fabrication to achieve alignment with the prior devices. This is entirely applicable in the general process, but once two levels of bonding are involved, the occurrence of the mark becoming buried as a layer or even disappearing easily occurs. For example, when two wafers are bonded, a mark on a first wafer is brought into contact with the bonding interface and then peeled off at other locations along the first wafer, the mark is buried inside the top substrate of the first wafer. Resulting in subsequent device fabrication, the alignment of the device based on the mark is no longer possible.
Therefore, the applicability of the alignment marks in the current semiconductor device manufacturing process is weak.
Disclosure of Invention
The embodiment of the application provides a semiconductor structure and a preparation method thereof.
In a first aspect of an embodiment of the present application, a method for manufacturing a semiconductor structure is provided, including:
marking through holes are formed in the surface of the first initial wafer; wherein the marking through hole extends to the peeling layer of the first wafer;
Preparing a preceding device unit in the first initial wafer based on the marking position of the marking through hole to obtain a target first wafer;
bonding the target first wafer and the second wafer to obtain an intermediate semiconductor structure;
stripping the intermediate semiconductor along the stripping layer to obtain a target semiconductor structure;
and preparing a subsequent device unit corresponding to the previous device unit position at a target position of the target semiconductor surface corresponding to the marking position.
In an alternative embodiment of the present application, the exfoliation layer is a first oxide layer and the preceding device cell is a buried oxide layer cell; the latter device cell is the gate or drain of a transistor.
In an alternative embodiment of the present application, before the marking through holes are formed on the surface of the first initial wafer, the method further includes:
sequentially forming a second silicon dioxide layer and a silicon nitride layer on the surface of the first initial wafer;
correspondingly, the marking through hole penetrates through the second silicon oxide layer and the silicon nitride layer and extends to the first oxide layer.
In an alternative embodiment of the present application, the preparing a preceding device unit in the first initial wafer based on the marking location of the marking through hole to obtain a target first wafer includes:
Preparing the prior device unit in the first initial wafer based on the marking position of the marking through hole to obtain an intermediate first wafer;
and removing the second silicon dioxide layer and the silicon nitride layer on the surface of the middle first wafer to obtain the target first wafer.
In an alternative embodiment of the present application, the preparing the preceding device unit in the first initial wafer based on the marking location of the marking through hole, to obtain an intermediate first wafer, includes:
etching a groove on the surface of the first initial wafer based on the mark position; the grooves extend into a substrate above the first oxide layer in the first initial wafer;
forming a third silicon oxide layer with a first thickness on the surface of the etched first initial wafer based on a thermal oxidation process;
growing a fourth silicon oxide layer with a second thickness on the surface of the formed third silicon oxide layer based on an ethyl silicate process to obtain the intermediate first wafer; wherein the second thickness is greater than the first thickness.
In an alternative embodiment of the present application, the removing the second silicon oxide layer and the silicon nitride layer on the surface of the intermediate first wafer to obtain the target first wafer includes:
Grinding the middle first wafer to the silicon nitride layer;
and rinsing the grinded intermediate first wafer, and removing the silicon nitride layer and part of the second silicon dioxide layer to obtain the target first wafer.
In an optional embodiment of the present application, the method for preparing a semiconductor structure further includes:
forming a first trap-rich layer on the surface of the target first wafer;
correspondingly, the bonding the target first wafer and the second wafer to obtain the intermediate semiconductor structure includes:
and bonding the first trap rich layer on the surface of the target first wafer with the second wafer to obtain the intermediate semiconductor structure.
In an optional embodiment of the present application, the method for preparing a semiconductor structure further includes:
forming a second trap rich layer on the surface of the second wafer;
correspondingly, the bonding the target first wafer and the second wafer to obtain the intermediate semiconductor structure includes:
and bonding the first trap-rich layer on the surface of the target first wafer with the second trap-rich layer on the surface of the second wafer to obtain the intermediate semiconductor structure.
In an optional embodiment of the present application, the method for preparing a semiconductor structure further includes:
and processing the roughness of the surfaces of the first trap rich layer and/or the second trap rich layer to a preset target value.
In an alternative embodiment of the application, the first trap rich layer and the second trap rich layer are both made of polysilicon or amorphous silicon material.
In a second aspect of an embodiment of the present application, a semiconductor structure is provided, including:
a support substrate and a first silicon layer stacked from below and above; the first silicon layer comprises a plurality of independent preceding device units which are arranged at intervals;
the mark through hole is formed in the first silicon layer and penetrates through the first silicon layer; the marking through holes are used for marking positions of the prior device units.
In an alternative embodiment of the present application, the semiconductor structure further includes:
and the trap-rich layer is paved between the supporting substrate and the first silicon layer and is attached to each preceding device unit.
In an alternative embodiment of the present application, the semiconductor structure further includes:
and the rear device unit is arranged at a target position corresponding to the mark position on the surface of the first silicon layer.
In an alternative embodiment of the present application, the preceding device unit is a buried oxide layer unit; the latter device cell is the gate or drain of a transistor.
The embodiment of the application provides a preparation method of a semiconductor structure, which comprises the steps of firstly, forming a mark through hole on the surface of a first initial wafer, wherein the mark through hole extends to a stripping layer of the first wafer; after subsequent bonding and stripping, the marked through hole is always present, and one end of the through hole is exposed to the surface of the target semiconductor after being stripped along the stripping layer, and when subsequent alignment is required, the position of the prior device unit can be determined according to the marked through hole. That is, the mark through hole is used for preparing the following device unit corresponding to the position of the preceding device unit, so that the main alignment of the following device unit and the preceding device unit can be realized. According to the first aspect, the defect that the alignment mark of the prior device unit is hidden in the wafer level or is directly stripped due to the bonding and stripping processes in the traditional mode is avoided, the technical problem that the applicability of a semiconductor structure preparation method in the existing semiconductor device preparation process is weaker is solved, the mark through hole in the semiconductor preparation method provided by the embodiment of the application can be suitable for any type of bonding and stripping process, one end of the mark through hole is always exposed to the surface of a target semiconductor after stripping, the applicability is wider, and the reliability is higher; in the second aspect, the positional accuracy of the subsequent device unit prepared based on the mark position of the mark through hole can be improved, thereby improving the precision of the target semiconductor structure.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment of the present application;
fig. 2 is a schematic view of a process for preparing a target first wafer in a semiconductor structure preparation method according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a structure of a via mark in a method for fabricating a semiconductor structure according to an embodiment of the present application;
FIG. 4 is a schematic diagram illustrating a bonding process between a target first wafer and a target second wafer in a method for fabricating a semiconductor structure according to an embodiment of the present application;
FIG. 5 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment of the present application;
FIG. 6 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment of the present application;
FIG. 7 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment of the present application;
FIG. 8 is a schematic diagram illustrating a bonding process between a target first wafer and a target second wafer in a method for fabricating a semiconductor structure according to an embodiment of the present application;
Fig. 9 is a schematic diagram of a bonding process between a target first wafer and a target second wafer in a semiconductor structure manufacturing method according to an embodiment of the present application.
100, supporting a substrate; 200. a top layer substrate; 210. an oxygen-buried layer unit; 300. a first trap rich layer; 400. a second trap rich layer; 500. the through holes are marked.
Detailed Description
In carrying out the present application, applicants have found that alignment marks currently used in semiconductor device fabrication are less adaptable.
In view of the above problems, embodiments of the present application provide a semiconductor structure manufacturing method and a semiconductor structure. In order to make the objects, technical solutions and advantages of the present application more apparent, a semiconductor structure manufacturing method and a semiconductor structure according to the present application will be described in further detail below by way of examples with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The term "coupled" as used herein includes both direct and indirect coupling (coupling), unless otherwise indicated. In the description of the present application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element in question must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
In the present application, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In wafer fabrication, which may involve alignment between levels or between level devices, current marking methods typically mark the corresponding locations in the fabrication of the prior devices by patterning or the like, and then use that mark as a reference in subsequent fabrication to achieve alignment with the prior devices. This is entirely applicable in the general process, but once two levels of bonding are involved, the occurrence of the mark becoming buried as a layer or even disappearing easily occurs. For example, when two wafers are bonded, the mark on the first wafer is brought into contact with the bonding interface and then peeled off at other locations along the first wafer, the mark is buried within, for example, the first silicon layer that remains in the top substrate 200 of the first wafer. Thus, in the subsequent device preparation, for example, in the photolithography process, the alignment between the oxide in the substrate and the target position of the gate or the drain in the top device cannot be achieved based on the mark.
Therefore, the existing semiconductor structure preparation method in the semiconductor device preparation process is weak in applicability.
Referring to fig. 1, a method for manufacturing a semiconductor structure according to an embodiment of the application is specifically described below. The preparation method of the semiconductor structure provided by the embodiment of the application comprises the following steps 101-105:
step 101, a marking through hole 500 is opened on the surface of the first initial wafer.
For example, in fig. 2, an exemplary sandwich structure is shown at the wafer cleaning node, and the first initial wafer may be a sandwich structure (silicon layer-oxide layer-silicon layer) such as an SOI patterned wafer. Wherein the marking through hole 500 extends to the peeling layer of the first wafer; the peeling layer refers to a layer level of peeling after bonding, for example, a peeling layer prepared based on a hydrogen ion implantation method, and the peeling layer is a hydrogen ion implantation layer; an epitaxial wafer prepared based on silicon germanium epitaxial monocrystalline silicon, wherein the stripping layer is a silicon germanium stripping layer; of course, the release layer may also be an oxide layer or other layer, and is not particularly limited herein. The marked via 500 as in fig. 2 may be prepared based on photolithography and etching processes, etc.
Step 102, preparing a preceding device unit in the first initial wafer based on the marking position of the marking through hole 500, so as to obtain a target first wafer.
The preceding device unit may be a functional device, or a part of the functional device, or a wiring in a level, or an etched groove, an etched through hole, etc. formed in the preparation process, which are not exhaustive, and the preparation method of the corresponding preceding device unit may be flexibly adjusted according to the actual content, which is not limited herein.
The marking position is used to represent the position of the marking through hole 500, and it should be explained that the marking position may be the position where the marking through hole 500 is located, or may be the position having a fixed distance and a fixed direction from the marking through hole 500, and only the purpose of positioning based on the marking position when preparing the rear device unit may be achieved. The shape of the marking through hole 500 may be a cross shape as shown in fig. 3, or may be a vernier caliper shape, an arc shape, a circular shape, a polygonal shape, or the like, which is not meant to be exhaustive. The marking through hole 500 is cross-shaped, and can be aligned from two dimensions of the transverse direction and the longitudinal direction, so that the marking alignment effect is better.
Step 103, bonding the target first wafer and the second wafer to obtain the intermediate semiconductor structure.
For example, referring to fig. 4, the target first wafer formed in fig. 2 is placed upside down on the upper surface of the second wafer for bonding, and the bonding surface is the bonding surface between the first silicon layer of the top substrate 200 and the upper surface of the second wafer in the target first wafer, so as to form the intermediate semiconductor structure in fig. 4.
The bonding process can be flexibly set according to practical situations, and is not particularly limited herein. In the conventional alignment mark approach, alignment marks formed on the wafer surface for prior device units are easily bonded to the interior of the intermediate semiconductor structure, and the surface is not visible.
And 104, stripping the intermediate semiconductor along the stripping layer to obtain the target semiconductor structure.
The stripping process can be a level stripping process or a chemical polishing process to polish the surface layer of the wafer to the target layer. For example, referring to fig. 4, a CMP (chemical polishing) process may be used to remove the second silicon layer on the surface of the first silicon oxide layer, and then the first silicon oxide layer is removed based on an HF acid solution or the like, so as to form a target semiconductor structure with a flat surface.
In the conventional peeling manner, the following two cases may occur: in the first case, the alignment mark is stripped off during the stripping process, i.e., the alignment mark is no longer present in the target semiconductor structure; in the second case, the alignment mark is still buried inside the target semiconductor structure, and the surface is not visible.
Step 105, preparing a subsequent device unit corresponding to the preceding device unit position at a target position of the target semiconductor surface corresponding to the mark position.
The following device unit refers to a device unit that needs to be aligned with the previous device unit, and the following device unit may be a functional device, or a part of a functional device, or a certain wiring in a level, or an etched groove, an etched through hole, etc. formed in the preparation process, which are not exhaustive, and the corresponding preparation method of the following device unit may be flexibly adjusted according to the actual content, which is not limited in detail herein.
In the method for manufacturing a semiconductor structure provided by the embodiment of the application, firstly, a mark through hole 500 is formed on the surface of a first initial wafer, and the mark through hole 500 extends to a stripping layer of the first wafer; after subsequent bonding and peeling, the marking through hole 500 is always present, and one end of the through hole is exposed to the surface of the target semiconductor after being peeled along the peeling layer, and when alignment is required subsequently, the position of the preceding device unit can be determined based on the marking through hole 500. I.e., the subsequent device cell corresponding to the prior device cell location is prepared through the marked via 500, a predominantly alignment of the subsequent device cell with the prior device cell can be achieved.
According to the first aspect, the defect that the alignment mark of the prior device unit is hidden in the wafer level or is directly stripped due to the bonding and stripping processes in the traditional mode is avoided, the technical problem that the applicability of a semiconductor structure preparation method in the existing semiconductor device preparation process is weaker is solved, the mark through hole 500 in the semiconductor preparation method provided by the embodiment of the application can be suitable for any type of bonding and stripping process, one end of the mark through hole 500 is always exposed to the surface of a target semiconductor after stripping, the applicability is wider, and the reliability is higher;
In the second aspect, the positional accuracy of the subsequent device unit prepared based on the mark position of the mark through hole 500 can be improved, thereby improving the precision of the target semiconductor structure;
in a third aspect, in the target semiconductor structure obtained by the method for manufacturing a semiconductor structure provided by the embodiment of the present application, each oxygen-buried layer unit 210 in the first silicon layer in the top layer substrate 200 is independent from each other and is disposed at intervals, a gap exists between each oxygen-buried layer unit 210, once a transistor located on the first silicon layer in the top layer substrate 200 generates a collision ionization effect, an electron and a hole pair generated in the collision ionization effect can be guided to the supporting substrate 100 along the gap, so that performance influence on top functional devices such as a top transistor caused by accumulation of the generated electron and hole in the top layer substrate 200 is avoided, and robustness of the devices such as the transistor is improved;
in the fourth aspect, the conventional oxygen-buried layer covers the whole wafer, which affects the thermal conductivity of devices such as transistors on the top, and in the embodiment of the present application, the oxygen-buried layer units 210 are independent of each other and are arranged at intervals, and an interval gap exists between the oxygen-buried layer units 210, so that a heat dissipation space can be provided, and joule heat generated by the top functional device flows to the supporting substrate 100, so that the self-heating effect of the device is inhibited, and the heat dissipation performance of the semiconductor structure is improved; in the third aspect, the conventional buried oxide layer covers the whole wafer, and floating body effect (the threshold voltage of the device is caused to drift and the working state is unstable) is easy to generate due to the existence of large-area oxide, and in the embodiment of the present application, the buried oxide layer units 210 are independent and spaced apart from each other, and a gap exists between the buried oxide layer units 210, so that the floating body effect can be suppressed, even eliminated, and the effect of stabilizing the threshold voltage of the top functional device is further realized.
The top matrix 200 in an embodiment of the present application is briefly explained herein with reference to the drawings:
referring to fig. 4, 8 and 9, in the target first wafer that is not bonded, the top substrate 200 includes: stacked from below and above: a second silicon layer, a silicon oxide layer (BOX layer), and a first silicon layer, wherein the buried oxide layer unit 210 is at the first silicon layer;
the top layer substrate 200 in the intermediate semiconductor structure formed by bonding the target first wafer and the second wafer after inverting the target first wafer comprises: stacked from below and above: a first silicon layer, a silicon oxide layer (BOX layer), and a second silicon layer;
after the stripping, i.e. the stripping off of the second silicon layer in the intermediate semiconductor structure, the top layer matrix 200 in the final target semiconductor structure comprises only the first silicon layer comprising the buried oxide layer unit 210.
In an alternative embodiment of the present application, the exfoliation layer is a first oxide layer and the preceding device unit is a buried oxide layer unit 210; the latter device cell is the gate or drain of a transistor. In other words, in the embodiment of the present application, the first oxide layer is stripped during the stripping after bonding, which is used to align the buried oxide layer unit 210 with the gate or the drain in the top transistor during the preparation process, so as to achieve the precision of the semiconductor structure and improve the product yield and the product performance.
In an alternative embodiment of the present application, before the step 101 of forming the mark through hole 500 on the surface of the first initial wafer, the method for manufacturing a semiconductor structure further includes the following steps:
sequentially forming a second silicon dioxide layer and a silicon nitride layer on the surface of the first initial wafer;
with continued reference to fig. 2, a second silicon oxide layer (SiO 2) is grown on the surface of the first initial wafer by thermal oxidation, and then a silicon nitride layer (Si is grown by CVD (chemical vapor deposition) 3 N 4 ) The thickness of the second silicon dioxide layer can be 10-25 nm, and the thickness of the silicon nitride layer can be 50-250 nm, so that the silicon nitride layer is used for heat insulation and pollution prevention, and the prepared device or layer is prevented from being damaged or polluted at high temperature during photoetching.
Correspondingly, the marking through hole 500 penetrates the second silicon oxide layer and the silicon nitride layer and extends to the first oxide layer.
The marking through hole 500 penetrates through the second silicon oxide layer and the silicon nitride layer and extends to the first oxide layer, so that one end of the marking through hole 500 is conveniently exposed to the surface of the target semiconductor all the time after bonding stripping, alignment of the rear device unit is facilitated, position accuracy of the rear device unit prepared based on the marking position of the marking through hole 500 is improved, and further precision of the target semiconductor structure is improved. It should be noted that the extension to the first oxide layer may be the extension to the upper surface of the first oxide layer, or may extend into the first oxide layer, but does not penetrate the first oxide layer.
Referring to fig. 2 and fig. 5 together, in an alternative embodiment of the present application, the step 102 of preparing a preceding device unit in a first initial wafer based on the marking location of the marking through hole 500 to obtain a target first wafer includes the following steps 501-502:
step 501, preparing a preceding device unit in a first initial wafer based on the marking position of the marking through hole 500, so as to obtain an intermediate first wafer.
The preparation process of the preceding device unit is already described in detail in step 102, and will not be described in detail here.
Referring to fig. 2 and fig. 6 together, in an alternative embodiment of the present application, the step 501 of preparing a preceding device unit in a first initial wafer based on the marking position of the marking through hole 500 to obtain an intermediate first wafer may include the following steps 601-603:
step 601, etching a groove on the surface of the first initial wafer based on the mark position.
The grooves extend into the substrate above the first oxide layer in the first initial wafer. For example, in FIG. 2, the sandwich structure includes (from top to bottom: upper substrate-oxide layer-lower substrate) the grooves extending to the upper substrate.
And 602, forming a third silicon oxide layer with a first thickness on the surface of the etched first initial wafer based on a thermal oxidation process.
As shown in fig. 2, a third silicon oxide layer of 200A thickness is formed on the etched groove surface based on a thermal oxidation process.
And 603, growing a fourth silicon oxide layer with a second thickness on the surface of the formed third silicon oxide layer based on the ethyl silicate process to obtain an intermediate first wafer.
As in fig. 2, a fourth silicon oxide layer of a second thickness is grown on the surface of the formed third silicon oxide layer based on a ethyl silicate process (TEOS). Wherein the second thickness is greater than the first thickness.
The general temperature of the thermal oxidation process needs to be controlled above 900 ℃, the speed is low, but the film forming quality is high, certain defects can be generated after the wafer is etched, and the defect can be filled by forming a thinner third silicon oxide layer through the thermal oxidation process, so that the quality and the performance of a device are improved; after forming a fourth silicon oxide layer with better quality, the fourth silicon oxide layer can be formed based on an ethyl silicate process with higher film forming efficiency; through the superposition of the two processes, the film forming quality and the film forming efficiency can be simultaneously considered.
After the third silicon oxide layer and the fourth silicon oxide layer are formed through two processes, a Rapid Thermal Annealing (RTA) process can be performed to make the TEOS grown fourth silicon oxide layer film denser, and then as shown in fig. 2, the current wafer surface is treated by Chemical Mechanical Polishing (CMP) to improve the flatness of the wafer surface and remove the silicon oxide remaining on the surface layer.
And 502, removing the second silicon dioxide layer and the silicon nitride layer on the surface of the middle first wafer to obtain the target first wafer.
With continued reference to fig. 7, in an alternative embodiment of the present application, the step 502 of removing the second silicon oxide layer and the silicon nitride layer on the surface of the intermediate first wafer to obtain the target first wafer includes the following steps 701-702:
step 701, grinding the middle first wafer to a silicon nitride layer;
and step 702, rinsing the grinded intermediate first wafer to remove the silicon nitride layer and part of the second oxide layer, thereby obtaining the target first wafer.
For example, in fig. 2, after the completion of the preparation, the oxide on the crystal surface after polishing can be removed by an HF acid solution, and then the silicon nitride layer can be removed by hot phosphoric acid. In addition, the silicon oxide of the protruding portion may be further removed by an HF acid solution, or may be removed by other methods, which are not specifically limited herein, but only need to improve the flatness of the wafer surface. The second silicon dioxide layer and the silicon nitride layer on the surface of the first wafer in the middle can be removed after the preparation of the prior device unit is finished, and the wafer is protected by the silicon dioxide layer and the silicon nitride layer in the preparation process, so that the prepared device or layer is prevented from being damaged or polluted at high temperature during photoetching when the prior device unit is prepared.
In an alternative embodiment of the present application, the method for preparing a semiconductor structure further includes the following steps:
with continued reference to fig. 2 and 8, a first trap rich layer 300 is formed on the target first wafer surface;
the first trap rich layer 300 is laid on the surface of the first target wafer and is attached to each buried oxide layer unit 210. The first trap rich layer 300 may be made of a polycrystalline silicon material or an amorphous silicon material, and the thickness of the first trap rich layer 300 is 200 nm to 1000 nm.
Correspondingly, step 103, bonding the target first wafer and the second wafer to obtain the intermediate semiconductor structure, including the following steps:
and bonding the first trap rich layer 300 on the surface of the target first wafer with the second wafer to obtain the intermediate semiconductor structure.
For example, referring to fig. 8, a first trap rich layer 300 is formed on the surface of the target first wafer formed in fig. 2, and then the target first wafer is placed on the surface of the second wafer in a reverse manner for bonding, where the bonding surface is the bonding surface between the first trap rich layer 300 and the surface of the second wafer, so as to form the intermediate semiconductor structure in fig. 8. The process and parameters used in the bonding process can be flexibly adjusted according to practical situations, and are not limited in any way. It should be noted that the first trap rich layer 300 in the intermediate semiconductor structure is bonded to the support substrate 100 of the second wafer.
In an alternative embodiment of the present application, the first trap rich layer 300 in the first wafer is bonded to the second wafer, so as to obtain an intermediate semiconductor structure, and the first wafer and the second wafer may be bonded by using a low-temperature direct bonding process of a silicon wafer. The low-temperature direct bonding process of the silicon wafer can comprise the following steps: the process flows of CMP treatment, conventional cleaning, oxygen plasma activation treatment, hydrophilic treatment, room temperature pre-bonding, heat treatment, etc. are not described herein.
After bonding is completed, the intermediate semiconductor structure may be subjected to a correction process, for example, the second silicon layer of the top layer may be removed by a CMP (chemical polishing) process in fig. 8, and then the first silicon oxide layer may be removed by an HF acid solution or the like, thereby forming a target semiconductor structure having a flat surface.
In the first aspect, there is generally a fixed charge in the buried oxide layer, and the charge in the buried oxide layer attracts the opposite type of charge on the underlying support substrate 100 due to the attraction of the charge, thereby forming a conductive interface (PSC effect) on the surface of the support substrate 100, and reducing the effective resistivity of the support substrate 100. The formed conductive interface affects signal transmission between the upper layers, such as the top functional device layer, and other levels, and also affects the performance of the devices, such as rf devices or analog devices, in the top functional device layer, affecting the coupling between rf devices and the coupling between the top functional device and the substrate, resulting in signal interference. The existence of the buried oxide layer can cause the formation of the conductive interface, and in the embodiment of the application, a first trap-rich layer 300 is arranged between the supporting substrate 100 and the top layer substrate 200, and the first trap-rich layer 300 can capture electrons in the supporting substrate 100, so that the formation of the conductive interface in the supporting substrate 100 is inhibited, the signal influence among devices and circuits in the top semiconductor is avoided, and the signal transmission effect and the working performance of the semiconductor device are improved;
In the second aspect, since the first trap rich layer 300 is made of polysilicon or amorphous silicon material, and the top of the second wafer is made of polysilicon or amorphous silicon material, the bonding effect of the same material is better, and the product yield can be further improved.
In an alternative embodiment of the present application, the method for preparing a semiconductor structure further includes the following steps:
referring to fig. 9, a second trap rich layer 400 is formed on the surface of the second wafer;
the structure and the preparation method of the second trap-rich layer 400 may be the same as the first trap-rich layer 300, or may be different, and the embodiment of the present application is not limited specifically, and only the second trap-rich layer 400 and the first trap-rich layer 300 need to be made of the same material, i.e., the second trap-rich layer 400 may also be made of a polysilicon material or an amorphous silicon material, and the thickness of the second trap-rich layer 400 is 200 nm to 1000 nm.
Correspondingly, step 103, bonding the target first wafer and the second wafer to obtain the intermediate semiconductor structure, including the following steps:
and bonding the first trap rich layer 300 on the first wafer surface of the target with the second trap rich layer 400 on the second wafer surface to obtain the intermediate semiconductor structure.
With continued reference to fig. 9, a first trap rich layer 300 is formed on the surface of the target first wafer formed in fig. 2, and then the target first wafer is placed on the surface of the second trap rich layer 400 on the surface of the second wafer to bond, where the bonding surface is the bonding surface between the first trap rich layer 300 and the surface of the second trap rich layer 400, so as to form the intermediate semiconductor structure in fig. 9.
After bonding is completed, the intermediate semiconductor structure may be subjected to a correction process, for example, the second silicon layer in the top substrate may be removed by a CMP (chemical polishing) process in fig. 9, and then the first silicon oxide layer may be removed by an HF acid solution or the like, thereby forming a target semiconductor structure having a flat surface.
That is, the trap-rich layer is prepared on the surfaces of the first wafer and the second wafer, so that the formation of the conductive interface in the supporting substrate 100 can be inhibited, and on the premise of avoiding the influence of signals between devices and circuits in the top semiconductor, the preparation precision of the semiconductor product is improved by bonding the same materials, and the product performance and yield are further improved. Meanwhile, since the first trap rich layer 300 and the second trap rich layer 400 are made of the same material, bonding of the same material can improve bonding power and bonding interface flatness.
In an alternative embodiment of the present application, the method for preparing a semiconductor structure further includes the following steps:
the roughness of the surface of the first trap rich layer 300 and/or the second trap rich layer 400 is processed to a preset target value.
For example, the roughness of the surfaces of the first trap rich layer 300 and the second trap rich layer 400 can be processed to be less than 0.5 nm through a CMP (Chemical Mechanical Polishing) process, so that the flatness of the surfaces of the first trap rich layer 300 and the second trap rich layer 400 is improved, the problem that bonding cannot be performed due to protruding oxide after STI (shallow trench process) is avoided, and wafer bonding can be facilitated and the flatness of a bonding surface is improved after the roughness of the surfaces of the second trap rich layer 400 is processed to a preset target value.
After the roughness treatment is carried out, the steps of cleaning, plasma activation and the like can be carried out, and the embodiment of the application is not exhaustive and can be flexibly adjusted according to actual conditions.
One embodiment of the present application provides a semiconductor structure comprising:
a support substrate 100 and a first silicon layer stacked from below and above; the first silicon layer comprises a plurality of independent preceding device units which are arranged at intervals;
the mark through hole 500 is formed in the first silicon layer and penetrates through the first silicon layer; the marking via 500 is used to mark the marking location of the preceding device unit.
The schematic structural diagram of the semiconductor structure may refer to the target semiconductor structure obtained in fig. 4, and the marking through hole 500 in the semiconductor structure provided by the embodiment of the application penetrates through the first silicon layer; during the fabrication process, the marking via 500 is always present, regardless of the bond and the lift-off, and one end of the via remains exposed to the surface of the semiconductor structure after being lifted off along the lift-off layer, and the position of the preceding device unit can be determined based on the marking via 500 when alignment is subsequently required. I.e., the subsequent device cell corresponding to the prior device cell location is prepared through the marked via 500, a predominantly alignment of the subsequent device cell with the prior device cell can be achieved.
According to the first aspect, the defect that the alignment mark of the prior device unit is hidden in the wafer level or is directly stripped due to the bonding and stripping processes in the traditional mode is avoided, the technical problem that the applicability of a semiconductor structure preparation method in the existing semiconductor device preparation process is weaker is solved, the mark through hole 500 in the semiconductor preparation method provided by the embodiment of the application can be suitable for any type of bonding and stripping process, one end of the mark through hole 500 is always exposed to the surface of a target semiconductor after stripping, the applicability is wider, and the reliability is higher;
In the second aspect, the positional accuracy of the subsequent device unit prepared based on the mark position of the mark through hole 500 can be improved, thereby improving the precision of the obtained semiconductor structure;
in a third aspect, in the semiconductor structure obtained by the method for manufacturing a semiconductor structure provided by the embodiment of the present application, each buried oxide layer unit 210 in the first silicon layer is independent from each other and is disposed at intervals, a gap exists between each buried oxide layer unit 210, once a transistor located on the first silicon layer generates a collision ionization effect, an electron and a hole pair generated in the collision ionization effect can be guided to the supporting substrate 100 along the gap, so that the generated electron and hole are prevented from accumulating in the first silicon layer to affect performance of top functional devices such as a transistor at the top, and robustness of the devices such as the transistor is improved;
in the fourth aspect, the conventional oxygen-buried layer covers the whole wafer, which affects the thermal conductivity of devices such as transistors on the top, and in the embodiment of the present application, the oxygen-buried layer units 210 are independent of each other and are arranged at intervals, and an interval gap exists between the oxygen-buried layer units 210, so that a heat dissipation space can be provided, and joule heat generated by the top functional device flows to the supporting substrate 100, so that the self-heating effect of the device is inhibited, and the heat dissipation performance of the semiconductor structure is improved; in the third aspect, the conventional buried oxide layer covers the whole wafer, and floating body effect is easy to generate (the threshold voltage of the device is caused to drift, and the working state is unstable) due to the existence of large-area oxide, and in the embodiment of the application, the buried oxide layer units 210 are independent and are arranged at intervals, and interval gaps exist between the buried oxide layer units 210, so that the floating body effect can be restrained, even eliminated, and the effect of stabilizing the threshold voltage of the top functional device is further realized;
In an alternative embodiment of the present application, the semiconductor structure further includes:
and the trap-rich layer is paved between the supporting substrate and the first silicon layer and is attached to each preceding device unit.
The trap rich layer may be the first trap rich layer 300 on the surface of the first wafer, or may be the second trap rich layer 400 on the surface of the second wafer, or a combination of the first trap rich layer 300 and the second trap rich layer 400, which is not specifically limited in the embodiment of the present application.
In the first aspect, there is generally a fixed charge in the buried oxide layer, and the charge in the buried oxide layer attracts the opposite type of charge on the underlying support substrate 100 due to the attraction of the charge, thereby forming a conductive interface (PSC effect) on the surface of the support substrate 100, and reducing the effective resistivity of the support substrate 100. The formed conductive interface affects signal transmission between the upper layers, such as the top functional device layer, and other levels, and also affects the performance of the devices, such as rf devices or analog devices, in the top functional device layer, affecting the coupling between rf devices and the coupling between the top functional device and the substrate, resulting in signal interference. The existence of the buried oxide layer can cause the formation of the conductive interface, and in the embodiment of the application, a trap-rich layer is arranged between the support substrate 100 and the first silicon layer, and the trap-rich layer can capture electrons in the support substrate 100, so that the formation of the conductive interface in the support substrate 100 is inhibited, the signal influence among devices and circuits in the top semiconductor is avoided, and the signal transmission effect and the working performance of the semiconductor device are improved;
In the second aspect, the trap-rich layer is made of polysilicon or amorphous silicon material, and the top of the second wafer is made of polysilicon, amorphous silicon or monocrystalline silicon material, so that the bonding effect of the same material is better, and the product yield can be further improved.
In an alternative embodiment of the present application, the semiconductor structure further includes:
and the rear device unit is arranged at a target position corresponding to the mark position on the surface of the first silicon layer.
The following device unit refers to a device unit that needs to be aligned with the previous device unit, and the following device unit may be a functional device, or a part of a functional device, or a certain wiring in a level, or an etched groove, an etched through hole, etc. formed in the preparation process, which are not exhaustive, and the corresponding preparation method of the following device unit may be flexibly adjusted according to the actual content, which is not limited in detail herein.
In an alternative embodiment of the present application, the preceding device unit is a buried oxide layer unit; the latter device cell is the gate or drain of a transistor.
That is, the semiconductor structure provided by the embodiment of the application can realize the alignment of the buried oxide layer unit 210 and the grid electrode or the drain electrode in the top layer transistor based on the mark through hole 500 in the preparation process, and has higher precision, higher product yield and higher product performance.
The beneficial effects of the semiconductor device are already described in detail in the above embodiments, and are not described herein again.
It should be understood that, although the steps in the flowchart are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or stages are performed necessarily performed in sequence, but may be performed alternately or alternately with at least a portion of other steps or other steps.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (14)
1. A method of fabricating a semiconductor structure, comprising:
marking through holes are formed in the surface of the first initial wafer; wherein the marking through hole extends to the peeling layer of the first wafer;
preparing a preceding device unit in the first initial wafer based on the marking position of the marking through hole to obtain a target first wafer;
bonding the target first wafer and the second wafer to obtain an intermediate semiconductor structure;
stripping the intermediate semiconductor along the stripping layer to obtain a target semiconductor structure;
and preparing a subsequent device unit corresponding to the previous device unit position at a target position of the target semiconductor surface corresponding to the marking position.
2. The method of manufacturing a semiconductor structure according to claim 1, wherein the exfoliation layer is a first oxide layer and the preceding device cell is a buried oxide layer cell; the latter device cell is the gate or drain of a transistor.
3. The method of claim 2, wherein prior to the opening of the marking via on the first initial wafer surface, the method further comprises:
sequentially forming a second silicon dioxide layer and a silicon nitride layer on the surface of the first initial wafer;
correspondingly, the marking through hole penetrates through the second silicon oxide layer and the silicon nitride layer and extends to the first oxide layer.
4. The method of manufacturing a semiconductor structure according to claim 3, wherein the manufacturing a preceding device unit in the first initial wafer based on the mark position of the mark through hole, to obtain a target first wafer, includes:
preparing the prior device unit in the first initial wafer based on the marking position of the marking through hole to obtain an intermediate first wafer;
and removing the second silicon dioxide layer and the silicon nitride layer on the surface of the middle first wafer to obtain the target first wafer.
5. The method of manufacturing a semiconductor structure according to claim 4, wherein the manufacturing the preceding device unit in the first initial wafer based on the mark location of the mark via, resulting in an intermediate first wafer, comprises:
etching a groove on the surface of the first initial wafer based on the mark position; wherein the groove extends into a substrate above the first oxide layer in the first initial wafer;
forming a third silicon oxide layer with a first thickness on the surface of the etched first initial wafer based on a thermal oxidation process;
growing a fourth silicon oxide layer with a second thickness on the surface of the formed third silicon oxide layer based on an ethyl silicate process to obtain the intermediate first wafer; wherein the second thickness is greater than the first thickness.
6. The method of claim 4, wherein said removing the second silicon dioxide layer and the silicon nitride layer from the surface of the intermediate first wafer to obtain the target first wafer comprises:
grinding the middle first wafer to the silicon nitride layer;
and rinsing the grinded intermediate first wafer, and removing the silicon nitride layer and part of the second silicon dioxide layer to obtain the target first wafer.
7. The method of manufacturing a semiconductor structure of claim 4, further comprising:
forming a first trap-rich layer on the surface of the target first wafer;
correspondingly, the bonding the target first wafer and the second wafer to obtain the intermediate semiconductor structure includes:
and bonding the first trap rich layer on the surface of the target first wafer with the second wafer to obtain the intermediate semiconductor structure.
8. The method of manufacturing a semiconductor structure of claim 7, further comprising:
forming a second trap rich layer on the surface of the second wafer;
correspondingly, the bonding the target first wafer and the second wafer to obtain the intermediate semiconductor structure includes:
and bonding the first trap-rich layer on the surface of the target first wafer with the second trap-rich layer on the surface of the second wafer to obtain the intermediate semiconductor structure.
9. The method of fabricating a semiconductor structure of claim 8, further comprising:
and processing the roughness of the surfaces of the first trap rich layer and/or the second trap rich layer to a preset target value.
10. The method of claim 8, wherein the first trap rich layer and the second trap rich layer are each made of polysilicon or amorphous silicon material.
11. A semiconductor structure, comprising:
a support substrate and a first silicon layer stacked from below and above; the first silicon layer comprises a plurality of independent preceding device units which are arranged at intervals;
the mark through hole is formed in the first silicon layer and penetrates through the first silicon layer; the marking through holes are used for marking positions of the prior device units.
12. The semiconductor structure of claim 11, further comprising:
and the trap-rich layer is paved between the supporting substrate and the first silicon layer and is attached to each preceding device unit.
13. The semiconductor structure of claim 11, further comprising:
and the rear device unit is arranged at a target position corresponding to the mark position on the surface of the first silicon layer.
14. The semiconductor structure of claim 11, wherein the preceding device cell is a buried oxide layer cell; the latter device cell is the gate or drain of a transistor.
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