CN117115124A - Circuit board verification method and system based on image processing - Google Patents

Circuit board verification method and system based on image processing Download PDF

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Publication number
CN117115124A
CN117115124A CN202311136509.4A CN202311136509A CN117115124A CN 117115124 A CN117115124 A CN 117115124A CN 202311136509 A CN202311136509 A CN 202311136509A CN 117115124 A CN117115124 A CN 117115124A
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display
node
patch
verification
display area
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CN117115124B (en
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许滨
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Kunqian Computer Co ltd
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Kunqian Computer Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0004—Industrial image inspection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30141—Printed circuit board [PCB]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/30—Computing systems specially adapted for manufacturing

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  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • User Interface Of Digital Computer (AREA)

Abstract

The invention provides a circuit board verification method and a system based on image processing, wherein a first verification display interface is partitioned to obtain an entity display area, a primary result display area and a secondary result display area; generating a first display template corresponding to each circuit to be verified according to the patch layout diagram, and displaying the first display template in a first-level result display area; constructing a first display node corresponding to the circuit board to be verified, a second display node corresponding to the patch display area and a third display node corresponding to the verification dimension, generating a first display structure, and displaying in the second-level result display area; displaying the verification image in the entity display area, and updating the result attributes of the patch display area, the second display node and the third display node based on the verification result; and receiving click information of a user on the patch display area, the first display node, the second display node or the third display node, and carrying out linkage display on the verification image, the first display template and the first display structure according to the click information and corresponding result attributes.

Description

Circuit board verification method and system based on image processing
Technical Field
The present invention relates to data processing technology, and in particular, to a circuit board verification method and system based on image processing.
Background
Circuit boards are one of the important components of the electronics industry. Almost every electronic device, as small as an electronic watch, a calculator, as large as a computer, etc., has electronic components such as an integrated circuit, and a circuit board is used for electrically interconnecting the respective components. The circuit board comprises an insulating bottom plate, connecting wires and bonding pads for assembling and welding electronic elements, has the dual functions of a conductive line and the insulating bottom plate, but along with the continuous development of technology, the circuit board is increasingly more refined, miniaturized and high-density, so that various defects, such as welding leakage, paster inclination and the like, possibly exist in the welding process of the circuit board, and the normal use of the circuit board is affected.
Generally speaking, in the prior art, the technology such as optical detection and computer vision detection can be adopted to check the welding on the circuit board, but after the automatic check is carried out on the circuit board, only the circuit board with abnormal welding can be identified, and the welding patch with problems and the reasons of the abnormality can not be displayed in a linkage manner, so that the quick abnormal positioning of a user can not be assisted.
Therefore, how to link and display the abnormal patch area and the reason of the abnormality of the patch area to assist the user in rapidly positioning the abnormality becomes a urgent problem to be solved.
Disclosure of Invention
The embodiment of the invention provides a circuit board verification method and a circuit board verification system based on image processing, which can display abnormal patch areas and reasons of the abnormality of the patch areas in a linkage manner so as to assist a user to quickly locate the abnormality.
In a first aspect of the embodiment of the present invention, there is provided a circuit board verification method based on image processing, including:
generating a first verification display interface, and carrying out partition treatment on the first verification display interface to obtain an entity display area, a primary result display area and a secondary result display area;
obtaining patch layout diagrams of circuit boards to be verified of all types, generating first display templates corresponding to the circuit boards to be verified of all types one by one according to the patch layout diagrams, displaying the first display templates in the primary result display areas, wherein the first display templates comprise a plurality of patch display areas;
constructing a first display node corresponding to the circuit board to be verified, a second display node corresponding to the patch display area and a third display node corresponding to the verification dimension, generating a first display structure according to the first display node, the second display node and the third display node, and displaying the first display structure in the secondary result display area;
Collecting verification images of a circuit board to be verified and displaying the verification images in the entity display area, verifying the verification images according to a verification model to obtain verification results corresponding to each patch in each verification dimension, and updating result attributes of the patch display area, the second display node and the third display node based on the verification results;
and receiving click information of a user on the patch display area, the first display node, the second display node or the third display node, and carrying out linkage display on the verification image, the first display template and the first display structure according to the click information and the corresponding result attribute.
Optionally, in one possible implementation manner of the first aspect, the generating a first verification display interface, and performing partition processing on the first verification display interface to obtain an entity display area, a primary result display area, and a secondary result display area, includes:
a first verification display interface is called, a group of parallel boundary lines in the first verification display interface are obtained to serve as first parallel boundary lines, and the rest parallel boundary lines are taken as second parallel boundary lines;
determining a first intermediate point of the first parallel boundary line and a second intermediate point of the second parallel boundary line;
Dividing the first verification display interface according to the connection line of the first intermediate point or the second intermediate point to obtain a display area to be divided and a secondary result display area;
and acquiring two longer area lines in the display area to be divided as first parallel area lines, determining a third intermediate point of the first parallel area lines, and dividing the first verification display interface according to the connecting line of the third intermediate point to obtain an entity display area and a first-level result display area.
Optionally, in one possible implementation manner of the first aspect, the obtaining a patch layout diagram of each model of the circuit board to be verified, generating, according to the patch layout diagram, a first display template corresponding to each model of the circuit board to be verified one to one, includes:
obtaining patch layout diagrams of circuit boards to be verified of various types, extracting edge contours of edges of the circuit boards in the patch layout diagrams, obtaining initial display templates of the corresponding patch layout diagrams, and extracting preset patch display areas of the patch layout diagrams corresponding to various patches;
and updating the initial display templates based on the patch display areas to generate first display templates corresponding to the circuit boards to be verified in each model one by one.
Optionally, in one possible implementation manner of the first aspect, the verifying the verification image according to the verification model, to obtain verification results corresponding to each patch in each verification dimension, and updating, based on the verification results, result attributes of the patch display area, the second display node, and the third display node, includes:
performing verification on the verification image according to a verification model to obtain verification results corresponding to each patch in each verification dimension, wherein the verification dimensions at least comprise a patch position dimension, a patch posture dimension and a patch welding dimension, and the verification results comprise normal results or abnormal results;
if the checking results of the patch corresponding to all checking dimensions are normal results, taking the patch as a normal patch, taking a patch display area corresponding to the normal patch as a normal display area, and calling a preset normal display label to update the normal display area;
if the checking result of the patch corresponding to any checking dimension is an abnormal result, taking the patch as an abnormal patch, taking a patch display area corresponding to the abnormal patch as an abnormal display area, and calling a preset abnormal display label to update the abnormal display area;
And updating the second display node and the third display node according to the abnormal result.
Optionally, in a possible implementation manner of the first aspect, the updating the second display node and the third display node according to the abnormal result includes:
acquiring a second display node corresponding to the abnormal display area as a second abnormal node, and determining a verification dimension corresponding to the abnormal result as an abnormal dimension;
acquiring a plurality of third display nodes directly connected with the second abnormal nodes, and taking the third display nodes corresponding to the abnormal dimension as third abnormal nodes;
and displaying the second abnormal node and the third abnormal node in a display pixel value.
Optionally, in one possible implementation manner of the first aspect, the receiving click information of the patch display area, the first display node, the second display node, or the third display node by the user, and performing linkage display on the verification image, the first display template, and the first display structure according to the click information and the corresponding result attribute includes:
receiving click information of a user on the patch display area, determining the clicked patch display area as a patch linkage display area based on the click information, and carrying out linkage display on the verification image, the first display template and the first display structure based on the patch linkage display area;
And receiving click information of a user on the node in the first display structure, determining the clicked node as a linkage display node based on the click information, and carrying out linkage display on the verification image, the first display template and the first display structure based on the linkage display node and corresponding result attributes.
Optionally, in one possible implementation manner of the first aspect, the receiving the click information of the patch display area from the user, determining, based on the click information, the clicked patch display area as a patch linkage display area, and performing linkage display on the verification image, the first display template and the first display structure based on the patch linkage display area includes:
receiving click information of a user on any patch display area in the first display template, and determining the clicked patch display area as a patch linkage display area based on the click information;
positioning patches at the same position in the verification image as display patches based on the positions of the patch linkage display areas, and calling a linkage display frame to carry out frame selection on the display patches in the verification image;
acquiring a region line of the patch linkage display area in the first display template, and changing a pixel value of the region line into a preset display pixel value;
And determining a second display node corresponding to the patch linkage display area as a second retention node, acquiring a first display node and a third display node which are directly connected with the second retention node, and deleting the rest nodes in the first display structure to obtain a second display structure.
Optionally, in one possible implementation manner of the first aspect, the receiving click information of the node in the first display structure by the user, determining, based on the click information, the clicked node as a linked display node, and performing linked display on the verification image, the first display template and the first display structure based on the linked display node and the corresponding result attribute includes:
receiving click information of a user on any node in the first display structure, and determining the clicked node as a linkage display node based on the click information;
if the linkage display node is a first display node, all patches in the verification image are obtained to be used as display patches, and a selection frame is selected to carry out frame selection on the display patches in the verification image;
acquiring area lines of all the patch display areas in the first display template, changing pixel values of the area lines into preset display pixel values, and carrying out linkage display on the first display structure in the secondary result display area;
If the linkage display node is a second display node, the second display node is used as a second selected node, a patch display area corresponding to the second selected node is determined to be used as a selected display area, a regional line of the selected display area is obtained, and the pixel value of the regional line is changed into a preset display pixel value;
positioning patches at the same position in the verification image as selected patches based on the position of the selected display area, calling a linkage display frame to frame the selected patches in the verification image, and carrying out linkage display on the first display structure in the secondary result display area;
and if the linkage display node is a third display node, carrying out linkage display on the verification image, the first display template and the first display structure based on the third display node and the corresponding result attribute.
Optionally, in one possible implementation manner of the first aspect, if the linkage display node is a third display node, performing linkage display on the verification image, the first display template, and the first display structure based on the third display node and the corresponding result attribute, including:
if the linkage display node is a third display node, the third display node is used as a third selected node, and a second display node directly connected with the third selected node is determined to be used as a second connection node;
Acquiring a patch display area corresponding to the second connection node as a selected display area, acquiring a region line of the selected display area, and changing a pixel value of the region line into a preset display pixel value;
based on the position of the selected display area, positioning patches at the same position in the verification image to serve as selected patches, calling a linkage display frame to carry out frame selection on the selected patches in the verification image, and carrying out linkage display on the first display structure in the secondary result display area.
In a second aspect of the embodiment of the present invention, there is provided a circuit board verification system based on image processing, including:
the partition module is used for generating a first verification display interface, and partitioning the first verification display interface to obtain an entity display area, a primary result display area and a secondary result display area;
the generating module is used for acquiring patch layout diagrams of all types of circuit boards to be verified, generating first display templates corresponding to all types of circuit boards to be verified one by one according to the patch layout diagrams, displaying the first display templates in the primary result display areas, wherein the first display templates comprise a plurality of patch display areas;
The construction module is used for constructing a first display node corresponding to the circuit board to be verified, a second display node corresponding to the patch display area and a third display node corresponding to the verification dimension, generating a first display structure according to the first display node, the second display node and the third display node, and displaying the first display structure in the secondary result display area;
the updating module is used for collecting verification images of the circuit board to be verified and displaying the verification images in the entity display area, verifying the verification images according to the verification model to obtain verification results corresponding to each patch in each verification dimension, and updating the result attributes of the patch display area, the second display node and the third display node based on the verification results;
and the display module is used for receiving click information of a user on the patch display area, the first display node, the second display node or the third display node, and carrying out linkage display on the verification image, the first display template and the first display structure according to the click information and the corresponding result attribute.
In a third aspect of the embodiments of the present invention, there is provided a storage medium having stored therein a computer program for implementing the method of the first aspect and the various possible aspects of the first aspect when executed by a processor.
The beneficial effects of the invention are as follows:
1. the invention can carry out multidimensional display on the circuit board to be verified, can display corresponding verification images, first display structures and first display templates in a linkage way according to the requirements of users, and can assist the users to rapidly position abnormal patches and abnormal reasons corresponding to the abnormal patches. The invention can display the circuit board to be verified from 3 dimensions simultaneously, and simultaneously display the first display template, the first display structure display and the verification image of the circuit board to be verified, so that the corresponding patch display area, the second display node and the third display node are conveniently updated according to the verification results of each patch corresponding to each verification dimension, and the corresponding patches are displayed in a linkage manner according to the clicking information of the user, thereby helping the user to quickly locate the abnormal patches and the damage cause of the abnormal patches.
2. The invention can carry out regional display on the circuit board to be verified in multiple dimensions, respectively displays the circuit board to be verified in the primary result display area by the first display template of the circuit board to be verified, displays the circuit board to be verified in the secondary result display area by the first display structure, and displays the circuit board to be verified in the entity display area by the verification image, so that a user can determine the damaged circuit board and the corresponding damaged patch to be quickly positioned. According to the invention, the first verification display interface is partitioned into 3 areas, the screen is divided into 2 equally-divided areas, one equally-divided area is divided into a entity display area, a primary result display area and a secondary result display area again by a longer side, the first verification display interface is divided into the entity display area, the primary result display area and the secondary result display area, the secondary result display area needs to display a first display structure, and the first display structure can display whether a circuit board to be verified, a patch display area and verification dimensions are damaged or not, so that larger areas are needed to display the first verification display interface conveniently for subsequent users to observe and click, then a corresponding first display template is generated according to a patch layout diagram of the circuit board to be verified, a plurality of patch display areas contained in the first display template can display whether corresponding patches are abnormal or not according to normal display labels or abnormal display labels, a user can conveniently and rapidly locate abnormal patches, and simultaneously, nodes in the first display structure are synchronously updated, linkage display is convenient for subsequent users to click and determine abnormal dimensions of the abnormal patches.
3. According to the invention, the linkage display of the welding patches on the circuit board can be determined according to the display requirements of the user, so that the user is assisted in determining the abnormal dimension of the abnormal patches, and the subsequent maintenance of the abnormal dimension of the corresponding patches is facilitated. The user can click on the patch display area, the first display node, the second display node or the third display node, and the images displayed in the entity display area, the primary result display area and the secondary result display area are displayed in a linkage mode according to clicking operation of the user, so that the user can quickly locate normal and abnormal patches on the circuit board and determine the abnormal dimension of the abnormal patches, and meanwhile, the user is displayed in a linkage mode in the three display areas.
Drawings
FIG. 1 is a flow chart of a circuit board verification method based on image processing provided by the invention;
FIG. 2 is a schematic diagram of a first verification presentation interface according to the present invention;
FIG. 3 is a schematic view of a second display structure according to the present invention;
fig. 4 is a schematic structural diagram of a circuit board verification system based on image processing according to the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The technical scheme of the application is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
Referring to fig. 1, a flowchart of a circuit board verification method for image processing according to an embodiment of the present application is shown, where an execution subject of the method shown in fig. 1 may be a software and/or hardware device. The execution body of the present application may include, but is not limited to, at least one of: user equipment, network equipment, etc. The user equipment may include, but is not limited to, computers, smart phones, personal digital assistants (Personal Digital Assistant, abbreviated as PDA), and the above-mentioned electronic devices. The network device may include, but is not limited to, a single network server, a server group of multiple network servers, or a cloud of a large number of computers or network servers based on cloud computing, where cloud computing is one of distributed computing, and a super virtual computer consisting of a group of loosely coupled computers. This embodiment is not limited thereto. The method comprises the steps S1 to S5, and specifically comprises the following steps:
S1, generating a first verification display interface, and carrying out partition treatment on the first verification display interface to obtain an entity display area, a primary result display area and a secondary result display area.
It should be noted that in the prior art, the circuit board may be detected by optical detection, computer vision detection, etc. to detect the circuit board with the welding error, but the abnormal welding patch and the cause of the abnormality cannot be intuitively displayed to the user.
Therefore, the first verification display interface is generated, and the first verification display interface is subjected to partition processing to obtain the entity display area, the primary result display area and the secondary result display area, so that verification images, the first display templates and the first display structures can be conveniently and respectively displayed later, all patches and the states of the patches are displayed, and a user can conveniently and quickly locate the problem patches and corresponding abnormal reasons.
In some embodiments, in step S1 (generating a first verification display interface, and performing partition processing on the first verification display interface to obtain an entity display area, a primary result display area, and a secondary result display area), the method includes S11-S14:
s11, a first verification display interface is called, a group of parallel boundary lines in the first verification display interface are obtained to serve as first parallel boundary lines, and the rest parallel boundary lines are taken as second parallel boundary lines.
It can be understood that the invention can call the first verification display interface, and respectively obtain 2 groups of parallel interface lines in the first verification display interface, namely the first parallel boundary line and the second parallel boundary line, so as to facilitate the subsequent division of the screen by determining the intermediate point.
S12, determining a first middle point of the first parallel boundary line and a second middle point of the second parallel boundary line.
And S13, dividing the first verification display interface according to the connection line of the first intermediate point or the second intermediate point to obtain a display area to be divided and a secondary result display area.
It can be understood that the first intermediate point or the second intermediate point is respectively connected, and the first verification display interface is divided according to the connection to obtain a to-be-divided display area and a secondary result display area, and it is easy to understand that the first verification display interface is equally divided for the first time so as to divide the first verification display interface into 2 display areas, one is the to-be-divided display area, and the other is the secondary result display area.
S14, acquiring two longer area lines in the display area to be divided as first parallel area lines, determining a third intermediate point of the first parallel area lines, and dividing the first verification display interface according to the connecting line of the third intermediate point to obtain an entity display area and a first-level result display area.
It can be understood that the longer two area lines in the display area to be divided are taken as the first parallel area lines, the middle point of the first parallel area lines is determined to obtain the third middle point, and the first verification display interface is divided according to the connection line of the third middle point to obtain the entity display area and the first-level result display area.
It is easy to understand that the first verification display interface is divided for 2 times, so that the interface is divided into 3 display areas, namely an entity display area, a primary result display area and a secondary result display area, wherein the entity display area and the primary result display area are display areas obtained by dividing the display areas to be divided into equal parts again.
S2, obtaining patch layout diagrams of circuit boards to be verified of various types, generating first display templates corresponding to the circuit boards to be verified of various types one by one according to the patch layout diagrams, displaying the first display templates in the primary result display areas, wherein the first display templates comprise a plurality of patch display areas.
It should be noted that, each type of circuit board to be verified has a patch layout diagram corresponding to the circuit board to be verified, wherein the patch layout diagram is a standard circuit board diagram corresponding to each type of circuit board, and the patch layout diagram has a preset patch display area. It will be appreciated that the patch layout is a standard circuit board diagram corresponding to each model circuit board, and each patch on the standard circuit board diagram has a corresponding preset patch display area for reminding a user that the area can be soldered with the patch.
It can be understood that first display templates corresponding to the circuit boards to be verified in each model one by one are generated according to the patch layout diagram, the first display templates are displayed in the primary result display areas, and the first display templates comprise a plurality of patch display areas.
In some embodiments, in step S2 (obtaining a patch layout diagram of each model of circuit board to be verified, generating a first display template corresponding to each model of circuit board to be verified one by one according to the patch layout diagram), including S21-S22:
s21, obtaining patch layout diagrams of circuit boards to be verified of various types, extracting edge contours of edges of the circuit boards in the patch layout diagrams, obtaining initial display templates of the corresponding patch layout diagrams, and extracting preset patch display areas corresponding to the patch layout diagrams and the patches.
It can be understood that the edge contour of the edge of the circuit board in the patch layout is extracted, so as to obtain an initial display template corresponding to the patch layout, wherein the initial display template is the edge contour of the circuit board in the patch layout, and only the edge contour of the circuit board corresponding to the bottom plate is extracted, so as to obtain the initial display template. And extracting a patch layout diagram and a preset patch display area corresponding to each patch.
S22, updating the initial display templates based on the patch display areas, and generating first display templates corresponding to the circuit boards to be verified in each model one by one.
It can be understood that the extracted patch display area is used for updating the corresponding position in the initial display template, so that the first display templates corresponding to the circuit boards to be verified in one-to-one mode in various models are obtained.
S3, constructing a first display node corresponding to the circuit board to be verified, a second display node corresponding to the patch display area and a third display node corresponding to the verification dimension, generating a first display structure according to the first display node, the second display node and the third display node, and displaying the first display structure in the secondary result display area.
It can be understood that the invention constructs corresponding display nodes with the circuit board to be verified, the patch display area and the verification dimension respectively, constructs a first display node with the circuit board to be verified, constructs a second display node with the patch display area and constructs a third display node with the verification dimension.
Further, all the second display nodes are connected with the first display nodes respectively, and the third display nodes corresponding to all the verification dimensions are connected with all the second display nodes, so that a first display structure is generated, and the first display structure is displayed in the secondary result display area.
S4, collecting verification images of the circuit board to be verified and displaying the verification images in the entity display area, verifying the verification images according to the verification model to obtain verification results corresponding to each patch in each verification dimension, and updating result attributes of the patch display area, the second display node and the third display node based on the verification results.
It can be understood that, the verification image of the circuit board to be verified is displayed in the entity display area, and verification is performed on the verification image by using a verification model to obtain verification results corresponding to each patch in each verification dimension, for example, the verification results corresponding to each patch in each verification dimension on the verification image can be detected by using computer vision, optical detection can also be used, and the like, which are not described herein in detail in the prior art.
The verification dimension is a detection dimension of each patch, for example, a posture of the patch, whether the patch is missed to be welded, whether a position of the patch is misplaced, and the like, and a verification result is a normal result or an abnormal result.
Further, updating the result attributes of the patch display area, the second display node and the third display node by using the verification result.
In some embodiments, in step S4 (performing verification on the verification image according to a verification model to obtain verification results corresponding to each patch in each verification dimension, and updating result attributes of the patch display area, the second display node, and the third display node based on the verification results), the method includes S41-S44:
s41, performing verification on the verification image according to a verification model to obtain verification results corresponding to each patch in each verification dimension, wherein the verification dimensions at least comprise a patch position dimension, a patch posture dimension and a patch welding dimension, and the verification results comprise normal results or abnormal results.
It can be understood that the server may automatically perform verification on the verification image of the circuit board to be verified, so as to obtain verification results corresponding to each patch in each verification dimension, for example, verification results corresponding to the patch position dimension of the patch a are normal results, and verification results corresponding to the patch posture dimension of the patch a are abnormal results.
S42, if the checking results of the patch corresponding to all checking dimensions are normal results, taking the patch as a normal patch, taking a patch display area corresponding to the normal patch as a normal display area, and calling a preset normal display label to update the normal display area.
It should be noted that, the first display template is obtained from patch layout diagrams corresponding to the circuit boards to be verified by various types, so that the positions of the patch display areas in the first display template are in one-to-one correspondence with the positions of the corresponding patches in the verification image.
Therefore, if the verification results of the patch corresponding to all verification dimensions are normal results, the patch is used as a normal patch, and a patch display area corresponding to the normal patch is used as a normal display area, and at the moment, a preset normal display label is called to update the normal display area in the first display template.
For example, referring to fig. 2, if the verification results of the patch B corresponding to all verification dimensions are normal results, a preset normal display label is called to update the corresponding normal display area in the first display template, and hooking display is performed on the normal display area B corresponding to the patch B in the first display template.
S43, if the checking result of the patch corresponding to any checking dimension is an abnormal result, taking the patch as an abnormal patch, taking a patch display area corresponding to the abnormal patch as an abnormal display area, and calling a preset abnormal display label to update the abnormal display area.
It will be appreciated that if the verification result corresponding to any verification dimension of the patch is an abnormal result, for example, the verification result corresponding to the posture dimension of the patch a is an abnormal result, the patch welding is performed under the condition that the patch is bent.
Therefore, the patch is used as an abnormal patch, the patch display area corresponding to the abnormal patch is used as an abnormal display area, and the preset abnormal display label is called to update the abnormal display area.
For example, referring to fig. 2, if the verification result of the patch posture dimension corresponding to the patch a is an abnormal result, a preset abnormal display label is called to update the corresponding abnormal display area in the first display template, and the hook is played in the abnormal display area a corresponding to the patch a in the first display template.
S44, updating the second display node and the third display node according to the abnormal result.
It can be understood that the method and the device also update the second display node and the third display node in the first display structure according to the abnormal result, so that a subsequent user can conveniently and quickly determine the verification dimension of the abnormality corresponding to the abnormal patch, for example, the verification dimension of the abnormality of the patch A is the patch gesture dimension.
In some embodiments, in step S44 (updating the second exhibition node and the third exhibition node according to the exception result) includes S441-S443:
s441, a second display node corresponding to the abnormal display area is obtained to serve as a second abnormal node, and the verification dimension corresponding to the abnormal result is determined to serve as an abnormal dimension.
It is to be understood that the second display node corresponding to the abnormal display area is used as a second abnormal node, and the verification dimension corresponding to the abnormal result is determined as an abnormal dimension.
For example, an abnormality display area a corresponding to the patch a, and an abnormality of the posture of the patch corresponding to the patch a are used as abnormality dimensions.
S442, a plurality of third display nodes directly connected with the second abnormal node are obtained, and the third display node corresponding to the abnormal dimension is used as the third abnormal node.
It can be understood that a plurality of third display nodes directly connected with the second abnormal node are obtained, and the third display node corresponding to the abnormal dimension is used as the third abnormal node.
S443, displaying the second abnormal node and the third abnormal node in a display pixel value.
It will be appreciated that referring to fig. 2, if an abnormal node is shown, the second abnormal node and the third abnormal node are displayed with a display pixel value, for example, a black display, a blue display, and a red display, which are not limited herein.
S5, receiving click information of a user on the patch display area, the first display node, the second display node or the third display node, and carrying out linkage display on the verification image, the first display template and the first display structure according to the click information and corresponding result attributes.
It is understood that the user may click on the patch display area, the first display node, the second display node, or the third display node, thereby performing a coordinated display of the verification image, the first display template, and the first display structure.
It is easy to understand that the invention can carry out linkage display on the patch display area, the first display node, the second display node or the third display node clicked by the user and the related part according to the requirement of the user, and the images in the entity display area, the primary result display area and the secondary result display area are displayed in a linkage manner, so that the user can quickly determine the abnormal patch and the abnormal cause.
In some embodiments, in step S5 (receiving click information of the patch display area, the first display node, the second display node, or the third display node from the user, and performing coordinated display on the verification image, the first display template, and the first display structure according to the click information and the corresponding result attribute), the method includes S51-S52:
s51, receiving click information of a user on the patch display area, determining the clicked patch display area as a patch linkage display area based on the click information, and carrying out linkage display on the verification image, the first display template and the first display structure based on the patch linkage display area.
It can be appreciated that if the user clicks on the patch display area, the clicked patch display area is used as a patch linkage display area, and the verification image, the first display template and the first display structure are displayed in a linkage manner based on the patch linkage display area.
In some embodiments, in step S51 (receiving click information of the patch display area from the user, determining the clicked patch display area as a patch linkage display area based on the click information, and performing linkage display on the verification image, the first display template, and the first display structure based on the patch linkage display area), the method includes S511-S514:
S511, receiving click information of a user on any patch display area in the first display template, and determining the clicked patch display area as a patch linkage display area based on the click information.
It is understood that the clicked patch display area is used as a patch linkage display area. For example, the user clicks on the abnormality presentation area a.
S512, based on the positions of the patch linkage display areas, positioning patches at the same positions in the verification image to serve as display patches, and calling a linkage display frame to frame the display patches in the verification image.
It can be understood that all the patch display areas are extracted from the patch display areas of the patches in the patch layout diagram, so that the patches at the same position in the verification image can be directly positioned as display patches according to the positions of the patch linkage display areas, and the linkage display frames are taken to carry out frame selection on the display patches in the verification image.
For example, when the user clicks the abnormal display area a, the patch a corresponding to the abnormal display area a is automatically determined, and the linked display frame is invoked to frame the patch a, for example, a round frame is invoked to frame the patch a, so that the user can conveniently and quickly locate the problem patch.
S513, obtaining an area line of the patch linkage display area in the first display template, and changing the pixel value of the area line into a preset display pixel value.
It can be understood that the area line of the patch linkage display area in the first display template is obtained, and the pixel value of the area line is changed to a preset display pixel value, for example, the pixel value of the area line is changed to red, which is not limited herein.
S514, determining a second display node corresponding to the patch linkage display area as a second reserved node, acquiring a first display node and a third display node which are directly connected with the second reserved node, and deleting the rest nodes in the first display structure to obtain a second display structure.
It can be understood that determining the second display node corresponding to the patch linkage display area as the second retention node, retaining the first display node and the third display node which are directly connected with the second retention node, and deleting all other display nodes to obtain the second display structure.
For example, referring to fig. 3, a user selects an abnormal display area a, reserves a second display node corresponding to the abnormal display area a, reserves all display nodes directly connected with the second display node, and deletes the rest nodes to obtain a second display structure.
S52, receiving click information of a user on the node in the first display structure, determining the clicked node as a linkage display node based on the click information, and carrying out linkage display on the verification image, the first display template and the first display structure based on the linkage display node and corresponding result attributes.
It can be appreciated that the user can click on the node in the first display structure, take the clicked node as a linkage display node, and perform linkage display on the verification image, the first display template and the first display structure based on the linkage display node and the corresponding result attribute.
In some embodiments, in step S52 (receiving click information of a node in the first display structure from a user, determining the clicked node as a linked display node based on the click information, and performing linked display on the verification image, the first display template, and the first display structure based on the linked display node and the corresponding result attribute), S521-S526 include:
s521, receiving click information of a user on any node in the first display structure, and determining the clicked node as a linkage display node based on the click information.
It can be understood that the server may receive click information of a user on any node in the first display structure, and use the clicked node as a linkage display node.
S522, if the linkage display node is the first display node, all patches in the verification image are obtained to be used as display patches, and a selection frame is selected to frame the display patches in the verification image.
It is easy to understand that the user selects the first display node, and the first display node corresponds to the circuit board to be verified, so that the server displays all information on the circuit board and displays all patches.
It can be appreciated that if the linked display node is the first display node, all patches in the verification image are obtained as display patches, and a selection frame is selected to frame all the display patches in the verification image.
S523, obtaining all area lines of the patch display areas in the first display template, changing pixel values of the area lines into preset display pixel values, and carrying out linkage display on the first display structure in the second-level result display area.
It can be understood that the pixel values of the area lines of all the patch display areas in the first display template are changed to preset display pixel values, and meanwhile, the first display structure is displayed in a linkage way.
S524, if the linkage display node is a second display node, the second display node is taken as a second selected node, a patch display area corresponding to the second selected node is determined as a selected display area, a region line of the selected display area is obtained, and a pixel value of the region line is changed into a preset display pixel value.
It can be understood that if the linked display node is a second display node, the second display node is taken as a second selected node, the patch display area corresponding to the second selected node is determined as a selected display area, and the pixel value of the area line corresponding to the selected display area is changed to a preset display pixel value.
S525, positioning patches at the same positions in the verification image as selected patches based on the positions of the selected display areas, calling a linkage display frame to frame the selected patches in the verification image, and carrying out linkage display on the first display structure in the secondary result display area.
It will be appreciated that retrieving the linked display frame frames the patches (selected patches) in the verification image corresponding to the positions of the selected display areas and displaying the first display structure in a linked manner.
The selected patches are patches corresponding to the positions of the selected display areas in the verification image.
It will be appreciated that selection of the second display node highlights the corresponding tile and corresponding tile display area and does not operate on the first display structure.
S526, if the linkage display node is a third display node, carrying out linkage display on the verification image, the first display template and the first display structure based on the third display node and the corresponding result attribute.
It may be appreciated that if the linked display node is a third display node, the verification image, the first display template, and the first display structure are displayed in a linked manner based on the third display node and the corresponding result attribute.
In some embodiments, in step S526 (if the linked display node is a third display node, the verification image, the first display template, and the first display structure are displayed in a linked manner based on the third display node and the corresponding result attribute), including:
if the linkage display node is a third display node, the third display node is used as a third selected node, and a second display node directly connected with the third selected node is determined to be used as a second connection node.
It can be appreciated that when the linked display node is the third display node, the three display nodes are used as third selected nodes, and the second display node directly connected with the third selected nodes is determined to be used as the second connection node.
And acquiring a patch display area corresponding to the second connection node as a selected display area, acquiring a region line of the selected display area, and changing a pixel value of the region line into a preset display pixel value.
It can be understood that the patch display area corresponding to the second connection node is obtained as a selected display area, the area line of the selected display area is obtained, and the pixel value of the area line is changed to a preset display pixel value.
Based on the position of the selected display area, positioning patches at the same position in the verification image to serve as selected patches, calling a linkage display frame to carry out frame selection on the selected patches in the verification image, and carrying out linkage display on the first display structure in the secondary result display area.
It can be understood that the method and the device can perform frame selection on the selected patch corresponding to the second connection node directly connected with the third selected node, and simultaneously perform linkage display on the first display structure in the secondary result display area.
It is to be understood that, the principle is the same as that of selecting the second display node, when the user selects the third display node, the second display node connected with the third display node is first determined to be the second connection node, and the patch display area corresponding to the second connection node and the patch corresponding to the patch display area are determined to be highlighted.
Through the embodiment, the abnormal patch and the cause of the abnormality at the abnormal circuit board can be displayed, and the multidimensional linkage display can be performed according to the requirement of a user, so that the user is assisted in rapidly positioning the abnormal patch and knowing the cause of the abnormality.
On the basis of the above embodiment, when the user clicks the third display node, the server may further call, according to the result attribute of the third display node, a patch display layer preset corresponding to each third display node, where the patch display layer includes a normal display layer and an abnormal display layer, and performs coverage display on a corresponding patch linkage display area, and specifically includes:
and if the linkage display node is a third display node, taking the third display node as a third selected node, and calling a normal display layer corresponding to the third selected node when judging that the third selected node does not display with the display pixel value.
It can be understood that if the linked display node is a third display node, the third display node is taken as a third selected node, and when the third selected node is judged not to be displayed with the display pixel value, the verification dimension corresponding to the third selected node is indicated to be a normal result, and the normal display layer corresponding to the third selected node is called.
And acquiring a second display node directly connected with the third selected node as a second connection node, and determining a patch display area corresponding to the second connection node as a selected display area.
It can be appreciated that the patch display area corresponding to the second connection node is determined as the selected display area.
And receiving the triggering time of clicking information of the third selected node by a user, calling the normal display layer to cover the upper part of the selected display area based on the triggering time, acquiring a region line of the selected display area in the first display template, and changing the pixel value of the region line into a preset display pixel value.
It can be understood that, based on the triggering duration, the normal display layer is invoked to cover the upper side of the selected display area, and the pixel value of the area line of the selected display area in the first display template is changed to a preset display pixel value, when the user triggers the normal third display node, the normal display layer, such as a green layer, is invoked to cover the upper side of the selected display area, which represents that the verification dimension is normal, and when the gesture of clicking the third selected node by the user is released, the corresponding normal display layer is automatically cancelled. It will be appreciated that if the third presentation node is abnormal, an abnormal presentation layer, such as a red layer, is invoked to cover the corresponding selected presentation area, representing the verification dimension as abnormal.
And based on the selected display area, determining the corresponding patch as the selected patch, calling a linkage display frame to carry out frame selection on the selected patch, and carrying out linkage display on the first display structure in the secondary result display area.
It will be appreciated that consistent with the principles of step S525, a coordinated presentation is performed.
Referring to fig. 4, a circuit board verification system for image processing according to an embodiment of the present invention includes:
the partition module is used for generating a first verification display interface, and partitioning the first verification display interface to obtain an entity display area, a primary result display area and a secondary result display area;
the generating module is used for acquiring patch layout diagrams of all types of circuit boards to be verified, generating first display templates corresponding to all types of circuit boards to be verified one by one according to the patch layout diagrams, displaying the first display templates in the primary result display areas, wherein the first display templates comprise a plurality of patch display areas;
the construction module is used for constructing a first display node corresponding to the circuit board to be verified, a second display node corresponding to the patch display area and a third display node corresponding to the verification dimension, generating a first display structure according to the first display node, the second display node and the third display node, and displaying the first display structure in the secondary result display area;
The updating module is used for collecting verification images of the circuit board to be verified and displaying the verification images in the entity display area, verifying the verification images according to the verification model to obtain verification results corresponding to each patch in each verification dimension, and updating the result attributes of the patch display area, the second display node and the third display node based on the verification results;
and the display module is used for receiving click information of a user on the patch display area, the first display node, the second display node or the third display node, and carrying out linkage display on the verification image, the first display template and the first display structure according to the click information and the corresponding result attribute.
The present invention also provides a storage medium having stored therein a computer program for implementing the methods provided by the various embodiments described above when executed by a processor.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (10)

1. A circuit board verification method based on image processing, comprising:
generating a first verification display interface, and carrying out partition treatment on the first verification display interface to obtain an entity display area, a primary result display area and a secondary result display area;
obtaining patch layout diagrams of circuit boards to be verified of all types, generating first display templates corresponding to the circuit boards to be verified of all types one by one according to the patch layout diagrams, displaying the first display templates in the primary result display areas, wherein the first display templates comprise a plurality of patch display areas;
constructing a first display node corresponding to the circuit board to be verified, a second display node corresponding to the patch display area and a third display node corresponding to the verification dimension, generating a first display structure according to the first display node, the second display node and the third display node, and displaying the first display structure in the secondary result display area;
collecting verification images of a circuit board to be verified and displaying the verification images in the entity display area, verifying the verification images according to a verification model to obtain verification results corresponding to each patch in each verification dimension, and updating result attributes of the patch display area, the second display node and the third display node based on the verification results;
And receiving click information of a user on the patch display area, the first display node, the second display node or the third display node, and carrying out linkage display on the verification image, the first display template and the first display structure according to the click information and the corresponding result attribute.
2. The image processing-based circuit board verification method according to claim 1, wherein,
the generating a first verification display interface, and performing partition processing on the first verification display interface to obtain an entity display area, a primary result display area and a secondary result display area, including:
a first verification display interface is called, a group of parallel boundary lines in the first verification display interface are obtained to serve as first parallel boundary lines, and the rest parallel boundary lines are taken as second parallel boundary lines;
determining a first intermediate point of the first parallel boundary line and a second intermediate point of the second parallel boundary line;
dividing the first verification display interface according to the connection line of the first intermediate point or the second intermediate point to obtain a display area to be divided and a secondary result display area;
and acquiring two longer area lines in the display area to be divided as first parallel area lines, determining a third intermediate point of the first parallel area lines, and dividing the first verification display interface according to the connecting line of the third intermediate point to obtain an entity display area and a first-level result display area.
3. The image processing-based circuit board verification method according to claim 2, wherein,
the method for obtaining the patch layout diagrams of the circuit boards to be verified of all types comprises the steps of generating first display templates corresponding to the circuit boards to be verified of all types one by one according to the patch layout diagrams, and comprising the following steps:
obtaining patch layout diagrams of circuit boards to be verified of various types, extracting edge contours of edges of the circuit boards in the patch layout diagrams, obtaining initial display templates of the corresponding patch layout diagrams, and extracting preset patch display areas of the patch layout diagrams corresponding to various patches;
and updating the initial display templates based on the patch display areas to generate first display templates corresponding to the circuit boards to be verified in each model one by one.
4. The image processing-based circuit board verification method according to claim 1, wherein,
the verification is carried out on the verification image according to a verification model to obtain verification results corresponding to each patch in each verification dimension, and the updating of the result attributes of the patch display area, the second display node and the third display node is carried out based on the verification results, and the method comprises the following steps:
performing verification on the verification image according to a verification model to obtain verification results corresponding to each patch in each verification dimension, wherein the verification dimensions at least comprise a patch position dimension, a patch posture dimension and a patch welding dimension, and the verification results comprise normal results or abnormal results;
If the checking results of the patch corresponding to all checking dimensions are normal results, taking the patch as a normal patch, taking a patch display area corresponding to the normal patch as a normal display area, and calling a preset normal display label to update the normal display area;
if the checking result of the patch corresponding to any checking dimension is an abnormal result, taking the patch as an abnormal patch, taking a patch display area corresponding to the abnormal patch as an abnormal display area, and calling a preset abnormal display label to update the abnormal display area;
and updating the second display node and the third display node according to the abnormal result.
5. The method for inspecting a circuit board based on image processing according to claim 4, wherein,
the updating processing of the second display node and the third display node according to the abnormal result comprises the following steps:
acquiring a second display node corresponding to the abnormal display area as a second abnormal node, and determining a verification dimension corresponding to the abnormal result as an abnormal dimension;
acquiring a plurality of third display nodes directly connected with the second abnormal nodes, and taking the third display nodes corresponding to the abnormal dimension as third abnormal nodes;
And displaying the second abnormal node and the third abnormal node in a display pixel value.
6. The image processing-based circuit board verification method according to claim 1, wherein,
the receiving user clicks information on the patch display area, the first display node, the second display node or the third display node, and performing linkage display on the verification image, the first display template and the first display structure according to the clicking information and corresponding result attributes, including:
receiving click information of a user on the patch display area, determining the clicked patch display area as a patch linkage display area based on the click information, and carrying out linkage display on the verification image, the first display template and the first display structure based on the patch linkage display area;
and receiving click information of a user on the node in the first display structure, determining the clicked node as a linkage display node based on the click information, and carrying out linkage display on the verification image, the first display template and the first display structure based on the linkage display node and corresponding result attributes.
7. The method for inspecting a circuit board based on image processing according to claim 6, wherein,
The receiving user is to the click information of paster show district, based on click information confirms the paster show district that is clicked as paster linkage show district, based on the linkage show district of paster carries out the linkage show to verification image, first show template and first show structure, includes:
receiving click information of a user on any patch display area in the first display template, and determining the clicked patch display area as a patch linkage display area based on the click information;
positioning patches at the same position in the verification image as display patches based on the positions of the patch linkage display areas, and calling a linkage display frame to carry out frame selection on the display patches in the verification image;
acquiring a region line of the patch linkage display area in the first display template, and changing a pixel value of the region line into a preset display pixel value;
and determining a second display node corresponding to the patch linkage display area as a second retention node, acquiring a first display node and a third display node which are directly connected with the second retention node, and deleting the rest nodes in the first display structure to obtain a second display structure.
8. The method for inspecting a circuit board based on image processing according to claim 6, wherein,
the method for displaying the verification image, the first display template and the first display structure in a linkage way comprises the steps of receiving click information of a user on a node in the first display structure, determining the clicked node as a linkage display node based on the click information, and displaying the verification image, the first display template and the first display structure in a linkage way based on the linkage display node and corresponding result attributes, wherein the method comprises the following steps:
receiving click information of a user on any node in the first display structure, and determining the clicked node as a linkage display node based on the click information;
if the linkage display node is a first display node, all patches in the verification image are obtained to be used as display patches, and a selection frame is selected to carry out frame selection on the display patches in the verification image;
acquiring area lines of all the patch display areas in the first display template, changing pixel values of the area lines into preset display pixel values, and carrying out linkage display on the first display structure in the secondary result display area;
if the linkage display node is a second display node, the second display node is used as a second selected node, a patch display area corresponding to the second selected node is determined to be used as a selected display area, a regional line of the selected display area is obtained, and the pixel value of the regional line is changed into a preset display pixel value;
Positioning patches at the same position in the verification image as selected patches based on the position of the selected display area, calling a linkage display frame to frame the selected patches in the verification image, and carrying out linkage display on the first display structure in the secondary result display area;
and if the linkage display node is a third display node, carrying out linkage display on the verification image, the first display template and the first display structure based on the third display node and the corresponding result attribute.
9. The image processing-based circuit board verification method according to claim 8, wherein,
if the linked display node is a third display node, performing linked display on the verification image, the first display template and the first display structure based on the third display node and the corresponding result attribute, including:
if the linkage display node is a third display node, the third display node is used as a third selected node, and a second display node directly connected with the third selected node is determined to be used as a second connection node;
acquiring a patch display area corresponding to the second connection node as a selected display area, acquiring a region line of the selected display area, and changing a pixel value of the region line into a preset display pixel value;
Based on the position of the selected display area, positioning patches at the same position in the verification image to serve as selected patches, calling a linkage display frame to carry out frame selection on the selected patches in the verification image, and carrying out linkage display on the first display structure in the secondary result display area.
10. A circuit board verification system based on image processing, comprising:
the partition module is used for generating a first verification display interface, and partitioning the first verification display interface to obtain an entity display area, a primary result display area and a secondary result display area;
the generating module is used for acquiring patch layout diagrams of all types of circuit boards to be verified, generating first display templates corresponding to all types of circuit boards to be verified one by one according to the patch layout diagrams, displaying the first display templates in the primary result display areas, wherein the first display templates comprise a plurality of patch display areas;
the construction module is used for constructing a first display node corresponding to the circuit board to be verified, a second display node corresponding to the patch display area and a third display node corresponding to the verification dimension, generating a first display structure according to the first display node, the second display node and the third display node, and displaying the first display structure in the secondary result display area;
The updating module is used for collecting verification images of the circuit board to be verified and displaying the verification images in the entity display area, verifying the verification images according to the verification model to obtain verification results corresponding to each patch in each verification dimension, and updating the result attributes of the patch display area, the second display node and the third display node based on the verification results;
and the display module is used for receiving click information of a user on the patch display area, the first display node, the second display node or the third display node, and carrying out linkage display on the verification image, the first display template and the first display structure according to the click information and the corresponding result attribute.
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