CN117097154A - Three-in-one chip with boost, current mirror and sample hold functions - Google Patents

Three-in-one chip with boost, current mirror and sample hold functions Download PDF

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Publication number
CN117097154A
CN117097154A CN202310942732.1A CN202310942732A CN117097154A CN 117097154 A CN117097154 A CN 117097154A CN 202310942732 A CN202310942732 A CN 202310942732A CN 117097154 A CN117097154 A CN 117097154A
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China
Prior art keywords
module
current mirror
chip
chip pin
current
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CN202310942732.1A
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Inventor
周媛媛
李景虎
黄云洪
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Xiamen EOchip Semiconductor Co Ltd
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Xiamen EOchip Semiconductor Co Ltd
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Priority to CN202310942732.1A priority Critical patent/CN117097154A/en
Publication of CN117097154A publication Critical patent/CN117097154A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a three-in-one chip with boost, current mirror and sample hold functions, belongs to the field of integrated circuits and optical communication, and aims to solve the problems that the traditional ROSA is overlarge in volume, the production cost is overlarge, and the research, the development and the debugging of products of different chip design companies are complicated. The invention has the single-channel structure: the method comprises the steps that a boosting module, a current mirror module and a sample holding module are designed on a chip by adopting the same process, the boosting module lifts 3.3V power supply voltage outside the chip to 30V-60V as the power supply of the current mirror module, the current mirror module generates mirror image voltage and fast-changing mirror image current, and the mirror image voltage output by the current mirror module provides reverse bias high voltage for an APD; the sampling and holding module samples and holds the rapidly-changed mirror current transmitted by the current mirror, and outputs the sampling and holding result through a chip pin VOP; two-channel structure: the same technology is adopted on a chip to design a boost loop module, a boost loop sharing module, a double-path current mirror module and a double-path sampling and holding module.

Description

Three-in-one chip with boost, current mirror and sample hold functions
Technical Field
The invention belongs to the field of integrated circuits and optical communication, and relates to a chip with three-in-one boost, current mirror and sample-hold functions.
Background
At a receiving end (ROSA) of the optical fiber communication module, an optical signal is converted into a current signal through an Avalanche Photodiode (APD), and then the current signal is converted into a voltage signal through a transimpedance amplifier (TIA). When an Avalanche Photodiode (APD) works normally, about 45V of reverse bias high voltage is needed to be provided at two ends of the APD, so that electrons in the APD form an avalanche state, and an amplification effect, namely a multiplication effect of the APD, is generated on weak photocurrent. Therefore, the APD has high sensitivity and small dark current, and can receive optical signals sent from a long distance.
Fig. 1 shows a conventional rosa_pcb structure. In fig. 1, avalanche photodiodes APD and TIA are packaged in the form of components TO-CAN, and a boost DC/DC boost chip with some necessary peripheral components converts the 3.3V input voltage TO 30V-60V output voltage, which is supplied TO SAMPLE HOLD chip SAMPLE HOLD. The current mirror output MIROUT of SAMPLE HOLD chip SAMPLE HOLD provides the 30-60V reverse bias voltage and current required by the APD. The magnitude of the photocurrent generated by the APD is monitored via the MIR1 and MIR2 pins. And welding the DC/DC boosting chip, the current mirror sampling holding chip and the TO-CAN on the same PCB circuit board TO form an optical module of the receiving end.
In practical application, the DC/DC boost chip and the current mirror sample-hold chip of different chip design companies are required to be purchased for matching, and the compatibility and stability of the two chips are required to be considered by optical module research personnel. The single DC/DC chip is generally packaged by TO23-6, the packaging area is 2.9mm by 2.8mm, the packaging area of the current mirror sample-hold chip is 3.5mm by 3.5mm, and the two chips are required TO be placed on a PCB circuit board at a certain distance, so that the volume of the whole receiving end optical module is much larger, and the volume and cost of the SFP package cannot be further reduced.
Disclosure of Invention
Aiming at the problems of overlarge volume and overlarge production cost of the traditional ROSA and complex research, development and debugging of products of different chip design companies, the invention provides a three-in-one chip with boost, current mirror and sample-hold functions.
The three-in-one chip with boost, current Mirror and Sample Hold functions adopts the same technology to design a boost module DC/DC, a Current Mirror module Current Mirror and a Sample Hold module Sample Hold on the chip, and is in a single-channel mode;
the boosting module DC/DC boosts the 3.3V power supply voltage outside the chip to 30V-60V as a power supply of the Current Mirror module Current Mirror, the Current Mirror module Current Mirror generates Mirror voltage and fast-changing Mirror Current, and the Mirror voltage output by the Current Mirror module Current Mirror provides reverse bias high voltage for the avalanche photodiode APD;
The Sample Hold module samples and holds the rapidly-changed Mirror Current transmitted by the Current Mirror, and transmits the sampled and held result to an external analog-to-digital conversion module ADC through a chip pin VOP to analyze the rapidly-changed APD photocurrent.
Preferably, the three-in-one chip is characterized by further comprising a lifting voltage control circuit, wherein the lifting voltage control circuit is used as a three-in-one chip peripheral circuit and is used for adjusting the DC/DC output voltage of the boosting module to obtain different output voltages within the range of 30V-60V and returning the different output voltages to the inside of the chip.
Preferably, the boost module DC/DC includes a switching transistor Switch, a Driver, a modulation comparator PWM COM, an operational amplifier A1, a saw-tooth oscillator Sawtooth OSC, and a Current detection Current Sense;
the output signal of the sawtooth wave oscillator and the output signal of the Current Sense are added and then connected to the inverting terminal of the PWM comparator PWM COM;
the inverting input end of the operational amplifier A1 is connected with the chip pin FB; the chip pin FB is connected with an external lifting voltage control circuit;
the non-inverting input end of the operational amplifier A1 is connected with a reference voltage VREF;
the output end of the operational amplifier A1 is connected with the positive phase end of the pulse width modulation comparator PWM COM;
the output end of the pulse width modulation comparator PWM COM is connected with the input end of the Driver;
The output end of the Driver is connected with the grid electrode of the switching tube Switch;
the source end of the switching tube Switch is connected with the ground;
the drain end of the switching tube Switch is connected with the chip pin SW; the chip pin SW is connected with an external VDC3.3V power supply;
the Current Mirror module Current Mirror comprises PMOS transistors MP 1-MP 4, a Current limiting unit Current LIMIT and an operational amplifier A2; the source ends of the PMOS transistors MP 1-MP 3 are simultaneously connected with a chip pin MIRIN;
the drain end of the PMOS transistor MP1 is connected with the input end of the CURRENT LIMIT unit;
the output end of the CURRENT LIMIT unit is connected with the source end of the PMOS transistor MP 4;
the other output end of the CURRENT LIMIT unit is connected with a chip pin RLIM;
the gate end of the PMOS transistor MP4 is connected with the output end of the operational amplifier A2;
the drain end of the PMOS transistor MP4 is connected with a chip pin MIROUT; providing an inverse bias high voltage for an Avalanche Photodiode (APD) through a chip pin (MIROUT);
the drain end of the PMOS transistor MP2 is connected with a chip pin MIR1;
the drain end of the PMOS transistor MP3 is connected with a chip pin MIR2;
the external monitoring circuit collects Mirror Current generated by a Current Mirror module Current Mirror through a chip pin MIR1 and a chip pin MIR2 so as to monitor the photo Current of the APD; the mirror current is also output to a Sample Hold module;
The Sample Hold module comprises a Sample Hold unit Sample/Hold, an operational amplifier A3, a full differential operational amplifier A4, a D trigger Q and an exclusive or gate XOR;
two input ends of the SAMPLE/HOLD unit are respectively connected with the drain end of the PMOS transistor MP2 and the drain end of the MP 3;
the pair of output ends of the SAMPLE/HOLD unit are respectively connected with the non-inverting input end and the inverting input end of the full differential operational amplifier A4; the inverting output end of the full differential operational amplifier A4 is connected with a chip pin VOP; the chip pin VOP is connected with an external analog-to-digital conversion module ADC;
the other pair of output ends of the SAMPLE/HOLD unit are respectively connected with the non-inverting input end of the operational amplifier A3 and the chip pin GAIN;
the output end of the operational amplifier A3 is connected with the data input end D of the trigger Q;
the output end Q of the D trigger Q is connected with a chip pin GAIN through a resistor R11;
the output end of the exclusive or gate XOR is connected with the clock end CLK of the D trigger Q;
two input ends of the exclusive or gate XOR are respectively connected with a chip pin SENOR and a chip pin SEN;
the chip pin SEN is a sample hold enable signal input pin, and the chip pin SENXOR is a sample enable trigger edge adjustment pin.
Preferably, the sample hold enabling signal input by the chip pin SEN enters a signal hold stage after a bundle of sample pulse signals is input; when the SENSOR pin is low, the rising edge of the SEN pin triggers sampling enabling; when the SEN xor pin is high, the SEN pin falling edge triggers the sample enable.
The invention also provides another technical scheme, and the three-in-one chip with boost, current Mirror and Sample Hold functions adopts the same technology to design a boost loop module DC/DC loop1, a boost loop module DC/DC loop2, a boost loop sharing module Common Block, a double-path Current Mirror module Current Mirror and a double-path Sample Hold module Sample Hold on the chip, which is a double-channel mode;
the method comprises the steps that a boosting loop module DC/DC loop1 and a boosting loop module DC/DC loop2 respectively raise an external 3.3V power voltage to 30V-60V to serve as two paths of input currents of a two-path Current Mirror module Current Mirror, the two paths of Current Mirror module Current Mirror generates two paths of Mirror voltages and fast-changing Mirror currents, and the two paths of Mirror voltages respectively provide reverse bias high voltages for two avalanche photodiodes APDs;
the two-way sampling and holding module Sample Hold samples and holds two paths of rapidly-changed Mirror currents transmitted by the Current Mirror, and the two sampling and holding results are respectively transmitted to the two external analog-digital conversion modules ADC to analyze the photo-currents of the APD which are rapidly changed.
Preferably, the circuit structures of the boost loop module DC/DC loop1 and the boost loop module DC/DC loop2 are the same, and a switch output end SW1 of the boost loop module DC/DC loop1 is connected with a chip pin SW1;
The feedback signal FB1 of the boost loop module DC/DC loop1 is connected with the chip pin FB1;
the plurality of output ends of the boosting loop sharing module Common Block are connected with the plurality of input ends of the boosting loop module DC/DC loop 1;
the switch output end SW2 of the boost loop module DC/DC loop2 is connected with the chip pin SW2;
the feedback signal FB2 of the boost loop module DC/DC loop2 is connected with the chip pin FB2;
the plurality of output ends of the boosting loop sharing module Common Block are connected with the plurality of input ends of the boosting loop module DC/DC loop 2;
the voltage output by the DC/DC loop1 of the boost loop module is introduced into the chip through a chip pin MIRIN_CH1 after being subjected to proportion adjustment, and the voltage output by the DC/DC loop2 of the boost loop module is introduced into the chip through a chip pin MIRIN_CH2 after being subjected to proportion adjustment;
the Current Mirror input end MIRIN_CH1 of the Current Mirror module Current Mirror is connected with the chip pin MIRIN_CH1;
the Current Mirror input end MIRIN_CH1 of the Current Mirror module Current Mirror is connected with the chip pin MIRIN_CH1;
the Current limiting end RLIM_CH1 of the Current Mirror module Current Mirror is connected with the chip pin RLIM_CH1;
the Current limiting end RLIM_CH2 of the Current Mirror module Current Mirror is connected with the chip pin RLIM_CH2;
the Current Mirror module Current Mirror has its Current Mirror output MIR1_CH1 connected to the chip pins MIR1_CH1 and the Current Mirror input MIR1_CH1 of the Sample Hold module Sample Hold;
The Current Mirror module Current Mirror has its Current Mirror output MIR2_CH1 connected to the chip pin MIR2_CH1 and the Current Mirror input MIR2_CH1 of the Sample Hold module Sample Hold;
the Current Mirror module Current Mirror has its Current Mirror output MIR1_CH2 connected to the chip pins MIR1_CH2 and the Current Mirror input MIR1_CH2 of the Sample Hold module Sample Hold;
the Current Mirror module Current Mirror has its Current Mirror output MIR 2-CH 2 connected to the chip pin MIR 2-CH 2 and the Current Mirror input MIR 2-CH 2 of the Sample Hold module Sample Hold;
the output end MIROUT_CH1 of the Current Mirror module Current Mirror is connected with a chip pin MIROUT_CH1; providing an inverse bias high voltage for the avalanche photodiode APD1 through a chip pin mirout_ch1;
the output end MIROUT_CH2 of the Current Mirror module Current Mirror is connected with a chip pin MIROUT_CH2; providing an inverse bias high voltage for the avalanche photodiode APD2 through a chip pin mirout_ch2;
an external monitoring circuit collects an APD1 Mirror Current generated by a Current Mirror module Current Mirror through a chip pin MIR1_CH1 and a chip pin MIR2_CH1 to monitor an APD1 photocurrent; the other external monitoring circuit collects an APD2 Mirror image Current generated by a Current Mirror module Current Mirror through a chip pin MIR1_CH2 and a chip pin MIR2_CH2 so as to monitor an APD2 photocurrent; the two paths of mirror currents are also output to a double-path sampling Hold module;
The output end VOP_CH1 of the holding sampling voltage of the two-way sampling Hold module Sample Hold is connected with a chip pin VOP_CH1;
the output end VOP_CH2 of the holding sampling voltage of the Sample Hold of the two-way sampling Hold module is connected with a chip pin VOP_CH2; the chip pins VOP_CH1 and VOP_CH2 are respectively connected with two paths of external analog-to-digital conversion modules ADC;
the sampling enabling input end SEN_CH1 of the two-way sampling holding module Sample Hold is connected with the chip pin SEN_CH1;
the sampling enabling input end SEN_CH2 of the two-way sampling holding module Sample Hold is connected with the chip pin SEN_CH2;
the sampling enable triggering edge adjusting end SENOR_CH1 of the two-way sampling Hold module Sample Hold is connected with a chip pin SENOR_CH1;
the sampling enable triggering edge adjusting end SENOR_CH2 of the two-way sampling Hold module Sample Hold is connected with a chip pin SENOR_CH2;
the GAIN indication output end and the GAIN control input end GAIN_CH1 of the two-way Sample Hold module are connected with a chip pin GAIN_CH1;
the GAIN indication output end and the GAIN control input end GAIN_CH2 of the two-way Sample Hold module are connected with the chip pin GAIN_CH2.
Preferably, the boost loop sharing module Common Block includes a Sawtooth oscillator Sawtooth OSC, a BIAS Current BIAS, a band gap reference band gap and a Current Sense, and is shared by the boost loop module DC/DC loop1 and the boost loop module DC/DC loop 2;
The boost loop module DC/DC loop1 comprises a switching tube Switch1, a modulation comparator PWM COM1, a Driver1 and an operational amplifier A1; the signal of the output end of the Sawtooth oscillator Sawtooth OSC and the signal of the output end of the Current Sense of the Current detection are added and then connected to the inverting end of the pulse width modulation comparator PWM COM 1;
the inverting input end of the operational amplifier A1 is connected with a chip pin FB1;
the non-inverting input end of the operational amplifier A1 is connected with a reference voltage VREF output by Bandgap;
the output end of the operational amplifier A1 is connected with the positive phase end of the pulse width modulation comparator PWM COM 1;
the output end of the pulse width modulation comparator PWM COM1 is connected with the input end of the Driver 1;
the output end of the Driver1 is connected with the grid electrode of the switching tube Switch 1;
the drain end of the switching tube Switch1 is connected with the chip pin SW1; the chip pin SW1 is connected with an external VDC3.3V power supply;
the source end of the switching tube Switch1 is connected with the ground;
the boost loop module DC/DC loop2 comprises a switching tube Switch2, a modulation comparator PWM COM2, a Driver2 and an operational amplifier A2; the signal of the output end of the Sawtooth oscillator Sawtooth OSC and the signal of the output end of the Current Sense of the Current detection are added and then connected to the inverting end of the pulse width modulation comparator PWM COM 2;
the inverting input end of the operational amplifier A2 is connected with the chip pin FB2;
The non-inverting input end of the operational amplifier A2 is connected with a reference voltage VREF output by Bandgap;
the output end of the operational amplifier A2 is connected with the positive phase end of the pulse width modulation comparator PWM COM 2;
the output end of the pulse width modulation comparator PWM COM2 is connected with the input end of the Driver 2;
the output end of the Driver2 is connected with the grid electrode of the switching tube Switch 2;
the drain end of the switching tube Switch2 is connected with the chip pin SW2; chip pin SW2 is connected to an external VDC3.3V power supply;
the source terminal of the switching tube Switch2 is connected to the ground.
Preferably, the two-way Current Mirror module Current Mirror comprises a Current Mirror module Current Mirror1 and a Current Mirror module Current Mirror2 which have the same structure, wherein the Current Mirror module Current Mirror1 comprises PMOS transistors MP 1-MP 3, MP7, a Current limiting unit Current Limit1 and an operational amplifier A5;
the source ends of the PMOS transistors MP 1-MP 3 are simultaneously connected with a chip pin MIRIN_CH1;
the drain end of the PMOS transistor MP1 is connected with the input end of the Current limiting unit Current Limit 1;
the output end of the Current limiting unit Current Limit1 is connected with the source end of the PMOS transistor MP 7;
the other output end of the Current limiting unit Current Limit1 is connected with a chip pin RLIM_CH1;
the gate end of the PMOS transistor MP7 is connected with the output end of the operational amplifier A5;
the drain end of the PMOS transistor MP7 is connected with a chip pin MIROUT_CH1;
The drain end of the PMOS transistor MP2 is simultaneously connected with the chip pin MIR1_CH1 and one input end of the SAMPLE-HOLD module SAMPLE/HOLD 1;
the drain end of the PMOS transistor MP3 is simultaneously connected with the chip pin MIR2_CH1 and the other input end of the SAMPLE-HOLD module SAMPLE/HOLD 1;
the Current Mirror module Current Mirror2 comprises PMOS transistors MP 1-MP 3 and MP7, a Current limiting unit Current Limit2 and an operational amplifier A6;
the source ends of the PMOS transistors MP 4-MP 6 are simultaneously connected with a chip pin MIRIN_CH2;
the drain end of the PMOS transistor MP6 is connected with the input end of the Current limiting unit Current Limit 2;
the output end of the Current limiting unit Current Limit2 is connected with the source end of the PMOS transistor MP 8;
the other output end of the Current limiting unit Current Limit2 is connected with a chip pin RLIM_CH2;
the gate end of the PMOS transistor MP8 is connected with the output end of the operational amplifier A6;
the drain end of the PMOS transistor MP8 is connected with a chip pin MIROUT_CH2;
the drain end of the PMOS transistor MP5 is simultaneously connected with the chip pin MIR1_CH2 and one input end of the SAMPLE/HOLD module SAMPLE/HOLD 2;
the drain terminal of the PMOS transistor MP4 is simultaneously connected to the chip pin mir2_ch2 and the other input terminal of the SAMPLE/HOLD module SAMPLE/HOLD 2.
Preferably, the two-way Sample Hold module Sample Hold comprises a Sample Hold module Sample Hold1 and a Sample Hold module Sample Hold2 which have the same structure;
The Sample Hold module Sample Hold1 comprises a Sample Hold unit Sample/Hold1, a full differential operational amplifier A3, an operational amplifier A7, a D trigger Q1 and an exclusive or gate XOR1;
a pair of output ends of the SAMPLE/HOLD unit SAMPLE/HOLD1 are respectively connected with a non-inverting input end and an inverting input end of the full differential operational amplifier A3; the inverting output end of the full differential operational amplifier A3 is connected with a chip pin VOP_CH1; the chip pin VOP_CH1 is connected with an external analog-to-digital conversion module ADC;
a pair of output ends of the SAMPLE/HOLD1 are connected with a non-inverting input end of the operational amplifier A7 and the chip pin GAIN_CH1;
the output end of the operational amplifier A7 is connected with the data input end D of the D trigger Q1;
the output end Q of the D trigger Q1 is connected with a chip pin GAIN through a resistor R11; the method comprises the steps of carrying out a first treatment on the surface of the
The output end of the exclusive or gate XOR1 is connected with the clock end CLK of the D flip-flop Q1;
two input ends of the exclusive or gate XOR1 are respectively connected with chip pins SENOR_CH1 and SEN_CH1;
the Sample Hold module Sample Hold2 comprises a Sample Hold unit Sample/Hold2, a full differential operational amplifier A4, an operational amplifier A8, a D trigger Q2 and an exclusive or gate XOR2;
the pair of output ends of the SAMPLE/HOLD unit SAMPLE/HOLD2 are respectively connected with the non-inverting input end and the inverting input end of the full differential operational amplifier A4; the inverting output end of the full differential operational amplifier A4 is connected with a chip pin VOP_CH2; the chip pin VOP_CH2 is connected with another external analog-to-digital conversion module ADC;
A pair of output ends of the SAMPLE/HOLD unit SAMPLE/HOLD2 are connected with a non-inverting input end of the operational amplifier A8 and a chip pin GAIN_CH2;
the output end of the operational amplifier A8 is connected with the data input end D of the D trigger Q2;
the output end Q of the D trigger Q2 is connected with a chip pin GAIN through a resistor R14; the method comprises the steps of carrying out a first treatment on the surface of the
The output end of the exclusive or gate XOR2 is connected with the clock end CLK of the D flip-flop Q2;
the two inputs of exclusive or gate XOR2 are connected to chip pins senxor_ch2, sen_ch2, respectively.
Preferably, the three-in-one chip is characterized by further comprising two lifting voltage control circuits, wherein the lifting voltage control circuits are used as three-in-one chip peripheral circuits, and the two lifting voltage control circuits respectively regulate the output voltages of the boosting loop module DC/DC loop1 and the boosting loop module DC/DC loop2 to obtain two paths of different output voltages within the range of 30V-60V, and the two paths of different output voltages are returned into the chip.
The invention has the beneficial effects that: the three-in-one chip frame is provided, the chips simultaneously have boost, current mirror and sample hold functions, a design mode that a plurality of chips are welded on a PCB (printed circuit board) and then are debugged in the traditional ROSA is changed, and a single chip with the three-in-one function is adopted to realize power supply to an APD, monitor the current of the APD and output a sample hold signal. The PCB occupation area can be reduced, the research and development difficulty is reduced, and the overall cost can be reduced along with the reduction of the area and the research and development time.
Drawings
Fig. 1 is a conventional rosa_pcb structure diagram;
FIG. 2 is a block diagram of a three-in-one chip with boost, current mirror and sample-and-hold functions, a single channel structure;
FIG. 3 is a schematic diagram of the internal structure of the three-in-one chip with boost, current mirror and sample-and-hold functions, a single channel structure;
FIG. 4 is a block diagram of a three-in-one chip with boost, current mirror and sample-and-hold functions of the present invention, a dual channel architecture;
fig. 5 is a schematic diagram of the internal structure of the three-in-one chip with boost, current mirror and sample-and-hold functions, and the dual-channel structure.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.
The first embodiment is as follows: the three-in-one chip with boost, current Mirror and Sample Hold functions in this embodiment is described below with reference to fig. 2 and fig. 3, where the boost module DC/DC, current Mirror module Current Mirror and Sample Hold module Sample Hold are designed by the same process on the chip, and are in a single channel mode;
the boosting module DC/DC boosts the 3.3V power supply voltage outside the chip to 30V-60V as a power supply of the Current Mirror module Current Mirror, the Current Mirror module Current Mirror generates Mirror voltage and fast-changing Mirror Current, and the Mirror voltage output by the Current Mirror module Current Mirror provides reverse bias high voltage for the avalanche photodiode APD;
the Sample Hold module samples and holds the rapidly-changed Mirror Current transmitted by the Current Mirror, and transmits the sampled and held result to an external analog-to-digital conversion module ADC through a chip pin VOP to analyze the rapidly-changed APD photocurrent.
When the traditional ROSA_PCB structure is described, two independent chips, namely a DC/DC boosting chip and a current mirror sample-hold chip, are used for providing reverse bias voltage and current monitoring functions for APDs, the two independent chips are welded on a PCB, the independent chips occupy a larger PCB area, and the debugging difficulty is increased by using the independent chips of different chip design companies, so that the research and development cost is increased. The three-in-one chip with boost, current mirror and sample-hold functions provided by fig. 2 and fig. 3 is that the three-in-one chip with the functions is designed and manufactured by using the same process, and the final whole packaging area is 3mm x 3mm, so that the problems that the area occupied by a discrete chip on a PCB circuit board is large, the cost of a single chip is high, and the research, development and debugging period of the PCB circuit board is long are solved.
Fig. 2 is a block diagram of a single channel mode chip, and is mainly divided into three functional modules: (1) the boosting module DC/DC boosts the 3.3V power supply voltage outside the chip to 30V-60V, then is connected to the chip pin MIRIN, and different output voltages are obtained by adjusting the proportion of the external resistor R10 and the resistor R8. According to the practical application scheme, source or sink current can be added to the FB pin through an external current source to adjust output voltage in real time, so that the APD obtains optimal sensitivity. The lifting voltage control circuit is used as a three-in-one chip peripheral circuit and is used for adjusting the DC/DC output voltage of the boosting module to obtain different output voltages within the range of 30V-60V and returning the different output voltages to the inside of the chip. The lifting voltage control circuit comprises resistors R8-R10 and capacitors C4-C6. (2) The Current Mirror module Current Mirror adopts 30V-60V high voltage generated by DC/DC as a power supply, the output end MIROUT of the Current Mirror also generates high voltage with a certain difference value with MIRIN, the high voltage is connected with the cathode of an APD outside the chip through a chip pin MIROUT to provide reverse bias high voltage for the APD, after the APD receives a light signal to generate photocurrent, the Mirror Current of a Mirror Current source circuit Mirror flows out of APD with a certain scaling ratio at a MIR1 port and a MIR2 port, and the magnitude of the photocurrent generated by the APD can be calculated by measuring the voltage drop on the resistors R4 and R5, so that the purpose of Current monitoring is achieved. The monitoring circuit is used as a peripheral circuit and comprises a resistor R4-5 and a capacitor C1-C2. (3) The Sample Hold module samples and holds the rapidly-changing Current transmitted by the Current Mirror module Current Mirror, controls the GAIN of the Current Mirror or monitors the internal automatic Current GAIN through the chip input/output pin GAIN, for example, when GAIN is used as an output pin, the Mirror sampling Current ratio is 5 when the GAIN pin is detected to be at a low level: 4, a step of; when the GAIN pin is detected to be at a high level, the proportion of the mirror image sampling current is 5:1. when GAIN is used as an input pin, the ratio of the forced mirror sampling current is 5 when the GAIN pin is low: 4, a step of; the ratio of the forced mirror sampling current is 5 when the GAIN pin is high: 1. the chip pin SEN is a sample hold enable signal, and a beam of sample pulse signals is given to the pin and then enters a signal hold stage. The SENEXOR is sampling enabling triggering edge adjustment, and when the SENEXOR pin is low level, the rising edge of the SEN pin triggers sampling enabling; when the SENSOR pin is high level, the falling edge of the SEN pin triggers sampling enabling; and finally, transmitting the sampling and holding result to an external ADC through a chip pin VOP, and analyzing the photo-current of the APD which changes at high speed.
Fig. 3 is a specific chip internal structure of a single channel, and a boosting module DC/DC, a Current Mirror module Current Mirror and a Sample Hold module Sample Hold are designed on the chip by adopting the same process, wherein the boosting module DC/DC comprises a switching tube Switch, a Driver, a modulation comparator PWM COM, an operational amplifier A1, a Sawtooth oscillator Sawtooth OSC and a Current detection Current sensor;
the output signal of the sawtooth wave oscillator and the output signal of the Current Sense are added and then connected to the inverting terminal of the PWM comparator PWM COM;
the inverting input end of the operational amplifier A1 is connected with the chip pin FB; the chip pin FB is connected with an external lifting voltage control circuit;
the non-inverting input end of the operational amplifier A1 is connected with a reference voltage VREF;
the output end of the operational amplifier A1 is connected with the positive phase end of the pulse width modulation comparator PWM COM;
the output end of the pulse width modulation comparator PWM COM is connected with the input end of the Driver;
the output end of the Driver is connected with the grid electrode of the switching tube Switch;
the source end of the switching tube Switch is connected with the ground;
the drain end of the switching tube Switch is connected with the chip pin SW; the chip pin SW is connected with an external VDC3.3V power supply;
the Current Mirror module Current Mirror comprises PMOS transistors MP 1-MP 4, a Current limiting unit Current LIMIT and an operational amplifier A2; the source ends of the PMOS transistors MP 1-MP 3 are simultaneously connected with a chip pin MIRIN;
The drain end of the PMOS transistor MP1 is connected with the input end of the CURRENT LIMIT unit;
the output end of the CURRENT LIMIT unit is connected with the source end of the PMOS transistor MP 4;
the other output end of the CURRENT LIMIT unit is connected with a chip pin RLIM;
the gate end of the PMOS transistor MP4 is connected with the output end of the operational amplifier A2;
the drain end of the PMOS transistor MP4 is connected with a chip pin MIROUT; providing an inverse bias high voltage for an Avalanche Photodiode (APD) through a chip pin (MIROUT);
the drain end of the PMOS transistor MP2 is connected with a chip pin MIR1;
the drain end of the PMOS transistor MP3 is connected with a chip pin MIR2;
the external monitoring circuit collects Mirror Current generated by a Current Mirror module Current Mirror through a chip pin MIR1 and a chip pin MIR2 so as to monitor the photo Current of the APD; the mirror current is also output to a Sample Hold module;
the Sample Hold module comprises a Sample Hold unit Sample/Hold, an operational amplifier A3, a full differential operational amplifier A4, a D trigger Q and an exclusive or gate XOR;
two input ends of the SAMPLE/HOLD unit are respectively connected with the drain end of the PMOS transistor MP2 and the drain end of the MP 3;
the pair of output ends of the SAMPLE/HOLD unit are respectively connected with the non-inverting input end and the inverting input end of the full differential operational amplifier A4; the inverting output end of the full differential operational amplifier A4 is connected with a chip pin VOP; the chip pin VOP is connected with an external analog-to-digital conversion module ADC;
The other pair of output ends of the SAMPLE/HOLD unit are respectively connected with the non-inverting input end of the operational amplifier A3 and the chip pin GAIN;
the output end of the operational amplifier A3 is connected with the data input end D of the trigger Q;
the output end Q of the D trigger Q is connected with a chip pin GAIN through a resistor R11;
the output end of the exclusive or gate XOR is connected with the clock end CLK of the D trigger Q;
two input ends of the exclusive or gate XOR are respectively connected with a chip pin SENOR and a chip pin SEN;
the chip pin SEN is a sample hold enable signal input pin, and the chip pin SENXOR is a sample enable trigger edge adjustment pin.
Working principle: the Sawtooth oscillator Sawtooth OSC generates Sawtooth wave and output signal of Current Sense to be superimposed as inverting input of PWM comparator PWM COM, error amplifier A1 divides MIRIN voltage by voltage of resistors R10 and R8 to obtain V FB The output of the error amplification is outputted to the non-inverting input terminal of the pulse width modulation comparator PWM COM. The output of the PWM COM generates a square wave with an adjustable duty ratio, and the Driver drives the large-size switching tube Switch. The frequency of the sawtooth oscillator can be adjusted within a range from hundreds of KHz to one or two MHz, so that the relation between the magnitude of the inductor L1 and the output voltage MIRIN ripple can be balanced.
The high voltage MIRIN output by DC/DC is used as the power supply of the PMOS transistors MP 1-MP 3 mirror image tube, the photocurrent generated by APD is finally provided by MP1, the currents of MP2 and MP3 mirror images MP1, the mirror image proportion is 5:4,5:1, the ratio can also be adjusted by registers inside the chip. The Current limiting unit Current Limit can Limit the maximum APD photocurrent of the MIROUT pin, and prevent the photocurrent from being too large and burning out an APD device. The operational amplifier A2 and the PMOS transistor MP4 generate a voltage having a certain difference from MIRIN and are supplied to MIROUT.
The SAMPLE/HOLD module SAMPLEs the output signal of the mirror current source circuit according to the sampling and holding time sequence, then amplifies to a certain multiple through the operational amplifier A4, and then keeps the output to the ADC analysis outside the chip, and finally the upper computer outputs a value capable of reflecting the photo current of the APD. The operational amplifier A3, the D trigger Q1, the resistor R11 and the exclusive OR gate XOR1 are combined into a functional unit with gain indication output, gain control and sampling enabling triggering edge adjustment.
The whole three-in-one chip also integrates multiple protection functions such as soft start circuit, over-temperature protection, over-current protection, current limiting protection and the like, and prolongs the service life of the chip.
The second embodiment is as follows: next, the three-in-one chip with boost, current mirror and sample-and-hold functions according to the present embodiment is a two-channel mode, as described in the present embodiment with reference to fig. 4 and 5. The method comprises the steps that a boosting loop module DC/DC loop1, a boosting loop module DC/DC loop2, a boosting loop sharing module Common Block, a double-path Current Mirror module Current Mirror and a double-path Sample Hold module Sample Hold are designed on a chip by adopting the same process, the boosting loop module DC/DC loop1 and the boosting loop module DC/DC loop2 respectively raise external 3.3V power supply voltage to 30V-60V to serve as two paths of input Current of the double-path Current Mirror module Current Mirror, the double-path Current Mirror module Current Mirror generates two paths of Mirror voltage and rapidly-changed Mirror Current, and the two paths of Mirror voltage respectively provide anti-bias high voltage for two avalanche photodiodes APDs;
The two-way sampling and holding module Sample Hold samples and holds two paths of rapidly-changed Mirror currents transmitted by the Current Mirror, and the two sampling and holding results are respectively transmitted to the two external analog-digital conversion modules ADC to analyze the photo-currents of the APD which are rapidly changed.
Fig. 4 is a two-channel overall block diagram, the circuit structures of the boost loop module DC/DC loop1 and the boost loop module DC/DC loop2 are the same, and a switch output end SW1 of the boost loop module DC/DC loop1 is connected with a chip pin SW1;
the feedback signal FB1 of the boost loop module DC/DC loop1 is connected with the chip pin FB1;
the plurality of output ends of the boosting loop sharing module Common Block are connected with the plurality of input ends of the boosting loop module DC/DC loop 1;
the switch output end SW2 of the boost loop module DC/DC loop2 is connected with the chip pin SW2;
the feedback signal FB2 of the boost loop module DC/DC loop2 is connected with the chip pin FB2;
the plurality of output ends of the boosting loop sharing module Common Block are connected with the plurality of input ends of the boosting loop module DC/DC loop 2;
the voltage output by the DC/DC loop1 of the boost loop module is introduced into the chip through a chip pin MIRIN_CH1 after being subjected to proportion adjustment, and the voltage output by the DC/DC loop2 of the boost loop module is introduced into the chip through a chip pin MIRIN_CH2 after being subjected to proportion adjustment;
The Current Mirror input end MIRIN_CH1 of the Current Mirror module Current Mirror is connected with the chip pin MIRIN_CH1;
the Current Mirror input end MIRIN_CH1 of the Current Mirror module Current Mirror is connected with the chip pin MIRIN_CH1;
the Current limiting end RLIM_CH1 of the Current Mirror module Current Mirror is connected with the chip pin RLIM_CH1;
the Current limiting end RLIM_CH2 of the Current Mirror module Current Mirror is connected with the chip pin RLIM_CH2;
the Current Mirror module Current Mirror has its Current Mirror output MIR1_CH1 connected to the chip pins MIR1_CH1 and the Current Mirror input MIR1_CH1 of the Sample Hold module Sample Hold;
the Current Mirror module Current Mirror has its Current Mirror output MIR2_CH1 connected to the chip pin MIR2_CH1 and the Current Mirror input MIR2_CH1 of the Sample Hold module Sample Hold;
the Current Mirror module Current Mirror has its Current Mirror output MIR1_CH2 connected to the chip pins MIR1_CH2 and the Current Mirror input MIR1_CH2 of the Sample Hold module Sample Hold;
the Current Mirror module Current Mirror has its Current Mirror output MIR 2-CH 2 connected to the chip pin MIR 2-CH 2 and the Current Mirror input MIR 2-CH 2 of the Sample Hold module Sample Hold;
the output end MIROUT_CH1 of the Current Mirror module Current Mirror is connected with a chip pin MIROUT_CH1; providing an inverse bias high voltage for the avalanche photodiode APD1 through a chip pin mirout_ch1;
The output end MIROUT_CH2 of the Current Mirror module Current Mirror is connected with a chip pin MIROUT_CH2; providing an inverse bias high voltage for the avalanche photodiode APD2 through a chip pin mirout_ch2;
an external monitoring circuit collects an APD1 Mirror Current generated by a Current Mirror module Current Mirror through a chip pin MIR1_CH1 and a chip pin MIR2_CH1 to monitor an APD1 photocurrent; the other external monitoring circuit collects an APD2 Mirror image Current generated by a Current Mirror module Current Mirror through a chip pin MIR1_CH2 and a chip pin MIR2_CH2 so as to monitor an APD2 photocurrent; the two paths of mirror currents are also output to a double-path sampling Hold module;
the output end VOP_CH1 of the holding sampling voltage of the two-way sampling Hold module Sample Hold is connected with a chip pin VOP_CH1;
the output end VOP_CH2 of the holding sampling voltage of the Sample Hold of the two-way sampling Hold module is connected with a chip pin VOP_CH2; the chip pins VOP_CH1 and VOP_CH2 are respectively connected with two paths of external analog-to-digital conversion modules ADC;
the sampling enabling input end SEN_CH1 of the two-way sampling holding module Sample Hold is connected with the chip pin SEN_CH1;
the sampling enabling input end SEN_CH2 of the two-way sampling holding module Sample Hold is connected with the chip pin SEN_CH2;
The sampling enable triggering edge adjusting end SENOR_CH1 of the two-way sampling Hold module Sample Hold is connected with a chip pin SENOR_CH1;
the sampling enable triggering edge adjusting end SENOR_CH2 of the two-way sampling Hold module Sample Hold is connected with a chip pin SENOR_CH2;
the GAIN indication output end and the GAIN control input end GAIN_CH1 of the two-way Sample Hold module are connected with a chip pin GAIN_CH1;
the GAIN indication output end and the GAIN control input end GAIN_CH2 of the two-way Sample Hold module are connected with the chip pin GAIN_CH2.
FIG. 5 is an internal structure of a chip, and a boost loop module DC/DC loop1, a boost loop module DC/DC loop2, a boost loop sharing module Common Block, a dual Current Mirror module Current Mirror and a dual Sample Hold module Sample Hold are designed on the chip by adopting the same process, wherein the boost loop sharing module Common Block comprises a Sawtooth oscillator Sawtooth OSC, a BIAS Current BIAS, a band gap reference band gap and a Current detection Current sensor, and is shared by the boost loop module DC/DC loop1 and the boost loop module DC/DC loop 2;
the boost loop module DC/DC loop1 comprises a switching tube Switch1, a modulation comparator PWM COM1, a Driver1 and an operational amplifier A1; the signal of the output end of the Sawtooth oscillator Sawtooth OSC and the signal of the output end of the Current Sense of the Current detection are added and then connected to the inverting end of the pulse width modulation comparator PWM COM 1;
The inverting input end of the operational amplifier A1 is connected with a chip pin FB1;
the non-inverting input end of the operational amplifier A1 is connected with a reference voltage VREF output by Bandgap;
the output end of the operational amplifier A1 is connected with the positive phase end of the pulse width modulation comparator PWM COM 1;
the output end of the pulse width modulation comparator PWM COM1 is connected with the input end of the Driver 1;
the output end of the Driver1 is connected with the grid electrode of the switching tube Switch 1;
the drain end of the switching tube Switch1 is connected with the chip pin SW1; the chip pin SW1 is connected with an external VDC3.3V power supply;
the source end of the switching tube Switch1 is connected with the ground;
the boost loop module DC/DC loop2 comprises a switching tube Switch2, a modulation comparator PWM COM2, a Driver2 and an operational amplifier A2; the signal of the output end of the Sawtooth oscillator Sawtooth OSC and the signal of the output end of the Current Sense of the Current detection are added and then connected to the inverting end of the pulse width modulation comparator PWM COM 2;
the inverting input end of the operational amplifier A2 is connected with the chip pin FB2;
the non-inverting input end of the operational amplifier A2 is connected with a reference voltage VREF output by Bandgap;
the output end of the operational amplifier A2 is connected with the positive phase end of the pulse width modulation comparator PWM COM 2;
the output end of the pulse width modulation comparator PWM COM2 is connected with the input end of the Driver 2;
the output end of the Driver2 is connected with the grid electrode of the switching tube Switch 2;
The drain end of the switching tube Switch2 is connected with the chip pin SW2; chip pin SW2 is connected to an external VDC3.3V power supply;
the source terminal of the switching tube Switch2 is connected to the ground.
The Current Mirror module Current Mirror comprises a Current Mirror module Current Mirror1 and a Current Mirror module Current Mirror2 which have the same structure, wherein the Current Mirror module Current Mirror1 comprises PMOS transistors MP 1-MP 3, MP7, a Current limiting unit Current Limit1 and an operational amplifier A5;
the source ends of the PMOS transistors MP 1-MP 3 are simultaneously connected with a chip pin MIRIN_CH1;
the drain end of the PMOS transistor MP1 is connected with the input end of the Current limiting unit Current Limit 1;
the output end of the Current limiting unit Current Limit1 is connected with the source end of the PMOS transistor MP 7;
the other output end of the Current limiting unit Current Limit1 is connected with a chip pin RLIM_CH1;
the gate end of the PMOS transistor MP7 is connected with the output end of the operational amplifier A5;
the drain end of the PMOS transistor MP7 is connected with a chip pin MIROUT_CH1;
the drain end of the PMOS transistor MP2 is simultaneously connected with the chip pin MIR1_CH1 and one input end of the SAMPLE-HOLD module SAMPLE/HOLD 1;
the drain end of the PMOS transistor MP3 is simultaneously connected with the chip pin MIR2_CH1 and the other input end of the SAMPLE-HOLD module SAMPLE/HOLD 1;
the Current Mirror module Current Mirror2 comprises PMOS transistors MP 1-MP 3 and MP7, a Current limiting unit Current Limit2 and an operational amplifier A6;
The source ends of the PMOS transistors MP 4-MP 6 are simultaneously connected with a chip pin MIRIN_CH2;
the drain end of the PMOS transistor MP6 is connected with the input end of the Current limiting unit Current Limit 2;
the output end of the Current limiting unit Current Limit2 is connected with the source end of the PMOS transistor MP 8;
the other output end of the Current limiting unit Current Limit2 is connected with a chip pin RLIM_CH2;
the gate end of the PMOS transistor MP8 is connected with the output end of the operational amplifier A6;
the drain end of the PMOS transistor MP8 is connected with a chip pin MIROUT_CH2;
the drain end of the PMOS transistor MP5 is simultaneously connected with the chip pin MIR1_CH2 and one input end of the SAMPLE/HOLD module SAMPLE/HOLD 2;
the drain terminal of the PMOS transistor MP4 is simultaneously connected to the chip pin mir2_ch2 and the other input terminal of the SAMPLE/HOLD module SAMPLE/HOLD 2.
The double-path Sample Hold module Sample Hold comprises a Sample Hold module Sample Hold1 and a Sample Hold module Sample Hold2 which have the same structure;
the Sample Hold module Sample Hold1 comprises a Sample Hold unit Sample/Hold1, a full differential operational amplifier A3, an operational amplifier A7, a D trigger Q1 and an exclusive or gate XOR1;
a pair of output ends of the SAMPLE/HOLD unit SAMPLE/HOLD1 are respectively connected with a non-inverting input end and an inverting input end of the full differential operational amplifier A3; the inverting output end of the full differential operational amplifier A3 is connected with a chip pin VOP_CH1; the chip pin VOP_CH1 is connected with an external analog-to-digital conversion module ADC;
A pair of output ends of the SAMPLE/HOLD1 are connected with a non-inverting input end of the operational amplifier A7 and the chip pin GAIN_CH1;
the output end of the operational amplifier A7 is connected with the data input end D of the D trigger Q1;
the output end Q of the D trigger Q1 is connected with a chip pin GAIN through a resistor R11; the method comprises the steps of carrying out a first treatment on the surface of the
The output end of the exclusive or gate XOR1 is connected with the clock end CLK of the D flip-flop Q1;
two input ends of the exclusive or gate XOR1 are respectively connected with chip pins SENOR_CH1 and SEN_CH1;
the Sample Hold module Sample Hold2 comprises a Sample Hold unit Sample/Hold2, a full differential operational amplifier A4, an operational amplifier A8, a D trigger Q2 and an exclusive or gate XOR2;
the pair of output ends of the SAMPLE/HOLD unit SAMPLE/HOLD2 are respectively connected with the non-inverting input end and the inverting input end of the full differential operational amplifier A4; the inverting output end of the full differential operational amplifier A4 is connected with a chip pin VOP_CH2; the chip pin VOP_CH2 is connected with another external analog-to-digital conversion module ADC;
a pair of output ends of the SAMPLE/HOLD unit SAMPLE/HOLD2 are connected with a non-inverting input end of the operational amplifier A8 and a chip pin GAIN_CH2;
the output end of the operational amplifier A8 is connected with the data input end D of the D trigger Q2;
the output end Q of the D trigger Q2 is connected with a chip pin GAIN through a resistor R14; the method comprises the steps of carrying out a first treatment on the surface of the
The output end of the exclusive or gate XOR2 is connected with the clock end CLK of the D flip-flop Q2;
The two inputs of exclusive or gate XOR2 are connected to chip pins senxor_ch2, sen_ch2, respectively.
Working principle: the implementation scheme is the function upgrading of the single-channel three-in-one chip, two DC/DC, two Current Mirror modules Current minor and two Sample hold holes are integrated inside, reverse bias voltage can be provided for two APDs at the same time, two Sample hold signals can be transmitted to two external ADC for analysis, and finally function judgment is made by an upper computer. The chip pins en_ch1 and en_ch2 may enable two channels, respectively. The two DC/DCs of the three-in-one chip are further optimized in function and area, for example, the generation of reference voltage can be uniformly provided by a band gap reference voltage module in the chip, BIAS current BIAS simultaneously provides current for Loop1 and Loop2, a sawtooth wave oscillator can be converted and generated by other oscillators in the chip, and the size of the three-in-one chip can be reasonably designed according to the overall requirement power consumption of the chip, and the packaging area of the two-channel three-in-one chip is only 4mm by 4mm through area optimization of all aspects.
By analogy, the three-in-one chip can also increase the number of channels to 4 channels or 8 channels, provide reverse bias voltage for four APDs or 8 APDs, further reduce the volume of the optical module at the receiving end by using the three-in-one chip with multiple channels, improve the throughput of data by increasing the number of TIAs, and greatly reduce the research and development cost.
The invention provides a three-in-one chip with boost, current mirror and sample-hold functions, which changes the traditional optical module that a plurality of discrete chips are welded on a synchronous PCB circuit board to realize the function of receiving optical signals, and three important functional modules are integrated and designed by using the same high-voltage and high-speed process, and finally manufactured on the same bare DIE, and the bare DIE is packaged and then used by optical module design manufacturers. The final effect is that the volume of the optical module is reduced, and the research and development cost and the debugging difficulty are reduced.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the different dependent claims and the features described herein may be combined in ways other than as described in the original claims. It is also to be understood that features described in connection with separate embodiments may be used in other described embodiments.

Claims (10)

1. The three-in-one chip with boost, current Mirror and Sample Hold functions is characterized in that the same technology is adopted on the chip to design a boost module DC/DC, a Current Mirror module Current Mirror and a Sample Hold module Sample Hold, and the three-in-one chip is in a single-channel mode;
the boosting module DC/DC boosts the 3.3V power supply voltage outside the chip to 30V-60V as a power supply of the Current Mirror module Current Mirror, the Current Mirror module Current Mirror generates Mirror voltage and fast-changing Mirror Current, and the Mirror voltage output by the Current Mirror module Current Mirror provides reverse bias high voltage for the avalanche photodiode APD;
the Sample Hold module samples and holds the rapidly-changed Mirror Current transmitted by the Current Mirror, and transmits the sampled and held result to an external analog-to-digital conversion module ADC through a chip pin VOP to analyze the rapidly-changed APD photocurrent.
2. The three-in-one chip with the boost, current mirror and sample-and-hold functions according to claim 1, further comprising a boost voltage control circuit, wherein the boost voltage control circuit is used as a three-in-one chip peripheral circuit, and the boost voltage control circuit adjusts the DC/DC output voltage of the boost module to obtain different output voltages within the range of 30V-60V and return the different output voltages to the inside of the chip.
3. The three-in-one chip with boost, current mirror and sample-and-hold functions according to claim 2, wherein the boost module DC/DC comprises a switching transistor Switch, a Driver, a modulation comparator PWM COM, an operational amplifier A1, a Sawtooth oscillator sawtooh OSC and a Current detection Current Sense;
the output signal of the sawtooth wave oscillator and the output signal of the Current Sense are added and then connected to the inverting terminal of the PWM comparator PWM COM;
the inverting input end of the operational amplifier A1 is connected with the chip pin FB; the chip pin FB is connected with an external lifting voltage control circuit;
the non-inverting input end of the operational amplifier A1 is connected with a reference voltage VREF;
the output end of the operational amplifier A1 is connected with the positive phase end of the pulse width modulation comparator PWM COM;
the output end of the pulse width modulation comparator PWM COM is connected with the input end of the Driver;
the output end of the Driver is connected with the grid electrode of the switching tube Switch;
the source end of the switching tube Switch is connected with the ground;
the drain end of the switching tube Switch is connected with the chip pin SW; the chip pin SW is connected with an external VDC3.3V power supply;
the Current Mirror module Current Mirror comprises PMOS transistors MP 1-MP 4, a Current limiting unit Current LIMIT and an operational amplifier A2; the source ends of the PMOS transistors MP 1-MP 3 are simultaneously connected with a chip pin MIRIN;
The drain end of the PMOS transistor MP1 is connected with the input end of the CURRENT LIMIT unit;
the output end of the CURRENT LIMIT unit is connected with the source end of the PMOS transistor MP 4;
the other output end of the CURRENT LIMIT unit is connected with a chip pin RLIM;
the gate end of the PMOS transistor MP4 is connected with the output end of the operational amplifier A2;
the drain end of the PMOS transistor MP4 is connected with a chip pin MIROUT; providing an inverse bias high voltage for an Avalanche Photodiode (APD) through a chip pin (MIROUT);
the drain end of the PMOS transistor MP2 is connected with a chip pin MIR1;
the drain end of the PMOS transistor MP3 is connected with a chip pin MIR2;
the external monitoring circuit collects Mirror Current generated by a Current Mirror module Current Mirror through a chip pin MIR1 and a chip pin MIR2 so as to monitor the photo Current of the APD; the mirror current is also output to a Sample Hold module;
the Sample Hold module comprises a Sample Hold unit Sample/Hold, an operational amplifier A3, a full differential operational amplifier A4, a D trigger Q and an exclusive or gate XOR;
two input ends of the SAMPLE/HOLD unit are respectively connected with the drain end of the PMOS transistor MP2 and the drain end of the MP 3;
the pair of output ends of the SAMPLE/HOLD unit are respectively connected with the non-inverting input end and the inverting input end of the full differential operational amplifier A4; the inverting output end of the full differential operational amplifier A4 is connected with a chip pin VOP; the chip pin VOP is connected with an external analog-to-digital conversion module ADC;
The other pair of output ends of the SAMPLE/HOLD unit are respectively connected with the non-inverting input end of the operational amplifier A3 and the chip pin GAIN;
the output end of the operational amplifier A3 is connected with the data input end D of the trigger Q;
the output end Q of the D trigger Q is connected with a chip pin GAIN through a resistor R11;
the output end of the exclusive or gate XOR is connected with the clock end CLK of the D trigger Q;
two input ends of the exclusive or gate XOR are respectively connected with a chip pin SENOR and a chip pin SEN;
the chip pin SEN is a sample hold enable signal input pin, and the chip pin SENXOR is a sample enable trigger edge adjustment pin.
4. The three-in-one chip with boost, current mirror and sample-and-hold function according to claim 3, wherein the sample-and-hold enable signal input by the chip pin SEN enters a signal hold stage after a bundle of sample pulse signals is input; when the SENSOR pin is low, the rising edge of the SEN pin triggers sampling enabling; when the SEN xor pin is high, the SEN pin falling edge triggers the sample enable.
5. The three-in-one chip with boost, current Mirror and Sample Hold functions is characterized in that the same technology is adopted on the chip to design a boost loop module DC/DC loop1, a boost loop module DC/DC loop2, a boost loop sharing module Common Block, a two-way Current Mirror module Current Mirror and a two-way Sample Hold module Sample Hold, which are in a two-channel mode;
The method comprises the steps that a boosting loop module DC/DC loop1 and a boosting loop module DC/DC loop2 respectively raise an external 3.3V power voltage to 30V-60V to serve as two paths of input currents of a two-path Current Mirror module Current Mirror, the two paths of Current Mirror module Current Mirror generates two paths of Mirror voltages and fast-changing Mirror currents, and the two paths of Mirror voltages respectively provide reverse bias high voltages for two avalanche photodiodes APDs;
the two-way sampling and holding module Sample Hold samples and holds two paths of rapidly-changed Mirror currents transmitted by the Current Mirror, and the two sampling and holding results are respectively transmitted to the two external analog-digital conversion modules ADC to analyze the photo-currents of the APD which are rapidly changed.
6. The three-in-one chip with boost, current mirror and sample-and-hold functions according to claim 5, wherein the circuit structures of the boost loop module DC/DC loop1 and the boost loop module DC/DC loop2 are the same, and the switch output terminal SW1 of the boost loop module DC/DC loop1 is connected with the chip pin SW1;
the feedback signal FB1 of the boost loop module DC/DC loop1 is connected with the chip pin FB1;
the plurality of output ends of the boosting loop sharing module Common Block are connected with the plurality of input ends of the boosting loop module DC/DC loop 1;
The switch output end SW2 of the boost loop module DC/DC loop2 is connected with the chip pin SW2;
the feedback signal FB2 of the boost loop module DC/DC loop2 is connected with the chip pin FB2;
the plurality of output ends of the boosting loop sharing module Common Block are connected with the plurality of input ends of the boosting loop module DC/DC loop 2;
the voltage output by the DC/DC loop1 of the boost loop module is introduced into the chip through a chip pin MIRIN_CH1 after being subjected to proportion adjustment, and the voltage output by the DC/DC loop2 of the boost loop module is introduced into the chip through a chip pin MIRIN_CH2 after being subjected to proportion adjustment;
the Current Mirror input end MIRIN_CH1 of the Current Mirror module Current Mirror is connected with the chip pin MIRIN_CH1;
the Current Mirror input end MIRIN_CH1 of the Current Mirror module Current Mirror is connected with the chip pin MIRIN_CH1;
the Current limiting end RLIM_CH1 of the Current Mirror module Current Mirror is connected with the chip pin RLIM_CH1;
the Current limiting end RLIM_CH2 of the Current Mirror module Current Mirror is connected with the chip pin RLIM_CH2;
the Current Mirror module Current Mirror has its Current Mirror output MIR1_CH1 connected to the chip pins MIR1_CH1 and the Current Mirror input MIR1_CH1 of the Sample Hold module Sample Hold;
the Current Mirror module Current Mirror has its Current Mirror output MIR2_CH1 connected to the chip pin MIR2_CH1 and the Current Mirror input MIR2_CH1 of the Sample Hold module Sample Hold;
The Current Mirror module Current Mirror has its Current Mirror output MIR1_CH2 connected to the chip pins MIR1_CH2 and the Current Mirror input MIR1_CH2 of the Sample Hold module Sample Hold;
the Current Mirror module Current Mirror has its Current Mirror output MIR 2-CH 2 connected to the chip pin MIR 2-CH 2 and the Current Mirror input MIR 2-CH 2 of the Sample Hold module Sample Hold;
the output end MIROUT_CH1 of the Current Mirror module Current Mirror is connected with a chip pin MIROUT_CH1; providing an inverse bias high voltage for the avalanche photodiode APD1 through a chip pin mirout_ch1;
the output end MIROUT_CH2 of the Current Mirror module Current Mirror is connected with a chip pin MIROUT_CH2; providing an inverse bias high voltage for the avalanche photodiode APD2 through a chip pin mirout_ch2;
an external monitoring circuit collects an APD1 Mirror Current generated by a Current Mirror module Current Mirror through a chip pin MIR1_CH1 and a chip pin MIR2_CH1 to monitor an APD1 photocurrent; the other external monitoring circuit collects an APD2 Mirror image Current generated by a Current Mirror module Current Mirror through a chip pin MIR1_CH2 and a chip pin MIR2_CH2 so as to monitor an APD2 photocurrent; the two paths of mirror currents are also output to a double-path sampling Hold module;
The output end VOP_CH1 of the holding sampling voltage of the two-way sampling Hold module Sample Hold is connected with a chip pin VOP_CH1;
the output end VOP_CH2 of the holding sampling voltage of the Sample Hold of the two-way sampling Hold module is connected with a chip pin VOP_CH2; the chip pins VOP_CH1 and VOP_CH2 are respectively connected with two paths of external analog-to-digital conversion modules ADC;
the sampling enabling input end SEN_CH1 of the two-way sampling holding module Sample Hold is connected with the chip pin SEN_CH1;
the sampling enabling input end SEN_CH2 of the two-way sampling holding module Sample Hold is connected with the chip pin SEN_CH2;
the sampling enable triggering edge adjusting end SENOR_CH1 of the two-way sampling Hold module Sample Hold is connected with a chip pin SENOR_CH1;
the sampling enable triggering edge adjusting end SENOR_CH2 of the two-way sampling Hold module Sample Hold is connected with a chip pin SENOR_CH2;
the GAIN indication output end and the GAIN control input end GAIN_CH1 of the two-way Sample Hold module are connected with a chip pin GAIN_CH1;
the GAIN indication output end and the GAIN control input end GAIN_CH2 of the two-way Sample Hold module are connected with the chip pin GAIN_CH2.
7. The three-in-one chip with boost, current mirror and sample-and-hold functions of claim 5 or 6, wherein the boost loop Common module Common Block includes a Sawtooth oscillator Sawtooth OSC, a BIAS Current BIAS, a band gap reference band gap and a Current Sense, and is Common to the boost loop module DC/DC loop1 and the boost loop module DC/DC loop 2;
The boost loop module DC/DC loop1 comprises a switching tube Switch1, a modulation comparator PWM COM1, a Driver1 and an operational amplifier A1; the signal of the output end of the Sawtooth oscillator Sawtooth OSC and the signal of the output end of the Current Sense of the Current detection are added and then connected to the inverting end of the pulse width modulation comparator PWM COM 1;
the inverting input end of the operational amplifier A1 is connected with a chip pin FB1;
the non-inverting input end of the operational amplifier A1 is connected with a reference voltage VREF output by Bandgap;
the output end of the operational amplifier A1 is connected with the positive phase end of the pulse width modulation comparator PWM COM 1;
the output end of the pulse width modulation comparator PWM COM1 is connected with the input end of the Driver 1;
the output end of the Driver1 is connected with the grid electrode of the switching tube Switch 1;
the drain end of the switching tube Switch1 is connected with the chip pin SW1; the chip pin SW1 is connected with an external VDC3.3V power supply;
the source end of the switching tube Switch1 is connected with the ground;
the boost loop module DC/DC loop2 comprises a switching tube Switch2, a modulation comparator PWM COM2, a Driver2 and an operational amplifier A2; the signal of the output end of the Sawtooth oscillator Sawtooth OSC and the signal of the output end of the Current Sense of the Current detection are added and then connected to the inverting end of the pulse width modulation comparator PWM COM 2;
the inverting input end of the operational amplifier A2 is connected with the chip pin FB2;
The non-inverting input end of the operational amplifier A2 is connected with a reference voltage VREF output by Bandgap;
the output end of the operational amplifier A2 is connected with the positive phase end of the pulse width modulation comparator PWM COM 2;
the output end of the pulse width modulation comparator PWM COM2 is connected with the input end of the Driver 2;
the output end of the Driver2 is connected with the grid electrode of the switching tube Switch 2;
the drain end of the switching tube Switch2 is connected with the chip pin SW2; chip pin SW2 is connected to an external VDC3.3V power supply;
the source terminal of the switching tube Switch2 is connected to the ground.
8. The three-in-one chip with boost, current Mirror and sample-and-hold functions according to claim 5, wherein the two-way Current Mirror module Current Mirror comprises a Current Mirror module Current Mirror1 and a Current Mirror module Current Mirror2 with the same structure, and the Current Mirror module Current Mirror1 comprises PMOS transistors MP 1-MP 3, MP7, a Current limiting unit Current Limit1 and an operational amplifier A5;
the source ends of the PMOS transistors MP 1-MP 3 are simultaneously connected with a chip pin MIRIN_CH1;
the drain end of the PMOS transistor MP1 is connected with the input end of the Current limiting unit Current Limit 1;
the output end of the Current limiting unit Current Limit1 is connected with the source end of the PMOS transistor MP 7;
the other output end of the Current limiting unit Current Limit1 is connected with a chip pin RLIM_CH1;
The gate end of the PMOS transistor MP7 is connected with the output end of the operational amplifier A5;
the drain end of the PMOS transistor MP7 is connected with a chip pin MIROUT_CH1;
the drain end of the PMOS transistor MP2 is simultaneously connected with the chip pin MIR1_CH1 and one input end of the SAMPLE-HOLD module SAMPLE/HOLD 1;
the drain end of the PMOS transistor MP3 is simultaneously connected with the chip pin MIR2_CH1 and the other input end of the SAMPLE-HOLD module SAMPLE/HOLD 1;
the Current Mirror module Current Mirror2 comprises PMOS transistors MP 1-MP 3 and MP7, a Current limiting unit Current Limit2 and an operational amplifier A6;
the source ends of the PMOS transistors MP 4-MP 6 are simultaneously connected with a chip pin MIRIN_CH2;
the drain end of the PMOS transistor MP6 is connected with the input end of the Current limiting unit Current Limit 2;
the output end of the Current limiting unit Current Limit2 is connected with the source end of the PMOS transistor MP 8;
the other output end of the Current limiting unit Current Limit2 is connected with a chip pin RLIM_CH2;
the gate end of the PMOS transistor MP8 is connected with the output end of the operational amplifier A6;
the drain end of the PMOS transistor MP8 is connected with a chip pin MIROUT_CH2;
the drain end of the PMOS transistor MP5 is simultaneously connected with the chip pin MIR1_CH2 and one input end of the SAMPLE/HOLD module SAMPLE/HOLD 2;
the drain terminal of the PMOS transistor MP4 is simultaneously connected to the chip pin mir2_ch2 and the other input terminal of the SAMPLE/HOLD module SAMPLE/HOLD 2.
9. The three-in-one chip with boost, current mirror and Sample Hold functions of claim 5, wherein the two-way Sample Hold module Sample Hold comprises a Sample Hold module Sample Hold1 and a Sample Hold module Sample Hold2 with the same structure;
the Sample Hold module Sample Hold1 comprises a Sample Hold unit Sample/Hold1, a full differential operational amplifier A3, an operational amplifier A7, a D trigger Q1 and an exclusive or gate XOR1;
a pair of output ends of the SAMPLE/HOLD unit SAMPLE/HOLD1 are respectively connected with a non-inverting input end and an inverting input end of the full differential operational amplifier A3; the inverting output end of the full differential operational amplifier A3 is connected with a chip pin VOP_CH1; the chip pin VOP_CH1 is connected with an external analog-to-digital conversion module ADC;
a pair of output ends of the SAMPLE/HOLD1 are connected with a non-inverting input end of the operational amplifier A7 and the chip pin GAIN_CH1;
the output end of the operational amplifier A7 is connected with the data input end D of the D trigger Q1;
the output end Q of the D trigger Q1 is connected with a chip pin GAIN through a resistor R11; the method comprises the steps of carrying out a first treatment on the surface of the
The output end of the exclusive or gate XOR1 is connected with the clock end CLK of the D flip-flop Q1;
two input ends of the exclusive or gate XOR1 are respectively connected with chip pins SENOR_CH1 and SEN_CH1;
the Sample Hold module Sample Hold2 comprises a Sample Hold unit Sample/Hold2, a full differential operational amplifier A4, an operational amplifier A8, a D trigger Q2 and an exclusive or gate XOR2;
The pair of output ends of the SAMPLE/HOLD unit SAMPLE/HOLD2 are respectively connected with the non-inverting input end and the inverting input end of the full differential operational amplifier A4; the inverting output end of the full differential operational amplifier A4 is connected with a chip pin VOP_CH2; the chip pin VOP_CH2 is connected with another external analog-to-digital conversion module ADC;
a pair of output ends of the SAMPLE/HOLD unit SAMPLE/HOLD2 are connected with a non-inverting input end of the operational amplifier A8 and a chip pin GAIN_CH2;
the output end of the operational amplifier A8 is connected with the data input end D of the D trigger Q2;
the output end Q of the D trigger Q2 is connected with a chip pin GAIN through a resistor R14; the method comprises the steps of carrying out a first treatment on the surface of the
The output end of the exclusive or gate XOR2 is connected with the clock end CLK of the D flip-flop Q2;
the two inputs of exclusive or gate XOR2 are connected to chip pins senxor_ch2, sen_ch2, respectively.
10. The three-in-one chip with boost, current mirror and sample hold function according to claim 5, further comprising two boost voltage control circuits, wherein the boost voltage control circuits are used as three-in-one chip peripheral circuits, and the two boost voltage control circuits respectively regulate the output voltages of the boost loop module DC/DC loop1 and the boost loop module DC/DC loop2 to obtain two paths of different output voltages within the range of 30V-60V to return to the inside of the chip.
CN202310942732.1A 2023-07-28 2023-07-28 Three-in-one chip with boost, current mirror and sample hold functions Pending CN117097154A (en)

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CN202310942732.1A CN117097154A (en) 2023-07-28 2023-07-28 Three-in-one chip with boost, current mirror and sample hold functions

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