CN117096152A - Layout, wafer detection standard piece and mask - Google Patents
Layout, wafer detection standard piece and mask Download PDFInfo
- Publication number
- CN117096152A CN117096152A CN202310937202.8A CN202310937202A CN117096152A CN 117096152 A CN117096152 A CN 117096152A CN 202310937202 A CN202310937202 A CN 202310937202A CN 117096152 A CN117096152 A CN 117096152A
- Authority
- CN
- China
- Prior art keywords
- defect
- wafer
- layout
- chip
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 85
- 230000007547 defect Effects 0.000 claims abstract description 171
- 238000010586 diagram Methods 0.000 claims abstract description 86
- 238000012360 testing method Methods 0.000 claims abstract description 21
- 230000002950 deficient Effects 0.000 claims description 46
- 238000013461 design Methods 0.000 claims description 28
- 238000007689 inspection Methods 0.000 claims description 24
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000012545 processing Methods 0.000 claims description 7
- 230000003287 optical effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 description 12
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/9501—Semiconductor wafers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/01—Arrangements or apparatus for facilitating the optical investigation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Immunology (AREA)
- General Health & Medical Sciences (AREA)
- Pathology (AREA)
- Biochemistry (AREA)
- Analytical Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Health & Medical Sciences (AREA)
- General Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Automation & Control Theory (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The application provides a layout, a wafer detection standard piece and a mask, wherein the layout comprises four structural drawings, and a first structural drawing comprises various line patterns and connecting wire pin patterns in a defect-free chip; the second structure diagram comprises other pin patterns in the defect-free chip; the third structure diagram is a chip electrical property test area in a defect-free chip; the fourth structure diagram is a round test area in a defect-free chip; after the wafer is manufactured according to the different structural diagram areas in the layout, the AOI detection equipment is used for comparing the different structural diagram areas with all areas of the whole wafer, the number of different defects is counted, the number is compared with respective preset thresholds, and the detection rate corresponding to various defects on the surface of the wafer is determined. According to the embodiment of the specification, the defect layout and the wafer detection standard piece are designed to improve the convenience and the accuracy of the wafer surface appearance defect detection through setting the defect-free layout.
Description
Technical Field
The application relates to the technical field of semiconductor wafer detection processes, in particular to a layout, a wafer detection standard piece and a mask.
Background
Defects exist in the processing of semiconductor wafer chips due to various process steps and influencing factors, and particularly, the quality of the chips needs to be initially screened before the wafer chips are packaged, for example, an AOI (Automatic Optic Inspection, automatic optical inspection) defect detection device is adopted to detect the defects on the surfaces of the wafer chips.
However, with the high requirements of semiconductor wafer fabrication, the variety of defects on the wafer surface is increasing. Only adopting AOI detection equipment can not accurately detect tiny defects and similar defects on the surface of a wafer, so that the identification accuracy is lower.
Therefore, a new solution for wafer surface defect detection is needed.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a layout, a wafer inspection standard wafer and a mask, which are applied to a process of inspecting surface defects of a semiconductor wafer.
The embodiment of the specification provides the following technical scheme:
embodiments of the present description provide a layout, including four block diagrams,
the first structure diagram comprises various line patterns and connecting line pin patterns in a defect-free chip;
the second structure diagram comprises other pin patterns in the defect-free chip;
the third structure diagram is a chip electrical property test area in a defect-free chip;
the fourth structure diagram is a round test area in a defect-free chip;
after the wafer is manufactured according to the different structural diagram areas in the layout, the AOI detection equipment is used for comparing the different structural diagram areas with all areas of the whole wafer, the number of different defects is counted, the number is compared with respective preset thresholds, and the detection rate corresponding to various defects on the surface of the wafer is determined.
Another layout provided by the embodiment of the specification comprises four defect structure diagrams;
the first defect structure diagram comprises defect patterns of various connecting wires in the chip and defect patterns of corresponding pins of the connecting wires;
the second defect structure diagram comprises other pin defect patterns in the chip;
the third defect structure includes a scratch line pattern in the chip;
the fourth defect structure diagram includes a circular test pattern;
and manufacturing the wafer according to the areas of different defect structure diagrams in the layout, comparing the different defect structure diagrams with the defect-free structure pattern examples by using AOI detection equipment, counting the number of different defects, comparing the number with respective preset thresholds, and determining the detection rate corresponding to various defects on the surface of the wafer.
The wafer detection standard piece provided in the embodiments of the present specification is applied to semiconductor wafer AOI detection, and the wafer detection standard piece includes:
a non-defective pattern and a defective pattern; the non-defective pattern and the defective pattern are oppositely arranged;
the number of the pattern areas in the non-defective pattern and the defective pattern is the same as the pattern area layout;
and processing and manufacturing the non-defective pattern and the defective pattern in the layout on a wafer, scanning the wafer by using an AOI (automatic optical inspection) detection device, comparing a non-defective chip area with a whole chip area, counting the number of detected defects, comparing the number with a design value, and determining the defect type of the wafer and the detection rate corresponding to each defect type.
Compared with the prior art, the beneficial effects that above-mentioned at least one technical scheme that this description embodiment adopted can reach include at least:
according to the embodiment of the specification, the defect layout and the wafer detection standard piece are designed to improve the convenience and the accuracy of the wafer surface appearance defect detection through setting the defect-free layout.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a wafer inspection standard wafer in accordance with the present application;
FIG. 2 is a schematic diagram of a layout and various block diagram areas in the present application;
FIG. 3 is a schematic diagram of a first block diagram of a layout in accordance with the present application;
FIG. 4 is a schematic diagram of a second block diagram of a layout in accordance with the present application;
FIG. 5 is a schematic diagram of a third block diagram in a layout according to the present application;
FIG. 6 is a schematic diagram of a fourth block diagram of a layout in accordance with the present application;
FIG. 7 is a schematic layout of a wafer inspection standard wafer according to the present application;
FIG. 8 is a schematic diagram of electrical performance testing on a wafer chip according to the present application;
FIG. 9 is a schematic diagram of a wafer surface defect in accordance with the present application;
FIG. 10 is a schematic diagram of a first defect structure in another layout of the present application;
FIG. 11 is a schematic diagram of a second defect structure in another layout according to the present application;
FIG. 12 is a schematic diagram of a third defect structure in another layout according to the present application;
FIG. 13 is a schematic diagram of a fourth defect structure in another layout according to the present application.
Detailed Description
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, apparatus may be implemented and/or methods practiced using any number and aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the present application may be practiced without these specific details.
In the prior art, the quality of the wafer chip needs to be initially screened before the wafer chip is packaged, for example, AOI (Automatic Optic Inspection) defect detection equipment is adopted to detect the surface defects of the wafer chip. However, with the high requirements of semiconductor wafer fabrication, the variety of defects on the wafer surface is increasing. Only adopting AOI detection equipment can not accurately detect tiny defects and similar defects on the surface of a wafer, so that the identification accuracy is lower.
Based on the embodiment of the specification, through carrying out overall design on various lines and pin patterns which are attached to the actual appearance of the chip, manufacturing a wafer through a chip processing flow, comparing a chip area attached to the actual appearance of the chip with all areas of the whole wafer by using AOI detection equipment as a sample, counting the number of different defects, comparing the number with respective preset thresholds, and determining the detection rate corresponding to various defects on the surface of the wafer. And the defect patterns of the chip connecting wire bars and the pins and various physical detection defects of the wafer chip are integrally designed, a defect-free layout and a defect-free layout are set to be wafer detection standard pieces, in the wafer surface defect detection process, AOI detection equipment is used for comparing different structural diagram areas of a sample with all areas or defect areas of the whole wafer, the number of different defects is counted, and the number is compared with respective preset thresholds, so that the detection rate corresponding to various defects on the wafer surface is determined.
According to the embodiment of the specification, the defect layout and the wafer detection standard piece are designed to improve the convenience and the accuracy of the wafer surface appearance defect detection through setting the defect-free layout.
The following describes the technical scheme provided by each embodiment of the present application with reference to the accompanying drawings.
As shown in fig. 2, a layout provided in the embodiment of the present specification includes four structural diagram regions for a defect-free layout, for example, each structural diagram region is marked in fig. 2, for example, S1 and S5 represent a first structural diagram region, S2 represent a second structural diagram region, S3 represent a third structural diagram region, and S4 represent a fourth structural diagram region.
The first structure diagram comprises various line patterns and connecting line pin patterns in a defect-free chip; the second structure diagram comprises other pin patterns in the defect-free chip; the third structure diagram is a chip electrical property test area in a defect-free chip; the fourth block diagram is a circular test area in a defect-free chip.
Patterns corresponding to the structural diagram areas in the defect-free layout are shown in fig. 3-6. FIG. 3 simulates various lines and bond pad structures in a normal defect-free chip (e.g., the block diagram of FIG. 3). FIG. 4 simulates other pin patterns in a defect-free chip as normally black squares. FIG. 5 is a schematic diagram of a chip electrical performance test area of a defect-free chip, which is a normally white area. FIG. 6 is set to a circular test area in a defect free chip, with normal areas only having values of the diameter of the circle.
Therefore, the defect-free layout designed in the embodiment of the specification is manufactured on a wafer through a chip processing flow, the areas of different structural drawings are compared with all areas of the whole wafer by using AOI detection equipment, the number of different defects is counted, the number is compared with respective preset thresholds, and the detection rate corresponding to various defects on the surface of the wafer is determined. In some embodiments the entire wafer die is provided with patterns in multiple defect-free layouts.
For example, an AOI detection device is used for scanning a wafer, a flawless die is used as a sample, the flawless die is compared with a whole wafer with a region, the block region in the chip can be simulated by the structural diagram region of S2, the number of defects detected by different sizes is counted according to a design value, and then the detection rate of the device for the defects can be obtained by comparing the number with the design value.
And for example, scanning the wafer by using AOI detection equipment, comparing the wafer with all areas of the whole wafer by using flawless die, simulating the detection condition of scratches in the chip by using the structural area of S3, counting the number of defects detected by different sizes according to the design value, and comparing the number of the defects with the design value to obtain the detection rate of the equipment for the defects.
For example, the AOI detection device is used for scanning the wafer, flawless die is used as a sample, the flawless die is compared with all areas of the whole wafer, the structural diagram area of S4 can simulate the detection condition of the defects of the bump (raised circular defects) in the chip, the number of the defects detected by different sizes is counted according to the design value, and then the detection rate of the device for the defects can be obtained by comparing the number with the design value.
For another example, a wafer test plant needs to test the electrical properties of the chips on the wafer, pin the pins on the pad structure (fig. 8), power the chips through the pins, and collect current data. The strength and offset of the needle insertion all bring problems, an AOI detection device is used for scanning the tested wafer, S5 flawless die is used as a sample and is compared with all areas of the whole wafer, the structural diagram area of S5 can simulate the defect detection condition of needle marks in a chip, as shown in an example of FIG. 9, the number of detected defects with different sizes is counted according to a design value, and then the number is compared with the design value, so that the detection rate of the device for the defects can be obtained.
In some embodiments, the various lines in the first structure diagram are various connecting lines in chip manufacture, including different line widths and line routing.
Various connecting lines shown in a first structural diagram in the defect-free layout shown in fig. 3 are provided with different line patterns according to line lengths, widths, distances and the like, and connecting line pin patterns are shown as white boxes in fig. 3.
In some embodiments, the second structure is other pin patterns, such as various black squares.
The third structure pattern is a scratch line pattern after the chip electrical property is detected. As shown in fig. 5, different diagonal defects appear in the third structural diagram region.
According to the embodiment of the specification, the defect-free layout is integrally distributed and is close to the actual looks of the chip, after the wafer is manufactured according to different structural diagram areas in the layout, the AOI detection equipment is used for comparing the different structural diagram areas with all areas of the whole wafer, the number of different defects is counted, the number is compared with respective preset thresholds, and the detection rate corresponding to various defects on the surface of the wafer is determined.
In some embodiments, patterns of various structural patterns in the defect-free layout in the embodiments of the present disclosure are used to form standard pieces for detecting various defects on the wafer surface.
Similarly, the embodiment of the specification sets a defect layout, wherein the defect layout comprises four defect structure diagrams, and the first defect structure diagram comprises defect patterns of various connecting wires in a chip and defect patterns of corresponding pins of the connecting wires; the second defect structure diagram comprises other pin defect patterns in the chip; the third defect structure includes a scratch line pattern in the chip; the fourth defect structure diagram includes a circular test pattern; and manufacturing the wafer according to the areas of different defect structure diagrams in the layout, comparing the different defect structure diagrams with the defect-free structure pattern examples by using AOI detection equipment, counting the number of different defects, comparing the number with respective preset thresholds, and determining the detection rate corresponding to various defects on the surface of the wafer.
Similar to the non-defective layout design, the number of graphic areas in the defective layout and the non-defective layout is the same as the layout of the graphic areas. The left part of fig. 1 is exemplified as an overall layout of the defect layout, and an enlarged view is also shown in fig. 2. The defect map includes four defect structure diagrams corresponding to defect-free structure diagrams. Patterns with different sizes are added and subtracted at different positions in the first defect structure diagram S1, and the sizes comprise 1um-40um. Thus being beneficial to directly comparing and obtaining defects in the morphology. The chip is characterized by further comprising sharp angle patterns with different sizes in the white square block, and the sharp angle patterns are used for simulating needle marks brought by the chip electrical property test needles. The second defect structure diagram shows other pin defect patterns, such as white squares of different sizes in the black squares in S2 shown in fig. 11 to characterize defects of different sizes, the size range including 1um-40um. In the third defect structure diagram, the scratch line pattern of the chip is shown, and as shown in fig. 12, the defect area in S3 has different oblique lines, the width of the oblique line comprises 1um-40um, and the length is 100um. The area is used for representing scratch detection, and the simulation equipment can detect scratch with the width. The circular test patterns in the fourth defect structure diagram, such as a plurality of circles of different sizes in S4 shown in fig. 13, characterize a protruding circular defect (bump) on the wafer.
And (3) manufacturing the wafer according to the areas of different defect structure diagrams in the overall defect layout by designing the overall defect layout, comparing the different defect structure diagrams with defect-free structure pattern examples by using AOI detection equipment, counting the number of different defects, comparing the number with respective preset thresholds, and determining the detection rate corresponding to various defects on the surface of the wafer.
If the AOI detection device is used for scanning the wafer, the defect-free die is used as a sample, the sample is compared with a defective area (see fig. 1 or 7), the pattern of S1 can simulate whether the line area in the chip has defects, the defects of the patterns are increased, the number of defects with different sizes are counted according to the design value, and then the number of defects is compared with the design value, so that the detection rate of the device for the defects can be obtained.
In some embodiments the defect size of the connection line ranges from 1 μm to 40 μm. The scratch line pattern includes different oblique lines, the width of the oblique lines includes 1 μm-40 μm, and the length is 100 μm. The circular test pattern includes circles of different sizes arranged according to a preset rule, and the diameter of the circle includes 1 μm to 40 μm.
Specifically, as shown in fig. 10, in each case where the pattern of the chip connection line in the first defect structure diagram in the defect layout is increased or decreased, the specific size range includes 1 μm to 40 μm. As shown in FIG. 12, the defective area in S3 has different diagonal lines, and the width of the diagonal line is 1um-40um, and the length is 100um. The area is used for representing scratch detection, and the simulation equipment can detect scratch with the width. A plurality of circles of different sizes are used to characterize the raised circular defects (bumps) on the wafer as shown in S4 of fig. 13.
In some embodiments, the defect layout and the defect-free layout are simultaneously arranged to form standard pieces so as to detect various defects on the surface of the wafer, as shown in fig. 1 or 7. However, the arrangement of the defect layout and the defect-free layout on the standard chip can be specifically arranged according to actual conditions.
The wafer detection standard piece designed in the embodiment of the specification is applied to semiconductor wafer AOI detection, and comprises: a non-defective pattern and a defective pattern; the non-defective pattern and the defective pattern are oppositely arranged; the number of the pattern areas in the non-defective pattern and the defective pattern is the same as the pattern area layout; and processing and manufacturing the non-defective pattern and the defective pattern in the layout on a wafer, scanning the wafer by using an AOI (automatic optical inspection) detection device, comparing a non-defective chip area with a whole chip area and a defective chip area, counting the number of various defects detected, comparing the number with a design value, and determining the defect type of the wafer and the detection rate corresponding to each defect type.
In some embodiments, the wafer inspection standard chip is disposed on a mask, and corresponding non-defective patterns and defective patterns are manufactured on the wafer after exposure through the mask, so as to perform the inspection rate corresponding to various defect types of the wafer.
Specifically, the defective pattern and the non-defective pattern are manufactured on a wafer by using a wafer inspection standard wafer and a mask plate through a chip processing flow, and the arrangement mode on the wafer is shown in fig. 1 or fig. 7. If the left column is defective and the right column is not defective in fig. 1, or if the left column and the right column of defective patterns are staggered in fig. 7, the wafer is placed on the AOI inspection device to measure, so that the effect of the chip during inspection can be simulated, and the inspection capability of the AOI inspection device can be confirmed according to the comparison between the detected defect result and the design result.
For example, an AOI detection device is used for scanning a wafer, a flawless die is used as a sample, the sample is compared with a flawed area, the pattern of S1 can simulate whether a line area in a chip has a pattern missing or not, the defects of the pattern increasing are detected, the number of defects with different sizes is counted according to a design value, and then the number of defects detected by the device is compared with the design value, so that the detection rate of the device for the defects can be obtained.
For another example, an AOI detection device is used for scanning a wafer, flawless die is used as a sample, the sample is compared with all areas of the whole wafer, the pattern of S2 can simulate whether the square areas in the chip have defects or not, the number of defects detected by different sizes is counted according to a design value, and then the number of defects detected by different sizes is compared with the design value, so that the detection rate of the device for the defects can be obtained.
For example, the AOI detection device is used for scanning the wafer, flawless die is used as a sample, the sample is compared with all areas of the whole wafer, the pattern of S3 can simulate the detection condition of scratch in the chip, the number of defects with different sizes is counted according to the design value, and then the number of defects detected by the device is compared with the design value, so that the detection rate of the device for the defects can be obtained.
For another example, an AOI detection device is used for scanning a wafer, flawless die is used as a sample, the sample is compared with all areas of the whole wafer, the pattern of S4 can simulate the detection condition of the bump defects in the chip, the number of defects detected by different sizes is counted according to a design value, and then the number of defects detected by different sizes is compared with the design value, so that the detection rate of the device for the defects can be obtained.
For another example, a wafer test plant needs to test the electrical properties of the chips on the wafer, pin the pins on the pad structure (fig. 8), power the chips through the pins, and collect current data. The strength and offset of the needle insertion all bring problems, an AOI detection device is used for scanning the tested wafer, S5 flawless die is used as a sample and is compared with all areas of the whole wafer, the pattern of S5 can simulate the defect detection condition of needle marks in a chip as shown in figure 9, the number of detected defects with different sizes is counted according to a design value, and then the number of detected defects is compared with the design value, so that the detection rate of the device for the defects can be obtained.
According to the method, the defect-free layout is set to serve as a standard pattern, namely, the actual looks of the chip is closed, the defect-free layout is directly compared with the whole wafer area in the wafer surface defect detection process, so that the convenience and the accuracy of wafer surface morphology defect detection are improved, and the convenience of wafer surface defect detection is improved. Meanwhile, the whole design of different morphologies close to the chip saves the process steps in the whole process flow, saves the process cost and the like. Similarly, a defect layout comprising various defects is designed, and the detection of the defects on the surface of the wafer can be conveniently and accurately realized by respectively comparing corresponding areas after the defective pattern and the non-defective pattern are manufactured on the wafer. Similarly, a wafer inspection standard sheet is designed, and defect patterns and non-defect patterns are simultaneously arranged on the wafer inspection standard sheet, the non-defect patterns are used as standard patterns and are respectively and directly compared with the whole area or the defective area of the wafer, and the number of various defect types is counted and then compared with respective design values, so that the detection rate of the various defect types in the wafer surface defect inspection is determined.
The same and similar parts of the embodiments in this specification are all referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the description is relatively simple, and reference is made to the description of parts of the system embodiments.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present application should be included in the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. A layout is characterized in that the layout comprises four structural diagrams,
the first structure diagram comprises various line patterns and connecting line pin patterns in a defect-free chip;
the second structure diagram comprises other pin patterns in the defect-free chip;
the third structure diagram is a chip electrical property test area in a defect-free chip;
the fourth structure diagram is a round test area in a defect-free chip;
after the wafer is manufactured according to the different structural diagram areas in the layout, the AOI detection equipment is used for comparing the different structural diagram areas with all areas of the whole wafer, the number of different defects is counted, the number is compared with respective preset thresholds, and the detection rate corresponding to various defects on the surface of the wafer is determined.
2. The layout according to claim 1, wherein the various lines in the first structure diagram are various connecting lines in chip fabrication, including different line widths and line routing.
3. The layout according to claim 1, wherein the third structure pattern exhibits a scribe line pattern after the chip electrical property is detected.
4. The layout according to claim 1, wherein patterns in various structural drawings on the layout form standard pieces so as to detect various defects on the surface of a wafer.
5. A layout, characterized in that the layout comprises four defect structure diagrams;
the first defect structure diagram comprises defect patterns of various connecting wires in the chip and defect patterns of corresponding pins of the connecting wires;
the second defect structure diagram comprises other pin defect patterns in the chip;
the third defect structure includes a scratch line pattern in the chip;
the fourth defect structure diagram includes a circular test pattern;
and manufacturing the wafer according to the areas of different defect structure diagrams in the layout, comparing the different defect structure diagrams with the defect-free structure pattern examples by using AOI detection equipment, counting the number of different defects, comparing the number with respective preset thresholds, and determining the detection rate corresponding to various defects on the surface of the wafer.
6. Layout according to claim 5, characterized in that the defect size of the connection lines is in the range of 1 μm-40 μm.
7. The layout according to claim 5, wherein the scratch line pattern comprises different oblique lines, the width of the oblique lines comprises 1 μm-40 μm, and the length is 100 μm; the circular test pattern includes circles of different sizes arranged according to a preset rule, and the diameter of the circle includes 1 μm to 40 μm.
8. The layout according to claim 5, wherein the layout and the corresponding defect-free layout form a standard wafer for detecting various defects on the wafer surface.
9. A wafer inspection standard wafer, characterized in that is applied to semiconductor wafer AOI inspection, the wafer inspection standard wafer comprising:
a non-defective pattern and a defective pattern; the non-defective pattern and the defective pattern are oppositely arranged;
the number of the pattern areas in the non-defective pattern and the defective pattern is the same as the pattern area layout;
and processing and manufacturing the non-defective pattern and the defective pattern in the layout on a wafer, scanning the wafer by using an AOI (automatic optical inspection) detection device, comparing a non-defective chip area with a whole chip area and a defective chip area, counting the number of various defects detected, comparing the number with a design value, and determining the defect type of the wafer and the detection rate corresponding to each defect type.
10. A mask, characterized in that the layout according to claim 1 or 5 or the wafer inspection standard piece according to claim 9 is arranged on the mask, and corresponding non-defective patterns and defective patterns are manufactured on a wafer after exposure through the mask, so as to perform the inspection rate corresponding to various defect types of the wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310937202.8A CN117096152A (en) | 2023-07-27 | 2023-07-27 | Layout, wafer detection standard piece and mask |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310937202.8A CN117096152A (en) | 2023-07-27 | 2023-07-27 | Layout, wafer detection standard piece and mask |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117096152A true CN117096152A (en) | 2023-11-21 |
Family
ID=88781291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310937202.8A Pending CN117096152A (en) | 2023-07-27 | 2023-07-27 | Layout, wafer detection standard piece and mask |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117096152A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110197797A (en) * | 2018-02-27 | 2019-09-03 | 上海微电子装备（集团）股份有限公司 | A kind of defects detection standard film |
| CN116149130A (en) * | 2023-04-19 | 2023-05-23 | 魅杰光电科技(上海)有限公司 | Layout, mask and exposure verification method of lithography machine |
-
2023
- 2023-07-27 CN CN202310937202.8A patent/CN117096152A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110197797A (en) * | 2018-02-27 | 2019-09-03 | 上海微电子装备（集团）股份有限公司 | A kind of defects detection standard film |
| CN116149130A (en) * | 2023-04-19 | 2023-05-23 | 魅杰光电科技(上海)有限公司 | Layout, mask and exposure verification method of lithography machine |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100267463B1 (en) | Method of measurement of yield loss chips and poor chips classified by a type according to defected chips on the wafer | |
| JP4227959B2 (en) | Inspection method using vertical slice imaging | |
| US7733099B2 (en) | Monitoring pattern for detecting a defect in a semiconductor device and method for detecting a defect | |
| US8054097B2 (en) | Method and system for automatically managing probe mark shifts | |
| CN109075096B (en) | Computer-aided weak pattern detection and identification system | |
| CN111653500A (en) | Method for judging wafer yield loss | |
| KR101385753B1 (en) | Method for inspecting critical dimension uniformity at the high speed measurement | |
| CN117096152A (en) | Layout, wafer detection standard piece and mask | |
| JP2004363304A5 (en) | ||
| KR20080002044A (en) | Method of setting an inspection area | |
| CN117038664B (en) | Layout, wafer AOI detection standard chip and wafer surface defect detection method | |
| US20050065739A1 (en) | Method of qualifying a process tool with wafer defect maps | |
| CN1404122A (en) | Detection method of electric defect in inner conducting layer of tested area | |
| JP2001110867A (en) | Manufacture of electronic device and quality control system for electronic device | |
| CN117191506A (en) | Standard sheet for testing capability of inspecting machine to grasp defect and inspecting method | |
| US6917194B2 (en) | External verification of package processed linewidths and spacings in semiconductor packages | |
| TW201925804A (en) | Method for diagnosing a semiconductor wafer | |
| CN109211924A (en) | The defects of chip manufacturing proces detection method | |
| KR20080001734A (en) | Method of inspecting a defect point of mask | |
| US11631620B2 (en) | Semiconductor device and method of testing a semiconductor device | |
| JPS594019A (en) | Comparing and inspecting method for pattern | |
| KR970011652B1 (en) | Test method of lithography process margin of semiconductor | |
| CN113496908A (en) | Semiconductor device detection method, semiconductor device and electronic equipment | |
| KR100268779B1 (en) | Pattern defect inspection method | |
| CN115309007A (en) | Photoetching line width test structure based on optical microscope and inspection method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |