CN117092684A

CN117092684A - Radiation detector and radiation imaging system

Info

Publication number: CN117092684A
Application number: CN202310545410.3A
Authority: CN
Inventors: 大泽和嵩; 渡边高典; 山口智奈
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 2022-05-18
Filing date: 2023-05-15
Publication date: 2023-11-21

Abstract

The present invention relates to a radiation detector and a radiation imaging system. A radiation detector includes: a pixel array in which pixels are arranged in a matrix shape, each pixel having a radiation detection element configured to convert radiation into electric charge and an amplification transistor configured to amplify a signal from the radiation detection element and output the amplified signal; and a signal wiring provided for each pixel column, wherein the signal wiring does not overlap with an active layer in which the amplifying transistor is arranged in a plan view.

Description

Radiation detector and radiation imaging system

Technical Field

The present invention relates to a radiation detector and a radiation imaging system.

Background

Japanese patent application laid-open No.2019-87640 discloses a method of improving the accuracy of detecting energy rays by defining the thickness of a detection region of an energy ray detector (radiation detector).

When radiation is incident on the radiation detector, degradation may occur.

Disclosure of Invention

An object of the present invention is to provide a radiation detector with enhanced detection sensitivity.

An aspect of the present disclosure is a radiation detector including: a pixel array in which pixels are arranged in a matrix shape, each pixel having a radiation detection element configured to convert radiation into electric charge and an amplification transistor configured to amplify a signal from the radiation detection element and output the amplified signal; and a signal wiring provided for each pixel column, wherein the signal wiring does not overlap with an active layer in which the amplifying transistor is arranged in a plan view.

According to the present invention, a radiation detector with enhanced detection sensitivity can be provided.

Further features of the invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.

Drawings

Fig. 1 is a diagram showing a configuration of an imaging apparatus according to a first embodiment;

fig. 2 is an equivalent circuit diagram of a pixel according to the first embodiment;

fig. 3A to 3C are top views of a pixel according to the first embodiment;

fig. 4 is a diagram showing a configuration of an imaging apparatus according to a second embodiment;

fig. 5 is an equivalent circuit diagram of a pixel according to the second embodiment;

fig. 6A to 6C are top views of a pixel according to a second embodiment;

fig. 7 is a top view of a pixel according to a third embodiment;

fig. 8A to 8C are top views of a pixel according to a fourth embodiment;

fig. 9A to 9C are top views of a pixel according to a fifth embodiment;

fig. 10A to 10C are top views of a pixel according to a sixth embodiment;

fig. 11A to 11C are top views of a pixel according to a seventh embodiment;

fig. 12 is a top view of a pixel according to an eighth embodiment;

fig. 13 is a top view of a pixel according to a ninth embodiment;

fig. 14 is a top view of a pixel according to a tenth embodiment;

Fig. 15 is a top view of a pixel according to an eleventh embodiment;

fig. 16 is a schematic diagram for describing a radiation imaging system according to a twelfth embodiment; and

fig. 17 is a schematic diagram for describing a radiation imaging system according to the thirteenth embodiment.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the following embodiments will only show specific examples of the technical idea of the present invention, and are not intended to limit the present invention. The embodiments will describe a number of features. However, these multiple characteristics are not all necessary for the present invention, and the multiple characteristics may be combined together arbitrarily.

The dimensions and positional relationships of the elements in the drawings are exaggerated to make the description clear, as the case may be. Hereinafter, the same configuration will be denoted by the same symbol, and a description thereof will be omitted in some cases.

The degradation of the radiation detector is understood as follows.

When radiation is incident on the radiation detector, charges generated in the insulating layer are held in the insulating layer. The charge held in the insulating layer fluctuates the channel potential of the transistor within the pixel and shifts the threshold value. Thus, the operating point of the transistor within the pixel fluctuates. Further, the charge held in the insulating layer changes the width of a depletion layer formed as a PN junction portion of a source, a drain, or the like of a transistor in a pixel, and fluctuates parasitic capacitance. Further, the electric charge held in the insulating layer has an influence on the potential of the detection diode, and increases the dark current. Alternatively, when the charge held in the insulating layer increases the dark current of the floating node, fluctuation occurs in the operating point of the pixel circuit.

These factors caused by the charge held in the insulating layer have an effect on the sensor output and disable the output of the desired signal.

Since the amount of charge held in the insulating layer increases according to the irradiation amount of radiation, the pixel output deviates from a desired output according to the irradiation amount. Therefore, this phenomenon will be referred to as degradation of the sensor due to radiation hereinafter.

First embodiment

(configuration of imaging apparatus)

Fig. 1 is a diagram showing the configuration of an imaging apparatus (radiation detector) according to the present embodiment. The imaging device according to the present embodiment has a signal wiring 10-1 and a pixel 11. The pixels 11 are arranged in a matrix shape in the pixel array 13 in a plurality of rows and a plurality of columns. One signal wiring 10-1 is arranged for one pixel column in which the pixels 11 are arranged. Further, the imaging apparatus has a vertical scanning circuit 14. The pixels 11 of one row arranged on a plurality of columns are connected to a vertical scanning circuit 14 via one control line 12. The vertical scanning circuit 14 controls the accumulation period of the pixels 11.

The imaging apparatus has a column circuit unit 15, a horizontal scanning circuit 16, and an output circuit 17. The column circuit unit 15 includes a plurality of column circuits. One of the plurality of column circuits is arranged to correspond to the signal wiring 10-1. Each of the plurality of column circuits processes a signal output from the pixel 11 to the signal wiring 10-1, and outputs the processed signal to the output circuit 17. Examples of this processing are AD conversion, amplification, and the like.

The horizontal scanning circuit 16 sequentially selects a plurality of column circuits included in the column circuit unit 15. Accordingly, the signal held by each of the plurality of column circuits is sequentially output to the output circuit 17. The output circuit 17 outputs a signal to the outside of the imaging apparatus. The signal output from the output circuit 17 is a signal output from the imaging device.

The image forming apparatus also has a control circuit (control unit) 18. The control circuit 18 is connected to each of the vertical scanning circuit 14, the column circuit unit 15, and the horizontal scanning circuit 16 via a driving line that supplies a driving signal, and controls these circuits.

(Circuit configuration of pixels)

Fig. 2 is a circuit diagram showing circuits of two rows and two columns in the pixel 11 shown in fig. 1. Hereinafter, it is assumed that the electric charge accumulated in the detection diode D1 serving as the radiation detection element is electrons. Therefore, in the present embodiment, all the transistors included in the pixel 11 are N-type transistors. Meanwhile, the charge accumulated in the detection diode may be holes. In this case, the transistor of the pixel 11 may be a P-type transistor. That is, the definition of the conductivity type to be used in the following description may be changed according to the polarity of the electric charge as the signal processing.

The pixel 11 has a detection diode D1 serving as a radiation detection element (photoelectric conversion unit), a transfer transistor M1, a charge holding unit C1, a reset transistor M2, an amplifying transistor M3, and a selection transistor M4.

The detection diode D1 converts radiation into electric charges. The radiation detected by the detection diode D1 may be ionizing radiation such as X-rays and gamma rays, or may be particle radiation such as alpha rays, beta rays, electron rays, neutron rays, proton rays, heavy ion rays, and electron rays. The detection diode D1 according to the present embodiment detects an electron ray. The detection diode D1 has a single crystal semiconductor layer made of, for example, silicon or germanium, but may have a polycrystalline semiconductor layer.

The transfer transistor M1 is disposed on an electrical path between the detection diode D1 and a node connected to the charge holding unit C1, the reset transistor M2, and the amplifying transistor M3. A power supply voltage is supplied to each of the drains of the reset transistor M2 and the amplifying transistor M3. The selection transistor M4 is provided on an electrical path between the amplifying transistor M3 and the signal wiring 10-1. The amplifying transistor M3 is electrically connected to the signal wiring 10-1 via the selection transistor M4. The charge holding unit C1 includes a floating diffusion unit (floating diffusion capacitance) provided inside the semiconductor substrate and a parasitic capacitance of an electric path from the transfer transistor M1 to the amplifying transistor M3 via the floating diffusion unit.

Each of the signal RES, the signal TX, and the signal SEL is a signal supplied from the vertical scanning circuit 14 shown in fig. 1 via the control line 12. In fig. 2, the end of each signal indicates the pixel row to which the signal is supplied. For example, the signal RES (m) indicates the signal RES supplied to the pixel of the m-th row.

A current source (not shown) is connected to the signal wiring 10-1. When the signal SEL (M) becomes an active level, the selection transistor M4 of the pixel 11 of the mth row is turned on. Accordingly, a current is supplied from the current source to the amplifying transistor M3 of the pixel 11 of the mth row. In each pixel 11 of the M-th row, a source follower circuit is formed of a power supply voltage VDD, an amplifying transistor M3, and a current source (not shown) connected to the signal wiring 10-1. By formation of the source follower circuit, the amplifying transistor M3 outputs a signal based on the potential of the charge holding unit C1 to the signal wiring 10-1 via the transistor M4.

Further, when the signal SEL (m+1) becomes an active level, the selection transistor M4 of the pixel 11 of the m+1 th row is turned on. Thus, a current is supplied from the current source to the amplifying transistor M3 of the m+1th row. In each pixel 11 of the m+1th row, a source follower circuit is formed of a power supply voltage VDD, an amplifying transistor M3, and a current source (not shown) connected to the signal wiring 10-1. By formation of the source follower circuit, the amplifying transistor M3 outputs a signal based on the potential of the charge holding unit C1 to the signal wiring 10-1 via the transistor M4.

(Pixel plan view)

Fig. 3A to 3C are schematic diagrams for describing the layout of the pixel 11 shown in fig. 1. In fig. 3A to 3C, a legend indicates an active region, a polysilicon layer, a first wiring layer, a second wiring layer, a contact plug, and a via plug. The active region is a surface of a semiconductor substrate, and is a portion where an element such as a transistor is formed. The portion of the surface of the semiconductor substrate other than the active region may be an element isolation region. The element isolation region may have a structure including an insulator such as STI (shallow trench isolation), or a PN isolation structure of a conductivity type using a semiconductor. A polysilicon layer may be formed on a surface of the semiconductor substrate. The polysilicon layer forms, for example, the gate electrode of the transistor. The polysilicon layer is not limited to polysilicon, but may be another metal. The first wiring layer and the second wiring layer are made of an electric conductor and are arranged on the surface of the semiconductor substrate. The first wiring layer and the second wiring layer are arranged in this order from the surface of the semiconductor substrate. An interlayer insulating film is arranged between the semiconductor substrate and the first wiring layer, and an interlayer insulating film is arranged between the first wiring layer and the second wiring layer. The contact plug is made of an electrical conductor and electrically connects the semiconductor substrate and the first wiring layer, and connects the polysilicon layer and the first wiring layer. The via plug is made of an electrical conductor and electrically connects the first wiring layer and the second wiring layer. The structure of the wiring is not limited thereto, and a third wiring layer may be arranged between the first wiring layer and the second wiring layer.

Fig. 3A is a schematic top surface view showing an active region, a polysilicon layer, and a contact plug. Fig. 3B is a top surface schematic view showing a state in which a first wiring layer and a via plug are added to the structure shown in fig. 3A. The contact plug is located between the semiconductor substrate and the first wiring layer, but in fig. 3B, the contact plug is drawn on the first wiring layer. The purpose of this is to facilitate understanding of the location of the contact plugs. Fig. 3C is a top surface schematic view showing a state in which a second wiring layer is added to the structure shown in fig. 3B. Also in fig. 3C, a via plug is drawn on the second wiring layer so as to understand the via plug, just like the contact plug shown in fig. 3B. Note that the contact plug and the via plug are similarly drawn in the following figures.

In fig. 3A, the active region includes a region 33, a gate electrode 34, a charge holding unit 38, a gate electrode 35, and a region 40. The region 33 is a region in which the detection diode D1 is arranged. The transfer transistor M1 includes a gate electrode 34, a region 33, and a charge holding unit 38. The charge holding unit 38 is the charge holding unit C1 shown in fig. 2. The reset transistor M2 includes a charge holding unit 38, a gate electrode 35, and a region 40. The other active region includes the amplifying transistor M3 and the selecting transistor M4, and includes a gate electrode 36 of the amplifying transistor M3 and a gate electrode 37 of the selecting transistor M4. The region 41 is a region for supplying an electric potential to a well (well). The well is a semiconductor region in which the corresponding element is provided. For example, the signal charge may be electrons, the transistor may be an N-type transistor, and the well may be a P-type semiconductor region.

In the present embodiment, the detection diode region is defined as an active layer, but may be defined as a semiconductor region having the same conductivity type as that of a well of a transistor using PN isolation.

As shown in fig. 3B, the first wiring layer includes a plurality of wiring lines. The wiring 42 supplies the control signal RES to the gate electrode 35 of the reset transistor M2. The wiring 43 supplies the control signal TX to the gate electrode 34 of the transfer transistor M1. The wiring 44 supplies a control signal SEL to the gate electrode 37 of the selection transistor M4. The wiring 45 is a signal output line electrically connecting the signal wiring to the source/drain region of the selection transistor M4. The wiring 46 is a wiring for supplying a voltage to the well. For example, when the signal charge is an electron, the voltage supplied by the wiring 46 may be Ground (GND). The wiring 47 is a wiring for electrically connecting the charge holding unit 38 and the gate electrode 36 of the amplifying transistor M3. The capacitance component of the charge holding unit C1 includes the wiring 47, the charge holding unit 38, and the gate electrode 36. The wiring 48 is a wiring for supplying voltage to the region 40. For example, when the signal charge is an electron, the voltage supplied by the wiring 48 may be a power supply voltage VDD. The wiring 49 is a wiring for supplying voltage to the region 36-2. For example, when the signal charge is an electron, the voltage supplied by the wiring 49 may be a power supply voltage VDD. Here, the wirings 42 to 46 are global wiring lines commonly provided for a plurality of pixels. The long edges of the wirings 42 to 46 are along the X direction and parallel to each other.

As shown in fig. 3C, the second wiring layer includes a plurality of wiring lines. The power supply wiring 31 is electrically connected to the source/drain region of the amplifying transistor M3 via a via plug, a wiring 48, and a contact plug. A power supply voltage is supplied to the source/drain region of the amplifying transistor M3 through the power supply wiring 31. The power supply wiring 32 is electrically connected to the region 41 via a via plug, a wiring 46, and a contact plug. Gnd is supplied to the region 41 through the power supply wiring 32. The signal wiring 10-1 is a vertical output line. The signal wiring 10-1 is electrically connected to the source/drain region of the selection transistor M4 via a via plug, a wiring 45, and a contact plug. The pixel signal is output from the selection transistor M4 through the signal wiring 10-1. As described above, the wiring 31 that supplies the power supply voltage to the amplifying transistor M3, the power supply wiring 32 that supplies the potential to the well, and the signal wiring 10-1 are formed in the same layer. The long sides of these wiring lines 31, 32 and 10-1 are along the Y direction and parallel to each other.

Hereinafter, a mechanism of deterioration due to radiation found by the present inventors will be described.

It is known that, when radiation is incident on the radiation detector, charges generated in the insulating layer are held in the insulating layer in the radiation detector. Since the electric charges held in the insulating layer fluctuate the electric potential of the channel of the pixel driving transistor and shift the threshold value, fluctuation occurs in the operating point of the pixel driving transistor. Further, parasitic capacitance fluctuates due to the charge held in the insulating layer changing the width of the depletion layer formed as the PN junction portion of the source, drain, or the like of the pixel drive transistor. Further, the electric charge held in the insulating layer has an influence on the potential of the detection diode, and the dark current increases. The increased dark current fluctuates the potential of the charge holding unit. By these operations, the charge held in the insulating layer affects the sensor output and disables the output of the desired signal. Since the held charge increases according to the absorbed dose, the pixel output deviates from the desired output according to the irradiation amount. Therefore, this phenomenon appears as sensor deterioration due to radiation.

According to the findings of the present inventors, the amount of charge held in the insulating layer by irradiation of radiation depends on the electric field of the insulating layer during irradiation of radiation. Further, the degree of characteristic degradation during operation of the sensor depends on the electric field around the held charge. When the electric field is large, the influence of the held charge increases. As a result, the degradation resistance of the detector decreases.

In view of this, the present inventors have noted the layout relationship between the signal wiring 10-1 and the active layer of the amplifying transistor M3, and have found that it is effective to arrange the signal wiring 10-1 and the active layer of the amplifying transistor M3 so as not to overlap each other.

For example, the distance between the active layer of the amplifying transistor M3 and the signal wiring 10-1 will be discussed with respect to the following case: the film thickness between the wiring layers is hundreds of nanometers long, and the pixel pitch is about several micrometers long. When the signal wiring 10-1 is formed at the end of the pixel so as to be away from the active layer of the amplifying transistor M3, the distance can be increased by, for example, about 10 times, compared with the case where the signal wiring 10-1 is formed so as to overlap the active layer of the amplifying transistor M3 in a plan view. Therefore, the electric field between the active layer of the amplifying transistor M3 and the signal wiring 10-1 is reduced by one digit. As a result, the degradation resistance of the detector to radiation is improved by at least one digit. As described above, according to the present embodiment, the electric field between the active layer of the amplifying transistor M3 and the signal wiring 10-1 can be significantly reduced. Therefore, the degradation resistance of the detector to radiation can be improved. Note that an active layer of a transistor can be regarded as an active layer in which a transistor is arranged.

In addition to the above-described charges held in the insulating film, an increase in interface level (interface level) due to the total dose effect or the displacement damage dose effect is also one of the causes of sensor deterioration due to radiation irradiation.

According to the findings of the present inventors, the amount of increase in the interface level due to radiation irradiation depends on the electric field around the interface during irradiation. Since an increase in the interface level is suppressed when the electric field around the interface is small, the deterioration resistance of the sensor can be improved.

In the arrangement in which the signal wiring is formed on the upper portion of the active layer of the transistor, the electric field around the active layer of the transistor easily fluctuates according to the potential of the signal wiring, which varies according to the detected radiation dose. Since the amount of increase in the interface level depends on the electric field around the interface, in the above configuration, the degradation of the pixel changes according to the potential of the signal wiring. That is, the degradation amplitude of the corresponding pixel row changes according to the output image pattern of the sensor, and a phenomenon such as image sticking occurs.

The present embodiment is characterized in that the signal wiring 10-1 is not formed at the upper portion of the active layer of the transistor, that is, the signal wiring 10-1 and the active layer of the transistor do not overlap each other in a plan view, as shown in fig. 3C. Note that since fluctuation of the surrounding electric field due to the potential of the signal wiring is reduced with respect to the active layer of the transistor, the above-described image sticking can be reduced.

Further, the electric charge held in the insulating film has an effect on the potential of the gate channel of the pixel driving transistor, and fluctuates the threshold value of the transistor.

The present embodiment is characterized in that the signal wiring 10-1 is not formed in an upper portion of the gate channel region of the transistor, that is, the signal wiring 10-1 does not overlap with the gate channel region of the transistor in a plan view. According to this characteristic, fluctuation of influence of electric charges held in the insulating film due to the electric potential of the signal wiring can be reduced with respect to the channel of the pixel driving transistor. Therefore, the phenomenon that stripes appear per column or per row due to radiation-induced deterioration found by the present inventors as a problem can be reduced. The mechanism found by the present inventors will be described below.

Further, the width of the depletion layer of the PN junction portion of the diffusion region of the transistor changes due to the influence of the electric charge held in the insulating film. As a result, parasitic capacitance of the pixel transistor fluctuates, and a time constant with respect to driving of the pixel circuit changes. On the other hand, the amount of charge held depends on the electric field applied to the insulating film during radiation irradiation. When the signal wiring is formed at the upper portion of the PN junction portion, the amount of charge held in the insulating film becomes nonuniform for each column in accordance with the difference in potential of the signal wiring for each pixel column in the radiation irradiation period. As a result, in the degraded image, fixed pattern noise per pixel column appears in the sensor output. In this phenomenon, a fine difference of each column, which is not visually identifiable before degradation, is enhanced to be apparent according to the degree of degradation. The reasons for the difference of each column include a difference in parasitic capacitance of the vertical signal line, a difference in layout position of a driving circuit connected to the vertical signal line, a difference in power supply impedance of a circuit driving the vertical signal line, and the like.

Further, according to the findings of the present inventors, the leakage current of the PN junction portion formed as the source and drain of the pixel driving transistor increases according to the charge held in the vicinity of the PN junction portion. As is known in the general CMOS sensor technology, the leakage current deteriorates the imaging performance. The influence of the leakage current is particularly remarkable when the detection diode, the input unit of the amplifying transistor, and the like operate as a floating node.

In view of this, the present embodiment adopts a layout in which the signal wiring 10-1 is not formed in the upper portion of the diffusion region (source/drain region) of the transistor, that is, a layout in which the signal wiring 10-1 and the diffusion region of the transistor do not overlap each other in a plan view. With such a layout, an increase in leakage current due to radiation irradiation can be reduced. Therefore, deterioration of imaging performance due to radiation irradiation can be reduced. Further, asymmetry of deterioration due to radiation due to asymmetry of impedance or the like of the row or column or the driving circuit can be reduced. As a result, radiation resistance can also be improved in terms of periodic noise of the image.

Note that the present embodiment provides a surface-illuminated radiation detector (imaging apparatus) capable of capturing an image by performing radiation illumination from a surface (i.e., front surface side) of a semiconductor substrate in which wiring is formed. The irradiated radiation may pass through the wiring layer and the interlayer insulating film and reach the detection diode.

Further, the radiation detected by the imaging apparatus according to the present embodiment may be ionizing radiation such as X-rays and gamma rays, or may be particle radiation such as alpha rays, beta rays, neutron rays, proton rays, electron rays, heavy ion rays, and meson rays.

Second embodiment

The first embodiment describes a mode in which one signal wiring is provided for one pixel column. The present embodiment will describe a mode in which a plurality of signal wiring lines are provided for one pixel column.

(imaging device configuration)

Fig. 4 is a diagram showing a configuration of an imaging apparatus according to the present embodiment. In each of the columns of the present embodiment, a signal is output from the pixel array 11 to each of the signal wiring lines 10-1 to 10-5. Note that the same unit is repeatedly provided in the array of the pixels 11 as an equivalent circuit, but there may be different portions as a physical layout to correspond to the connected signal wiring lines. The present embodiment will describe a configuration in which five signal wiring lines are provided for one pixel column, but the number of signal wiring lines is not particularly limited as long as at least two signal wiring lines are provided.

(Circuit configuration of pixels)

Fig. 5 is an equivalent circuit diagram showing the circuits of two rows and two columns in the pixel 11 shown in fig. 4. The pixels of the m-th row and the pixels of the m+1th row are connected to the signal wiring line 10-1 and the signal wiring line 10-2, respectively. Similarly, the pixel of the m+2 th row, the pixel of the m+3 th row, and the pixel of the m+4 th row are connected to the signal wiring line 10-3, the signal wiring line 10-4, and the signal wiring line 10-5, respectively. As with the signal wiring 10-1 of the first embodiment, a current source (not shown) is connected to the signal wiring lines 10-2 to 10-5.

When the signal SEL (M) becomes an active level, the selection transistor M4 of the pixel of the M-th row is turned on. Accordingly, a current is supplied from the current source to the amplifying transistor M3 of the pixel of the M-th row. In each pixel of the M-th row, a source follower circuit is formed of a power supply voltage VDD, an amplifying transistor M3, and a current source (not shown) connected to the signal wiring line 10-1. By the formation of the source follower circuit, the amplifying transistor M3 outputs a signal based on the potential of the charge holding unit C1 to the signal wiring line 10-1 via the transistor M4.

Further, when the signal SEL (m+1) becomes an active level, the selection transistor M4 of the pixel of the m+1 th row is turned on. Accordingly, a current is supplied from the current source to the amplifying transistor M3 of the m+1th row. In each pixel of the m+1th row, a source follower circuit is formed of a power supply voltage VDD, an amplifying transistor M3, and a current source (not shown) connected to the signal wiring line 10-2. By the formation of the source follower circuit, the amplifying transistor M3 outputs a signal based on the potential of the charge holding unit C1 to the signal wiring line 10-2 via the transistor M4.

As described above, the pixels of the m-th row and the pixels of the m+1th row are connected to different signal wiring lines, respectively. Further, the pixels of the m+2th row to the pixels of the m+4 th row (not shown) are also connected to different signal wiring lines, respectively.

According to the configuration, acceleration of the detector can be achieved with a plurality of signal wiring lines. In addition, in this case, the signal wiring line is not formed at the upper portion of the active layer of the amplifying transistor either. Thus, the effect of the first embodiment is obtained.

(plan view of the pixel)

Fig. 6A to 6C are schematic diagrams for describing one layout of the pixel 11 shown in fig. 4. The signal wiring lines 10-1 to 10-5 are arranged adjacent to each other and are formed to be sandwiched between the power supply wiring 32 and the power supply wiring 60. Note that the signal wiring lines 10-1 to 10-5 are formed in the same layer as the power supply wiring 31 supplying the power supply voltage to the amplifying transistor M3 and the power supply wiring 32 supplying the potential to the well.

As described above, in the present embodiment, a plurality of signal wiring lines are formed and arranged adjacent to each other. The expression "being arranged adjacent to each other" may mean that, for example, wirings other than the signal wiring lines are not arranged between the signal wiring lines in at least the same wiring layer.

In the present embodiment, the signal wiring line 10-1 is adjacent to the signal wiring line 10-2 and the power wiring line 32, and the signal wiring line 10-5 is adjacent to the signal wiring line 10-4 and the power wiring line 60. Meanwhile, the wiring lines adjacent to the signal wiring lines 10-2, 10-3, and 10-4 on the right and left sides thereof are signal wiring lines. That is, the signal wiring lines are arranged adjacent to each other, so that the symmetry of crosstalk occurring in the signal wiring lines 10-2 to 10-4 can be improved. In addition, symmetry of an electric field occurring around the signal wiring lines 10-2 to 10-4 is also improved. According to this arrangement, for each signal wiring, the non-uniformity of the electric field intensity between adjacent wiring lines can be reduced. Accordingly, the difference in degradation between pixels due to radiation irradiation can be reduced, and fixed pattern noise after degradation due to radiation can be reduced.

Further, the interval between adjacent signal wiring lines is smaller than the interval between the signal wiring line adjacent to the power wiring line and the power wiring line. That is, the interval between adjacent signal wiring lines is smaller than the interval between the power wiring line 32 and the signal wiring line 10-1 and the interval between the power wiring line 60 and the signal wiring line 10-5. As described above, the interval between the power supply wiring and the signal wiring lines is wider than the interval between the signal wiring lines, so that the electric field around the signal wiring lines can be reduced. Therefore, since the influence of the electric charge held in the insulating film on each signal wiring line can be reduced, noise after degradation can be reduced. Further, since an increase in the interface level during radiation irradiation can be reduced for the interface around the signal wiring line, the deterioration resistance to radiation can be improved. Note that the interval between adjacent signal wiring lines may not be constant, and the interval between the power wiring line 32 and the signal wiring line 10-1 may be different from the interval between the power wiring line 60 and the signal wiring line 10-5. In general, the maximum interval among the intervals between adjacent signal wiring lines may be only smaller than both the interval between the power supply wiring 32 and the signal wiring line 10-1 and the interval between the power supply wiring 60 and the signal wiring line 10-5.

Third embodiment

A third embodiment of the invention is shown in fig. 7. In fig. 7, the description of the same components as those of fig. 6A to 6C is the same. Fig. 7 is a diagram showing all active areas, polysilicon layer, contact plugs, via plugs, first wiring layer, and second wiring layer. The structure of each layer is understood with reference to other embodiments, and thus partial illustrations of each layer will be omitted.

The connection wiring 70 is connected to the source 71 of the selection transistor, is formed in a layer different from that of the signal wiring lines 10-1 to 10-5, and is connected to the signal wiring lines 10-1 to 10-5 via a via plug (hole) 72. A connection wiring 70 is provided for each amplifying transistor M3. Further, the connection wiring 70 is laid out so as to be substantially orthogonal to at least any one of the signal wiring lines 10-1 to 10-5 in a plan view.

In the present embodiment, the asymmetry of parasitic capacitance between the connection wiring 70 connected to the amplifying transistor and the respective signal wiring lines 10-1 to 10-5 can be reduced. Therefore, the difference in degradation resistance of each pixel row can be reduced, and fixed pattern noise after radiation irradiation can be reduced.

The connection wiring 70 has a wide portion 74 at a portion thereof overlapping the signal wiring lines 10-1 to 10-5, the wide portion 74 has a constant width larger than that of the other portion, and the through hole 72 is provided at a position where the wide portion 74 and the signal wiring line outputting the pixel signal overlap each other. Thus, the positions where the through holes 72 are provided differ depending on the pixels. However, the planar layout of the individual pixels in the pixel array may be formed in substantially the same shape except for the through holes 72. In the present embodiment, the through holes 72 are arranged at different periods on the same pixel column on the basis of fixed repetition. In the present embodiment, the output of the amplifying transistor of the m-th row is connected to the signal wiring line 10-1 via the via hole 72, and the output of the amplifying transistor of the m+1th row is connected to the signal wiring line 10-2 through the via hole 73. That is, the pixel layout can be changed according to the difference in the read signal wiring lines using only the via holes. Therefore, symmetry of coupling with other wiring lines in the charge holding unit, the amplifying transistor, and the like can be improved for each pixel. Therefore, the difference in degradation resistance between the respective pixels can be reduced, and the fixed pattern noise after irradiation of radiation can be reduced.

In the present embodiment, the overlapping area of the portions where the signal wiring lines 10-1 to 10-5 and the connection wiring line 70 cross each other in a plan view may have substantially the same value at the intersection of all pixels. Thus, the period asymmetry of each pixel row can be reduced. Therefore, the degree of variation in the degradation resistance per line can be further reduced, and the fixed pattern noise after irradiation of radiation can be reduced.

Fourth embodiment

A pixel layout according to a fourth embodiment of the present invention is shown in fig. 8A to 8C. In this embodiment, a power supply wiring 31 that supplies the drain potential of the amplifying transistor, a power supply wiring 32 that supplies the well potential, a power supply wiring 80 that supplies the drain potential of the reset transistor M2, and a contact 81 that supplies the well potential to the semiconductor substrate are provided. In the present embodiment, the power supply wiring 32 is arranged to be sandwiched between the power supply wiring 31 and the power supply wiring 80.

In general, in the NMOS type pixel configuration, the well potential is a low potential such as a ground potential, and the drain potential and the reset potential of the amplifying transistor are high potentials. In addition, in the case of the optical fiber,

in the reset state, the potential of the pixel signal wiring becomes high to follow the drain potential of the reset transistor. In the present embodiment, the power supply wiring 80 (of the same pixel) and the power supply wiring 31 (of an adjacent pixel) are arranged adjacent to the signal wiring 10-1. By arranging the signal wiring 10-1 and the power wiring 80 adjacent to each other and arranging the signal wiring 10-1 and the power wiring 31 adjacent to each other, an electric field in a lateral direction around the signal wiring 10-1 can be reduced as compared with a layout in which the signal wiring 10-1 and the power wiring 32 are arranged adjacent to each other. Therefore, the influence of the electric charges held in the insulating film can be reduced, and noise after degradation can be reduced.

Fifth embodiment

A fifth embodiment of the present invention will be described using fig. 9A to 9C.

The fifth embodiment is different from the fourth embodiment in the arrangement order of the power supply wirings 31, 32, and 80. In the present embodiment, the power supply wiring 31, the power supply wiring 80, and the power supply wiring 32 are arranged in this order, and the power supply wiring 80 is arranged to be sandwiched between the power supply wiring 31 and the power supply wiring 32. Accordingly, capacitive coupling through parasitic capacitance between the power supply wiring 80 and the signal wiring 10-1 can be reduced. In the power supply wiring 80, in some cases, voltage fluctuation occurs instantaneously during the reset operation of the sensor. In this embodiment, by the shielding operation of the power supply wiring 32, the signal wiring 10-1 can be shielded from the voltage fluctuation of the power supply wiring 80. Therefore, the instantaneous fluctuation of the electric field in the lateral direction around the signal wiring can be reduced. Therefore, fluctuations in the pixel output after degradation depending on the voltage state can be reduced.

Sixth embodiment

The sixth embodiment has a configuration in which the above-described first to fifth embodiments are combined together. The present embodiment will be described with reference to fig. 10A to 10C.

In the present embodiment, no signal wiring is formed on the upper portion of the active layer of the amplifying transistor. Further, the signal wiring includes a plurality of signal wiring lines, and the signal wiring lines are arranged adjacent to each other. Further, connection wirings orthogonal to any of the signal wiring lines are provided. All pixels of the pixel array have the same layout in plan view except for the through holes connecting the connection wirings and the signal wiring lines. In all the signal wiring lines, the areas of the portions where the signal wiring lines and the connection wirings are orthogonal to each other are the same in a plan view. Three power supply wiring lines are provided.

According to this configuration, high-speed reading can be realized in the sensor that suppresses the influence of deterioration due to radiation on image quality. Thus, a detector capable of acquiring image data at a high frame rate can be manufactured.

Seventh embodiment

The present embodiment will describe an example in which imaging acceleration is achieved while an effect of improving radiation resistance is obtained. Fig. 11A to 11C are schematic diagrams for describing a pixel layout according to the present embodiment. Here, an example in which the pixel pitch is 2 μm is shown. The description of the reference numerals of the respective components is the same as that of the above-described embodiments. Here, the wiring has an L/S (line and space) of 0.2 μm, and the amplifying transistor has a channel width of 0.4 μm. The signal wiring lines 10-1 to 10-3 are arranged so as not to overlap with the channels or source/drains of the amplifying transistors. Therefore, in the present embodiment, the signal wiring line is arranged at the upper portion of the detection diode D1 (region 33). Further, the power supply wiring 110 that drives the pixel is arranged in an upper portion of a region in which transistors constituting the pixel circuit are arranged. The power wiring 110 is shown as a single one in fig. 11C, but may include a plurality of power wiring lines. For example, a power supply wiring 31 that supplies the drain potential of the amplifying transistor, a power supply wiring 32 that supplies the well potential, and a power supply wiring 80 that supplies the drain potential of the reset transistor M2 are arranged in the upper portion of the region in which the transistors are arranged (see fig. 9A to 9C and fig. 10A to 10C).

In the present embodiment, the number of signal wiring lines per pixel pitch may be at least three when performing layout according to the present invention. Thus, radiation resistance and acceleration can be achieved at the same time.

Eighth embodiment

The eighth embodiment will describe the following modes: the amplifying transistor is arranged to be included in the radiation detecting element in a plan view, so that the sensitivity of the detector can be improved.

In the present embodiment, the radiation detection element D1 (region 33) is defined by the active layer 120 and the frame-like passive layer 121 provided for each unit pixel, as shown in fig. 12. The passive layer 121 has a pixel isolation structure formed around the radiation detection elements D1, and the plurality of radiation detection elements D1 are isolated by the passive layer 121. The active region 33 of the radiation detection element D1 is located inside the region surrounded by the inactive layer 121 having the pixel isolation structure.

In the present embodiment, the charge holding unit 38 is arranged to be surrounded by the active region 33 of the detection element D1. Furthermore, the gate electrode 36 of the amplifying transistor is similarly arranged to be surrounded by the active region 33 of the detection element D1. More specifically, both the charge holding unit and the amplifying transistor are arranged in a region inside the passive layer 121 (having a pixel isolation structure) and surrounded by the active region 33. The expression "region surrounded by active region" means a region in which the active region exists in substantially all directions. The entire periphery of the region may be surrounded by one active region in plan view, or a part of the entire periphery may be an isolation region. By employing such an arrangement, the charge holding unit 38 and the gate electrode 36 of the amplifying transistor can be arranged adjacent to each other. As a result, the parasitic capacitance of the charge holding unit can be reduced. Thus, high sensitivity of the detector can be obtained.

With reference to fig. 12, the present embodiment describes a mode in which the detection element is defined by the active layer. However, even if the detection element is defined according to the conductivity type or concentration of the semiconductor region, the same effect can be obtained.

Ninth embodiment

A ninth embodiment of the present invention will describe a mode of using a pixel circuit system called a three-transistor system in a CMOS area sensor technology in which a transfer transistor is not provided and a radiation detection element and a charge holding unit are electrically connected to each other. In the present embodiment, the amplifying transistor is arranged to be surrounded by the detection diode in a plan view, so that the sensitivity of the detector can be improved.

In the present embodiment, the radiation detection elements of the unit pixels are defined by the active layer 33 and the passive layer 121, and are isolated from the radiation detection elements of the adjacent pixels by the frame-like passive layer 121, as shown in fig. 13. In the present embodiment, the wiring 131 connects the extraction unit 132 for extracting electric charges from the radiation detection element and the gate electrode 36 of the amplifying transistor.

In the present embodiment, the gate electrode 36 of the amplifying transistor is arranged to be surrounded by the active layer 33 of the radiation detecting element, so that a layout in which the extracting unit 132 of the radiation detecting element and the gate electrode 36 of the amplifying transistor are close to each other can be obtained. Therefore, the wiring 131 connecting the extraction unit 132 and the gate electrode 36 can be shortened. According to this arrangement, it is possible to reduce the parasitic capacitance of the radiation detection element and increase the conversion gain. As a result, high sensitivity of the detector is achieved.

Further, the present invention is not affected by degradation of the transfer transistor M1 due to radiation, as compared with a radiation detector having pixels each including the transfer transistor M1. Therefore, the deterioration resistance to radiation can be improved.

With reference to fig. 13, the present embodiment describes a mode in which the detection element is defined by the active layer. However, even if the detection element is defined according to the conductivity type or concentration of the semiconductor region, the same effect can be obtained.

Further, even in a mode in which a plurality of signal wiring lines are arranged in one pixel column, the wiring 131 connecting the charge holding unit and the gate of the amplifying transistor can be shortened. Thus, the same effect is obtained.

Tenth embodiment

The tenth embodiment will describe a pattern of relative positions between connection wirings orthogonal to signal wiring lines and between layout of pixel isolation and layout of signal wiring lines arranged in transitional symmetry on a pixel-by-pixel basis.

As shown in fig. 14, in the present embodiment, the pixel 11 has a connection wiring 141 that connects the amplifying transistor and the signal wiring line. The connection wiring 141 is provided for each amplifying transistor, and is formed in a metal layer different from the signal wiring lines, orthogonal to at least any of the signal wiring lines. The connection wiring and the signal wiring line are connected to each other via a via hole. Starting from the contact for connecting the connection wiring and the transistor, the connection wiring extends in a direction of a signal wiring line which is arranged collectively on only one direction side (right side in fig. 14) of the pixel in a plan view. Note that the connection wiring 141 may have a wide portion at a portion thereof overlapping with the signal wiring line, the wide portion having a constant width larger than that of the other portion (see fig. 7).

As shown in fig. 14, the signal wiring lines 10-1 to 10-6 of one pixel column are arranged at the same period as the pixel pitch in the pixel array 13. In this case, in the repetition period, the center of the region in which the plurality of signal wiring lines are arranged is shifted substantially half-phase (half phase) with respect to the center of the detection diode region. With such an arrangement, the distance between the extraction position of the detection diode and the vertical signal line can be maintained, and the electric field in the insulating film can be reduced. Thus, radiation resistance can be improved.

Further, the pixels 11 have the same layout in plan view except for the through holes, and only the through holes are arranged on the same pixel column at different periods on the basis of fixed repetition. Further, in the present embodiment, the overlapping area of the portions where the signal wiring lines 10-1 to 10-6 and the connection wiring 141 cross each other in a plan view may have substantially the same value at the intersection of all pixels. According to this arrangement, in addition to the signal wiring lines, symmetry can be improved. Therefore, after the radiation irradiation, the difference in degradation resistance of each pixel can be further reduced.

Further, in the present embodiment, the interval between adjacent signal wiring lines is smaller than the interval between the signal wiring line adjacent to the power wiring line and the power wiring line. That is, the interval between adjacent signal wiring lines is smaller than the interval between the signal wiring line 10-1 and the power supply wiring line 31 of the same pixel and the interval between the signal wiring line 10-6 and the power supply wiring line 31 of the adjacent pixel. As described above, the interval between the power supply wiring and the signal wiring lines is wider than the interval between the signal wiring lines, so that the electric field around the signal wiring lines can be reduced. Therefore, since the influence of the electric charges held in the insulating film on the respective signal wiring lines is reduced, noise after degradation can be reduced. Further, since an increase in the surface level during radiation irradiation is reduced for the interface around the signal wiring line, the deterioration resistance to radiation can be improved. Note that the interval between adjacent signal wiring lines may not be constant, and the interval between the power wiring line 31 and the signal wiring line 10-1 (of the same pixel) and the interval between the power wiring line 31 and the signal wiring line 10-6 (of the adjacent pixel) may be different. In general, the maximum interval among the intervals between adjacent signal wiring lines may be only smaller than the interval between the power wiring line 31 (of the same pixel) and the signal wiring line 10-1 and the interval between the power wiring line 31 (of the adjacent pixel) and the signal wiring line 10-6. Note that this embodiment describes a configuration in which six signal wiring lines are arranged for one pixel column. However, the number of signal wiring lines is not particularly limited as long as at least two signal wiring lines are arranged.

Eleventh embodiment

The above-described first to tenth embodiments may be arbitrarily combined together without impeding their effects. With reference to fig. 15, an eleventh embodiment will describe a configuration in which the above-described embodiments are combined together.

In the present embodiment, no signal wiring is formed on the upper portion of the active layer of the amplifying transistor. Further, the signal wiring includes a plurality of signal wiring lines, and the signal wiring lines are arranged adjacent to each other. Further, connection wirings orthogonal to any of the signal wiring lines are provided. The pixels of the pixel array have the same layout in plan view except for the through holes connecting the connection wirings and the signal wiring lines. The area of the portion where the signal wiring lines and the connection wirings are orthogonal to each other in a plan view is the same in all the signal wiring lines. Three power supply wiring lines are provided. The power supply wiring line is arranged to overlap with the amplifying transistor in a plan view. The signal wiring lines are arranged so as not to overlap the amplifying transistors, but at least three signal wiring lines are arranged so as to overlap the active layers of the radiation detecting elements. The amplifying transistor is arranged inside the pixel isolation structure in a plan view and employs pixel circuitry called a three transistor system. Starting from the contact for connecting the connection wiring and the transistor, the connection wiring extends only in the direction of the signal wiring lines which are arranged collectively on the right side of the pixel in a plan view.

It can be easily understood that the first to tenth embodiments are combined in a manner different from that described above. For example, a four transistor system (first embodiment) using transfer transistors may be employed instead of the three transistor system. Further, instead of the configuration in which the power supply wiring 31, the power supply wiring 32, and the power supply wiring 80 are arranged in this order, a configuration in which the power supply wiring 31, the power supply wiring 80, and the power supply wiring 32 are arranged in this order may be adopted (fifth embodiment).

According to the present embodiment, high-speed reading can be realized in a sensor that suppresses the influence of deterioration due to radiation on image quality. Thus, a detector capable of acquiring image data at a high frame rate can be manufactured.

Twelfth embodiment

Referring to fig. 16, a radiation imaging apparatus 801 in which a radiation detector according to any one of the first to eleventh embodiments described above is incorporated and a radiation imaging system 800 using the same will be described.

The radiation imaging system 800 is configured to electrically capture an optical image formed of radiation and obtain an electrical radiation image (i.e., radiation image data). The radiation imaging system 800 includes, for example, a radiation imaging apparatus 801, an exposure control unit 802, a radiation source 803, and a computer 804. The radiation imaging system 800 is capable of displaying the captured radiation image on a display device (not shown) or transmitting radiation image data to the outside via a communication device (not shown). The radiation imaging system 800 may be suitably used in fields such as medical image diagnosis, nondestructive inspection, and the like.

The radiation source 803 for performing radiation irradiation starts radiation irradiation according to an exposure instruction from the exposure control unit 802. The radiation emitted from the radiation source 803 is irradiated to the radiation imaging apparatus 801 after passing through a subject not shown. The radiation source 803 stops radiation emission according to a stop instruction from the exposure control unit 802.

The radiation imaging apparatus 801 includes the radiation detector 100 according to any one of the first to eleventh embodiments described above, a control unit 805 for controlling the radiation detector 100, and a signal processing unit 806 for processing a signal output from the radiation detector.

For example, when the signal output from the radiation detector 100 is an analog signal, the signal processing unit 806 can perform a/D conversion on the analog signal and output the converted signal as radiation image data to the computer 804. Further, for example, the signal processing unit 806 may generate a stop signal for stopping irradiation of radiation from the radiation source 803 based on a signal output from the radiation detector 100. A stop signal is supplied to the exposure control unit 802 via the computer 804, and the exposure control unit 802 transmits a stop instruction to the radiation source 803 in response to the stop signal.

The control unit 805 may be constituted by, for example, a PLD (programmable logic device) such as an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), a general-purpose computer containing a program, or a combination of all or some of the foregoing components.

Further, the signal processing unit 806 is shown as being arranged in the control unit 805 or as part of the function of the control unit 805, but is not limited to this configuration. The control unit 805 and the signal processing unit 806 may be configured to be separate from each other. Further, the signal processing unit 806 may be disposed separately from the radiation imaging apparatus 801. For example, the computer 804 may have a function of a signal processing unit 806. Accordingly, the signal processing unit 806 may be included in the radiation imaging system 800 as a signal processing apparatus that processes a signal output from the radiation imaging apparatus 801.

The computer 804 may perform control of the radiation imaging apparatus 801 and the exposure control unit 802, or perform processing to receive radiation image data from the radiation imaging apparatus 801 and display the received data as a radiation image. Further, the computer 804 may function as an input unit used by a user to input conditions for capturing a radiographic image.

As an example of the sequence, when the user turns on the exposure switch, the exposure control unit 802 having the exposure switch gives an exposure instruction to the radiation source 803, and gives a start notification notifying the start of radiation emission to the computer 804. The computer 804 that received the start notification notifies the control unit 805 of the radiation imaging apparatus 801 of the start of radiation irradiation in response to the start notification. According to this operation, the control unit 805 causes a signal corresponding to the incident radiation to be generated in the radiation detector 100.

In the radiation imaging apparatus and the radiation imaging system using the radiation imaging apparatus of the present embodiment, even if the radiation detector is cooled during imaging, excessive force applied to the thinner and mechanically weaker semiconductor layer due to thermal shrinkage imbalance of the respective units can be effectively prevented. Therefore, a radiation imaging apparatus which has excellent reliability and durability and is capable of obtaining a high-quality radiation image can be realized and practically used in various fields such as medical and industrial fields.

Thirteenth embodiment

As a radiation imaging system including the radiation detector according to any one of the first to eleventh embodiments described above, a Transmission Electron Microscope (TEM) system will be described with reference to a schematic configuration diagram of fig. 17. The apparatus EQP used as a transmission electron microscope has an electron beam source 1002 (electron gun), an irradiation lens 1004, a vacuum chamber 1001 (barrel), an objective lens 1006, a magnifying lens system 1007, and a radiation detector 1100.

An electron beam 1003, which is radiation emitted from an electron beam source 1002 (electron gun) serving as a radiation source, is focused by an irradiation lens 1004 and irradiated to a sample S held by a sample holder as an analysis target. The space through which the electron beam 1003 passes is defined by a vacuum chamber 1001 (drum) provided in the apparatus EQP. The space is kept in a vacuum state.

The electron beam 1003 passing through the sample S is amplified by the objective lens 1006 and the magnifying lens system 1007, and forms an image on the light receiving surface of the radiation detector 1100. An electron optical system for irradiating the sample S with electron rays is referred to as an irradiation optical system, and an electron optical system for forming an electron ray passing through the sample S into an image on a light receiving surface of the radiation detector 1100 is referred to as an image forming optical system.

The electron beam source 1002 is controlled by an electron beam source control device 1011. The illumination lens 1004 is controlled by an illumination lens control apparatus 1012. The objective lens 1006 is controlled by an objective lens control device 1013. The magnifying lens system 1007 is controlled by a magnifying lens system control apparatus 1014. The control mechanism 1005 of the sample holder is controlled by a holder control device 1015 which controls the drive mechanism of the sample holder.

The radiation detector 1100 detects the electron beam 1003 that has passed through the sample S. The output signal from the radiation detector 1100 is processed by a signal processing apparatus 1016 and an image processing apparatus 1018 to generate an image signal. The generated image signal (transmission electronic image) is displayed on an image display monitor 1020 and an analysis monitor 1021 serving as display devices.

In the Transmission Electron Microscope (TEM) system of the present embodiment including the radiation detector according to any one of the first to eleventh embodiments, even if the radiation detector is cooled during imaging, excessive force applied to the thinner and mechanically weaker semiconductor layer due to thermal shrinkage imbalance of the respective units can be effectively prevented. Accordingly, a Transmission Electron Microscope (TEM) system having good reliability and durability and capable of obtaining a high-quality captured image can be realized.

Note that the electron microscope according to the present embodiment is not limited to the Transmission Electron Microscope (TEM) given as an example, but may be, for example, a Scanning Electron Microscope (SEM) or a Scanning Transmission Electron Microscope (STEM). In addition, an electron microscope including a processing function such as ion beam milling and Ion Beam Induced Deposition (IBID) or a dual beam electron microscope such as a FIB-SEM including a Focused Ion Beam (FIB) may be used as such.

While the invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims

1. A radiation detector, comprising:

a pixel array in which pixels are arranged in a matrix shape, each pixel having a radiation detection element configured to convert radiation into electric charge and an amplification transistor configured to amplify a signal from the radiation detection element and output the amplified signal; and

signal wiring provided for each pixel column,

wherein the signal wiring does not overlap with an active layer in which the amplifying transistor is arranged in a plan view.

2. The radiation detector according to claim 1, wherein the active layer in which the amplifying transistor is arranged is a channel region of the amplifying transistor.

3. The radiation detector according to claim 1, wherein the active layer in which the amplifying transistor is arranged is a diffusion region of the amplifying transistor.

4. The radiation detector according to claim 1, wherein the signal wiring includes at least two signal wiring lines arranged for one pixel column.

5. The radiation detector according to claim 4,

wherein the signal wiring line and the wiring line for supplying the power supply voltage to the amplifying transistor are formed in the same layer

Wherein the signal wiring lines are arranged adjacent to each other.

6. The radiation detector according to claim 4,

wherein a connection wiring provided for each amplifying transistor and orthogonal to at least any of the signal wiring lines is provided,

wherein the signal wiring line and the connection wiring line are formed in different layers and are electrically connected to each other via a via hole, and

wherein the planar layout of the pixels is substantially identical in shape except for the through holes.

7. The radiation detector according to claim 6, wherein an overlapping area of a portion where the signal wiring and the connection wiring intersect each other has substantially the same value at all intersection points.

8. The radiation detector according to claim 4,

wherein the pixel has a power supply wiring arranged in parallel with the signal wiring line, and

wherein an interval between adjacent signal wiring lines is smaller than an interval between a signal wiring line adjacent to the power wiring line and the power wiring line.

9. The radiation detector according to claim 8,

wherein the pixel includes a reset transistor, and

wherein the power supply wiring includes a first power supply wiring that supplies a drain potential of the amplifying transistor, a second power supply wiring that supplies a well potential, and a third power supply wiring that supplies a drain potential of the reset transistor.

10. The radiation detector according to claim 9, wherein the second power supply wiring is arranged between the first power supply wiring and the third power supply wiring.

11. The radiation detector according to claim 9, wherein the third power supply wiring is arranged between the first power supply wiring and the second power supply wiring.

12. The radiation detector according to claim 9, wherein the first power supply wiring, the second power supply wiring, and the third power supply wiring are arranged at an upper portion of a region where the amplifying transistor is arranged.

13. The radiation detector according to claim 1,

wherein the signal wiring is arranged at an upper portion of a region where the radiation detection element is arranged, and

wherein the signal wiring includes at least three signal wiring lines for each pixel column.

14. The radiation detector according to claim 1, wherein the radiation detector is of a surface irradiation type.

15. A radiation imaging system comprising:

the radiation detector according to claim 1; and

and a signal processing unit that processes a signal output from the radiation detector.

16. A radiation imaging system comprising:

the radiation detector according to claim 1; and

a source of radiation.