CN117082964A - Preparation method of laminated superconducting structure, laminated superconducting structure and quantum chip - Google Patents
Preparation method of laminated superconducting structure, laminated superconducting structure and quantum chip Download PDFInfo
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- CN117082964A CN117082964A CN202311283237.0A CN202311283237A CN117082964A CN 117082964 A CN117082964 A CN 117082964A CN 202311283237 A CN202311283237 A CN 202311283237A CN 117082964 A CN117082964 A CN 117082964A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 250
- 229910052751 metal Inorganic materials 0.000 claims abstract description 104
- 239000002184 metal Substances 0.000 claims abstract description 104
- 239000011241 protective layer Substances 0.000 claims abstract description 68
- 238000005530 etching Methods 0.000 claims abstract description 50
- 239000000463 material Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 7
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 20
- 229910052782 aluminium Inorganic materials 0.000 claims description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 13
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 7
- 229910052731 fluorine Inorganic materials 0.000 claims description 7
- 239000011737 fluorine Substances 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 239000002253 acid Substances 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 14
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000004132 cross linking Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/80—Constructional details
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- Manufacturing & Machinery (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
The application discloses a preparation method of a laminated superconducting structure, the laminated superconducting structure and a quantum chip, and belongs to the field of quantum chip preparation. The preparation method of the laminated superconducting structure comprises the following steps: providing a substrate with a first superconducting metal layer on the surface; forming a protective layer on the first superconducting metal layer; forming a dielectric layer covering the protective layer on the first superconducting metal layer; etching the dielectric layer by taking the protective layer as an etching stop layer to form an opening exposing the protective layer; etching the protective layer in a mode that the etching selection ratio of the protective layer relative to the first superconducting metal layer is larger than 1 so as to expose the first superconducting metal layer; and forming a second superconducting metal layer connected with the first superconducting metal layer on the dielectric layer and in the opening. By the mode, when the superconducting layer is manufactured by using materials such as tantalum and tin in the manufacturing process of the quantum chip laminated structure, the superconducting layer is effectively prevented from being broken due to the fact that the superconducting layer is etched when the dielectric layer is etched.
Description
Technical Field
The application belongs to the technical field of quantum chip preparation, and particularly relates to a preparation method of a laminated superconducting structure, the laminated superconducting structure and a quantum chip.
Background
In quantum chips, the prior art two-dimensional planar wiring technology can no longer meet the current bit development requirements due to the complex coupling between the qubits and the need for high-level interconnects. In order to solve the problem of complex wiring in quantum chips, stacked superconducting structures are gradually introduced; stacked superconducting structures refer to the introduction of two or more mutually parallel metal layers into a quantum chip, dividing the superconducting metal layers into a plurality of horizontal layers.
The laminated superconducting structure process generally needs to fill low-loss dielectric layer materials between superconducting layers, the laminated superconducting layers are connected through holes etched in the dielectric layers, loss is caused by the dielectric layers, a tantalum film, a tin film and the like of the superconducting layers with better performance can be selected, compared with a traditional aluminum film, the quality factors and the coherence time of the tantalum film and the tin film are respectively produced by the aluminum film, the dielectric layers are generally produced by materials such as silicon nitride, germanium and monocrystalline silicon, fluorine-based plasma etching is generally adopted in the process of etching the dielectric layers, but fluorine-based plasma can also etch the superconducting layers produced by the tantalum film and the tin film, so that the etching end point is not easy to control, and the superconducting layers can be etched to cause open circuit in the process of etching the dielectric layers.
Disclosure of Invention
The application aims to provide a preparation method of a laminated superconducting structure, the laminated superconducting structure and a quantum chip, so as to solve the problem that a superconducting layer is easy to etch to cause open circuit when a fluorine-based ion etches a dielectric layer in the process of manufacturing the laminated superconducting structure of the quantum chip in the prior art, and protect the superconducting layer from being affected by etching under the condition of ensuring that the dielectric layer is well etched.
In order to solve the above technical problems, the present application provides a method for preparing a stacked superconducting structure, including:
providing a substrate with a first superconducting metal layer on the surface;
forming a protective layer on the first superconducting metal layer;
forming a dielectric layer coating the protective layer on the first superconducting metal layer;
etching the dielectric layer by taking the protective layer as an etching stop layer to form an opening exposing the protective layer;
etching the protective layer in a mode that the etching selection ratio of the protective layer relative to the first superconducting metal layer is larger than 1 so as to expose the first superconducting metal layer;
and forming a second superconducting metal layer connected with the first superconducting metal layer on the dielectric layer and in the opening.
Preferably, the step of forming a protective layer on the first superconducting metal layer includes:
forming a first photoresist layer on the first superconducting metal layer;
photoetching the first photoresist layer to form a through hole exposing part of the first superconducting metal layer;
depositing a protective layer on the first superconducting metal layer through the through hole;
and removing the first photoresist layer.
Preferably, the through hole is in a truncated cone shape, and a dimension of one end, close to the first superconducting metal layer, is larger than a dimension of one end, far away from the first superconducting metal layer.
Preferably, the step of etching the dielectric layer with the protective layer as an etching stop layer to form an opening exposing the protective layer includes:
forming a second photoresist layer on the dielectric layer;
forming a window exposing the dielectric layer in the area of the second photoresist layer opposite to the protective layer by utilizing a photoetching mode;
etching the dielectric layer through the window to form the opening;
and removing the second photoresist layer.
Preferably, the window and the opening are the same size;
the size of the opening is not larger than the size of the protective layer.
Preferably, the etching of the dielectric layer adopts a fluorine-based plasma etching mode.
Preferably, the material of the protective layer is aluminum;
the material of the first superconducting metal layer is tantalum or tin;
and etching to remove the protective layer by using a mixed acid corrosive liquid.
Preferably, the step of forming a second superconducting metal layer connected to the first superconducting metal layer on the dielectric layer and in the opening includes:
etching an oxide layer on the first superconducting metal layer;
and forming a second superconducting metal layer connected with the first superconducting metal layer on the dielectric layer and in the opening.
The application also provides a laminated superconducting structure, which is manufactured by adopting the manufacturing method of the laminated superconducting structure in any one of the previous embodiments.
The application also provides a quantum chip which comprises the laminated superconducting structure.
Compared with the prior art, the protective layer is added between the dielectric layer and the first superconducting metal layer in advance, the protective layer is not affected by etching when the dielectric layer is etched, and the protective layer can be removed in other process modes; therefore, the problem that in the traditional process, the etching end point is difficult to control when the dielectric layer is etched is avoided, the first superconducting metal layer is protected, and the preparation of the quantum chip laminated wiring structure is better realized.
Drawings
FIG. 1 is a schematic diagram of a stacked superconducting structure of a quantum chip according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a method for preparing a quantum chip stacked superconducting structure according to an embodiment of the present application;
fig. 3, fig. 4, and fig. 5 are schematic views of steps of a preparation method of a quantum chip stacked superconducting structure according to an embodiment of the present application.
Reference numerals illustrate: 1-substrate, 2-first superconducting metal layer, 3-first photoresist layer, 31-through hole, 4-protective layer, 5-dielectric layer, 51-opening, 6-second photoresist layer, 61-window, 7-second superconducting metal layer.
Detailed Description
Specific embodiments of the present application will be described in more detail below with reference to the drawings. Advantages and features of the application will become more apparent from the following description and claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the application.
In the description of the present application, it should be understood that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
As disclosed in the background art, in the field of quantum chip fabrication technology, due to the complex coupling between qubits and the need for high interconnection, stacked superconducting structures are increasingly introduced for this purpose, i.e., a plurality of mutually parallel metal layers are introduced into a quantum chip, dividing the superconducting metal layers into a plurality of horizontal layers; in the manufacturing process, due to the material characteristics of the superconducting layer and the dielectric layer, when the dielectric layer is etched, the superconducting layer is possibly etched to cause disconnection due to the fact that the etching end point is not easy to control.
Referring to fig. 2, in order to solve the above-mentioned problems, the present application provides a method for preparing a stacked superconducting structure, a stacked superconducting structure and a quantum chip, wherein a protective layer 4 is added between a dielectric layer 5 and a first superconducting metal layer 2, and the protective layer 4 is not affected by etching when the dielectric layer 5 is etched, so as to protect the first superconducting metal layer 2; and, before the subsequent process, the protective layer 4 can be completely removed by other technical means, so as to realize the preparation of the quantum chip laminated superconducting structure. Wherein the first superconducting metal layer 2 is provided with structures such as qubits, resonant cavities and the like, and the second superconducting metal layer 7 is provided with structures such as control lines and the like.
Referring to fig. 1, an embodiment of the present application provides a method for preparing a stacked superconducting structure, which can be used for preparing a stacked superconducting structure, and the method for preparing a stacked superconducting structure controls an etching endpoint when etching a dielectric layer 5, thereby avoiding etching a bottom superconducting layer and preventing a first superconducting metal layer 2 from being broken.
The preparation method of the laminated superconducting structure provided by the embodiment of the application comprises the following steps:
s1: a substrate 1 having a first superconducting metal layer 2 on a surface thereof is provided.
Specifically, a base, which may be a substrate 1 sheet such as a silicon substrate 1, a silicon dioxide substrate 1 or a sapphire substrate 1, is first provided, and a first superconducting metal layer 2 is formed on the substrate 1 by a plating or deposition or mounting process or the like.
The first superconducting metal layer 2 on the surface of the substrate 1 is subjected to photoetching to form sub-devices such as a transmission line and a resonator, and a part of a region which is separated from the sub-devices is reserved as a connection region with other superconducting metal layers.
S2: a protective layer 4 is formed on the first superconducting metal layer 2.
Referring to fig. 3, the step of forming the protective layer 4 on the first superconducting metal layer 2 further includes:
forming a first photoresist layer 3 on the first superconducting metal layer 2;
photoetching the first photoresist layer 3 to form a through hole 31 exposing part of the first superconducting metal layer 2;
depositing a protective layer 4 on the first superconducting metal layer 2 through the via 31;
the first photoresist layer 3 is removed.
Specifically, in the prior art, the etching endpoint is not easy to control when the dielectric layer 5 is etched, and the first superconducting metal layer 2 is easy to continue to be etched after the dielectric layer 5 is etched, so that the first superconducting metal layer 2 is etched and shorted; thus, in the embodiment of the present application, a protection layer 4 is provided, in the etching direction, the protection layer 4 is located between the first superconducting metal layer 2 and the dielectric layer 5, so as to protect the first superconducting layer from being etched after etching the dielectric layer 5, and the material of the protection layer 4 may be aluminum.
In addition, the steps to achieve the formation of the protective layer 4 at the corresponding position on the first superconducting metal layer 2 are as follows:
first, a first photoresist layer 3 is deposited on a first superconducting metal layer 2, a through hole 31 is formed on the first photoresist layer 3 through exposure and development, then an aluminum film is deposited on the first superconducting metal layer 2 through the through hole 31, and finally the first photoresist layer 3 is soaked and dissolved by an organic solvent, wherein the aluminum film is a protective layer 3.
It is noted that the first photoresist layer 3 is a negative photoresist, the negative photoresist exposure area is insoluble in the developing solution, and the negative photoresist exposure causes the photoresist to be crosslinked, so that the exposure intensity of the upper layer area of the first photoresist layer 3 is high, the crosslinking is strong, the exposure intensity of the lower layer is low, and the crosslinking is weak, so that the upper layer area and the lower layer area of the first photoresist layer 3 have different dissolution speeds for the developing solution, and the solubility of the first photoresist layer 3 gradually becomes strong from top to bottom, so that a structure with narrow upper part and wide lower part is formed after the first photoresist layer 3 is developed, and stripping is facilitated.
The through hole 31 formed by exposing and developing the first photoresist layer 3 is specifically in a truncated cone shape, that is, the structure with the narrow top and the wide bottom is that the dimension of the end close to the first superconducting metal layer 2 is larger than the dimension of the end far from the first superconducting metal layer 2. Regarding the above-described through-hole 31 formed with the upper narrow and lower wide structure, there are advantageous effects thereof, which are specifically expressed as follows: when the protective layer 4 is plated on the first superconducting metal layer 2 through the through hole 31, the thin film of the protective layer 4 is difficult to be plated on the side wall of the photoresist due to the structure of the through hole 31 with the narrow upper part and the wide lower part, so that the first photoresist layer 3 can be dissolved by the organic solution when the first photoresist layer 3 is subsequently stripped through the side wall of the through hole 31, and the aluminum film on the first photoresist layer 3 also falls off, and only the aluminum film attached to the first superconducting metal layer 2 is remained. If the through hole 31 of the first photoresist layer 3 is in a vertical structure or a structure with a wide upper part and a narrow lower part, the side wall of the through hole 31 is easier to be plated with an aluminum film when the protective layer 4 is coated, so that the solution cannot be completely contacted with the first photoresist layer 3 when the organic solvent is soaked, and the stripping of the first photoresist layer 3 is affected.
S3: a dielectric layer 5 covering the protective layer 4 is formed on the first superconducting metal layer 2.
Referring to fig. 4, the dielectric layer 5 not only serves as a supporting layer between the first superconducting metal layer 2 and the second superconducting metal layer 7, but also can prevent crosstalk between two adjacent superconducting metal layers, and its thickness is generally 5 to 10 times that of the first superconducting metal layer, and can be specifically set to 1 μm, and its material is generally a dielectric material such as silicon nitride, germanium, and monocrystalline silicon, and can be etched.
S4: the dielectric layer 5 is etched with the protective layer 4 as an etching stop layer, forming an opening 51 exposing the protective layer 4.
Specifically, the above-mentioned dielectric layer 5 is etched by using a fluorine-based gas to form an opening 51 penetrating the dielectric layer 5, and it is noted that the fluorine-based gas is generally used to etch the dielectric layer 5 and cannot etch the protective layer 4-aluminum film, so that the protective layer 4 plays a role in protecting the first superconducting metal layer 2, and prevents the first superconducting metal layer 2 from being etched to cause open circuit due to the inability to control the etching end point of the dielectric layer 5.
In the embodiment of the present application, the dielectric layer 5 is etched by using the protective layer 4 as an etching stop layer, and the step of forming the opening 51 exposing the protective layer 4 is as follows:
a second photoresist layer 6 is formed on the dielectric layer 5;
forming a window 61 exposing the cut-off layer in a region of the second photoresist layer 6 opposite to the protective layer 4 by using a photolithography method;
etching the dielectric layer 5 through the window 61 to form an opening 51;
the second photoresist layer 6 is removed.
Specifically, a second photoresist layer 6 is formed on the dielectric layer 5, and a window 61 exposing the dielectric layer 5 is formed in a region of the second photoresist layer 6 opposite to the protective layer 4 by using a photolithography mode, so as to form a positioning function of subsequent etching in a region of the second photoresist layer 6 opposite to the protective layer 4; it should be noted that, the size of the opening 51 formed by etching the dielectric layer 5 through the window 61 is the same as the size of the window 61 of the first photoresist layer 3, and the sizes of the opening 51 and the window 61 are not larger than the size of the protection layer 4, so that the protection layer 4 can completely protect the first superconducting metal layer 2 when etching the dielectric layer 5, and if the sizes of the opening 51 and the window 61 are larger than the size of the protection layer 4, a part of the first superconducting metal layer 2 is etched, thereby causing the first superconducting metal layer 2 to be broken; after the completion of the above steps, the second photoresist layer 6 is cleaned and removed by an organic solution.
S5: -etching the protective layer (4) in such a way that the etching selectivity of the protective layer (4) with respect to the first superconducting metal layer (2) is greater than 1, so as to expose the first superconducting metal layer (2).
Referring to fig. 5, after the etching of the dielectric layer 5 is completed, the function of the protective layer 4 is fully achieved, and the protective layer 4 needs to be removed in order to continue the step after the etching of the dielectric layer 5, in this embodiment of the present application, the material of the protective layer 4 is aluminum, and the material of the first superconducting metal layer 2 is tantalum or tin, so that the protective layer 4 can be removed by using an aluminum etching solution (a mixed acid, a mature semiconductor aluminum wet etching solution, the main component of which is nitric acid), and the first superconducting metal layer 2 covered by the protective layer 4 is exposed, thereby performing the subsequent process.
S6: a second superconducting metal layer 7 is formed on the dielectric layer 5 and in the opening 51 to connect the first superconducting metal layer 2.
The implementation steps are as follows: etching the oxide layer on the first superconducting metal layer 2;
a second superconducting metal layer 7 is formed on the dielectric layer 5 and in the opening 51 to connect the first superconducting metal layer 2.
After the protective layer 4 is completely removed, an oxide layer is formed on the surface of the first superconducting metal layer 2 due to the contact of the first superconducting metal layer 2 with oxygen, and the communication between the first superconducting metal layer 2 and the second superconducting metal layer 7 is reduced or even isolated by the oxide layer, so that the surface of the first superconducting metal layer 2 needs to be etched by argon plasma after the protective layer 4 is removed, and the surface oxide layer is removed.
Finally, a second superconducting metal layer 7 is formed on the dielectric layer 5 and on the inner wall of the opening 51 etched by the dielectric layer 5, and the second superconducting metal layer 7 is electrically connected with the first superconducting metal layer 2 in the opening 51.
The application also provides a laminated superconducting structure, which is manufactured by adopting the manufacturing method of the laminated superconducting structure in any one of the previous embodiments.
The application also provides a quantum chip which comprises the laminated superconducting structure. And will not be described in detail herein.
In the description of the present specification, a description of the terms "one embodiment," "some embodiments," "examples," or "particular examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
While the foregoing is directed to embodiments of the present application, other and further embodiments of the application may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (10)
1. A method of preparing a stacked superconducting structure, comprising:
providing a substrate (1) having a first superconducting metal layer (2) on a surface thereof;
forming a protective layer (4) on the first superconducting metal layer (2);
forming a dielectric layer (5) covering the protective layer (4) on the first superconducting metal layer (2);
etching the dielectric layer (5) by taking the protective layer (4) as an etching stop layer to form an opening (51) exposing the protective layer (4);
etching the protective layer (4) in such a manner that the etching selectivity of the protective layer (4) with respect to the first superconducting metal layer (2) is greater than 1, to expose the first superconducting metal layer (2);
a second superconducting metal layer (7) is formed on the dielectric layer (5) and in the opening (51) to connect the first superconducting metal layer (2).
2. A method of producing a laminated superconducting structure according to claim 1, wherein the step of forming a protective layer (4) on the first superconducting metal layer (2) comprises:
forming a first photoresist layer (3) on the first superconducting metal layer (2);
photoetching the first photoresist layer (3) to form a through hole (31) exposing part of the first superconducting metal layer (2);
-depositing a protective layer (4) on the first superconducting metal layer (2) through the via (31);
-removing the first photoresist layer (3).
3. The method of manufacturing a laminated superconducting structure according to claim 2, wherein the through hole (31) has a truncated cone shape, and the dimension near the end of the first superconducting metal layer (2) is larger than the dimension far from the end of the first superconducting metal layer (2).
4. The method of manufacturing a laminated superconducting structure according to claim 1, wherein the step of etching the dielectric layer (5) with the protective layer (4) as an etch stop layer to form an opening (51) exposing the protective layer (4) comprises:
a second photoresist layer (6) is formed on the dielectric layer (5);
forming a window (61) exposing the dielectric layer (5) in a region of the second photoresist layer (6) opposite to the protective layer (4) by using a photoetching mode;
etching the dielectric layer (5) through the window (61) to form the opening (51);
-removing the second photoresist layer (6).
5. The method of manufacturing a laminated superconducting structure according to claim 4, wherein,
the window (61) and the opening (51) are the same size;
the size of the opening (51) is not larger than the size of the protective layer (4).
6. The method for preparing a laminated superconducting structure according to claim 4, wherein the etching of the dielectric layer (5) is performed by fluorine-based plasma etching.
7. Method for the preparation of a laminated superconducting structure according to claim 1, characterized in that the material of the protective layer (4) is aluminium;
the material of the first superconducting metal layer (2) is tantalum or tin;
the protective layer (4) is etched away using a mixed acid etching solution.
8. A method of producing a stacked superconducting structure according to claim 1, wherein the step of forming a second superconducting metal layer (7) connecting the first superconducting metal layer (2) on the dielectric layer (5) and in the opening (51) comprises:
etching the oxide layer on the first superconducting metal layer (2);
a second superconducting metal layer (7) is formed on the dielectric layer (5) and in the opening (51) to connect the first superconducting metal layer (2).
9. A laminated superconducting structure, characterized in that it is produced by the method for producing a laminated superconducting structure according to any one of claims 1 to 9.
10. A quantum chip comprising the stacked superconducting structure of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311283237.0A CN117082964A (en) | 2023-09-28 | 2023-09-28 | Preparation method of laminated superconducting structure, laminated superconducting structure and quantum chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311283237.0A CN117082964A (en) | 2023-09-28 | 2023-09-28 | Preparation method of laminated superconducting structure, laminated superconducting structure and quantum chip |
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| CN117082964A true CN117082964A (en) | 2023-11-17 |
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| CN202311283237.0A Pending CN117082964A (en) | 2023-09-28 | 2023-09-28 | Preparation method of laminated superconducting structure, laminated superconducting structure and quantum chip |
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- 2023-09-28 CN CN202311283237.0A patent/CN117082964A/en active Pending
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