CN117081584A - The vibration source device - Google Patents

Abstract

The disclosure relates to the technical field of radio transmission, and provides a local oscillator source device. The device comprises: a crystal oscillator for providing a first reference signal at a first frequency; the frequency doubling circuit is connected with the crystal oscillator and is used for carrying out frequency multiplication on the first reference signal to obtain a second reference signal with a second frequency, and the second frequency is an integer multiple of the first frequency; the digital-to-analog conversion circuit is connected with the frequency doubling circuit and is used for carrying out analog-to-digital conversion on the second reference signal to obtain a continuous wave signal with a third frequency; the phase-locked loop circuit comprises an integer frequency divider, a phase discriminator, a filter and a voltage-controlled oscillator which are sequentially connected, and is used for tracking continuous wave signals and outputting local reference oscillation signals from the voltage-controlled oscillator. According to the technical scheme, the local oscillation source device is realized in a mode of combining the frequency doubling circuit, the digital-to-analog conversion circuit and the phase-locked loop circuit comprising the integer frequency divider, so that the phase noise and the spurious index of the local oscillation source device can be optimized.

Description

The vibration source device

Technical Field

The present disclosure relates to the field of radio transmission technologies, and in particular, to a local oscillator source device.

Background

In millimeter wave communication, since the local oscillator source frequency of a millimeter wave transceiver is generally four times that of the middle-low frequency band of the fifth generation mobile communication, the phase noise and spurious indexes thereof are correspondingly deteriorated by about 12dB (decibel). In order not to affect millimeter wave modulation and demodulation performance, it is necessary to deteriorate phase noise and spurious indexes as little as possible.

To achieve sufficiently small frequency resolution, the local oscillator source circuit may select a fractional-divider phase-locked loop technique. But the phase noise and spurious indexes of the fractional-n pll circuit are poor, the distance from the fractional-n pll circuit is about at least 3dB, and the phase discrimination frequency is low, which further limits the improvement of the phase noise and spurious indexes of the pll circuit.

How to realize higher phase discrimination frequency and sufficiently small frequency resolution at the same time is a technical problem to be solved.

Disclosure of Invention

In view of this, embodiments of the present disclosure provide a local oscillator source device, an electronic apparatus, and a computer readable storage medium, so as to solve the problem in the prior art that phase noise and spurious indexes of a phase-locked loop circuit are poor at a high phase discrimination frequency.

The embodiment of the disclosure provides a local oscillator source device, which comprises: a crystal oscillator for providing a first reference signal at a first frequency; the frequency doubling circuit is connected with the crystal oscillator and is used for carrying out frequency multiplication on the first reference signal to obtain a second reference signal with a second frequency, wherein the second frequency is an integer multiple of the first frequency; the digital-to-analog conversion circuit is connected with the frequency doubling circuit and is used for carrying out analog-to-digital conversion on the second reference signal to obtain a continuous wave signal with a third frequency; the phase-locked loop circuit comprises an integer frequency divider, a phase discriminator, a filter and a voltage-controlled oscillator which are sequentially connected, wherein the phase discriminator is connected with the digital-to-analog conversion circuit, the input end of the integer frequency divider is connected with the output end of the voltage-controlled oscillator, the output end of the integer frequency divider is connected with the input end of the phase discriminator, and the phase-locked loop circuit is used for tracking continuous wave signals and outputting local reference oscillation signals from the voltage-controlled oscillator.

Further, the digital-to-analog conversion circuit comprises a digital-to-analog converter and a first frequency divider, and is used for performing digital-to-analog conversion on the second reference signal and performing frequency reduction on an analog signal obtained by digital-to-analog conversion.

Further, the resolution of the digital-to-analog converter is 48 bits.

Further, the frequency of the analog signal of the output of the digital-to-analog converter includes 1600MHz to 2000MHz.

Further, the first frequency divider is a four frequency divider.

Further, the frequency doubling circuit is a 60-frequency doubling circuit, and the second frequency is 6 gigahertz.

Further, the division ratio of the integer divider includes 16 to 26.

Further, the third frequency comprises 400MHz to 500MHz.

Further, the apparatus also includes a filter circuit coupled between the frequency multiplier circuit and the digital-to-analog conversion circuit.

Further, the crystal oscillator includes a general crystal oscillator or a voltage controlled crystal oscillator.

Compared with the prior art, the embodiment of the disclosure has the beneficial effects that: the technical scheme of the embodiment of the disclosure realizes the local oscillation source device by adopting a mode of combining a frequency multiplication circuit, a digital-to-analog conversion circuit and a phase-locked loop circuit comprising an integer frequency divider. The integer frequency divider can optimize phase noise of a phase discriminator of the phase-locked loop circuit, the digital-to-analog conversion circuit can output signals with higher frequency and finer frequency resolution as reference signals of the phase discriminator, and the frequency division ratio is greatly reduced, so that the phase noise index of the local oscillator source device can be optimized. In addition, the technical scheme of the embodiment of the disclosure does not adopt a fractional frequency divider, and no spurious is caused by the fractional frequency divider, so that spurious indexes of the local oscillator source device can be optimized.

Further, the technical scheme of the embodiment of the disclosure adopts the four frequency dividers to reduce the output frequency of the digital-to-analog converter to the phase discrimination frequency range allowed by the phase-locked loop circuit, and can optimize the output spurious by 12dB, thereby further improving the spurious index of the local oscillator source device.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are required for the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 is a schematic diagram of a local oscillator source circuit in the prior art;

fig. 2 is a schematic structural diagram of a local oscillator source circuit according to an embodiment of the disclosure;

fig. 3 is a schematic structural diagram of another local oscillator source circuit according to an embodiment of the disclosure.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the disclosed embodiments. However, it will be apparent to one skilled in the art that the present disclosure may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present disclosure with unnecessary detail.

In the related art, a receiving/transmitting subharmonic mixer of a transceiver of millimeter wave or the like microwaves requires a local microwave frequency oscillation source to provide a stable local reference oscillation signal. The local oscillation source device in the embodiment of the disclosure is a local microwave frequency oscillation source. The local oscillation source device can output the output signal of the quartz crystal oscillator as a reference signal after being subjected to frequency doubling for two or more times by a phase-locked loop technology, and the output signal is used as a local reference oscillation signal. The output local reference oscillation signal has the requirement of high stability and low phase noise.

Fig. 1 is a schematic diagram of a conventional local oscillator source circuit. As shown in fig. 1, a reference source signal of 100MHz (megahertz) frequency from an OCXO (Oven Controlled CrystalOscillator, constant temperature quartz crystal oscillator) or a VCXO (VoltageControlled Crystal Oscillator, voltage controlled quartz crystal oscillator) is input as a reference signal to the phase locked loop circuit. The high-frequency signal output by the wideband VCO (Voltage-Controlled Oscillator) is divided by a fractional divider to 100MHz and phase-discriminated with the reference signal in the phase discriminator, thereby being frequency-locked with the reference signal. The frequency range of a wideband VCO is typically octave, such as 6.4GHz (gigahertz) to 12.8GHz.

The local oscillator source circuit shown in fig. 1 includes a crystal oscillator 101 and a Phase locked loop circuit including a Phase Detector (PD) 102, a Low Pass Filter (LPF) 103, a voltage controlled oscillator 104, and a fractional divider 105. The crystal oscillator outputs a reference source signal with the frequency of 100MHz to the phase-locked loop circuit, and the voltage-controlled oscillator outputs a local reference oscillation signal with the frequency of 6.4GHz to 12.8GHz.

The most important indicators of the phase-locked loop circuit are phase noise and spurs, which are directly related to the spectral purity of the transceiver and the EVM (Error Vector Magnitude, vector amplitude error) indicator of the modulation/demodulation. Phase noise of phase-locked loop circuitWherein->Is the noise floor of the phase discriminator>For phase discrimination frequency, N is the divide value of the divider. The phase detector base noise of different phase-locked loop circuit chips is different, and for similar devices, the base noise of the integer frequency division phase detector is optimized by 3dB compared with that of the fractional frequency divider. Meanwhile, the smaller the N value is, the better the phase noise of the whole phase-locked loop circuit is, and the phase noise is optimized by 3dB when the N value is reduced by one time.

To achieve smaller frequency steps, conventional schemes typically employ fractional-frequency pll circuit chips. The phase discrimination frequency of the existing fractional frequency-division phase-locked loop circuit chip is about 100MHz at the highest, for local oscillation sources with higher output frequencies such as 10GHz, the frequency division value N is up to 100, and the phase noise index of the local oscillation sources is greatly influenced by the 3dB bottom noise deterioration combined with the fractional frequency-division phase discriminator. Meanwhile, the fractional frequency division phase discriminator has higher integer boundary strays, the strays cannot be filtered by the loop filter, the strays can be generated on two sides of the local oscillation source frequency spectrum, and the strays are also deteriorated in 20log N trend along with the frequency multiplication of the local oscillation source to the millimeter wave frequency band.

Therefore, the conventional local oscillator source scheme adopting the fractional frequency division phase discrimination technology cannot achieve the optimal phase noise and spurious emission, which is problematic in millimeter wave frequency band application, and cannot improve the phase discrimination frequency without adopting the fractional frequency division phase discrimination technology.

To solve the above technical problems in the prior art, embodiments of the present disclosure provide a local oscillator source device.

A local oscillation source device according to an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

Fig. 2 is a schematic structural diagram of a local oscillator circuit of a local oscillator device according to an embodiment of the disclosure. As shown in fig. 2, the local oscillator source device includes:

a crystal oscillator 201 for providing a first reference signal at a first frequency.

Specifically, the crystal oscillator 201 may be a general crystal oscillator or a voltage controlled crystal oscillator, and is not limited thereto.

The frequency multiplier circuit 202 is connected to the crystal oscillator, and is configured to multiply the first reference signal to obtain a second reference signal with a second frequency, where the second frequency is an integer multiple of the first frequency.

Specifically, a circuit that can generate an output signal frequency that is an integer multiple of the input signal frequency is called a frequency multiplier circuit. Assuming that the input signal frequency is n, the first frequency multiplication 2n, respectively 3n,4n … …, etc. is referred to as frequency multiplication, where n is a natural number.

The digital-to-analog conversion circuit 203 is connected to the frequency multiplication circuit and is configured to perform analog-to-digital conversion on the second reference signal to obtain a continuous wave signal with a third frequency.

Specifically, the digital-to-analog conversion circuit includes a DAC (Digital to Analog Converter, digital-to-analog converter). In the disclosed embodiment, the DAC is a high-speed DAC chip, for example, a high-speed DAC chip with a maximum conversion speed of 6GSPS (Gigabit Samples Per Second, gigabit per second) may be used. The high-speed DAC chip can output signals with higher frequency and finer frequency resolution as reference signals of the phase discriminator, and the frequency division ratio is greatly reduced, so that the local oscillator source phase noise index can be optimized.

The phase-locked loop circuit comprises an integer frequency divider 204, a phase discriminator 205, a filter 206 and a voltage-controlled oscillator 207 which are sequentially connected, wherein the phase discriminator is connected with the digital-to-analog conversion circuit, the input end of the integer frequency divider is connected with the output end of the voltage-controlled oscillator, the output end of the integer frequency divider is connected with the input end of the phase discriminator, and the phase-locked loop circuit is used for tracking continuous wave signals and outputting local reference oscillation signals from the voltage-controlled oscillator.

In particular, the phase detector used in combination with the integer divider is an integer divide phase detector that optimizes the phase noise of the 3dB phase detector. Further, the phase-locked loop circuit including the integer divider is an integer division phase-locked loop circuit. The technical scheme of the embodiment of the disclosure does not adopt the fractional frequency division phase discriminator matched with the fractional frequency divider, so that the spurious caused by the fractional frequency division does not exist.

The technical scheme of the embodiment of the disclosure adopts a mode of combining a frequency multiplication circuit, a DAC and an integer frequency division phase discriminator to realize the phase-locked loop circuit scheme of the local oscillator source device, thereby having lower phase noise and spurious.

As shown in fig. 2, the reference source signal with 100MHz frequency output by the crystal oscillator is sequentially processed by the frequency doubling circuit and the digital-to-analog conversion circuit and then input into the phase-locked loop circuit, and the voltage-controlled oscillator in the phase-locked loop circuit outputs the local reference oscillation signal with 6.4GHz to 12.8GHz frequency.

A phase locked loop circuit is a special system that can track another system, whose output signal can be synchronized in frequency and phase with the input reference signal.

The phase-locked loop circuit in the embodiment of the disclosure comprises a forward path formed by a phase discriminator, a filter and a voltage-controlled oscillator, and a feedback path of frequency phase formed by an integer frequency divider. The phase-locked loop circuit is not limited to a system structure comprising only a phase detector, a filter, a voltage-controlled oscillator and an integer frequency divider, and can also comprise an amplifier, a mixer and other components, wherein the amplifier and the mixer can be connected between the output end of the voltage-controlled oscillator and the input end of the phase detector to adjust the frequency and the phase of the input phase detector.

The filter may be a low pass filter, which is a loop filter. Loop filters are an important component of phase locked loops. As a low pass filter, the order of the loop filter determines the order of the phase locked loop. Typical loop filters include, but are not limited to, RC (resistor-capacitor) integrating filters, proportional-integral filters, and active integrating filters.

The output instantaneous frequency of a voltage controlled oscillator is controlled by an input voltage which can produce an output signal frequency in the range up to a few hertz-hundreds of gigahertz from the input dc voltage to it.

When the phase-locked loop circuit starts to work, the frequency of the input reference signal input into the phase-locked loop circuit from the digital-to-analog conversion circuit is different from the natural oscillation frequency of the voltage-controlled oscillator, and the frequency difference can cause the phase difference between the frequency of the input reference signal and the natural oscillation frequency of the voltage-controlled oscillator to be continuously changed and continuously span the angle of 2 pi. Since the phase detector characteristic is periodic with a phase difference of 2pi, the error voltage output from the phase detector always swings within a certain range. This error voltage is changed into a control voltage by a loop filter and applied to the voltage controlled oscillator, so that the frequency of the voltage controlled oscillator tends to the frequency of the input reference signal until the frequency of the voltage controlled oscillator changes to be equal to the frequency of the input reference signal and a certain condition is satisfied, at which the loop is stabilized. At this time, the phase difference between the two frequencies does not change with time but is a constant, the loop enters a locked state, and the phase-locked loop circuit follows the previous system.

As shown in fig. 3, the local oscillation source circuit is improved from the conventional local oscillation source circuit. In the embodiment of the present disclosure, the crystal oscillator 301 may be a general crystal oscillator or a voltage controlled crystal oscillator.

As shown in fig. 3, a reference source signal with 100MHz frequency from a common crystal oscillator or a voltage controlled crystal oscillator is processed by a frequency multiplier circuit, and then a high frequency sampling clock is output to a digital-to-analog conversion circuit.

In one embodiment of the present disclosure, the local oscillator source apparatus further includes a filter circuit connected between the frequency multiplier circuit and the digital-to-analog conversion circuit. In this case, a reference source signal of 100MHz frequency from the OCXO or VCXO is processed by the frequency multiplier circuit and the filter circuit and then outputs a high frequency sampling clock to the digital-to-analog conversion circuit. As shown in fig. 3, the frequency multiplier circuit includes a frequency multiplier 302. The frequency multiplier is a circuit for making the frequency of the output signal equal to the integral multiple of the frequency of the input signal, and the value of the integral multiple is the frequency multiplication coefficient. The harmonic frequency generated by the frequency multiplier is integral multiple with the fundamental frequency, and a filter circuit comprising a band-pass filter is designed to filter other frequencies, so that signals with integral multiple frequencies can be obtained.

Specifically, after the first reference signal with the frequency of 100MHz from the crystal oscillator 301 is processed by the frequency multiplier 302 with the frequency multiplication coefficient of 60, the second reference signal with the frequency of 6000MHz is obtained as the high-frequency sampling clock. The digital-to-analog converter 303 performs digital-to-analog conversion on the high-frequency sampling clock to obtain a continuous wave signal with a frequency range of 1600MHz to 2000MHz. The first frequency divider 304 performs a four-division process on the continuous wave signal to obtain a continuous wave signal with a frequency range of 400MHz to 500MHz, and outputs the continuous wave signal with the frequency range of 400MHz to 500MHz to the phase detector 205. The phase detector 205, the filter 206 and the voltage-controlled oscillator 207 form a forward path of the phase-locked loop, and a feedback path of the frequency phase of the phase-locked loop is formed by the integer divider 204.

In the embodiment of the disclosure, the first frequency may be 100MHz, the frequency doubling circuit may be a 60 frequency doubling circuit, and correspondingly, the second frequency is 6ghz, and the second frequency is the sampling frequency of the DAC chip. Further, the frequency multiplication coefficient of the frequency multiplication circuit can be adjusted according to the model selection condition of the devices of the crystal oscillator 301 and the digital-to-analog converter 303. When the output frequency of the crystal oscillator is 200MHz and the sampling frequency of the DAC is 6GHz, a frequency multiplication circuit with a frequency multiplication coefficient of 30 can be selected.

In the embodiment of the present disclosure, as shown in fig. 3, the digital-to-analog conversion circuit may include a digital-to-analog converter 303 and a first frequency divider 304, for performing digital-to-analog conversion on the second reference signal, and performing frequency reduction on an analog signal obtained by the digital-to-analog conversion. The digital-to-analog converter is a high-speed digital-to-analog converter.

In an embodiment of the disclosure, the first frequency divider and the integer frequency divider are both frequency dividing devices. In contrast to the function of a frequency multiplier to multiply the frequency of an input signal, a frequency divider reduces the frequency of the input signal to a lower multiple, which can divide the frequency of the input signal into an output signal of a lower integer multiple of the frequency. The frequency divider is typically composed of flip-flops, counters, etc. It divides the period of the input signal into smaller periods, and the frequency at which the output signal is generated is an integer fraction of the frequency of the input signal, which may be 1/2, 1/3, 1/4, etc.

The frequency divider may be implemented to divide the higher frequency signal to obtain the desired low frequency signal. In practical applications, the required division factor may be an integer or a fraction. The integer frequency division is simple to realize, and a counter chip or a programmable logic device can be adopted for design. Frequency dividers are one of the most common basic circuits in digital system design. Digital frequency dividers generally have two types: one type is a frequency divider with uniformly distributed pulse waveforms, namely a conventional frequency divider, and the other type is a frequency divider with unevenly distributed pulse waveforms. Conventional frequency dividers generally can only divide by integer multiples, and the frequency division multiple must be even. However, in some cases, the clock source is not in an even multiple relationship with the desired frequency, and a frequency divider with an uneven waveform is required, and the frequency divider can divide by a fractional multiple in addition to an integer multiple, so that a relatively continuous frequency output can be obtained.

In the technical solution of the embodiment of the disclosure, a DAC chip with high sampling frequency and low noise floor is preferable, for example, a DAC chip with sampling frequency of 6 GHz. When a DAC chip with the sampling frequency of 6GHz is selected, the frequency multiplication circuit is required to have a frequency multiplication coefficient of 60 times, and a pure 6GHz sampling clock can be generated after a 100MHz signal is combined by a multi-stage frequency multiplier and a filter of the frequency multiplication circuit. The high-speed DAC of the embodiments of the present disclosure can output a continuous wave signal of a frequency range DC (Direct Current) to 2.5GHz by configuring an internal NCO (Numerically ControlledOscillator, digitally controlled oscillator). The highest phase discrimination frequency supported by the integer frequency division phase discriminator is usually 500MHz, so the output frequency range of the DAC chip can be configured to be 1600MHz to 2000MHz, and the signal is reduced to 400MHz to 500MHz by a four frequency divider. Here, the DAC chip output signals of 400MHz to 500MHz are not directly configured because spurious emissions of the DAC chip output signals can be reduced by the four-divider by an amplitude of 20log4, about 12dB.

In another embodiment of the present disclosure, the DAC chip may output a continuous wave signal with a frequency range of DC (Direct Current) to 2.5GHz, or may be configured to output a continuous wave signal with a frequency range of 800MHz to 1000MHz, and the DAC chip may reduce the continuous wave signal to 400MHz to 500MHz by using a frequency divider to match the highest phase discrimination frequency of 500MHz supported by the integer frequency division phase discriminator. The divide-by-two divider also reduces spurious emissions of the DAC chip output signal.

By the above-mentioned method, when the DAC chip can output continuous wave signals with the frequency range of DC (Direct Current) to 3GHz, the output frequency range of the DAC chip can be configured to be 2400MHz to 3000MHz, and then the signals are reduced to 400MHz to 500MHz by a six-frequency divider so as to match with the highest phase discrimination frequency of 500MHz supported by the integer frequency division phase discriminator. The six divider also reduces spurious emissions of the DAC chip output signal.

Further, the DAC chips with different types have different sampling frequencies, and after the DAC chip is selected, the frequency division coefficient of the frequency divider can be selected according to the sampling frequency of the DAC chip and the highest phase discrimination frequency of 500MHz supported by the integer frequency division phase discriminator.

In one embodiment of the present disclosure, the resolution of the digital-to-analog converter is 48 bits. Where resolution refers to the minimum difference between the digital input value and the analog output value of the DAC chip. The resolution of a DAC chip is typically expressed in bits, such as 8 bits, 10 bits, 12 bits, etc. The higher the resolution, the higher the output accuracy of the DAC chip. Another performance indicator of the DAC chip is the sampling rate, which refers to the sampling rate of the digital signal input by the DAC chip. The higher the sampling rate of the DAC chip, the wider the signal bandwidth that can be processed and the less distorted the output signal.

The internal NCO of the DAC in the embodiment of the disclosure can support 48 bits (bit number) at maximum, namely can output frequency resolution asThe MHz continuous wave signal is very fine and is enough to meet the frequency resolution requirement of the vibration source device.

In one embodiment of the present disclosure, the frequency of the analog signal output by the digital-to-analog converter may be 1600MHz to 2000MHz, and correspondingly, the first frequency divider may be a four frequency divider. After the analog signal output by the digital-to-analog converter passes through the first frequency divider, a continuous wave signal with a third frequency, namely, a frequency range of 400MHz to 500MHz, is obtained.

The VCO output signal is divided by N by an integer divider, and then compared with the signal output by the first divider 304 in a phase detector to obtain a frequency and phase, and finally the frequency is locked. In the embodiment of the present disclosure, N is an integer, and its value is an integer frequency division ratio. In the disclosed embodiments, the integer divide ratio N may be adjusted such that the divided signal frequency is between 400MHz and 500MHz. In a phase locked loop circuit, a phase discrimination frequencyThe phase discrimination frequency can be achieved by adjusting the output frequency of the DAC chip from 400MHz to 500MHz. The frequency of the present vibration source, namely the output frequency of the VCO +.>Phase discrimination frequency->The relation of (2) is thatWhere N is the division ratio of the integer divider, the configuration of 16 to 26 may satisfy the requirement, i.e., N is 16, 26, or an integer between 16 and 26.

The data of phase noise PN1 in the loop when the output frequency of the local oscillator source circuit in the prior art is 10GHz as shown in fig. 1 is shown in equation (1):

（1）；

the data of phase noise PN2 in the loop when the output frequency of the local oscillator source circuit of the embodiment of the disclosure is 10GHz as shown in fig. 3 is shown in equation (2):

（2）；

therefore, compared with the local oscillator source circuit in the prior art, the local oscillator source circuit in the technical scheme of the embodiment of the disclosure can optimize the phase noise by 10dB.

When the fractional frequency phase-locked loop technology is adopted in the prior art, the integer boundary spurious worst is about-60 dBc, wherein dBc is a relative power unit, which is a logarithmic expression form of the ratio of the output power of a certain frequency point to the output power of the carrier frequency, and dB is a logarithmic expression form of the ratio of any two powers. The technical scheme of the embodiment of the disclosure adopts an integer frequency division phase-locked loop circuit, and no integer boundary spurious exists, and all spurious sources of the spurious sources are output spurious sources of a DAC chip. In one embodiment of the present disclosure, the DAC output spur is the worst-85 dBc at 2GHz frequency, and after four divisions, the spur will be optimized by 12dB, i.e., -97dBc. After the phase-locked loop circuit is used as the phase-identifying signal, the output end is deteriorated to-97 dBc+20log 20= -71dBc at the frequency of 10 GHz. Therefore, compared with the local oscillator source device of the technical scheme in the prior art, the technical scheme of the embodiment of the disclosure can optimize about 11dB of spurious emission.

In another embodiment of the present disclosure, the phase detector contribution to the phase noise can be optimized by 3dB due to the use of an integer divided pll circuit, where the phase discrimination frequency can be up to 500MHz, which is 5 times that of a fractional divided pll circuit. The phase noise optimization with the rise of the phase discrimination frequency is 10log5 = 7dB. It can be seen that the integrated phase noise is optimized to 10dB. Furthermore, integer divided phase-locked loop circuits do not have integer boundary spurs that are characteristic of fractional divided phase-locked loop circuits. Therefore, the technical scheme of the embodiment of the disclosure obviously improves the phase noise and the stray index of the vibration source.

In the local oscillator source device of the embodiment of the disclosure, the high-speed DAC is adopted to replace the OCXO/VCXO in the traditional scheme as the reference clock, and the integer frequency division phase-locked loop circuit with lower noise and higher phase discrimination frequency is adopted to replace the decimal frequency division phase-locked loop circuit in the traditional scheme, so that the phase noise and spurious indexes of the local oscillator source device are improved.

Furthermore, the technical scheme of the embodiment of the disclosure adopts the four frequency dividers to reduce the output frequency of the DAC to the phase discrimination frequency range allowed by the phase-locked loop circuit, and can optimize the output spurious by 12dB, thereby further improving the spurious index of the local oscillator source device.

The above embodiments are merely for illustrating the technical solution of the present disclosure, and are not limiting thereof; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the disclosure, and are intended to be included in the scope of the present disclosure.

Claims (10)

1. A local oscillator source device, the local oscillator source device comprising:

a crystal oscillator for providing a first reference signal at a first frequency;

the frequency doubling circuit is connected with the crystal oscillator and is used for carrying out frequency doubling on the first reference signal to obtain a second reference signal with a second frequency, wherein the second frequency is an integer multiple of the first frequency;

the digital-to-analog conversion circuit is connected with the frequency multiplication circuit and is used for carrying out analog-to-digital conversion on the second reference signal to obtain a continuous wave signal with a third frequency;

the phase-locked loop circuit comprises an integer frequency divider, a phase discriminator, a filter and a voltage-controlled oscillator which are sequentially connected, wherein the phase discriminator is connected with the digital-to-analog conversion circuit, the input end of the integer frequency divider is connected with the output end of the voltage-controlled oscillator, the output end of the integer frequency divider is connected with the input end of the phase discriminator, and the phase-locked loop circuit is used for tracking the continuous wave signal and outputting a local reference oscillation signal from the voltage-controlled oscillator.

2. The local oscillator source device according to claim 1, wherein the digital-to-analog conversion circuit includes a digital-to-analog converter and a first frequency divider for digital-to-analog converting the second reference signal and frequency reducing an analog signal obtained by digital-to-analog conversion.

3. The local oscillator source device of claim 2, wherein the digital-to-analog converter has a resolution of 48 bits.

4. The local oscillator source device of claim 2, wherein the frequency of the analog signal output by the digital-to-analog converter comprises 1600MHz to 2000MHz.

5. The local oscillator source device of claim 2, wherein the first frequency divider is a divide-by-four frequency divider.

6. The local oscillator source device of claim 1, wherein the frequency doubling circuit is a 60-frequency doubling circuit and the second frequency is 6 ghz.

7. The local oscillator source apparatus of claim 1, wherein the divide ratio of the integer divider comprises 16 to 26.

8. The local oscillator source device of claim 1, wherein the third frequency comprises 400MHz to 500MHz.

9. The local oscillator source device of claim 1, further comprising a filter circuit coupled between the frequency multiplier circuit and the digital-to-analog conversion circuit.

10. The local oscillator source apparatus according to any one of claims 1 to 9, wherein the crystal oscillator comprises a normal crystal oscillator or a voltage controlled crystal oscillator.