CN117080248A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN117080248A
CN117080248A CN202210497216.8A CN202210497216A CN117080248A CN 117080248 A CN117080248 A CN 117080248A CN 202210497216 A CN202210497216 A CN 202210497216A CN 117080248 A CN117080248 A CN 117080248A
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China
Prior art keywords
region
semiconductor device
etching
gate region
forming
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CN202210497216.8A
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Chinese (zh)
Inventor
丁瑜
邢超
王伟
焦圣杰
范桂林
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SiEn Qingdao Integrated Circuits Co Ltd
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SiEn Qingdao Integrated Circuits Co Ltd
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Priority to CN202210497216.8A priority Critical patent/CN117080248A/en
Publication of CN117080248A publication Critical patent/CN117080248A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application discloses a preparation method of a semiconductor device, which comprises the steps of providing a semiconductor substrate, forming a well region and a gate region on the semiconductor substrate, forming local doping regions on the surfaces of the well region close to two sides of the gate region, etching the well region, forming grooves on two sides of the gate region, and forming an embedded epitaxial layer in the grooves. By optimizing the growth process of the embedded epitaxial layer, before forming the trench, the surface of the well region at two sides of the gate region is doped with doped ions to form a local doped region, and the local doped region can reduce the side etching to the upper opening position of the trench during the growth of the embedded epitaxial layer, thereby improving the performance of the semiconductor device.

Description

Method for manufacturing semiconductor device
Technical Field
The application relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor device.
Background
As integrated circuits are increasingly being developed toward smaller linewidths, higher carrier mobility is required to improve device performance. And the SiGe strain material is embedded in the PMOS source/drain region, so that compressive stress can be generated on the channel with the <110> crystal orientation, and the migration rate of carriers on the channel can be improved. In addition, the shape of the groove in the PMOS source and drain region is changed from U-shaped to be similar to the shape of the diamond profile, namely, the embedded SiGe strain material in the diamond-shaped groove is more beneficial to stress concentration in the channel direction.
The conventional method for embedding the SiGe strain material in the trench of the source/drain region is generally realized by adopting an epitaxial growth technology, and in the epitaxial growth process, a pre-cleaning step is needed to be carried out on the trench, and then the SiGe strain material is epitaxially grown inside and outside the trench. However, the pre-cleaning step in the epitaxial growth process may cause problems of side over-etching at the upper opening of the diamond-type trench to different degrees, thereby affecting the performance of the semiconductor device.
Therefore, how to provide a novel method for manufacturing a semiconductor device, which can reduce the side etching of the diamond-shaped trench at the upper opening position in the pre-cleaning step, and further improve the performance of the semiconductor device, is a problem to be solved in the art.
Disclosure of Invention
The application aims to provide a preparation method of a semiconductor device, which reduces the side etching of a well region at the upper opening position of a groove in an embedded epitaxial layer growth step by forming a local doping region between the groove and a gate region, thereby improving the performance of the semiconductor device.
In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, including the steps of:
providing a semiconductor substrate, and forming a well region and a gate region on the semiconductor substrate;
doping ion implantation is carried out on the surfaces of the well regions close to the two sides of the gate region, so that a local doping region is formed;
etching the well region, forming grooves on two sides of the gate region, wherein the local doping region comprises a region between the groove and the gate region and extends to the lower part of the gate region;
and filling the epitaxial layer in the groove to form an embedded epitaxial layer, and carrying out source-drain doping in the embedded epitaxial layer to form a source region and a drain region.
In one possible embodiment, the type of dopant ion implantation of the locally doped region comprises boron or boron difluoride implantation at a dopant ion implantation angle of 0-45 DEG, the dopant concentration of boron in the locally doped region ranging from 3E14 to 3E16atoms/cm 2 。
In one possible embodiment, before the step of etching the well region and forming the trench in the well region on both sides of the gate region, the method further comprises the steps of:
and forming a hard mask layer on the surfaces of the well region and the gate region, wherein the trench forming region is defined by the hard mask layer.
In one possible implementation, before the step of forming the hard mask layer, doping ion implantation is performed on the surfaces of the well regions near two sides of the gate region to form local doping regions;
or after the step of forming the hard mask layer, carrying out doped ion implantation on the surfaces of the well regions close to the two sides of the gate region to form a local doped region.
In one possible embodiment, the step of etching the well region and forming the trench in the well region on both sides of the gate region specifically includes:
carrying out first groove etching on the well region by taking the hard mask layer as a mask so as to form grooves with U-shaped morphology in a self-aligned mode on two sides of the gate region;
and (3) taking the hard mask layer as a mask, and carrying out second groove etching on the groove so as to enlarge the volume of the groove and make the shape of the groove diamond.
In one possible embodiment, the second trench etch uses a wet etch using TMAN as the etching solution.
In one possible embodiment, the step of filling the trench with an epitaxial layer to form an embedded epitaxial layer further comprises pre-cleaning the trench.
In one possible embodiment, the pre-cleaning step is a cleaning step comprising SF 6 And Cl 2 Etching and cleaning the groove.
In one possible embodiment, the SF is 6 The gas flow range is 1-100 sccm, the time of acting in a gaseous state is 3-30 s, and the time of acting in a plasma state is 3-30 s; cl 2 The gas flow is 1-100 sccm, the time of acting in the gas state is 3-30 s, and the time of acting in the plasma state is 3-30 s.
In one possible embodiment, the embedded epitaxial layer is an embedded SiGe epitaxial layer and the source and drain regions are P-type doped.
Compared with the prior art, the application has the following beneficial effects:
the application provides a preparation method of a semiconductor device, which comprises the steps of providing a semiconductor substrate, forming a well region and a gate region on the semiconductor substrate, forming a local doping region on the surface of the well region close to two sides of the gate region, etching the well region, forming grooves on two sides of the gate region, and forming an embedded epitaxial layer in the grooves. By optimizing the growth process of the embedded epitaxial layer, before forming the trench, the surface of the well region at two sides of the gate region is doped with doped ions to form a local doped region, and the local doped region can reduce the side etching to the upper opening position of the trench during the growth of the embedded epitaxial layer, thereby improving the performance of the semiconductor device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;
fig. 2 to 5 are schematic structural views of a semiconductor device according to an embodiment of the present application at different stages of fabrication;
fig. 6A is a cross-sectional view of a diamond-shaped groove of a semiconductor device according to an embodiment of the present disclosure;
fig. 6B is a cross-sectional view of an embedded epitaxial layer of a semiconductor device formed in accordance with the prior art;
fig. 6C is a cross-sectional view of a semiconductor device embedded epitaxial layer according to an embodiment of the present application.
Illustration of:
10 a semiconductor substrate; a 20-well region; 210 a locally doped region; 30 gate regions; 40 gate insulating layer; a 50 hard mask layer; 60 grooves; 610U-shaped grooves; 620 diamond shaped groove; 70 embedded epitaxial layer.
Detailed Description
The following specific examples are presented to illustrate the present application, and those skilled in the art will readily appreciate the additional advantages and capabilities of the present application as disclosed herein. The application may be practiced or carried out in other embodiments that depart from the spirit and scope of the present application, and details of the present application may be modified or changed from various points of view and applications.
In the description of the present application, it should be noted that, unless explicitly stated and limited otherwise, the term "connected" should be interpreted broadly, and for example, it may be a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances. Furthermore, the terms "first" and "second," etc. are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
The mobility of carriers in the channel affects the magnitude of current in the channel, and the decrease in carrier mobility not only reduces the switching speed of the transistor, but also reduces the difference in resistance between on and off. For PMOS devices, compressive stress is applied in the direction of channel current flow to advantage hole mobility, and thus compressive stress is introduced in the direction of the channel to increase the mobility of holes in its channel. The embedded silicon germanium technology is provided for the mobility of holes in a PMOS device, silicon germanium is grown in a source-drain region through a selective epitaxial growth technology, so that the stress of a channel region is introduced, and the stress concentration in the channel direction is facilitated by a groove with a diamond-shaped section.
The epitaxial growth technique, which is usually selective, also includes a pre-cleaning process of the trench, such as introducing SF 6 And Cl 2 The formed plasma etches and cleans the groove. However, the sidewalls of the trench having the diamond-shaped cross section at the upper opening thereof may be subjected to uncontrolled overetching during the pre-cleaning process, resulting in leakage between the source and drain electrodes formed later and degrading the performance of the semiconductor device.
Analysis proves that before the groove is formed, partial boron ion implantation is carried out in the range of the side wall of the groove, so that the etching rate of Si in the side wall of the groove in the pre-cleaning process can be effectively reduced. Atomic radius of boron isAtomic radius of silicon ofBoron atoms have a smaller radius than silicon atoms, so that doping with boron ions creates tensile stresses in the crystal lattice of silicon, thereby reducing the rate at which silicon is etched. In addition, boron ions and fluorine ions and chlorine ions (F - /Cl - ) The coulomb repulsion can also play a certain role in inhibiting the etching rate of silicon.
Based on the above analysis, according to one aspect of the present application, there is provided a semiconductor device manufacturing method. Referring to fig. 1, the method comprises the following steps:
s1, a semiconductor substrate 10 is provided, and a well region 20 and a gate region 30 are formed on the semiconductor substrate 10.
Referring to fig. 2, a semiconductor substrate 10 is provided, and in one embodiment, the semiconductor substrate 10 may be a silicon substrate, or a silicon-on-insulator substrate, where the semiconductor substrate 10 is illustrated as a silicon substrate.
Ion implantation is performed on the upper region of the semiconductor substrate 10 to form a well region 20. In one embodiment, N-type dopant ions are implanted into the semiconductor substrate 10 to form a well region 20 with the N-type dopant ions. The N-type dopant ions may be, for example, phosphorus (P) ions, arsenic (As) ions, or antimony (Sb) ions, and the P-type dopant ions may be, for example, boron (B) ions, boron difluoride (bf2+) ions, gallium (Ga) ions, or indium (In) ions.
A gate insulating layer 40 is formed on the well region 20, and a polysilicon layer is formed on the gate insulating layer 40. The polysilicon layer is etched to form the gate region 30 using a photolithography and etching process. In one embodiment, the gate region 30 further includes an oxide layer formed on the polysilicon sidewall and a nitride layer formed on the oxide layer. The oxide layer is preferably a silicon oxide layer and the nitride layer is preferably a silicon nitride layer.
S2, carrying out doped ion implantation on the surfaces of the well region 20 near the two sides of the gate region 30 to form a local doped region 210.
Ion implantation is performed on the surface of the well region 20 near both sides of the gate region 30 to form a locally doped region 210 in the surface of the well region 20. In one embodiment, the doping ions may be boron (B) ions or boron difluoride (BF2+) ions, the doping ion implantation angle is 0-45 DEG, and the doping concentration of boron in the partial doped region 210 formed after doping is in the range of 3E 14-3E 16atoms/cm 2 。
Before or after forming the local doping region 210 in step S2, a hard mask layer 50 is further formed on the surfaces of the well region 20 and the gate region 30. The hard mask layer 50 may be used to protect the polysilicon of the gate from the subsequent trench 60 formation process; next, the hard mask layer 50 is patterned, so that the formation range of the subsequent trench 60 can be defined. The hard mask layer 50 is preferably a silicon nitride layer.
In one embodiment, referring to fig. 3A, ion doping is performed on the surface of the well region 20 near both sides of the gate region 30 to form a locally doped region 210 on the surface of the well region 20, and then a hard mask layer 50 is formed on the surfaces of the well region 20 (including the locally doped region 210) and the gate region 30. In another embodiment, referring to fig. 3B, a hard mask layer 50 is formed on the surfaces of the well region 20 and the gate region 30 before the locally doped region 210, and then the surfaces of the well region 20 near both sides of the gate region 30 are ion-doped by spacing the hard mask layer 50 to form the locally doped region 210.
S3, etching the well region 20, forming trenches 60 on both sides of the gate region 30, and the locally doped region 210 includes a region between the trenches 60 and the gate region 30 and extends below the gate region.
Referring to fig. 4A-4B, the formation of the trench 60 may be performed using a process means known in the art, such as dry etching, wet etching, or a combination of dry and wet processes, and the depth of the trench 60 may be determined according to the required depths of the source and drain regions. The shape of the groove 60 includes, but is not limited to, diamond, but may be rectangular, inverted trapezoidal, etc. as desired.
In one embodiment, the trench 60 is diamond-shaped, i.e., a "Σ" shape recognized in the industry, and it should be noted that diamond-shaped means that the cross section of the trench 60 has a shape similar to that of diamond. The diamond-shaped groove 620 is formed by the following steps: first, the patterned hard mask layer 50 is etched for the first time to form a U-shaped groove 610 in the well region 20; then, the U-shaped groove 610 is etched for the second time, so that the volume of the U-shaped groove 610 is enlarged, and a diamond-shaped groove 620 with a diamond cross section is formed, wherein the side wall of the diamond-shaped groove 620, which is close to the gate region 30, is the local doped region 210.
In one embodiment, the first etch is a dry etch and the second etch is a wet etch. The etchant for wet etching is selective to the crystal orientation, for example, an etchant containing tetramethyl ammonium hydroxide (TMAN) for starting etching from within the U-shaped groove 610 provided by the dry etching process at a lower etching rate in the <111> crystal orientation than in the other crystal orientations, so that the U-shaped groove 610 etches into a diamond-shaped groove 620.
And S4, filling an epitaxial layer in the groove 60 to form an embedded epitaxial layer 70, and carrying out source-drain doping in the embedded epitaxial layer 70 to form a source region and a drain region.
Referring to fig. 5, an embedded epitaxial layer 70 is formed in the diamond-type recess 620 by an epitaxial growth technique, including high vacuum chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition, molecular beam epitaxy, or the like. In one embodiment, the embedded epi layer 70 is formed by high vacuum chemical vapor deposition, the embedded epi layer 70 may be an embedded SiGe epi layer, and the source and drain regions may be P-type doped.
During the epitaxial growth process, a process of pre-cleaning the trench 60 is also included. In one embodiment, the pre-cleaning process is a SF-containing process 6 And Cl 2 Etching and cleaning the trench 60 with the process gas of (1), wherein SF 6 The gas flow is 1-100 sccm, the time of gas action is 3-30 s, the time of plasma action is 3-30 s, cl 2 The gas flow is 1-100 sccm, the time of acting in the gas state is 3-30 s, and the time of acting in the plasma state is 3-30 s.
It should be noted that, in the conventional pre-cleaning process, over etching is performed on the Si on the side wall of the diamond-shaped recess 620, especially on the side wall of the diamond-shaped recess 620 near the gate region 30, which may cause leakage of the gate region 30, and affect the performance of the device. The surface of the well region 20 near the gate region 30 is doped with boron ions before the trench 60 is formed to form the local doped region 210, so that over etching of the diamond-shaped recess 620 near the gate region 30 during the pre-cleaning process can be effectively reduced. Referring to FIG. 6, FIG. 6A is a block diagram of a diamond-shaped recess 620 prior to a pre-clean step, and FIG. 6B is a block diagram of an embedded SiGe epitaxial layer formed by the prior art, with an over-etch of Si on the sidewall adjacent to the gate region 30 ofFIG. 6C is a block diagram of an embedded SiGe epitaxial layer formed in accordance with an embodiment of the present application, wherein the sidewall Si over-etch near the gate region 30 is +.>Compared with the prior art, the applicationThe sidewall Si over-etch of the embedded SiGe epitaxial layer of an embodiment is reduced by more than 50%.
Preferably, before step S3, the locally doped region 210 before the etching process should further include an area surrounded by the top opening of the trench 60, besides the area between the trench 60 and the gate region 30, so as to form a complete protection for the opening edge of the subsequent diamond-type recess 620. The locally doped region 210 located in the region surrounded by the opening of the trench 60 is partially removed during the first etching and the subsequent pre-cleaning of the trench 60, so that the performance of the device is not affected, and finally the locally doped region 210 located in the region around the outside of the top opening of the diamond-type recess 620 is preserved. It should be appreciated that in this case, the locally doped region 210 should also include the entire top open area of the diamond-type recess 620 for the final device structure to be formed, not just the area between the trench and the gate region.
According to the technical scheme, the preparation method of the semiconductor device comprises the steps of providing a semiconductor substrate, forming a well region and a gate region on the semiconductor substrate, forming local doped regions on the surfaces of the well region close to two sides of the gate region, etching the well region, forming grooves on two sides of the gate region, and forming an embedded epitaxial layer in the grooves. By optimizing the growth process of the embedded epitaxial layer, before forming the trench, the surface of the well region at two sides of the gate region is doped with doping ions to form a local doped region, and the local doped region can reduce the side etching cleaning of the upper opening position of the trench before growing the embedded epitaxial layer, thereby improving the performance of the semiconductor device.
The foregoing is merely a preferred embodiment of the present application, and it should be noted that modifications and substitutions can be made by those skilled in the art without departing from the technical principles of the present application, and these modifications and substitutions should also be considered as being within the scope of the present application.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate, and forming a well region and a gate region on the semiconductor substrate;
carrying out doped ion implantation on the surfaces of the well regions close to the two sides of the gate region to form a local doped region;
etching the well region, forming grooves on two sides of the gate region, wherein the local doping region comprises a region between the groove and the gate region and extends to the lower part of the gate region;
and filling an epitaxial layer in the groove to form an embedded epitaxial layer, and carrying out source-drain doping in the embedded epitaxial layer to form a source region and a drain region.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the type of doping ion implantation of the local doping region comprises boron or boron difluoride implantation, the doping ion implantation angle is 0 to 45 °, and the doping concentration of boron in the local doping region is in the range of 3E14 to 3E16atoms/cm 2 。
3. The method of manufacturing a semiconductor device according to claim 1, further comprising, before the step of etching the well region and forming trenches in the well region on both sides of the gate region, the steps of:
and forming a hard mask layer on the surfaces of the well region and the gate region, wherein the trench forming region is defined by the hard mask layer.
4. The method of fabricating a semiconductor device according to claim 3, wherein before the forming a hard mask layer step, doping ion implantation is performed on the surfaces of the well regions adjacent to both sides of the gate region to form local doping regions;
or after the step of forming the hard mask layer, carrying out doped ion implantation on the surfaces of the well regions close to the two sides of the gate region to form a local doped region.
5. The method for manufacturing a semiconductor device according to any one of claims 3 to 4, wherein the step of etching the well region and forming trenches in the well region on both sides of the gate region specifically comprises:
taking the hard mask layer as a mask, and carrying out first trench etching on the well region to form grooves with U-shaped morphology in a self-aligned mode on two sides of the gate region;
and carrying out second groove etching on the groove by taking the hard mask layer as a mask, so that the volume of the groove is enlarged, and the shape of the groove is diamond-shaped.
6. The method of manufacturing a semiconductor device according to claim 5, wherein the second trench etching is wet etching, and wherein TMAN is used as an etching liquid.
7. The method of claim 1, further comprising pre-cleaning the trench prior to the step of filling the epitaxial layer in the trench to form the embedded epitaxial layer.
8. The method for manufacturing a semiconductor device according to claim 7, wherein the pre-cleaning step is a step of including SF 6 And Cl 2 Etching and cleaning the groove.
9. The method for manufacturing a semiconductor device according to claim 8, wherein the SF 6 The gas flow range is 1-100 sccm, the time of acting in a gaseous state is 3-30 s, and the time of acting in a plasma state is 3-30 s; the Cl 2 The gas flow is 1-100 sccm, the time of acting in the gas state is 3-30 s, and the time of acting in the plasma state is 3-30 s.
10. The method of manufacturing a semiconductor device according to claim 1, wherein the embedded epitaxial layer is an embedded SiGe epitaxial layer, and the source and drain regions are P-type doped.
CN202210497216.8A 2022-05-09 2022-05-09 Method for manufacturing semiconductor device Pending CN117080248A (en)

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Application Number Priority Date Filing Date Title
CN202210497216.8A CN117080248A (en) 2022-05-09 2022-05-09 Method for manufacturing semiconductor device

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