CN117080200A - Reconfigurable heterogeneous integrated three-dimensional radio frequency chip and manufacturing method thereof - Google Patents

Reconfigurable heterogeneous integrated three-dimensional radio frequency chip and manufacturing method thereof Download PDF

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CN117080200A
CN117080200A CN202311156676.5A CN202311156676A CN117080200A CN 117080200 A CN117080200 A CN 117080200A CN 202311156676 A CN202311156676 A CN 202311156676A CN 117080200 A CN117080200 A CN 117080200A
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radio frequency
chip
bare chip
pad
cpld
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杨进
张君直
朱健
刘梓枫
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CETC 55 Research Institute
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    • H—ELECTRICITY
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Abstract

The invention discloses a reconfigurable heterogeneous integrated three-dimensional radio frequency chip and a manufacturing method thereof, wherein the chip comprises: CPLD bare chip, silicon-based Fan-in structure, micro-salient point/micro-column and radio frequency bare chip, its characterized in that, reconfigurable heterogeneous integrated three-dimensional radio frequency chip includes silicon-based Fan-in structure, CPLD bare chip and radio frequency bare chip locate respectively the silicon-based Fan-in structure both sides, the circuit of silicon-based Fan-in structure with CPLD bare chip PAD is connected, the circuit is through RDL reconfiguration wiring, connects radio frequency bare chip control signal PAD, radio frequency bare chip still includes extension PAD, CPLD bare chip's power/ground/programming interface signal is drawn forth through extension PAD. The three-dimensional radio frequency chip realizes three-dimensional heterogeneous integration of 2 bare chips through a silicon-based Fan-in process reconstruction wiring and a chip flip-chip stacking process.

Description

Reconfigurable heterogeneous integrated three-dimensional radio frequency chip and manufacturing method thereof
Technical Field
The invention relates to a reconfigurable heterogeneous integrated three-dimensional radio frequency chip and a manufacturing method thereof, belonging to the technical field of radio frequency microsystems.
Background
The development of modern electronic equipment has put forward miniaturized, multifunctional and reconfigurable demands on radio frequency systems, and the functional complexity of radio frequency systems is increasingly improved. Active phased array (Active Electronically Scanned Array, AESA) technology requires that the rf system achieve high performance, scalability, low cost, and low profile characteristics, and current rf system integration architecture evolves from Multi-chip modules (MCM) to rf microsystems. Under the integrated architecture of the radio frequency micro system, a plurality of active and passive devices with different functions are integrated in a single package in a high density through heterogeneous integration technology to form a unit with the functions of the system or the subsystem. Radio frequency microsystems are often packaged in BGA or the like for further integration on a system motherboard by surface mount technology (Surface Mount Technology, SMT) to form a more complex and complete electronic system. Compared with MCM integration, the radio frequency system adopting the radio frequency microsystem integration architecture has the main advantages that:
1. under the technical trend of the post-molar age, the radio frequency microsystem can continuously absorb the latest technology of heterogeneous integration/system-in-package, so as to realize more complex and higher-performance system integration;
2. the radio frequency micro system adopts a standard packaging form, and the product structure and the process method have strong standardization and universality, so that the new product is short in introduction period, can quickly enter mass production, and is low in manufacturing cost;
3. the high-low frequency composite mother board is utilized, board-level system integration between the radio frequency micro system and functional units such as a power supply, digital processing and an antenna is realized through an SMT (surface mounting technology), a huge radio frequency/low frequency cable is eliminated, and the system integration density and reliability are greatly improved.
The interconnection technology is the core technology of the radio frequency micro system. Advanced package interconnection techniques at the front of research and application include flip-chip, chip embedding and fan-out, and three-dimensional stacking, as opposed to conventional wire bonding techniques. Radio frequency circuitry typically includes a variety of components and parts, such as compound semiconductors, silicon-based radio frequency chips, integrated passive devices, MEMS, etc., that employ different materials and processes, and that have widely differing interconnect and packaging requirements, so that radio frequency microsystems have very distinct heterogeneous integration characteristics and tend to integrate with a variety of advanced interconnect technologies.
The expansion of the integration dimension of the radio frequency microsystem in the Z direction through the three-dimensional stacking technology is a main technical direction of the current heterogeneous integration development, however, a large number of passive devices in the radio frequency link adopt a distributed parameter design, and when chips or packaging substrates are closely stacked, the coupling of electromagnetic fields may cause serious degradation of circuit performance or even failure to work normally. Therefore, the constraint of fully considering the radio frequency performance is the key of the application of the three-dimensional stacking technology by the radio frequency micro system. From the object of stacking interconnect, three-dimensional stacking techniques can be divided into two major types, chip stacking (3D-IC) and package stacking (Package on Package, poP).
In the traditional three-dimensional radio frequency chip, either a digital circuit chip or a radio frequency chip needs to be modified, and the other needs to be matched with redesign of a streaming sheet, so that the problems of long iteration period, high manufacturing cost and the like are caused.
Disclosure of Invention
The invention aims to provide a reconfigurable heterogeneous integrated three-dimensional radio frequency chip and a manufacturing method thereof, and provides a solution of a radio frequency digital integrated micro system. The reconfigurable heterogeneous integrated three-dimensional radio frequency chip creatively adopts a silicon-based Fan-in process reconfiguration wiring and a chip flip-chip stacking process to realize three-dimensional heterogeneous integration of 2 bare chips, firstly, a CPLD bare chip is subjected to RDL reconfiguration wiring through the silicon-based Fan-in process, design is carried out according to the mirror image layout of a radio frequency bare chip control signal PAD, and Fan-out is carried out through UBM (under bump metal layer); and the CPLD bare chips subjected to the Fan-in process are inverted and stacked on the radio frequency bare chips through the micro bumps/micro columns, so that signal interconnection among 2 kinds of bare chips is realized, and meanwhile, the power supply/ground/programming interface signals of the CPLD are led out through the expansion PAD of the radio frequency bare chips, so that a final complete three-dimensional radio frequency chip structure is formed. The three-dimensional radio frequency chip is assembled by a wire bonding mode. The CPLD bare chip can realize complex combination logic circuit functions and sequential logic circuit functions through online programming, has flexible dynamic reconfigurable capability, can meet various application scene requirements of the radio frequency chip, can replace a silicon-based special digital circuit chip customized and developed in the traditional three-dimensional radio frequency chip, solves the problem that any one party of the digital circuit chip or the radio frequency chip in the traditional three-dimensional radio frequency chip needs to be modified, and the other party needs to cooperate with a pain point of redesigning a flow sheet, thereby greatly shortening the iteration period, being beneficial to rapidly pushing out products and having strong engineering practicability.
The technical scheme for realizing the purpose of the invention is as follows:
the reconfigurable heterogeneous integrated three-dimensional radio frequency chip comprises a CPLD bare chip, a silicon-based Fan-in structure, micro bumps/micro columns and a radio frequency bare chip, wherein the reconfigurable heterogeneous integrated three-dimensional radio frequency chip comprises the silicon-based Fan-in structure, the CPLD bare chip and the radio frequency bare chip are respectively arranged on two sides of the silicon-based Fan-in structure, a circuit of the silicon-based Fan-in structure is connected with a CPLD bare chip PAD, the circuit is connected with a radio frequency bare chip control signal PAD through RDL reconstruction wiring, the radio frequency bare chip further comprises an expansion PAD, and power/ground/programming interface signals of the CPLD bare chip are led out through the expansion PAD.
Furthermore, the silicon-based Fan-in structure carries out RDL reconstruction wiring on the CPLD bare chip according to the mirror image layout of the radio frequency bare chip control signal PAD, and Fan-out is carried out through the UBM, and the UBM and the radio frequency bare chip control signal PAD are interconnected through the micro-salient points/micro-columns.
Further, the control signal PAD of the radio frequency bare chip is arranged on the inner side of the chip, the external PAD and the expansion PAD are arranged on the outer side of the chip, and part of the control signal PAD is led out to the expansion PAD through internal wiring.
Further, the external PAD and the extended PAD of the radio frequency bare chip are interconnected through wire bonding and external signals.
A method for manufacturing a reconfigurable heterogeneous integrated three-dimensional radio frequency chip comprises the following steps:
1) According to the layout of a CPLD bare chip PAD and a radio frequency bare chip control signal PAD, designing a silicon-based Fan-in structure;
2) Sputtering a metal layer on the CPLD bare chip, performing photoetching, and electroplating barrier metal on the PAD of the CPLD bare chip;
3) Forming a protection pad through photoetching, and removing the metal layers in other areas through corrosion;
4) Coating a first layer of PI glue, and photoetching to form a via hole 1 structure;
5) Sputtering a layer of seed layer metal, photoetching and electroplating to form an RDL1 wiring layer, and etching to remove the seed layer;
6) Coating a second layer of PI glue, and photoetching to form a via hole 2 structure;
7) Sputtering a layer of seed layer metal, and photoetching and electroplating to form an RDL2 wiring layer;
8) Photoresist coating, electroplating to form a UBM structure, and etching to remove the seed layer;
9) Coating a third layer of PI glue, and photoetching and windowing to expose the PAD structure;
10 Thinning the back of the CPLD wafer;
11 CPLD wafer dicing;
12 The CPLD silicon-based Fan-in structure is inverted and then stacked on the radio frequency bare chip through the micro bumps/micro columns to form a three-dimensional radio frequency chip structure.
The beneficial effects of the invention are as follows:
(1) The traditional monolithic radio frequency digital integrated chip adopts a technical route of silicon-based heterogeneous integrated compound semiconductors, firstly, materials of different compound semiconductors are epitaxially grown on a silicon substrate, then, the chip with the monolithic integration of the different compound semiconductor materials and the silicon materials on the same substrate is prepared by processing through a semiconductor process, the process implementation difficulty is high, the yield is low, and the large-scale popularization in engineering is difficult; in addition, each time of heterogeneous integration can only realize a silicon-based digital circuit with a specific function, the silicon-based digital circuit does not have reconfigurable capability, and the design is changed to be re-sliced; most critical, limited by process and design, not any desired digital circuit functions can be realized by heterogeneous integration, and the limitations are great. The reconfigurable heterogeneous integrated three-dimensional radio frequency chip adopts a three-dimensional heterogeneous integration process, based on the existing CPLD bare chip and radio frequency bare chip, the CPLD can realize complex combination logic circuit functions and sequential logic circuit functions through programming, meets the requirements of various application scenes of the radio frequency chip, only needs to replace different radio frequency bare chips when the whole design is changed, and can carry out silicon-based Fan-in reconfiguration wiring on the CPLD again without carrying out semiconductor flow chip again, thereby greatly simplifying the process flow, reducing the process difficulty, shortening the iteration period, being beneficial to rapidly pushing out products, preempting market pre-machines and being suitable for large-scale popularization in engineering.
(2) The traditional three-dimensional radio frequency chip adopts a silicon-based special digital circuit chip and a radio frequency chip which are custom-developed and realized through a three-dimensional stacking process. The digital circuit bare chip PAD is interconnected with the corresponding PAD of the radio frequency bare chip through a wire bonding process, so that the digital circuit chip and the radio frequency chip are designed cooperatively, the PAD layout of the interconnection part of the digital circuit bare chip PAD and the radio frequency chip is kept corresponding, the whole design is complex, the realization difficulty is high, the development period is long, the development flow sheet is required to be customized again for each design, and the engineering is difficult to popularize in a large range; in addition, no matter any one of the digital circuit chip or the radio frequency chip needs to be modified, the other needs to be matched with redesign of the streaming sheet, the iteration period is too long, the quick product pushing is not facilitated, and the market preemption is preempted. The reconfigurable heterogeneous integrated three-dimensional radio frequency chip adopts a three-dimensional heterogeneous integration process, based on the existing CPLD bare chip and radio frequency bare chip, the CPLD can realize complex combination logic circuit functions and sequential logic circuit functions through programming, meets the requirements of various application scenes of the radio frequency chip, only needs to replace different radio frequency bare chips when the whole design is changed, and can carry out silicon-based Fan-in reconfiguration wiring on the CPLD again without carrying out semiconductor flow chip again, thereby greatly simplifying the process flow, reducing the process difficulty, shortening the iteration period, being beneficial to rapidly pushing out products, preempting market pre-machines and being suitable for large-scale popularization in engineering.
(3) The traditional monolithic radio frequency digital integrated chip and the three-dimensional radio frequency chip can only realize a specific digital circuit function and have no reconfigurable capability in each design; the digital circuit function must be changed by redesigning the flow sheet, the iteration period is too long, and the product is not easy to be rapidly pushed out, and the market precedent is preempted. The reconfigurable heterogeneous integrated three-dimensional radio frequency chip provided by the invention can realize the functions of a complex combination logic circuit and a sequential logic circuit by programming based on the strong reconfigurable capability of the CPLD, so that the requirements of various application scenes of the radio frequency chip are met; the programming interface signal of the CPLD bare chip is led out through the expansion PAD of the radio frequency bare chip, and can be interconnected with the system processor IO, the system processor carries out on-line programming on the CPLD through the programming interface, changes the CPLD function in real time, realizes the dynamic reconfiguration of the three-dimensional radio frequency chip, lays a foundation for the intellectualization of the whole radio frequency system, does not need to carry out semiconductor flow sheet again in all operations, and has very strong innovation and engineering practicability.
(4) Compared with FPGA, DSP, CPU and other processors, the CPLD bare chip has small volume, low power consumption, FLASH memory integrated on the chip, relatively fixed internal connection, small path delay and predictability, can work at higher frequency, and has simple peripheral circuit; compared with MCU such as singlechip, CPLD stability is high when working, does not need external oscillator when not working, can not produce interference frequency signal to radio frequency circuit, can work under higher frequency. When the radio frequency chip works, only the complex combination logic circuit function and the sequential logic circuit function are provided externally to serve as control logic of the radio frequency chip, and a high-computation-force signal processing function is not needed; the CPLD can realize the functions of the complex combination logic circuit and the sequential logic circuit through online programming, has small volume and low power consumption, completely meets the working requirement of the radio frequency chip, is very suitable for being matched with the radio frequency bare chip to work, and is the optimal combination of the radio frequency chip adopting a three-dimensional heterogeneous integration scheme.
Drawings
Fig. 1 is an overall top view of a reconfigurable heterogeneous integrated three-dimensional radio frequency chip.
Fig. 2 is a bottom view of the entirety of a reconfigurable heterogeneous integrated three-dimensional radio frequency chip.
Fig. 3 is an overall side view of a reconfigurable heterogeneous integrated three-dimensional radio frequency chip.
Fig. 4 (a) and (b) are schematic diagrams of a reconfigurable heterogeneous integrated three-dimensional radio frequency chip upper layer CPLD bare chip.
Fig. 5 (a) and (b) are schematic diagrams of a reconfigurable heterogeneous integrated three-dimensional radio frequency chip upper layer CPLD bare chip Fan-in process.
Fig. 6 (a) and (b) are schematic diagrams of a reconfigurable heterogeneous integrated three-dimensional rf chip lower layer rf bare chip.
Fig. 7 is a schematic diagram of three-dimensional heterogeneous integration of a reconfigurable heterogeneous integrated three-dimensional radio frequency chip.
Fig. 8 (a) and (b) are schematic diagrams of wire bonding of a reconfigurable heterogeneous integrated three-dimensional radio frequency chip.
Wherein reference numerals are as follows: 1-CPLD bare chip, 2-CPLD bare chip PAD, 3-silicon-based Fan-in,4-RDL reconstruction wiring, 5-UBM (under bump metal layer), 6-micro bump/micro column, 7-radio frequency bare chip, 8-radio frequency bare chip control signal PAD, 9-radio frequency bare chip internal wiring, 10-radio frequency bare chip expansion PAD, 11-radio frequency bare chip external PAD and 12-lead bonding.
Description of the embodiments
The invention will be described in further detail with reference to the accompanying drawings.
Referring to fig. 1 to 3, the reconfigurable heterogeneous integrated three-dimensional radio frequency chip provided by the invention comprises an 11 part, wherein the 11 part comprises a CPLD bare chip 1, a CPLD bare chip PAD2, a silicon-based Fan-in3, an RDL reconfiguration wiring 4, a UBM5, a micro bump/micro column 6, a radio frequency bare chip 7, a radio frequency bare chip control signal PAD8, a radio frequency bare chip internal wiring 9, a radio frequency bare chip expansion PAD10 and a radio frequency bare chip external PAD11.
As shown in fig. 4 (a) and (b), the upper layer of the reconfigurable heterogeneous integrated three-dimensional radio frequency chip adopts a CPLD to realize the required digital circuit function. The CPLD bare chip has small volume, low power consumption, integrated FLASH memory on chip, relatively fixed internal connection, small path delay and predictability, can work at higher frequency, has simple peripheral circuit, can realize complex combination logic circuit function and sequential logic circuit function through online programming, and has flexible dynamic reconfigurable capability. PADs of the CPLD bare chip are arranged outside the chip.
As shown in fig. 5 (a) and (b), the upper layer of the reconfigurable heterogeneous integrated three-dimensional radio frequency chip is a CPLD bare chip, and according to the mirror image layout of a radio frequency bare chip control signal PAD, a silicon-based Fan-in process is adopted to perform RDL reconfiguration wiring on the CPLD bare chip, and Fan-out is performed through UBM.
As shown in fig. 6 (a) and (b), the lower layer of the reconfigurable heterogeneous integrated three-dimensional radio frequency chip is a radio frequency bare chip, and the radio frequency bare chip comprises but is not limited to GaAs, inP and other technologies, and functions of amplitude and phase control, frequency conversion, front-end reception and the like. The control signal PAD of the radio frequency bare chip is arranged on the inner side of the chip, the external PAD and the expansion PAD are arranged on the outer side of the chip, and part of the control signal PAD is led out to the expansion PAD through internal wiring.
As shown in FIG. 7, the reconfigurable heterogeneous integrated three-dimensional radio frequency chip adopts a three-dimensional heterogeneous integrated architecture, CPLD bare chips subjected to a Fan-in process are stacked on the radio frequency bare chips through micro bumps/micro columns after being inverted through a chip flip-chip stacking process, and signal interconnection among 2 kinds of bare chips is realized. The UBM of the CPLD bare chip and the control signal PAD of the radio frequency bare chip are interconnected through the micro-convex points/micro-columns, so that the CPLD can realize logic control of the control signal pin of the radio frequency bare chip through the programmable I/O pin; meanwhile, the power supply/ground/programming interface signals of the CPLD are led out through an expansion PAD of the radio frequency bare chip, so that a final complete three-dimensional radio frequency chip structure is formed.
As shown in fig. 8 (a) and (b), the reconfigurable heterogeneous integrated three-dimensional radio frequency chip is assembled by a wire bonding mode, and an external PAD and an extended PAD outside a radio frequency bare chip are interconnected by wire bonding and an external signal.
The invention also provides a manufacturing method of the reconfigurable heterogeneous integrated three-dimensional radio frequency chip, which comprises the following steps:
1) According to the layout of a CPLD bare chip PAD and a radio frequency bare chip control signal PAD, designing a silicon-based Fan-in structure;
2) Sputtering a metal layer on the CPLD bare chip, performing photoetching, and electroplating barrier metal on the PAD of the CPLD bare chip;
3) Forming a protection pad through photoetching, and removing the metal layers in other areas through corrosion;
4) Coating a first layer of PI glue, and photoetching to form a via hole 1 structure;
5) Sputtering a layer of seed layer metal, photoetching and electroplating to form an RDL1 wiring layer, and etching to remove the seed layer;
6) Coating a second layer of PI glue, and photoetching to form a via hole 2 structure;
7) Sputtering a layer of seed layer metal, and photoetching and electroplating to form an RDL2 wiring layer;
8) Photoresist coating, electroplating to form a UBM structure, and etching to remove the seed layer;
9) Coating a third layer of PI glue, and photoetching and windowing to expose the PAD structure;
10 Thinning the back of the CPLD wafer;
11 CPLD wafer dicing;
12 The CPLD silicon-based Fan-in structure is inverted and then stacked on the radio frequency bare chip through the micro bumps/micro columns to form a three-dimensional radio frequency chip structure.
According to the reconfigurable heterogeneous integrated three-dimensional radio frequency chip provided by the invention, the RDL reconfiguration wiring of the CPLD bare chip is realized by adopting a silicon-based Fan-in technology, and the three-dimensional heterogeneous integration between the CPLD bare chip and the radio frequency bare chip is realized by adopting a flip chip stacking technology. The CPLD bare chip has small volume, low power consumption, integrated FLASH memory on the chip, relatively fixed internal connection, small path delay and predictability, can work at higher frequency, has simple peripheral circuit, can realize complex combination logic circuit function and sequential logic circuit function through online programming, has flexible dynamic reconfigurable capability, and can meet various application scene requirements of the radio frequency chip; the CPLD can realize logic control of a control signal pin of the radio frequency bare chip through a programmable I/O pin; the radio frequency bare chip comprises but is not limited to GaAs, inP and other technologies, and has the functions of amplitude and phase control, frequency conversion, front end receiving and the like. The architecture of CPLD bare chip and radio frequency bare chip fully plays the reconfigurable capability of CPLD, and upgrades the original two-dimensional radio frequency bare chip into a three-dimensional radio frequency chip with on-line reconfigurable function. The programming interface signal of the CPLD bare chip is led out through the expansion PAD of the radio frequency bare chip, and can be interconnected with the system processor IO, the system processor carries out on-line programming on the CPLD through the programming interface, changes the CPLD function in real time, realizes the dynamic reconfiguration of the three-dimensional radio frequency chip, lays a foundation for the intellectualization of the whole radio frequency system, and does not need to carry out semiconductor streaming again in all operations. The whole three-dimensional radio frequency chip is realized based on a silicon-based three-dimensional isomerism integration process, and compared with a silicon-based heterogeneous integrated compound semiconductor process, the process difficulty is reduced, and the three-dimensional radio frequency chip has very strong innovation and engineering practicability.

Claims (5)

1. The reconfigurable heterogeneous integrated three-dimensional radio frequency chip comprises a CPLD bare chip and a radio frequency bare chip and is characterized by further comprising a silicon-based Fan-in structure, wherein the CPLD bare chip and the radio frequency bare chip are respectively arranged on two sides of the silicon-based Fan-in structure, a circuit of the silicon-based Fan-in structure is connected with a CPLD bare chip PAD, the circuit is connected with a radio frequency bare chip control signal PAD through RDL reconstruction wiring, the radio frequency bare chip further comprises an expansion PAD, and power/ground/programming interface signals of the CPLD bare chip are led out through the expansion PAD.
2. The reconfigurable heterogeneous integrated three-dimensional radio frequency chip according to claim 1, wherein the silicon-based Fan-in structure performs RDL reconfiguration wiring on the CPLD die according to a mirror image layout of a radio frequency die control signal PAD, and performs UBM Fan-out, and the UBM and the radio frequency die control signal PAD are interconnected through micro bumps/micro pillars.
3. The reconfigurable heterogeneous integrated three-dimensional radio frequency chip according to claim 1, wherein control signals PAD of the radio frequency bare chip are distributed on the inner side of the chip, external PAD and expansion PAD are distributed on the outer side of the chip, and part of the control signals PAD are led out to the expansion PAD through internal wiring.
4. The reconfigurable heterogeneous integrated three-dimensional radio frequency chip of claim 3, wherein the external PAD and the extended PAD of the radio frequency bare chip are interconnected by wire bonding and external signals.
5. A method of fabricating a reconfigurable heterogeneous integrated three-dimensional radio frequency chip of claim 1, comprising the steps of:
1) According to the layout of a CPLD bare chip PAD and a radio frequency bare chip control signal PAD, designing a silicon-based Fan-in structure;
2) Sputtering a metal layer on the CPLD bare chip, performing photoetching, and electroplating barrier metal on the PAD of the CPLD bare chip;
3) Forming a protection pad through photoetching, and removing the metal layers in other areas through corrosion;
4) Coating a first layer of PI glue, and photoetching to form a via hole 1 structure;
5) Sputtering a seed layer metal, photoetching and electroplating to form an RDL1 wiring layer, and etching to remove seed layers in other areas;
6) Coating a second layer of PI glue, and photoetching to form a via hole 2 structure;
7) Sputtering a layer of seed layer metal, and photoetching and electroplating to form an RDL2 wiring layer;
8) Photoresist coating, electroplating to form a UBM structure, and etching to remove seed layers in other areas;
9) Coating a third layer of PI glue, and photoetching and windowing to expose the PAD structure;
10 Thinning the back of the CPLD wafer;
11 CPLD wafer dicing;
12 The CPLD silicon-based Fan-in structure is inverted and then stacked on the radio frequency bare chip through the micro bumps/micro columns to form a three-dimensional radio frequency chip structure.
CN202311156676.5A 2023-09-08 2023-09-08 Reconfigurable heterogeneous integrated three-dimensional radio frequency chip and manufacturing method thereof Pending CN117080200A (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311156676.5A CN117080200A (en) 2023-09-08 2023-09-08 Reconfigurable heterogeneous integrated three-dimensional radio frequency chip and manufacturing method thereof

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CN117080200A true CN117080200A (en) 2023-11-17

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