CN117076127A

CN117076127A - Processing method, device and medium for calculation power scheduling

Info

Publication number: CN117076127A
Application number: CN202311104248.8A
Authority: CN
Inventors: 宋文平; 徐源浩; 郭敬宇
Original assignee: Zhengzhou Yunhai Information Technology Co Ltd
Current assignee: Zhengzhou Yunhai Information Technology Co Ltd
Priority date: 2023-08-30
Filing date: 2023-08-30
Publication date: 2023-11-17

Abstract

The invention discloses a processing method, a device and a medium for power calculation scheduling, which are suitable for the technical field of resource scheduling. According to the method, a fitting relation determined based on a performance test tool of an evaluation computer system is used under a cloud computing software cloud platform, computing nodes meeting a computing force request are filtered and selected in a filter by combining computing force ratio and specification information, target chip computing nodes corresponding to the maximum computing force value are selected for the computing nodes meeting the computing force request according to the fitting relation in a weighting device, the resource available domains of different chips are not required to be divided manually, and the chip computing nodes of different architectures are not required to be distinguished. In the batch creation of virtual machines, the calculation force balance of the virtual machines of the computer nodes with different structures is ensured through the calculation force value screening of the chips on different chips, and the customer business scene requirement is met.

Description

Processing method, device and medium for calculation power scheduling

Technical Field

The present invention relates to the field of resource scheduling technologies, and in particular, to a method, an apparatus, and a medium for processing power scheduling.

Background

With the rapid development of the central processing unit (Central Processing Unit, CPU) chip of the domestic architecture, the cloud computing software (OpenStack) cloud platform needs to nanotube computing nodes of different chip manufacturers to realize the balance of the computing power of the CPU. The OpenStack cloud platform consists of a series of cloud computing tools and services, various functions of the platform are used through application programming interface (Application Programming Interface, API) interfaces, the degree of freedom is high, and a user can configure each component in a self-defined mode to adapt to corresponding service requirements.

The current method for balancing the CPU calculation power is that users manually divide available domains, namely, the resource pool specification corresponding to the calculation nodes of different chip manufacturers is specified, and the calculation nodes of different architectures are distinguished to perform independent scheduling. In the pre-dividing process, the CPU calculation power corresponding to different models of each chip is different, the process of calculating different calculation powers in the artificial dividing is complicated, even errors occur, and the final CPU calculation power of each chip is unbalanced.

Therefore, how to implement balanced scheduling of CPU power of different chips is needed to be solved by those skilled in the art.

Disclosure of Invention

The invention aims to provide a processing method, a device and a medium for computing power scheduling, which are used for solving the problem of unbalanced CPU computing power of each chip caused by artificial division of available domains.

In order to solve the technical problems, the invention provides a processing method of power calculation scheduling, which comprises the following steps:

receiving creation specification information of a current cloud host;

the method comprises the steps that a filter based on a cloud computing software cloud platform screens according to the creation specification information, the fitting relation between the number of cores and the calculation force value of each chip calculation node at different chip calculation nodes to obtain initial chip calculation nodes, wherein the fitting relation is based on a fitting function determined by evaluating a computer system performance test tool and the number of cores and the calculation force value of the chip calculation nodes;

Screening out a target chip computing node corresponding to the maximum computing power value according to the fitting relation between the core number of each initial chip computing node and the computing power value based on the weighting device of the cloud computing software cloud platform;

and taking the target chip computing node as a scheduling specification of the current cloud host to realize computing power scheduling of the current cloud host.

In one aspect, the determining process of the fitting relation includes:

acquiring test indexes and corresponding weight parameters of the evaluation computer system performance test tool, wherein at least one of the number of the test indexes is determined based on model parameters of each chip computing node;

and determining the fitting relation according to the relation among the test index, the weight parameter and the core numbers of the chip computing nodes.

In another aspect, the determining the fitting relationship according to the test index, the weight parameter, and the relationship between the cores of the chip computing nodes includes:

acquiring test index parameters of the test indexes corresponding to the numbers of cores under the chip computing nodes;

determining a calculation force value corresponding to each core number according to each test index parameter and the corresponding weight parameter;

And determining a fitting relation corresponding to each chip computing node according to each core number and the corresponding computing force value.

On the other hand, the process for determining the calculation ratio value of each chip calculation node at different chip calculation nodes comprises the following steps:

taking one chip computing node of each chip computing node as a reference chip computing node, and taking the computing power of the reference chip computing node as a reference computing power;

and determining the calculation force ratio of the current chip calculation node relative to the reference chip calculation node according to the fitting relation of the chip calculation nodes and the reference calculation force, wherein the calculation force ratio is an integer ratio.

On the other hand, the step of screening according to the creation specification information, the fitting relation between the number of cores and the calculation force value of each chip calculation node at different chip calculation nodes to obtain an initial chip calculation node includes:

acquiring the calculation force demand value of the creation specification information;

taking a current chip computing node as a reference chip computing node, and determining a chip computing power threshold value of a chip type to which each chip computing node belongs according to the computing power requirement value and the computing power ratio of each chip computing node at the reference chip computing node of the current chip computing node;

Acquiring the current computing power of each chip computing node;

judging whether the current calculation force is larger than the chip calculation force threshold value of the same chip type;

if yes, taking the chip computing node which exceeds the chip computing power threshold and to which the current computing power belongs as the initial chip computing node.

On the other hand, the screening the target chip computing node corresponding to the maximum computing force value according to the fitting relation between the core number of each initial chip computing node and the computing force value includes:

determining a final calculation force value of each initial chip calculation node according to the core number of each initial chip calculation node and the fitting relation;

sorting the final calculation force value of each initial chip calculation node from big to small;

judging whether the sequenced initial chip computing nodes have the same final computing force value or not;

if the same final calculated force value exists, judging whether the initial chip calculation node to which the same final calculated force value belongs contains a first initial chip calculation node or not;

if the initial chip computing node comprises the first initial chip computing node, taking one of the initial chip computing nodes to which the same final computing force value belongs as the target chip computing node;

If the first initial chip computing node is not included, selecting the first initial chip computing node as the target chip computing node;

if the same final calculation force value does not exist, selecting a first initial chip calculation node as the target chip calculation node.

In another aspect, the creating specification information includes the calculation force requirement value and the memory requirement value, and the screening the target chip calculation node corresponding to the maximum calculation force value according to the fitting relation between the number of cores of each initial chip calculation node and the calculation force value includes:

acquiring the memory value of each initial chip computing node;

if the initial chip computing node comprises the first initial chip computing node, comparing the memory values of the initial chip computing nodes corresponding to the same final computing force value;

Taking an initial chip computing node which belongs to the largest memory value in the memory values of the initial chip computing nodes corresponding to the same final computing force value as the target chip computing node;

if the initial chip computing node does not contain the first initial chip computing node, taking the first initial chip computing node after sequencing as the target chip computing node;

and if the same final calculated force value does not exist, taking the first sequenced initial chip calculation node as the target chip calculation node.

In order to solve the technical problem, the invention also provides a processing device for computing power dispatching, which comprises:

the receiving module is used for receiving the creation specification information of the current cloud host;

the first screening module is used for screening the filter based on the cloud computing software cloud platform according to the creation specification information, the fitting relation between the core number of each chip computing node and the computing force value of each chip computing node at different chip computing nodes to obtain initial chip computing nodes, wherein the fitting relation is based on a fitting function determined by evaluating a computer system performance test tool and the core number and the computing force value of the chip computing nodes;

The second screening module is used for screening out a target chip computing node corresponding to the maximum computing force value according to the fitting relation between the core number of each initial chip computing node and the computing force value based on the weighting device of the cloud computing software cloud platform;

and the determining module is used for taking the target chip computing node as the scheduling specification of the current cloud host to realize the computing power scheduling of the current cloud host.

a memory for storing a computer program;

a processor for implementing the steps of the method of processing a power schedule as described above when executing the computer program.

To solve the above technical problem, the present invention further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the processing method for computing power scheduling as described above.

The invention has the beneficial effects that the processing method for the power calculation scheduling comprises the following steps: receiving creation specification information of a current cloud host; the method comprises the steps that a filter based on a cloud computing software cloud platform screens according to established specification information, fitting relations between the number of cores and the calculation force value of each chip calculation node and the calculation force value of each chip on different chips to obtain initial chip calculation nodes, wherein the fitting relations are based on a fitting function determined by evaluating a computer system performance test tool and the number of cores and the calculation force value of the chip calculation nodes; the weighting device based on the cloud computing software cloud platform screens out a target chip computing node corresponding to the maximum computing power value according to the fitting relation between the core number of each initial chip computing node and the computing power value; and taking the target chip computing node as a scheduling specification of the current cloud host to realize computing power scheduling of the current cloud host. According to the method, a fitting relation determined based on a performance test tool of an evaluation computer system is used under a cloud computing software cloud platform, computing nodes meeting a computing force request are filtered and selected in a filter by combining computing force ratio and specification information, target chip computing nodes corresponding to the maximum computing force value are selected for the computing nodes meeting the computing force request according to the fitting relation in a weighting device, the resource available domains of different chips are not required to be divided manually, and the chip computing nodes of different architectures are not required to be distinguished. In the batch creation of virtual machines, the calculation force balance of the virtual machines of the computer nodes with different structures is ensured through the calculation force value screening of the chips on different chips, and the customer business scene requirement is met.

The fitting relation determining process provided by the invention realizes the calculation force balance scheduling by utilizing the SPEC CPU testing tool, and can provide more accurate testing data based on the actual hardware range so as to obtain the fitting relation function of the corresponding CPU calculation force and core number; the determination process of the calculation ratio value is convenient for comparing with the residual CPU core number, and filtering out the calculation nodes of which the CPU does not meet the request; the initial chip computing node determines equal chip computing nodes with different chip types through the calculation ratio value, and filters computing nodes which do not meet the request by taking the chip calculation force threshold determined by the calculation ratio value as a standard through a filter, so that preliminary CPU calculation force balancing is realized; under the condition of the same maximum final calculation force value, compared with the condition that any chip calculation node is selected as a target chip calculation node, the embodiment further compares the memory value corresponding to the chip calculation node to determine the chip calculation node with the maximum memory value as the target chip calculation node, and diversity and authority are improved.

In addition, the invention also provides a processing device and a medium for the computational power scheduling, which have the same beneficial effects as the processing method for the computational power scheduling.

Drawings

For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a flowchart of a method for processing power schedule according to an embodiment of the present invention;

FIG. 2 is a schematic illustration of scheduling according to an embodiment of the present invention;

FIG. 3 is a block diagram of a processing device for power dispatch according to an embodiment of the present invention;

fig. 4 is a block diagram of another processing apparatus for power dispatch according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present invention.

The core of the invention is to provide a processing method, a device and a medium for power dispatching, so as to solve the problem of unbalanced CPU power of each chip caused by artificial division of available domains.

In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.

It should be noted that OpenStack is an open-source cloud computing platform, and aims to provide an infrastructure as a service (Infrastructure as a Service, iaaS) solution. The cloud computing system consists of a series of cloud computing tools and services, including computing, storage, network, identity verification and the like, and supports public cloud, private cloud, hybrid cloud, edge computing and other scenes. The platform employs a modular architecture, each module providing an API interface through which a user can use the various functions of OpenStack. The most core module is resource computing allocation (Nova), which provides functions such as creation, starting, stopping, deleting and the like of the virtual machine instance. In addition, openStack provides a plurality of modules such as an object store (Swift), a block store (Cinder), a network (neutral), an identity authentication (Keystone), a mirror image (Glance), a Web console (horizontal), and the like, so that the requirements of different users can be met. The invention utilizes the OpenStack cloud platform to realize balanced dispatching of the CPU computing power of the multi-architecture computing node.

Fig. 1 is a flowchart of a processing method of power scheduling according to an embodiment of the present invention, as shown in fig. 1, where the method includes:

s11: receiving creation specification information of a current cloud host;

s12: the method comprises the steps that a filter based on a cloud computing software cloud platform is used for screening according to established specification information, fitting relations between the core number and the calculation force value of each chip calculation node and calculation force values of each chip calculation node at different chip calculation nodes to obtain initial chip calculation nodes;

the fitting relation is based on a fitting function determined by the number of cores and the calculated force value of the computing node of the chip of the evaluating computer system performance testing tool;

s13: the weighting device based on the cloud computing software cloud platform screens out a target chip computing node corresponding to the maximum computing power value according to the fitting relation between the core number of each initial chip computing node and the computing power value;

s14: and taking the target chip computing node as a scheduling specification of the current cloud host to realize computing power scheduling of the current cloud host.

Specifically, the current creation specification information of the cloud host is received, and the request resource for the cloud host may be set by the user or may be obtained according to the actual situation, for example, the request resource is as follows:

Req：core＝4C，ram＝16G；

Indicating that the cloud host requires 4 CPU computing power, 16G memory.

The creation specification information may include one information parameter, i.e., calculation force, or may include two or more information parameters, i.e., calculation force, memory, and the like. The present invention is not limited to this, and may be set according to actual conditions.

Fig. 2 is a schematic scheduling diagram provided in the embodiment of the present invention, as shown in fig. 2, a core module Nova of an OpenStack cloud platform is adopted, and a controller calls and creates a virtual machine in an application programming interface, in this embodiment, calls for a cloud host, and corresponds different computing nodes to the cloud host, so as to implement computation force balancing corresponding to created batch cloud hosts, where the computation force balancing may be the same or equal, as long as computation forces of different cloud hosts have little difference. The controller invokes the compute nodes in the scheduler while the scheduler finds and obtains the corresponding candidate nodes in the resource pool. And screening by a computational power filter in the scheduler to obtain an initial chip computing node, and screening by a computational power weighting device to obtain a target chip computing node. And returning the target chip computing node to the controller of the dispatching host, and further creating a virtual machine to computing node service by the controller in combination with the target chip computing node.

The method comprises the following specific steps:

s21: creating a virtual machine;

s22: scheduling the computing nodes;

s23: obtaining candidate nodes;

s24: the calculation force filter screens to obtain an initial chip calculation node;

s25: the computing power weighting device screens to obtain a target chip computing node;

s26: returning to the dispatching host;

s27: a virtual machine is created.

It should be noted that, the filtering and screening policy is to consider out computing nodes that do not meet the request, or the hosts that are required precisely, leaving a set of hosts that meet the filtering algorithm. For the weight calculated by the weighting device, the consumption cost necessary for applying the virtual machine on a certain physical node is calculated by a specified weight calculation algorithm. The less the physical node is suitable for the virtual machine, the greater the consumption cost, the greater the weight, and the scheduling algorithm will select the host with the smallest weight. In the invention, the maximum value is selected from the computing node cluster obtained through weight calculation, and the computing power maximum value is used as the optimal computing power node for creating the virtual machine.

A specific filter screening strategy may be screened by one of the following means:

1. filtering the host according to the CPU number;

2. selecting a host with sufficient resources according to the specified random access memory (Random Access Memory, RAM) value;

3. Returning to a host in the cluster designated by the virtual machine parameter;

4. the hosts are selected according to rules specified by a check formatting tools (JSON) string.

With respect to the weight calculation function, the more the host has the remaining memory, the smaller the weight, the greater the likelihood of being selected to create a virtual machine thereon.

And filtering according to the established specification information, the fitting relation between the core number of each chip computing node and the calculation force value of each chip computing node at different chip computing nodes based on the filter of the cloud computing software cloud platform to obtain initial chip computing nodes. The core numbers of the calculation nodes of the chips are relatively different, so that the core numbers of the calculation nodes of the chips are equivalent in order to realize balanced scheduling of the CPU calculation power. However, the chip computing nodes of different chip types with the same core number have different equalities, for example, the 4 cores of the intel node are different from the 4 cores of the Feiteng node, the 4 cores of the intel node need the computing power of the Feiteng node to be more than the 4 cores, and a chip computing node with relative reference needs to be found to calculate the computing power ratio of the other chip relative to the reference chip computing node. And for the screening of each computational effort, the computational node meeting the request is found on the basis of the computational effort threshold of the current different chip types.

The fit relationship between the number of cores and the calculated force value for each chip computing node is a fit function between the number of cores and the calculated force value for the chip computing node based on evaluating test parameters of a computing system performance test tool (SPEC CPU). SPEC CPU is an industry standard set of CPU-intensive benchmarking suite. SPEC designed this suite to provide a comparative measure of computationally intensive performance across the broadest range of practical hardware using the workload of actual user application development. The test mode is divided into a rate test and a speed test, wherein the rate test mainly measures the multi-concurrent operation processing performance of the system, namely the multi-line in common, and the speed test mainly measures the single-task processing performance of the system, namely the single line in common. The SPEC CPU testing tool is used for testing the testing index parameters under different core numbers of different chip computing nodes. The comprehensive calculation power of the CPU under different core numbers can be obtained by carrying out weighted summation according to the test index parameters, based on the test result, along with the increase of the core number of the CPU, the calculation power value increase area of the calculation node is relaxed, the logarithmic increase trend is presented, and the corresponding fitting function can be determined according to the increase curve.

The method for determining the fitting function by the growth curve is not limited herein, and may be set according to actual situations.

Regarding the weighting device based on the cloud computing software cloud platform in the step S13, the target chip computing node corresponding to the maximum computing force value is selected according to the fitting relation between the core number of each initial chip computing node and the computing force value. And (3) screening the maximum calculated force value, namely obtaining a corresponding calculated force value, namely a residual calculated force value, based on the fitting relation between the core number of the initial chip calculation node screened in the step (S12) and the calculated force value, and finding a target chip calculation node corresponding to the maximum calculated force value according to the residual calculated force value. And taking the target chip computing node as a scheduling specification of the current cloud host to realize computing power scheduling of the current cloud host. It should be noted that, in the chip computing node, only different chips are used as the computing node, and each chip may be a chip with a different architecture, such as intel, sea light, feiteng, spread, etc., which is not limited herein.

The processing method for computing power scheduling provided by the embodiment of the invention comprises the following steps: receiving creation specification information of a current cloud host; the method comprises the steps that a filter based on a cloud computing software cloud platform screens according to established specification information, fitting relations between the number of cores and the calculation force value of each chip calculation node and the calculation force value of each chip on different chips to obtain initial chip calculation nodes, wherein the fitting relations are based on a fitting function determined by evaluating a computer system performance test tool and the number of cores and the calculation force value of the chip calculation nodes; the weighting device based on the cloud computing software cloud platform screens out a target chip computing node corresponding to the maximum computing power value according to the fitting relation between the core number of each initial chip computing node and the computing power value; and taking the target chip computing node as a scheduling specification of the current cloud host to realize computing power scheduling of the current cloud host. According to the method, a fitting relation determined based on a performance test tool of an evaluation computer system is used under a cloud computing software cloud platform, computing nodes meeting a computing force request are filtered and selected in a filter by combining computing force ratio and specification information, target chip computing nodes corresponding to the maximum computing force value are selected for the computing nodes meeting the computing force request according to the fitting relation in a weighting device, the resource available domains of different chips are not required to be divided manually, and the chip computing nodes of different architectures are not required to be distinguished. In the batch creation of virtual machines, the calculation force balance of the virtual machines of the computer nodes with different structures is ensured through the calculation force value screening of the chips on different chips, and the customer business scene requirement is met.

Based on the above embodiments, in some embodiments, the determining process of the fitting relation includes:

acquiring test indexes and corresponding weight parameters of a performance test tool of the evaluation computer system, wherein at least one of the number of the test indexes is determined based on model parameters of computing nodes of each chip;

and determining a fitting relation according to the relation among the test indexes, the weight parameters and the core numbers of the calculation nodes of each chip.

Specifically, the test index and the corresponding weight parameter of the SPEC CPU test tool are obtained, the weight parameter is the number of the weight parameters set according to the number of the test indexes, and in addition, the weight parameter is determined based on the model parameters of the calculation nodes of each chip.

For example, the test indexes for testing different chip computing nodes are respectively: integer data computation rate (SPECrate 2017 inter), integer data IO processing rate (specpeed 2017 inter), floating Point data computation rate (SPECrate 2017Floating Point), floating Point data IO processing rate (specpeed 2017Floating Point). Of course, other test indexes are also possible, and the test indexes mentioned as examples in this embodiment are just one embodiment. The specific value of the weight parameter may be set according to the actual situation, if the chip computing node pays attention to the integer data, the weight corresponding to the integer data computing rate and the integer data IO processing rate is larger, and if the chip computing node pays attention to the computing rate, the weight corresponding to the integer data computing rate and the floating point data computing rate is increased. And (3) summing up the weight parameters corresponding to the four test indexes to be 1.

The comprehensive calculation force of the CPU is calculated according to a weighted mode, and the formula is as follows:

total force = a x w1+b x w2+c x w3+d x w4;

wherein A is integer data computing rate, B is integer data IO processing rate, C is floating point data computing rate, D is floating point data IO processing rate, and w1, w2, w3 and w4 are weight parameters corresponding to the test indexes.

In some embodiments, determining the fit relationship from the relationship between the test index, the weight parameter, and the number of cores of each chip computing node comprises:

acquiring test index parameters of test indexes corresponding to the number of cores under each chip computing node;

Specifically, the fitting relation is determined according to the relation among the test index, the weight parameter and the core numbers of the chip computing nodes, that is, since one chip computing node comprises a plurality of cores, the computing force value corresponding to each core number is determined according to the test index parameter corresponding to the test index under different cores, and the weight parameter corresponding to the test index parameter is set at the same time. And determining the fitting relation of the calculation nodes of each chip according to the calculation force value corresponding to each core and the number of each core, namely, obtaining the corresponding coordinate function, namely, the fitting relation according to a plurality of (x, y).

For example: through test results, the calculation power value of the calculation node tends to be mild and shows logarithmic growth trend along with the increase of the CPU core number. The fitting relation function of CPU calculation force and core number on intel node is: y=10.84+44.19 lnx (x > =1), the fitted relation function of the CPU calculation force and the number of cores on the Feiteng node is: y=2.19+37.84 lnx (x > =1), where x is the number of cores configured by the SPEC CPU test tool and y is the calculated force value corresponding to the node.

It should be noted that, the specific fitting relation function mentioned in the present invention is only a function relation of the chip computing node under one model, and the function relation of the chip computing node of different models but the same manufacturer has the same solving mode, and only specific function parameters are different.

The fitting relation determining process provided by the embodiment of the invention realizes the balanced dispatching of calculation force by using the SPEC CPU testing tool, and can provide more accurate testing data based on the actual hardware range so as to obtain the fitting relation function of the corresponding CPU calculation force and core number.

On the basis of the above embodiments, in some embodiments, the determining process of the calculation ratio value of each chip calculation node at different chip calculation nodes includes:

Taking one chip computing node of each chip computing node as a reference chip computing node, and taking the computing force of the reference chip computing node as a reference computing force;

and determining the calculated force ratio of the current chip calculation node relative to the reference chip calculation node according to the fitting relation of the chip calculation nodes and the reference calculated force, wherein the calculated force ratio is an integer ratio.

Specifically, among the chip computing nodes of a plurality of different manufacturers, one chip computing node is used as a reference chip computing node, and the computing power of the reference chip computing node is used as a reference computing power. Determining the calculation force ratio of the current chip calculation node according to the reference chip calculation node and the reference calculation force, combining the above example, wherein the intel chip calculation node is taken as the reference chip calculation node, the corresponding calculation force mapping core number is 4, and when the Feiteng chip calculation node is reached, the corresponding calculation force mapping core number formula is as follows: req_core= (10.84+44.19ln4)/(2.19+37.84 lnx), where x is the number of cores corresponding to the calculation node of the Feiteng chip.

If the remainder exists in the obtained calculated force ratio, the calculated force ratio is rounded so as to be used as a threshold value of the calculation node.

The core number ratio in this embodiment is actually a calculation ratio.

The determination process of the calculation ratio value provided by the embodiment of the invention is convenient for comparing with the residual CPU core number, and filtering out the calculation nodes of which the CPU does not meet the request.

Based on the above embodiments, in some embodiments, the step S12 of screening the calculation ratio values of the chip calculation nodes at different chip calculation nodes according to the creation specification information, the fitting relation between the core number and the calculation force value of each chip calculation node, includes:

acquiring an calculation force demand value of the creation specification information;

taking the current chip computing node as a reference chip computing node, and determining a chip computing power threshold value of a chip type to which each chip computing node belongs according to a computing power demand value and a computing power ratio of each chip computing node at the reference chip computing node of the current chip computing node;

acquiring the current computing power of each chip computing node;

judging whether the current calculation force is larger than a chip calculation force threshold value of the same chip type;

if yes, taking the chip computing node which exceeds the current computing power threshold value of the chip computing power as an initial chip computing node.

Specifically, the current chip computing node is used as a reference chip computing node, and the chip computing force threshold value of the chip type of each chip computing node is determined according to the computing force demand value and the corresponding computing force ratio value. That is, there is a chip calculation threshold for each chip type corresponding to each chip calculation node. Under the same chip type, comparing the current computing power with a chip computing power threshold, and filtering out the current computing power if the current computing power is smaller than the chip computing power threshold, wherein only the chip computing node of the current computing power exceeding the chip computing power threshold is reserved as an initial chip computing node.

According to the initial chip computing node provided by the embodiment of the invention, the equal chip computing nodes with different chip types are determined through the calculation ratio value, and then the computing nodes which do not meet the request are filtered by using the chip calculation force threshold determined by the calculation ratio value as a standard through the filter, so that the preliminary CPU calculation force balancing is realized.

In some embodiments, the step of screening out the target chip computing node corresponding to the maximum computing force value according to the fitting relation between the core number of each initial chip computing node and the computing force value includes:

determining a final calculation force value of each initial chip calculation node according to the core number and the fitting relation of each initial chip calculation node;

sorting the final calculation force values of the calculation nodes of all the initial chips from big to small;

if the initial chip computing node comprises the first initial chip computing node, taking one of the initial chip computing nodes to which the same final computing force value belongs as a target chip computing node;

If the first initial chip computing node is not included, selecting the first initial chip computing node as a target chip computing node;

if the same final calculation force value does not exist, selecting the first initial chip calculation node as a target chip calculation node.

It can be understood that the target chip computing node in this embodiment is determined only by means of the computing power value, and the computing node with the largest CPU computing power is screened out from the clusters of different initial chip computing nodes to create the virtual machine. The final calculation force value of each initial chip calculation node is determined, and the calculation process is the same as that of the embodiment. And sequencing the final calculation force values, if the maximum final calculation force value comprises a plurality of initial chip calculation nodes, selecting one of the initial chip calculation nodes as a target chip calculation node, and if the initial chip calculation node corresponding to the maximum final calculation force value is only one of the initial chip calculation nodes as the target chip calculation node.

Judging whether the sequenced initial chip computing nodes have the same final computing force value or not; if the same final calculated force value exists, judging whether the initial chip calculation node to which the same final calculated force value belongs contains a first initial chip calculation node or not; if the initial chip computing node comprises the first initial chip computing node, taking one of the initial chip computing nodes to which the same final computing force value belongs as a target chip computing node; if the first initial chip computing node is not included, selecting the first initial chip computing node as a target chip computing node; if the same final calculation force value does not exist, selecting the first initial chip calculation node as a target chip calculation node.

For example: when the intel computing node is screened, the residual quantity of CPU cores is m1, the weighted residual quantity of cores remain_core 1=10.84+44.19ln (m 1), when the Feiteng computing node is screened, the residual quantity of CPU cores is m3, the weighted residual quantity of cores remain_core 3=2.19+37.84ln (m 3), finally, the maximum value is selected from the intel computing node cluster and the Feiteng computing node cluster, and the corresponding computing node creates a virtual machine for the optimal computing node.

First, two computing nodes node1 and node2 are prepared, node1 being an intel architecture, in which a CPU (48 cores) and a memory (256G) are provided. node2 is a Feiteng architecture in which the CPU (64 cores), the memory (256G). Second, 2 virtual machines of 4C16G specification are created in batches. When the 1 st virtual machine is scheduled, node1 and node2 both meet the calculation force request, the calculation force weight is the same, and one of node1 and node2 is selected to create a 4C16G virtual machine; if both node1 and node2 satisfy the calculation request, node1 calculates less force than node2, and node2 is selected to create a 6C16G virtual machine.

When the 1 st virtual machine is scheduled, node1 and node2 both meet the calculation force request, the calculation force weight is the same, and node1 is selected to create a 4C16G virtual machine; when the 2 nd virtual machine is scheduled, both node1 and node2 meet the calculation force request, the calculation force of node1 is smaller than that of node2, and node2 is selected to create a 6C16G virtual machine. It is worth noting that the chip computing nodes scheduled in each virtual machine can be the same or different, and only the appropriate scheduling chip computing node is selected from the current virtual machine, so that the CPU computing power is relatively balanced.

In some embodiments, determining that the target chip computing node creates specification information including a computing power requirement value and a memory requirement value according to two reference values of computing power and memory, and screening a target chip computing node corresponding to a maximum computing power value according to a fitting relation between the number of cores of each initial chip computing node and the computing power value, including:

acquiring the memory value of each initial chip computing node;

taking an initial chip computing node which is the largest memory value in the memory values of the initial chip computing nodes corresponding to the same final computing force value as a target chip computing node;

If the first initial chip computing node is not included, the first initial chip computing node after sequencing is used as a target chip computing node;

and if the same final calculated force value does not exist, taking the first initial chip calculation node after sequencing as a target chip calculation node.

Specifically, judging whether the same final calculation force value exists in each initial chip calculation node after sequencing; when the same final computing force value exists, judging whether the initial chip computing node to which the same final computing force value belongs contains a first initial chip computing node, namely whether the largest final computing force value contains a plurality of initial chip computing nodes or not, if so, comparing according to the memory values to determine the initial chip computing node to which the largest memory value corresponds in the memory values as a target chip computing node, and if not, selecting the first initial chip computing node as the target chip computing node, wherein the first initial chip computing node is selected as the target chip computing node under the conditions that the first initial chip computing node is not contained and the same final computing force value does not exist.

Compared with the case of selecting any chip computing node as the target chip computing node under the condition of the same maximum final computing power value, the embodiment of the invention further compares the memory value corresponding to the chip computing node to determine the chip computing node with the largest memory value as the target chip computing node, thereby improving diversity and authority.

The invention further discloses a processing device of the power calculation scheduling corresponding to the method, and fig. 3 is a structural diagram of the processing device of the power calculation scheduling provided by the embodiment of the invention. As shown in fig. 3, the processing device for power dispatch includes:

a receiving module 11, configured to receive creation specification information of a current cloud host;

the first screening module 12 is configured to screen, based on a filter of the cloud computing software cloud platform, according to the creation specification information, a fitting relation between the number of cores and the calculation force value of each chip calculation node, and the calculation force values of each chip calculation node at different chip calculation nodes to obtain an initial chip calculation node, where the fitting relation is based on a fitting function determined by evaluating a performance test tool of the computer system, and the number of cores and the calculation force value of the chip calculation node;

the second screening module 13 is configured to screen out a target chip computing node corresponding to the maximum computing power value according to a fitting relationship between the core number of each initial chip computing node and the computing power value based on a weighting device of the cloud computing software cloud platform;

the determining module 14 is configured to take the target chip computing node as a scheduling specification of the current cloud host to implement computing power scheduling of the current cloud host.

In some embodiments, the process of determining the fit relationship in the first screening module 12 includes:

the first acquisition module is used for acquiring test indexes of the performance test tool of the evaluation computer system and corresponding weight parameters, wherein at least one of the number of the test indexes is determined based on model parameters of the computing nodes of each chip;

and the first determining submodule is used for determining a fitting relation according to the relation among the test indexes, the weight parameters and the core numbers of the calculation nodes of each chip.

In some embodiments, the first determination submodule includes:

the second acquisition module is used for acquiring test index parameters of the test indexes corresponding to the number of cores under each chip computing node;

the second determining submodule is used for determining a calculation force value corresponding to each core number according to each test index parameter and the corresponding weight parameter;

and the third determination submodule is used for determining the fitting relation corresponding to each chip computing node according to each core number and the corresponding computing force value.

In some embodiments, the determining the calculation ratio value of each chip calculation node in the first screening module 12 at a different chip calculation node includes:

the first module is used for taking one chip computing node of each chip computing node as a reference chip computing node and taking the computing power of the reference chip computing node as a reference computing power;

And the fourth determination submodule is used for determining the calculation force ratio of the current chip calculation node relative to the reference chip calculation node according to the fitting relation of the chip calculation nodes and the reference calculation force, wherein the calculation force ratio is an integer ratio.

In some embodiments, the first screening module 12 includes:

the third acquisition module is used for acquiring the calculation force demand value of the creation specification information;

a fifth determining sub-module, configured to determine a chip computing power threshold of a chip type to which each chip computing node belongs according to a computing power requirement value and a computing power ratio of each chip computing node at a reference chip computing node of the current chip computing node by using the current chip computing node as the reference chip computing node;

the fourth acquisition module is used for acquiring the current computing power of each chip computing node;

the first judging module is used for judging whether the current calculation force is larger than a chip calculation force threshold value of the same chip type; if yes, triggering a second serving as a module;

and the second module is used for taking the chip computing node to which the current computing force exceeding the chip computing force threshold value belongs as an initial chip computing node.

In some embodiments, the second screening module 13 includes:

the sixth determining submodule is used for determining a final calculation force value of each initial chip calculation node according to the number of cores of each initial chip calculation node and the fitting relation;

The first ordering module is used for ordering the final calculation force value of each initial chip calculation node from large to small;

the second judging module is used for judging whether the sequenced initial chip computing nodes have the same final computing force value or not; if the same final calculation force value exists, triggering a third judging module, and if the same final calculation force value does not exist, triggering a third serving as a module;

the third judging module is used for judging whether the initial chip computing nodes to which the same final computing force value belongs contain the first initial chip computing node or not; triggering a fourth serving as a module if the first initial chip computing node is included, and triggering a fifth serving as a module if the first initial chip computing node is not included;

fourth, as a module, for taking one of the initial chip computing nodes to which the same final computing force value belongs as a target chip computing node;

fifthly, the first initial chip computing node is used as a target chip computing node;

and thirdly, a module is used for selecting the first initial chip computing node as a target chip computing node.

In some embodiments, the creation specification information includes a computational power requirement and a memory requirement, and the second filtering module 13 includes:

A seventh determining submodule, configured to determine a final calculation force value of each initial chip calculation node according to the number of cores of each initial chip calculation node and the fitting relation;

a fifth obtaining module, configured to obtain a memory value of each initial chip computing node;

the second ordering module is used for ordering the final calculation force value of each initial chip calculation node from large to small;

the fourth judging module is used for judging whether the sequenced initial chip computing nodes have the same final computing force value or not; if the same final calculation force value exists, triggering a fifth judging module, and if the same final calculation force value does not exist, triggering a sixth serving as a module;

a fifth judging module, configured to judge whether the initial chip computing nodes to which the same final computing power value belongs include a first initial chip computing node; if the first initial chip computing node is included, triggering a comparison module, and if the first initial chip computing node is not included, triggering a seventh serving as a module;

the comparison module is used for comparing the memory values of the initial chip computing nodes corresponding to the same final computing force value;

eighth, as a module, the initial chip computing node to which the largest memory value in the memory values of the initial chip computing nodes corresponding to the same final computing force value belongs is used as a target chip computing node;

Seventh, the first initial chip computing node after sorting is used as a target chip computing node;

and the sixth module is used for taking the first initial chip computing node after sequencing as a target chip computing node.

Since the embodiments of the device portion correspond to the above embodiments, the embodiments of the device portion are described with reference to the embodiments of the method portion, and are not described herein.

For the description of the processing device for computing power scheduling provided by the present invention, please refer to the above method embodiment, the present invention is not described herein again, and the processing device for computing power scheduling has the same advantages as the above processing method for computing power scheduling.

Fig. 4 is a block diagram of another processing apparatus for power scheduling according to an embodiment of the present invention, as shown in fig. 4, where the apparatus includes:

a memory 21 for storing a computer program;

a processor 22 for implementing the steps of the processing method of the computational power scheduling when executing the computer program.

The processing device for computing power scheduling provided in this embodiment may include, but is not limited to, a tablet computer, a notebook computer, a desktop computer, or the like.

Processor 22 may include one or more processing cores, such as a 4-core processor, an 8-core processor, or the like, among others. The processor 22 may be implemented in hardware in at least one of a digital signal processor (Digital Signal Processor, DSP), a Field programmable gate array (Field-Programmable Gate Array, FPGA), a programmable logic array (Programmable Logic Array, PLA). The processor 22 may also include a main processor, which is a processor for processing data in an awake state, also referred to as a central processor (Central Processing Unit, CPU), and a coprocessor; a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 22 may be integrated with an image processor (Graphics Processing Unit, GPU) for use in responsible for rendering and rendering of content required for display by the display screen. In some embodiments, the processor 22 may also include an artificial intelligence (Artificial Intelligence, AI) processor for processing computing operations related to machine learning.

Memory 21 may include one or more computer-readable storage media, which may be non-transitory. Memory 21 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 21 is at least used for storing a computer program 211, where the computer program is loaded and executed by the processor 22 to implement the relevant steps of the method for processing power scheduling disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 21 may further include an operating system 212, data 213, and the like, and the storage manner may be transient storage or permanent storage. The operating system 212 may include Windows, unix, linux, among other things. The data 213 may include, but is not limited to, data related to the processing method of the computational power schedule, and the like.

In some embodiments, the processing device for power dispatch may further include a display 23, an input/output interface 24, a communication interface 25, a power supply 26, and a communication bus 27.

Those skilled in the art will appreciate that the structure shown in fig. 4 is not limiting of the processing means for computing the force schedule and may include more or fewer components than illustrated.

The processor 22 implements the processing method of the computational power scheduling provided in any of the above embodiments by calling instructions stored in the memory 21.

Further, the present invention also provides a computer readable storage medium having a computer program stored thereon, which when executed by the processor 22 implements the steps of the method of processing computational power scheduling as described above.

It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium for performing all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

For an introduction to a computer readable storage medium provided by the present invention, please refer to the above method embodiment, the present invention is not described herein, and the method has the same advantages as the above processing method for computing power scheduling.

The method for processing the power calculation scheduling, the device for processing the power calculation scheduling and the medium provided by the invention are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.

It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Claims

1. A method of processing power dispatch, comprising:

receiving creation specification information of a current cloud host;

2. The method for processing power schedule according to claim 1, wherein the determining of the fitting relation includes:

3. The method according to claim 2, wherein determining the fitting relationship according to the relationship among the test index, the weight parameter, and the cores of the chip computing nodes comprises:

4. The method according to claim 1, wherein the determining the calculation ratio value of each of the chip calculation nodes at different chip calculation nodes comprises:

5. The method for processing power scheduling according to any one of claims 1 to 4, wherein the step of screening the power ratio values of the chip computing nodes at different chip computing nodes to obtain initial chip computing nodes according to the creation specification information, the fitting relation between the number of cores of each chip computing node and the power value, includes:

acquiring the current computing power of each chip computing node;

6. The method for processing power schedule according to claim 5, wherein said screening out the target chip computing node corresponding to the maximum power value according to the fitting relation between the number of cores of each of the initial chip computing nodes and the power value comprises:

7. The method according to claim 5, wherein the creating specification information includes the calculation force requirement value and the memory requirement value, and the selecting the target chip calculation node corresponding to the maximum calculation force value according to the fitting relation between the number of cores of each initial chip calculation node and the calculation force value includes:

acquiring the memory value of each initial chip computing node;

8. A processing apparatus for power dispatch, comprising:

9. A processing apparatus for power dispatch, comprising:

a memory for storing a computer program;

A processor for implementing the steps of the method of processing a power schedule according to any one of claims 1 to 7 when executing said computer program.

10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the method of processing a power schedule according to any of claims 1 to 7.