CN117075664A - 1.4V-6.5V input high power supply rejection ratio ultra-low noise voltage stabilizing device and system - Google Patents
1.4V-6.5V input high power supply rejection ratio ultra-low noise voltage stabilizing device and system Download PDFInfo
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Abstract
A1.4V-6.5V input high power supply rejection ratio ultra-low noise voltage stabilizing device and system comprises an input module, a power supply overcurrent protection module, an error amplification module, a reference control amplification module, a logic control module, a thermal protection module, a drive control module and an output module, wherein an input power supply is input into an LDO circuit through the input module and is output by the output module after being processed; the power supply overcurrent protection module is connected with the logic control module and the drive control module; the output end of the reference control amplification module is connected with the logic control module through a MOS tube; the input end of the error amplifying module is integrated with a grounding capacitor, and the output end of the error amplifying module is connected with the driving control module. According to the application, a JEFT structure is introduced into an input transistor of an error amplification module, so that the LDO circuit serving as a power management system can reduce noise and ensure small influence on overall performance, and the JEFT structure is integrated into a grounding capacitor at an input end to realize filtering of high-frequency noise and realize rapid transient response.
Description
Technical Field
The application relates to the technical field of power management, in particular to an ultra-low noise voltage stabilizing device and system with high power supply rejection ratio and 1.4V-6.5V input.
Background
With the advancement of modern information technology, mobile communication devices are rapidly changing. The low dropout linear regulator (LDO) is one of the important circuits of a power management system, also called a low dropout voltage regulator, is one of the linear DC voltage regulators, is used for providing a stable DC voltage power supply, and is applied to various fields of communication and infrastructure, medical treatment and health care, industry, instruments and the like, in particular to the power management circuits in mobile communication equipment and electronic equipment, such as mobile phones, tablet computers, cameras and the like. Compared with a general linear direct current voltage stabilizer, the LDO can work under the condition of smaller output-input voltage difference, has the characteristics of low cost, low power consumption, small volume, high precision and the like, becomes one of the most widely applied chips, and is sufficiently developed. For example, the application CN106385100a discloses an LDO circuit, which sets a gating structure in a dual power supply system to select any power supply in the dual power supply system to supply power to the inside of a chip, and simultaneously, detects surge voltage to turn off the dual power supply, so as to achieve safe power supply. The application CN110492556A discloses a system for outputting stable voltage when the battery is low in power by LDO voltage reduction and DC-DC voltage boosting, and by the scheme provided by the application, the battery can still normally output 3.3V for power supply when the battery is low in voltage below 3.3V, the residual electric quantity of the electric quantity can be discharged, the service life of the electric quantity of the battery is prolonged, the service time is prolonged, the user experience is good, and meanwhile, the circuit cost can be reduced.
The 5G age has come, and the mobile communication device has a shorter period of alternation, and the clock frequency requirements for IC systems have also increased significantly. LDOs as power management systems often require driving ultra-high speed digital integrated circuits, whose load current tends to vary in very short times. The conventional LDO device is only required to improve the transient response of the circuit by the charge and discharge process of the load capacitor, if the capacitance is smaller, the transient response is worse, if the capacitance is larger, the integration is not facilitated, and it is difficult to achieve low noise and high power supply rejection ratio in the LDO chip while achieving the fast transient response, so the prior art needs to be improved.
Disclosure of Invention
The application aims to provide a low-voltage ultra-low noise voltage regulator (LDO) which is optimized for fast transient response, has an operating voltage range of 1.4V to 6.5V and can support 3A output current (voltage drop of 140 mV). The high output current LDO of the present application is well suited for voltage regulation of high performance analog and mixed signal circuits operating with power rails ranging from 6V to as low as 1.2V. By means of an advanced proprietary architecture, in a specific error amplification module, compared with the traditional operational amplifier designed by adopting a CMOS device, the application provides that the first-stage operational amplifier adopts a JEFT form to reduce noise, and meanwhile, in order to meet the requirement that the gain is large enough to ensure the clamp potential, the second-stage operational amplifier adopts a circuit form of a Cascode to provide high gain, so that the stability of output voltage and high power supply rejection ratio under the condition of meeting low noise are realized, and based on the whole design of the circuit, for load transient response, a current control technology is provided, Q2 is controlled through a logic control module, and a release channel is provided during current conversion, so that the load capacitor can realize quick transient response by using a small output capacitor. The device can provide high power supply rejection ratio and low noise, and can realize excellent voltage and load transient response by using only a small ceramic output capacitor.
The application provides an ultralow noise voltage stabilizing device with a high power supply rejection ratio of 1.4V-6.5V input, which comprises an LDO circuit, wherein the LDO circuit comprises an input module, a power supply overcurrent protection module, an error amplification module Ref1, a reference control amplification module Ref2, a logic control module, a thermal protection module, a drive control module and an output module, wherein an input power supply is input into the LDO circuit through the input module and is output by the output module after being processed; the power supply overcurrent protection module is connected with the logic control module and the drive control module; the output end of the reference control amplification module Ref2 is connected with the logic control module through an MOS tube; the input end of the error amplification module Ref1 is integrated with a grounded capacitor, and the output end of the error amplification module Ref1 is connected with the driving control module.
Furthermore, the output end of the thermal protection module is connected with the input end of the logic control module to realize overheat protection control, so that a signal can be input into the logic control module through the reference control amplification module Ref2 to control the on/off of the whole chip.
Further, the circuit further comprises a bleeder transistor Q2, wherein the drain electrode of the bleeder transistor Q2 is connected with the output module through a current limiting resistor Rdis, and the grid electrode of the bleeder transistor Q2 is connected with the output end of the logic control module; and/or
The circuit also comprises a compensation transistor Q1, wherein the grid electrode of the compensation transistor Q1 is connected with the output end of the driving control module, the drain electrode of the compensation transistor Q is connected with the input module through a resistor, and the source electrode of the compensation transistor Q is connected with the output module.
Further, the compensation transistor Q1 and the bleeder transistor Q2 are NMOS transistors.
Further, schottky diodes are integrated on the compensation transistor Q1 and the bleeder transistor Q2 for current protection.
Furthermore, the error amplification module Ref1 is formed by two-stage amplification and comprises a noise reduction module and a gain module, wherein the noise reduction module is used as a first stage and is connected with the gain module used as a second stage.
Further, the noise reduction module comprises input tubes M1 and M2, PMOS tubes M7, M8, M9 and M10, and NMOS tubes M3, M4, M5 and M6; the drains of the input transistors M1 and M2 are connected to the sources of the NMOS transistors M3 and M4, the sources of the NMOS transistors M3 and M4 are connected to the drains of the NMOS transistors M5 and M6, the drains of the NMOS transistors M3 and M4 are connected to the drains of the PMOS transistors M7 and M8, the sources of the PMOS transistors M7 and M8 are connected to the drains of the PMOS transistors M9 and M10, the gate of the NMOS transistor M3 is connected to the voltage signal Vb3, the gate of the voltage signal Vb3 is connected to the gate of the NMOS transistor M4, the gate of the voltage signal Vb 5 is connected to the voltage signal Vb4, the gate of the voltage signal Vb4 is connected to the gate of the NMOS transistor M6, the gate of the PMOS transistor M7 is connected to the voltage signal Vb2, the gate of the voltage signal Vb2 is connected to the gate of the PMOS transistor M8, the gate of the PMOS transistor M9 is connected to the voltage signal Vb1, the gate of the PMOS transistor M10 is connected to the gate of the PMOS transistor M8, the drain of the PMOS transistor M9 and M10 is connected to the voltage signal V1, the gate of the voltage signal Vdd is connected to the gate of the PMOS transistor M1 and the voltage signal idc is connected to the voltage signal idc 2.
The gain module comprises a Miller compensation capacitor, a PMOS tube M11, NMOS tubes M12 and M13; the grid of the PMOS tube M11 is connected with the drain electrode of the PMOS tube M8 and the drain electrode of the NMOS tube M4, the source electrode of the PMOS tube M11 is connected with the source electrodes of the PMOS tubes M9 and M10, the drain electrode of the PMOS tube M11 is connected with the drain electrode of the NMOS tube M12, the two ends of the Miller compensation capacitor are connected with the grid electrode and the drain electrode of the PMOS tube M11, the grid electrode of the NMOS tube M12 is connected with the grid electrodes of the NMOS tubes M3 and M4, the grid electrode of the NMOS tube M13 is connected with the grid electrodes of the NMOS tubes M5 and M6, the source electrode of the NMOS tube M12 is connected with the drain electrode of the NMOS tube M13, the source electrode of the NMOS tube M13 is connected with the source electrodes of the NMOS tubes M5 and M6, the NMOS tube M12 is connected with the output voltage signal Vout, and the output voltage signal Vout is connected with the drain electrode of the PMOS tube M11.
According to the application, each component in the error amplification module Refl is connected in a specific connection mode, each connected component plays a respective characteristic role, and meanwhile, the overall processing performance is obtained through a circuit logic relationship, so that the technical effect of high power supply rejection ratio and ultra-low noise can be achieved.
Further, the input tube M1 is a JEFT transistor.
In a second aspect of the present application, an ultra-low noise voltage stabilizing system with a high power supply rejection ratio of 1.4V-6.5V input is provided, which comprises an input power supply and a low dropout linear regulator (LDO) circuit, wherein the LDO circuit comprises an input module, an overcurrent protection module, an error amplification module Ref1, a reference control amplification module Ref2, a logic control module, a thermal protection module, a drive control module, a soft start module, a charge pump module and an output module, the input power supply is input into the LDO circuit via the input module,
the charge pump module is used as a driving control module input;
the overcurrent protection module is used for protecting the whole circuit from damage caused by overlarge current;
the thermal protection module is used for protecting the logic control module from damaging devices by heat caused by overlarge current;
the error amplification module Ref1 is used for reducing noise and improving gain of signals;
the reference control amplification module Ref2 is used for providing a reference control signal;
the soft start module establishes a slope by controlling the output voltage;
the output end of the reference control amplification module Ref2 is connected with the logic control module to stabilize the control voltage;
the output module is used for outputting stable voltage.
The charge pump module is connected with the drive control module, the thermal protection module is connected with the logic control module, the soft start module is used as the input end of the error amplification module Ref1 through the reference resistor, and the output end of the reference control amplification module Ref2 flows into the logic control module through the MOS tube.
In a third aspect of the present application, an LDO chip is provided, comprising the ultra low noise voltage stabilizing system with high power supply rejection ratio of 1.4V-6.5V input provided in the second aspect, and a PCB design and packaging design.
The ultra-low noise voltage stabilizing device with high power supply rejection ratio of 1.4V-6.5V input, the system and the LDO chip provided by the application have the advantages that the maximum noise which can be output by the output end of the LDO chip is 5-11 mu Vrms when the chip works through integrating the LDO circuit, and the maximum noise is increased along with the increase of the output voltage. Meanwhile, the chip of the application adopts the DFN package with 8 pins of 3mm multiplied by 3mm, so that the chip is a very compact solution, can provide good thermal performance for the application of output current up to 3A, has wider layout between the ground and the ground, can ensure good heat dissipation performance under the condition of electric performance, has flat appearance and small occupied area, and is beneficial to better heat dissipation.
The low noise and high power supply rejection ratio function of the application is realized mainly by the designed error amplifier module. In the low noise module, the JEFT structure is innovatively introduced into the input transistor of the error amplifying module, so that noise is reduced, the influence on the overall performance is small, and meanwhile, the JEFT structure is integrated into the ground capacitor at the input end to filter high-frequency noise. In addition, the second stage of the error amplifying module adopts a Casode structure, and the structure provides high voltage gain for the error amplifying module, so that the effect of high power supply rejection ratio of the whole chip is realized.
Meanwhile, the application can realize quick transient response. Compared with other traditional LDO chips, the LDO chip has a faster rapid transient response effect, and the reason is that the chip is characterized by designing a discharging channel module and a complementary current module, and the logic control module is used for controlling Q1 and Q2 so as to realize rapid on and off.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a functional block diagram of an LDO circuit design of the present application;
FIG. 2 is a schematic diagram of an LDO chip in a top view;
FIG. 3 is a schematic diagram of the voltage dividing resistor of the LDO chip outputting positive voltage according to the present application;
FIG. 4 is a schematic diagram of an exemplary application of the LDO chip of the present application;
fig. 5 is a graph showing a load adjustment rate when vout=0.8v of the LDO chip of the present application;
FIGS. 6a and 6b are graphs illustrating exemplary operation of the LDO chip of the present application;
FIGS. 7a and 7b are graphs showing transient AC response of LDO chips of the present application;
FIG. 8a is a layout design of an LDO chip PCB of the present application;
FIG. 8b is a top view of the LDO chip PCB package of the present application;
FIG. 8c is a bottom view of the LDO chip PCB package of the present application;
FIG. 8d is a side view of the LDO chip PCB package form of the present application;
fig. 9 is a schematic circuit diagram of the error amplifying module Ref1 of the present application.
Detailed Description
It should be understood that the examples of typical applications described herein are for the purpose of illustration only and are not intended to limit the application.
In the related art, an LDO circuit belongs to a low dropout linear power supply management circuit, and plays a role in providing power for other circuits, and the LDO circuit generates stable output voltage after processing external voltage by a control circuit. The LDO can realize smaller power supply output voltage difference, reduces self power consumption, ensures that the output voltage of the LDO cannot easily change along with the power supply voltage and the load current, has certain anti-interference capability, and is very suitable for the stable operation of a subsequent circuit.
In the existing LDO circuit, the design of the LDO circuit integrated inside the existing LDO circuit can generate a low-frequency pole to influence the frequency stability of a loop due to the fact that an error amplifier has a large output impedance, and the traditional LDO circuit often introduces a miller capacitor to compensate the circuit, so that the stability of the loop is improved, but the bandwidth is reduced. In the transient response of the LDO, the conventional LDO technology relies on the charging and discharging process of the load capacitor to improve the transient response of the circuit, if the capacitor is smaller, the transient response is worse, and if the capacitor is larger, the high integration of the chip is not facilitated.
The application is a low-voltage ultralow-noise voltage stabilizer which is optimized for the rapid transient response, the working voltage range is 1.4V to 6.5V, and the output current (voltage drop is 140 mV) of 3A can be supported. The application provides an ultralow noise voltage stabilizer for fast transient response optimization, which aims at low noise and high power supply rejection ratio performance in an LDO chip and provides a first-stage error amplifier designed by a JFET (junction field effect transistor), and meanwhile, a second-stage Cascade operational amplifier is designed to provide gain so as to ensure high power supply rejection ratio and voltage clamping of the LDO. Meanwhile, based on the LDO circuit structure designed above, a one-way discharging channel is provided for transient response, so that rapid transient response can be realized by matching with a small capacitor. The high output current LDO of the present application is well suited for voltage regulation of high performance analog and mixed signal circuits operating with power rails ranging from 6V to as low as 1.2V. By virtue of the advanced proprietary architecture, the device can provide high power supply rejection ratio and low noise, and excellent voltage and load transient response can be achieved with only a small ceramic output capacitance.
The following describes the implementation steps of the present application in detail with reference to the accompanying drawings:
referring to fig. 1, the ultra-low noise voltage stabilizing circuit with high input power supply rejection ratio provided by the application comprises an input power supply and a low dropout linear voltage regulator LDO circuit, wherein the LDO circuit comprises an input module, an overcurrent protection module, an error amplification module Ref1, a reference control amplification module Ref2, a logic control module, a thermal protection module, a drive control module, a soft start module, a charge pump module, an output module, voltage dividing resistors R1 and R2, a bleeder NMOS tube Q2 and a compensation NMOS tube Q1; an input power supply is input to the LDO circuit via the input module. The output of the thermal protection module is connected with the input of the logic control module to realize overheat protection control, and an enabling signal is input to the logic control module through Ref2 to control the on/off of the whole chip. The output Vout realizes feedback through voltage dividing resistors R1 and R2, the output voltage is input to the input negative end of the error amplifying module Ref1, the reference voltage is provided by the soft starting module and input to the positive end of the Ref1, the voltage difference between the output voltage and the reference voltage is amplified through the error amplifying module, if the voltage is higher than the reference voltage, the output voltage is discharged through a discharging transistor Q2 to achieve the effect of reducing, if the voltage is low, a driving control module connected with a charge pump is used for starting a compensating transistor Q1 to conduct voltage compensation, the voltage is enabled to be stabilized near the reference voltage, and the effect of linear voltage stabilization is achieved.
The performance of the LDO chip is mainly determined by the error amplifying module Ref1, and the error amplifying module Ref1 is characterized in that a small capacitor to ground is integrated at the input end to perform a filtering function so as to eliminate high-frequency noise. Secondly, the amplifying module is composed of two parts, the first part achieves the effect of low noise, the input transistor is different from the conventional MOS transistor structure, JEFT is adopted as the input transistor to achieve the effect of low noise, and secondly, the second stage achieves the effect of high gain by amplifying a high output impedance through the characteristic of common source common grid, and voltage at the positive end and the negative end of the error amplifying module Ref1 can be clamped, so that a high power supply rejection ratio is achieved.
The specific design is as shown in fig. 9, and the error amplification module Ref1 is formed by two-stage amplification, and comprises a noise reduction module and a gain module, wherein the noise reduction module is used as a first stage and is connected with the gain module used as a second stage.
The noise reduction module comprises input tubes M1 and M2, PMOS tubes M7, M8, M9 and M10 and NMOS tubes M3, M4, M5 and M6; the drains of the input transistors M1 and M2 are connected to the sources of the NMOS transistors M3 and M4, the sources of the NMOS transistors M3 and M4 are connected to the drains of the NMOS transistors M5 and M6, the drains of the NMOS transistors M3 and M4 are connected to the drains of the PMOS transistors M7 and M8, the sources of the PMOS transistors M7 and M8 are connected to the drains of the PMOS transistors M9 and M10, the gate of the NMOS transistor M3 is connected to the voltage signal Vb3, the gate of the voltage signal Vb3 is connected to the gate of the NMOS transistor M4, the gate of the voltage signal Vb 5 is connected to the voltage signal Vb4, the gate of the voltage signal Vb4 is connected to the gate of the NMOS transistor M6, the gate of the PMOS transistor M7 is connected to the voltage signal Vb2, the gate of the voltage signal Vb2 is connected to the gate of the PMOS transistor M8, the gate of the PMOS transistor M9 is connected to the voltage signal Vb1, the gate of the PMOS transistor M10 is connected to the gate of the PMOS transistor M8, the drain of the PMOS transistor M9 and M10 is connected to the voltage signal V1, the gate of the voltage signal Vdd is connected to the gate of the PMOS transistor M1 and the voltage signal idc is connected to the voltage signal idc 2.
The gain module comprises a Miller compensation capacitor, a PMOS tube M11, NMOS tubes M12 and M13; the grid of the PMOS tube M11 is connected with the drain electrode of the PMOS tube M8 and the drain electrode of the NMOS tube M4, the source electrode of the PMOS tube M11 is connected with the source electrodes of the PMOS tubes M9 and M10, the drain electrode of the PMOS tube M11 is connected with the drain electrode of the NMOS tube M12, the two ends of the Miller compensation capacitor are connected with the grid electrode and the drain electrode of the PMOS tube M11, the grid electrode of the NMOS tube M12 is connected with the grid electrodes of the NMOS tubes M3 and M4, the grid electrode of the NMOS tube M13 is connected with the grid electrodes of the NMOS tubes M5 and M6, the source electrode of the NMOS tube M12 is connected with the drain electrode of the NMOS tube M13, the source electrode of the NMOS tube M13 is connected with the source electrodes of the NMOS tubes M5 and M6, the NMOS tube M12 is connected with the output voltage signal Vout, and the output voltage signal Vout is connected with the drain electrode of the PMOS tube M11.
In addition, compared with the traditional LDO structure, the application realizes the effect of quick transient response by designing a special discharging channel and a compensation channel, and integrates a Schottky diode on the control NMOS transistors Q1 and Q2 to perform current protection.
The drain electrode of the specific bleeder transistor Q2 is connected with the output end through a current limiting resistor Rdis, the grid electrode is connected with the output end of the logic control module, the grid electrode of the compensation transistor Q1 is connected with the output end of the drive control module, the source electrode is connected with the input end through a resistor, and the drain electrode is connected with the output end. The quick turn-on and turn-off are realized by the logic control module, so that quick transient response is realized.
Specifically, the overcurrent protection module is connected with the logic control module, the driving control module and the output end of the reference control amplification module Ref2, the charge pump module is connected with the driving control module, the thermal protection module is connected with the logic control module, the soft start module is used as the input end of the error amplification module Ref1 through the reference resistor, and the output end of the reference control amplification module Ref2 flows into the logic control module through the MOS tube.
The input capacitor plays a role IN reducing interference, the ceramic chip capacitor with the grade of X7R or higher is required to be placed between IN and GND, the area of a loop formed by the capacitor, IN and GND is reduced as much as possible, the total capacity of the suggested capacitor is preferably more than 10uF, and it is recommended to add a 100nF ceramic capacitor to be placed close to the input pin to increase high-frequency decoupling.
The output capacitor is used for bearing pulsation of inductive current, reducing output voltage ripple and simultaneously considering steady-state characteristics and dynamic characteristics. In most applications, a ceramic capacitor of the order of X7R or higher is used, preferably with a capacity greater than 47uF, and further preferably with an added ceramic capacitor of 100nF to increase the high frequency decoupling characteristics. Since the capacity of the ceramic capacitor varies with the direct voltage to which it is subjected, the withstand voltage of the capacitor is usually 1.5 to 2 times the actual voltage. The output capacitance needs to be placed very close to the VOUT leg of the chip.
Wherein the output voltage is obtained by selecting a proper voltage dividing resistor R H And R is L To adjust, to reduce the loss of the resistor, R is usually H And R is L The resistance of (2) will be between 10KΩ and 1MΩ. For an output positive voltage, for example, if the output voltage is 1.6V, referring to the exemplary voltage drop application circuit of FIG. 3, R is selected first 1 =20k, the R 1 Corresponds to R in FIG. 3 H R can then be calculated according to the following equation 1 2 =20k, the R 2 Corresponds to R in FIG. 3 L 。
The EN pin is used for external enabling control, is usually connected to a high level through a pull-up resistor of 10K, and is decoupled from a ceramic capacitor connected to the ground by more than 10nF near the EN pin. When the external enabling signal is on, the EN pin is in a high level, and the chip enables to work; when the external signal is off, the EN pin is low, and the chip is disabled.
Wherein, the soft start module can be configured by the SS pin to control the output voltage to establish the slope. At the same time, this capacitance also affects the output noise characteristics.
The SS pin capacitance has an effect on the output noise, where the low noise application Css capacitance is not less than 100nF.
Referring to fig. 2, the input high power rejection ratio ultra-low noise LDO chip pin diagram provided by the present application is shown. The chip adopts a DFN package with 8 pins and 3mm multiplied by 3 mm. The pins include two LDO output pins VOUT, one Vout discharge feedback pin SNS, one soft start control configuration pin and low noise configuration pin SS, one external enable control pin EN, one heat dissipation pad and reference ground GND, and two input power supply pins IN.
Wherein VOUT is the output of the LDO chip voltage, and a ceramic capacitor of at least 47uF is added between the output and GND.
The SNS is a discharge feedback pin and is used for adjusting output voltage. The output positive voltage is expressed by the following equation (3):
VOUT(V)＝0.8(V)×(1+R H /R L ) (3)
the SS is a soft start control configuration pin and a low noise configuration pin, and the capacitance of the SS is not lower than 100nF during low noise output.
The EN is external enabling control, and when the pin is high, the level signal is more than 1.1V, and the chip works.
Wherein GND is ground; IN is the ceramic capacitance between the input power supply pin and GND, which is at least 10 uF.
Referring to fig. 4, a schematic diagram of a typical application of the input high power rejection ratio ultra-low noise LDO device provided by the present application is shown.
The input end forms the input of the LDO chip of the application through two input capacitors cin1=0.1 uF and cin2=10 uF, the external enable signal EN is used as the enable end input of the LDO chip of the application, the SS pin is grounded through the capacitor of css=100 nF, the SNS pin is connected with the VOUT pin of the application through the capacitor of cff=10 nF, the VOUT pin is output through a voltage drop circuit of RH=RL=100 KΩ, and the VOUT pin is connected with GND through Cout1=47 uF and Cout2=0.1 uF to form a loop.
In order to verify the performance of the input high power supply rejection ratio ultra-low noise LDO provided by the application, the application is simulated. The influence on the load adjustment rate curve at different temperatures, the influence on the output load current curve at different temperatures, the influence on the power supply rejection ratio at different output currents and the influence on the output transient AC response curve at different maximum load currents are examined.
Referring to fig. 5, the load adjustment rate curve of the input high power rejection ratio ultra-low noise LDO chip according to the present application is shown when vout=0.8v. It can be seen that when the temperature is from-40 ℃ to 125 ℃, the maximum voltage difference of the output voltage is less than 0.01V, and the voltage difference caused by the temperature difference tends to increase along with the increase of the output load current.
Referring to fig. 6a and fig. 6b, typical operation characteristics of the LDO chip with ultra-low noise with high input power rejection ratio according to the present application are shown in the typical application examples.
Fig. 6a is a graph of the output load current of the LDO chip of the present application at vin=3.3v voltage drop VS. It can be seen that the maximum voltage drop difference due to the temperature difference is less than 50mV when the temperature is varied from-40 c to 125 c and the load current is varied from 0 to 3A, and there is a tendency that the load current increases.
FIG. 6b is a plot of the power supply rejection ratio of the present application at different load output currents. It can be seen that at a frequency of 10M, the output current is in the interval from 0.1A to 3A, the typical circuit power supply rejection ratio still has 60dB, and at low frequencies the typical circuit power supply rejection ratio reaches around 100 dB.
Referring to fig. 7a and 7b, output transient AC response curves of the input high power rejection ratio ultra-low noise LDO of the present application are shown in a typical application example.
Fig. 7a is a graph showing the transient AC response when the maximum load current is ramped from 0mA to 1A at an output voltage of 5V. It can be seen that when the maximum load current is suddenly changed from 0mA to 1A, the maximum amplitude difference of the output voltage of the LDO chip provided by the application is only 5mV.
Wherein, fig. 7b is an output transient AC response curve when the maximum load current jumps from 100mA to 2A when the output voltage is 5V. It can be seen that when the maximum load current is suddenly changed from 100mA to 2A, the maximum amplitude difference of the output voltage of the LDO chip provided by the application is only 40mV.
Referring to fig. 8a-8d, the present application provides a layout and packaging of an input high power rejection ratio ultra low noise LDO chip PCB.
Fig. 8a is a layout of an LDO chip PCB according to the present application. In order to reduce noise interference, the input capacitor CIN and the output capacitor COUT need to be as close to the chip as possible; in order to obtain better heat dissipation capability, the GND pin of the chip needs to increase the thickness and the area of the PCB copper connected with the GND pin as much as possible; the input capacitance CIN needs to be as close to IN and GND as possible, and the area of the input capacitance CIN needs to be as small as possible, and the area of the input capacitance COUT needs to be as close to OUT and GND pins as possible.
Fig. 8b-8d are diagrams illustrating the LDO chip package according to the present application, wherein the package adopted in the present application is a DFN package with 8 pins of 3mm×3mm, and the package size is shown in fig. 8 and table 1.
TABLE 1LDO chip package size
Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present application and should be understood that the scope of the application is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.
Claims (10)
1. An ultra-low noise voltage stabilizing device with 1.4V-6.5V input and high power supply rejection ratio comprises an LDO circuit, wherein the LDO circuit comprises an input module, a power supply overcurrent protection module, an error amplification module Ref1, a reference control amplification module Ref2, a logic control module, a drive control module and an output module,
the input power supply is input into the LDO circuit through the input module and is output by the output module after being processed;
the power supply overcurrent protection module is connected with the logic control module and the drive control module;
the output end of the reference control amplification module Ref2 is connected with the logic control module through an MOS tube;
the input end of the error amplification module Ref1 is integrated with a grounded capacitor, and the output end of the error amplification module Ref1 is connected with the driving control module.
2. The voltage stabilizing device according to claim 1, wherein the circuit further comprises a thermal protection module, and an output end of the thermal protection module is connected with an input end of the logic control module to realize overheat protection control, so that a signal can be input to the logic control module through the reference control amplifying module Ref2 to control the on/off of the whole chip.
3. The voltage stabilizing device according to claim 1 or 2, wherein the circuit further comprises a bleeder transistor Q2 having a drain connected to the output module through a current limiting resistor Rdis, and a gate connected to the output of the logic control module; and/or
The circuit also comprises a compensation transistor Q1, wherein the grid electrode of the compensation transistor Q1 is connected with the output end of the driving control module, the drain electrode of the compensation transistor Q is connected with the input module through a resistor, and the source electrode of the compensation transistor Q is connected with the output module.
4. The voltage regulator of claim 3, wherein the compensation transistor Q1 and the bleeder transistor Q2 are NMOS transistors.
5. The voltage regulator of claim 4, wherein schottky diodes are integrated on the compensation transistor Q1 and the bleeder transistor Q2 for current protection.
6. The voltage stabilizing device according to claim 1 or 2, wherein the error amplifying module Ref1 is formed by two stages of amplification, and comprises a noise reducing module and a gain module, and the noise reducing module is used as a first stage and is connected with the gain module used as a second stage.
7. The pressure stabilizing device of claim 6, wherein,
the noise reduction module comprises input tubes M1 and M2, PMOS tubes M7, M8, M9 and M10 and NMOS tubes M3, M4, M5 and M6;
the drains of the input tubes M1 and M2 are connected with the sources of NMOS tubes M3 and M4, the sources of NMOS tubes M3 and M4 are connected with the drains of NMOS tubes M5 and M6, the drains of NMOS tubes M3 and M4 are connected with the drains of PMOS tubes M7 and M8, the sources of PMOS tubes M7 and M8 are connected with the drains of PMOS tubes M9 and M10, the gates of NMOS tubes M3 and M4 are connected with a voltage signal Vb3, the gates of NMOS tubes M5 and M6 are connected with a voltage signal Vb4, the gates of PMOS tubes M7 and M8 are connected with a voltage signal Vb2, the gates of PMOS tubes M9 and M10 are connected with a voltage signal Vb1, the drains of PMOS tubes M8 and M4 are connected with a first-stage output voltage signal V1, and the sources of PMOS tubes M9 and M10 are connected with a voltage signal Vdd; the input tubes M1 and M2 are PMOS tubes, the grid electrode of the PMOS tube M1 is connected with the voltage signal Vbc, the grid electrode of the PMOS tube M2 is connected with the voltage signal Vref, the sources of the PMOS tubes M1 and M2 are connected with the current signal idc, and the current signal idc is connected with the voltage signal Vdd.
8. The pressure stabilizing device of claim 7, wherein,
the gain module comprises a Miller compensation capacitor C1, a PMOS tube M11, NMOS tubes M12 and M13;
the grid of the PMOS tube M11 is connected with the drain electrode of the PMOS tube M8 and the drain electrode of the NMOS tube M4, the source electrode of the PMOS tube M11 is connected with the source electrodes of the PMOS tubes M9 and M10, the drain electrode of the PMOS tube M11 is connected with the drain electrode of the NMOS tube M12, the anode and the cathode of the Miller compensation capacitor C1 are connected with the grid electrode of the PMOS tube M11 and the drain electrode, the grid electrode of the NMOS tube M12 is connected with the grid electrodes of the NMOS tubes M3 and M4, the grid electrode of the NMOS tube M13 is connected with the grid electrodes of the NMOS tubes M5 and M6, the source electrode of the NMOS tube M12 is connected with the drain electrode of the NMOS tube M13, the source electrodes of the NMOS tubes M13 are connected with the source electrodes of the NMOS tubes M5 and M6, and the drain electrodes of the NMOS tubes M11 and M12 are connected with the output voltage signal Vout.
9. The voltage regulator according to claim 7 or 8, wherein the input tube M1 is a JEFT transistor.
10. An ultra-low noise voltage stabilizing system with 1.4V-6.5V input and high power supply rejection ratio comprises an input power supply and a low dropout linear voltage regulator LDO circuit, wherein the LDO circuit comprises an input module, an overcurrent protection module, an error amplification module Ref1, a reference control amplification module Ref2, a logic control module, a thermal protection module, a drive control module, a soft start module, a charge pump module and an output module, wherein the input power supply is input into the LDO circuit through the input module,
the charge pump module is used as a driving control module input;
the overcurrent protection module is used for protecting the whole circuit from damage caused by overlarge current;
the thermal protection module is used for protecting the logic control module from damaging devices by heat caused by overlarge current;
the error amplification module Ref1 is used for reducing noise and improving gain of signals;
the reference control amplification module Ref2 is used for providing a reference control signal;
the soft start module establishes a slope by controlling the output voltage;
the output end of the reference control amplification module Ref2 is connected with the logic control module to stabilize the control voltage;
the output module is used for outputting stable voltage.
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