CN117062443A

CN117062443A - Three-dimensional memory device and method

Info

Publication number: CN117062443A
Application number: CN202310472448.2A
Authority: CN
Inventors: 林孟汉; 杨世海; 黄家恩; 徐志安
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-07-07
Filing date: 2023-04-27
Publication date: 2023-11-14

Abstract

The present disclosure relates generally to three-dimensional memory devices and methods. In one embodiment, a device includes: a first gate structure over the substrate, the first gate structure including a first gate electrode over a first side of the first gate dielectric; a first electrode and a second electrode disposed over a second side of the first gate dielectric opposite the first side; a second gate structure disposed between the first electrode and the second electrode, the second gate structure including a second gate electrode and a second gate dielectric surrounding the second gate electrode at least laterally; and a semiconductor film disposed between the first electrode and the second electrode and surrounding the second gate structure at least laterally, wherein at least one of the first gate dielectric or the second gate dielectric is a memory film.

Description

Three-dimensional memory device and method

Technical Field

The present disclosure relates generally to three-dimensional memory devices and methods.

Background

Semiconductor memories are used in integrated circuits for electronic applications, including radio, television, cell phone, and personal computing devices, for example. Semiconductor memories include two broad categories. One type is volatile memory; another type is nonvolatile memory. Volatile memory includes Random Access Memory (RAM), which can be further divided into two sub-categories: static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). Both SRAM and DRAM are volatile in that they lose their stored information when powered down.

On the other hand, a nonvolatile memory may hold data that it stores. One type of nonvolatile semiconductor memory is ferroelectric random access memory (FeRAM). Advantages of FeRAM include its fast write/read speed and small size.

Disclosure of Invention

According to a first embodiment of the present disclosure, there is provided a semiconductor device including: a first gate structure over the substrate, the first gate structure comprising a first gate electrode over a first side of a first gate dielectric; a first electrode disposed over a second side of the first gate dielectric opposite the first side; a second electrode disposed over a second side of the first gate dielectric; a second gate structure disposed between the first electrode and the second electrode, the second gate structure comprising a second gate electrode and a second gate dielectric, the second gate dielectric surrounding the second gate electrode at least laterally; and a semiconductor film disposed between the first electrode and the second electrode and surrounding the second gate structure at least laterally, wherein at least one of the first gate dielectric or the second gate dielectric is a memory film.

According to a second embodiment of the present disclosure, there is provided a semiconductor device including: a first gate dielectric extending in a first direction; a word line disposed over and extending in a second direction over a first side of the first gate dielectric, the second direction being perpendicular to the first direction; a first electrode disposed in the second direction over a second side of the first gate dielectric opposite the word line, the first electrode being part of or electrically coupled to a first bit line; a second electrode disposed over a second side of the first gate dielectric, the second electrode being part of or electrically coupled to the first source line; a semiconductor film disposed between the first electrode and the second electrode; and a first gate structure disposed over a portion of the semiconductor film in the first direction such that the portion of the semiconductor film is sandwiched between the first gate dielectric and the first gate structure, wherein top surfaces of the word line and the first gate structure are flush with each other.

According to a third embodiment of the present disclosure, there is provided a method of forming a semiconductor device, the method including: forming a multi-layer stack over a substrate, the multi-layer stack including a first dielectric layer, a second dielectric layer, and a third dielectric layer sandwiched between the first dielectric layer and the second dielectric layer, the third dielectric layer having a different material than the first dielectric layer and the second dielectric layer; forming a first trench extending through the multi-layer stack; recessing sidewalls of the second dielectric layer from the first trench to form sidewall recesses between the first dielectric layer and the second dielectric layer; forming a conductive line in the first trench and the sidewall recess; removing a portion of the first dielectric layer, a portion of the second dielectric layer, and at least a portion of the third dielectric layer to form a second trench adjacent the conductive line; forming a first gate dielectric in the second trench; and forming a first electrode, a second electrode, a semiconductor film, and a gate structure over the first gate dielectric and in the second trench, the semiconductor film and the gate structure being disposed between the first electrode and the second electrode.

Drawings

Aspects of the disclosure may be best understood from the following detailed description when read in connection with the accompanying drawings. It is noted that the various features are not drawn to scale according to industry standard practices. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates an example of a memory cell according to some embodiments.

Fig. 2-10, 11A, and 12 are three-dimensional views of intermediate stages in the manufacture of a memory array in accordance with some embodiments.

FIG. 11B is a cross-sectional view of an intermediate stage in the fabrication of a memory array, according to some embodiments.

Fig. 13A-15C are cross-sectional views of intermediate stages in the manufacture of a memory array in accordance with an alternative embodiment.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (e.g., "below," "lower," "above," "upper," and the like) may be used herein to facilitate a description of a relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Various embodiments provide a memory array having a plurality of memory cells. Each memory cell includes a vertical Field Effect Transistor (FET). Each vertical FET may have a first gate electrode provided by a word line and a second gate electrode provided by an auxiliary gate, a first source/drain electrode provided by a bit line, and a second source/drain electrode provided by a source line. Each vertical FET also includes at least one memory film (e.g., as a gate dielectric) and a semiconductor channel region. The first gate electrode and the second gate electrode may be disposed over sides of the memory film and the semiconductor channel region.

Fig. 1 illustrates a memory cell 50 in a three-dimensional view according to some embodiments. The plurality of memory cells 50 may form a memory array. The memory cells (or memory arrays) may be disposed in an interconnect structure of a semiconductor die, which may be formed in a back-end-of-line (BEOL) process. The memory cells 50 (or memory arrays) may be disposed in an interconnect layer of a semiconductor die, for example, over one or more active devices (e.g., transistors) formed on a semiconductor substrate.

Memory cell 50 may include a transistor 50A. Transistor 50A may be a vertical FET. Transistor 50A may include a first gate structure 122 (or alternatively referred to as a select gate) and a second gate structure 142 (or alternatively referred to as an auxiliary gate or control gate). The first gate structure 122 may include a first gate electrode 116 and a first gate dielectric 124. As shown in fig. 1, the first gate electrode 116 may be disposed over a first side of the first gate dielectric 124, for example, in the x-direction. The first gate electrode 116 may be (partially) provided by a portion of the word line. As shown in fig. 1, the first gate electrode 116 and the first gate dielectric 124 may extend in the y-direction. The second gate structure 142 may be disposed, for example, over a second side of the first gate dielectric 124 opposite the first side of the first gate dielectric 124. The second gate structure 142 may include a second gate electrode 146 laterally surrounded by at least a second gate dielectric 144.

The first source/drain electrode 132B and the second source/drain electrode 132S may be disposed over the second side of the first gate dielectric 124 and over the sidewalls of the second gate structure 142 in the y-direction. The first source/drain electrode 132B may be part of or electrically coupled to a bit line, and the second source/drain electrode 132S may be part of or electrically coupled to a source line. In some embodiments, the second source/drain electrode 132S (e.g., source line) is electrically coupled to ground. The first source/drain electrode 132B and the second source/drain electrode 132S may define boundaries of the memory cell 50. Although fig. 1 shows a particular arrangement of the first source/drain electrode 132B relative to the second source/drain electrode 132S, it should be understood that the arrangement of the first source/drain electrode 132B and the second source/drain electrode 132S may be reversed in some embodiments.

The semiconductor film 140 may be disposed between the first source/drain electrode 132B and the second source/drain electrode 132S and surrounds the second gate structure 142 at least at sides. The semiconductor film 140 may provide a channel region of the transistor 50A of the memory cell 50. In some embodiments, the first gate electrode 116 has a protrusion extending between the first dielectric layer 106A and the second dielectric layer 106B. The protrusion may be adjacent to the semiconductor film 140. When an appropriate voltage is applied through the first gate structure 122 and the second gate structure 142 (e.g., above the corresponding threshold voltage (V _th ) The semiconductor film 140) may allow a current to flow from the first source/drain electrode 132B to the second source/drain electrode 132S, for example, in the y direction shown in fig. 1. The transistor 50A is a vertical transistor. The channel width of the transistor 50A is in the z-direction, and the on-current I can be increased by increasing the thickness of the first gate electrode 116 _on Thus, the performance of the memory cell 50 can be improved without increasing the occupied space (footprint) of the memory cell 50.

In some embodiments, at least one of the first gate dielectric 124 or the second gate dielectric 144 is a memory film capable of storing bits. The memory film may be a ferroelectric film. In some embodiments, memory cell 50 may be referred to as a ferroelectric random access memory (FeRAM) using a ferroelectric film. Alternatively, the memory film may be a different type of memory material used to form other types of memories. The memory film (e.g., first gate dielectric 124 and/or second gate dielectric 144) of memory cell 50 may be polarized in one of two different directions and the polarization direction may be changed by applying an appropriate voltage difference across the memory film. The threshold voltage of the transistor changes depending on the polarization direction of the memory film, and a digital value (e.g., 0 or 1) may be stored. For example, when the memory film has a first direction of electrical polarization, transistor 50A may have a relatively low threshold voltage, and when the memory film has a second direction of electrical polarization, transistor 50A may have a relatively high threshold voltage. In some embodiments, the first gate structure 122 and the second gate structure 142 are independently provided with different voltages. The transistor 50A having such a dual gate structure may provide more options to provide a voltage difference across the memory film of the memory cell 50 than a transistor having a single gate structure.

Fig. 2-10, 11A, and 12 are three-dimensional views of intermediate stages in the manufacture of a memory array 100 in accordance with some embodiments. Fig. 11B shows a sectional view along section A-A' in the X direction of fig. 11A. The cross section A-A' extends through one of the first gate electrodes 116 and its adjacent second gate structure 142.

In fig. 2, a substrate 101 is provided. The substrate 101 may be formed over a base plate (not shown). The substrate 101 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., doped with a p-type or n-type dopant) or undoped. The substrate 101 may be a wafer, such as a silicon wafer. Typically, the SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multi-layer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 101 may comprise silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof.

Circuitry (not shown) and interconnect structures 102 may be formed over substrate 101. The circuit includes active devices (e.g., transistors) at the top surface of the substrate 101. The transistor may include a channel region, a gate structure located on the channel region, and source/drain regions adjacent the channel region. In some embodiments, the transistor may be a planar Field Effect Transistor (FET), a fin field effect transistor (finFET), a nano-field effect transistor (nano-FET), or the like. In addition, the circuit may also include other active devices (e.g., diodes, etc.) and/or passive devices (e.g., capacitors, resistors, etc.). An interlayer dielectric surrounds and isolates active devices (e.g., source/drain regions and gate structures) as well as passive devices. The interconnect structure 102 is located over an interlayer dielectric, the interconnect structure 102 including one or more stacked dielectric layers and an interconnect formed in the one or more dielectric layers. Interconnect structure 102 may include any number of dielectric layers (where interconnects are provided). In some embodiments, the dielectric layer is a low-k dielectric. The interconnect structure 102 and circuitry over the substrate 101 may be electrically coupled to form functional circuitry. In some embodiments, the functional circuitry includes logic circuitry, memory circuitry, sense amplifiers (sense amplifiers), controllers, input/output circuitry, image sensor circuitry, and the like, or combinations thereof. In some embodiments, the interconnects of interconnect structure 102 are patterned to provide power, ground, and/or signal lines for active devices over substrate 101.

According to some embodiments, a multi-layer stack 104 is formed over the substrate 101 and/or the interconnect structure 102. The multi-layer stack 104 may include a first dielectric layer 106A, a second dielectric layer 106B, and a third dielectric layer 108 interposed between the first dielectric layer 106A and the second dielectric layer 106B. In some embodiments, the first dielectric layer 106A and the second dielectric layer 106B are formed of a first dielectric material, and the third dielectric layer 108 is formed of a second dielectric material. Acceptable dielectric materials include: oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; etc.; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, and the like. Each layer of the multi-layer stack 104 may be formed by any acceptable deposition process, such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), and the like. The first dielectric layer 106A, the second dielectric layer 106B, and the third dielectric layer 108 will be used to define the shape of the first gate electrode 116 (e.g., word line) of the transistor 50A in subsequent processing. The second dielectric material of the third dielectric layer 108 has a high etch selectivity with respect to the etching of the first dielectric material of the first dielectric layer 106A and the second dielectric layer 106B. In some embodiments, the first dielectric layer 106A and the second dielectric layer 106B are formed of silicon oxide, and the third dielectric layer 108 is formed of silicon nitride. Other combinations of dielectric materials having acceptable etch selectivity to each other may also be used. In the illustrated embodiment, the multi-layer stack 104 includes two dielectric layers formed of a first dielectric material and one dielectric layer formed of a second dielectric material. The multi-layer stack 104 may include other numbers of dielectric layers formed from various dielectric materials.

In fig. 3, the multi-layer stack 104 is etched to form a plurality of trenches 110 in the multi-layer stack 104. The trench 110 may extend through the multi-layer stack 104, for example exposing the underlying interconnect structure 102. The trench 110 may extend in the y-direction. The etching may be any acceptable etching process. For example, a mask (not shown) is formed over the multi-layer stack 104. The mask may be formed of a photoresist (e.g., a single layer of photoresist, a triple layer of photoresist, etc.) or a hard mask (e.g., tiN or other suitable mask material in addition to the materials of the first dielectric layer 106A, the second dielectric layer 106B, and the third dielectric layer 108). The mask is then patterned to expose areas of the multi-layer stack 104 corresponding to the pattern of trenches 110 while masking the remainder of the multi-layer stack 104. Etching also includes etching exposed areas of the multi-layer stack 104 using a dry etch or a wet etch. For example, the dry etching may be Reactive Ion Etching (RIE), neutral Beam Etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. In some embodiments, as shown in fig. 3, the trench 110 has a width in the x-direction of 5nm to 1000 nm. The mask may be removed during or after formation of the trench 110.

In fig. 4, the third dielectric layer 108 is laterally etched from its sidewalls exposed to the trench 110, forming sidewall recesses 112 over the sidewalls of the remaining portions of the third dielectric layer 108. The sidewall recess 112 may be sandwiched between the first dielectric layer 106A and the second dielectric layer 106B. The third dielectric layer 108 may be etched by any acceptable process, such as wet etching. The etching may be isotropic. The wet etched etchant may be one that is selective to the material(s) of the third dielectric layer 108 (e.g., the material(s) of the third dielectric layer 108 are selectively removed at a faster rate than the material(s) of the first dielectric layer 106A and the second dielectric layer 106B are etched). In an embodiment in which the first dielectric layer 106A and the second dielectric layer 106B are formed of silicon oxide and the third dielectric layer 108 is formed of silicon nitride, the silicon oxide may be formed by a process such as phosphoric acid (H ₃ PO ₄ ) And the like to remove the third dielectric layer 108. As shown in fig. 4, the sidewall recess 112 may have a depth D in the x-direction. The depth D of the sidewall recess 112 may be adjusted by changing the etching time of etching.

In fig. 5, a first gate electrode 116 for the memory array 100 is formed in the trench 110 and the sidewall recess 112, according to some embodiments. The first gate electrode 116 may be a word line for the memory array 100. The first gate electrodes 116 may each include one or more layers, such as a seed layer, an adhesion layer, a diffusion barrier layer, a fill layer, and the like. In some embodiments, the first gate electrodes 116 each include one or more liner layers (e.g., diffusion barrier layers, adhesion layers, etc.) and a main layer sandwiched between the liner layers. In some embodiments, the material of the liner layer is a material having good adhesion to the material of the first, second, and third dielectric layers 106A, 106B, 108, and the material of the main layer is a material having good adhesion to the material of the liner layer and having low resistivity. For example, the liner layer may be a metal nitride such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, and the like. The primary layer may be a metal such as tungsten, ruthenium, molybdenum, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, and the like. In some embodiments, the liner layer is formed of titanium nitride and the main layer is formed of tungsten. The materials of the liner layer and the main layer may be formed by an acceptable deposition process, such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), and the like. For example, an liner layer may be deposited in trench 110 and around first dielectric layer 106A, second dielectric layer 106B, and third dielectric layer 108 using a conformal deposition process such as ALD, and a main layer may be subsequently deposited on the liner layer using a deposition process such as CVD or PVD. The thickness of the inner liner layer may be less than the thickness of the main layer. In some embodiments, excess material of the first gate electrode 116 (e.g., material over the top surface of the second dielectric layer 106B) may be removed by a planarization process, such as a CMP, an etchback process, or a combination thereof.

The material of the first gate electrode 116 may fill the trench 110 and the sidewall recess 112, and the first gate electrode 116 may each have a cross shape, a cross-like shape, or the like in a cross-sectional view in the x-direction. The first gate electrode 116 may extend in the y-direction. For example, in a cross-sectional view in the x-direction, the first gate electrode 116 may each include a first portion 116A, a second portion 116B, and a third portion 116C. The first portion 116A may be sandwiched between the second portion 116B and the third portion 116C and connected to the second portion 116B and the third portion 116C. The thickness of the first portion 116A (e.g., in the z-direction) may be different from the thickness of the second portion 116B and the third portion 116C, e.g., greater than the thickness of the second portion 116B and the third portion 116C. For example, the thickness of the first portion 116A may be equal to the total thickness of the multi-layer stack 104, and the thickness of the second portion 116B and the third portion 116C may be equal to the thickness of the third dielectric layer 108.

In fig. 6, portions of the multi-layer stack 104 aligned with sidewalls of the first gate electrodes 116 (or with the remaining portions of the third dielectric layer 108) are removed, forming trenches 120 between adjacent first gate electrodes 116, according to some embodiments. Removing portions of the multi-layer stack 104 may be performed by forming a mask that is patterned to have a pattern of: the exposed areas of the pattern correspond to the remaining portions of the third dielectric layer 108. The mask may be formed of a photoresist (e.g., a single layer of photoresist, a triple layer of photoresist, etc.) or a hard mask (e.g., tiN or other suitable mask material in addition to the materials of the first dielectric layer 106A, the second dielectric layer 106B, and the third dielectric layer 108). Etching includes etching exposed areas of the multi-layer stack 104 using dry etching or wet etching. For example, the dry etching may be Reactive Ion Etching (RIE), neutral Beam Etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. As a result, the third dielectric layer 108 is completely removed or substantially removed. The mask may be removed during or after formation of the trench 110.

The trench 120 may extend in the y-direction, leaving behind a first dielectric layer 106A and a second dielectric layer 106B, wherein the first dielectric layer 106A acts as a dielectric line disposed below the second portion 116B and the third portion 116C of the first gate electrode 116, and the second dielectric layer 106B acts as a dielectric line disposed above the second portion 116B and the third portion 116C of the first gate electrode 116. In some embodiments, in a cross-sectional view in the x-direction (e.g., fig. 11B), the first gate electrode 116, the first dielectric layer 106A, and the second dielectric layer 106B may form a rectangular or rectangular-like shape. The first dielectric layer 106A and the second dielectric layer 106B are disposed at four corners of the rectangle to sandwich the first gate electrode 116.

In fig. 7, a first gate dielectric 124 and isolation region 126 are formed in trench 120, according to some embodiments. For example, the first gate dielectric 124 may be conformally formed over the sidewalls of the first gate electrode 116, the first dielectric layer 106A, and the second dielectric layer 106B, and the substrate 101 (or the interconnect structure 102). Isolation regions 126 may be formed to fill the remainder of trench 120. Excess material of the first gate dielectric 124 and the isolation region 126 (e.g., material over the top surfaces of the second dielectric layer 106B and the first gate electrode 116) may be removed by CMP, an etchback process, or other suitable planarization process. In some embodiments, the first gate dielectric 124 is formed of a high-k dielectric material, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or a combination thereof. In some embodiments, the first gate dielectric 124 is formed from a memory film, such as a ferroelectric film, e.g., hafnium oxide, hafnium zirconium oxide, silicon doped hafnium oxide, and the like. In some embodiments, the first gate dielectric 124 has a thickness of 0.1nm to 50 nm. The material of the first gate dielectric 124 may be formed by any acceptable deposition process such as ALD, CVD, or the like. Acceptable dielectric materials for isolation regions 126 include: oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; etc.; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, and the like. Other acceptable dielectric materials may be used. The material of isolation region 126 may be formed by any acceptable deposition process, such as CVD (e.g., flowable CVD (FCVD)), PVD, suitable coating techniques, and the like.

In fig. 8, portions of isolation region 126 are removed to form openings 130A and 130B, leaving isolation region 126A and isolation region 126B sandwiched by openings 130A and 130B, according to some embodiments. In some embodiments, the thickness of isolation region 126A in the y-direction is greater than or equal to the thickness of isolation region 126B in the y-direction. Openings 130A and 130B may use an etchant (e.g., cl ₂ 、CF ₄ 、CH ₃ F、CH ₂ F ₂ Dry etching of the like or a combination thereof) is formed by isotropic etching (e.g., RIE or NBE). A pair of openings 130A and 130B may be provided for forming a pair of source/drain electrodes of a respective transistor 50A of a respective memory cell 50. Adjacent memory cells 50 may be separated by a corresponding isolation region 126B. In a subsequent process, the isolation region 126A will be replaced by the semiconductor film 140 and the second gate structure 142.

In fig. 9, according to some embodiments, conductive material is deposited in openings 130A and 130B to form first source/drain electrode 132B and second source/drain electrode 132S in opening 130A and opening 130B, respectively. The first source/drain electrode 132B and the second source/drain electrode 132S may each include one or more inner liners and a main layer. The liner layer may be one or more seed layers, adhesion layers, diffusion barrier layers, and the like. The main layer may be formed over the liner layer and have low resistivity. The thickness of the main layer may be greater than the thickness of the inner liner layer. In some embodiments, the first source/drain electrode 132B and the second source/drain electrode 132S may comprise similar materials as the first gate electrode 116. For example, the liner layer may be a metal nitride such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, and the like. The primary layer may be a metal such as tungsten, ruthenium, molybdenum, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, and the like. In some embodiments, the liner layer is formed of titanium nitride and the main layer is formed of tungsten. The materials of the liner layer and the main layer may be formed by an acceptable deposition process such as CVD, ALD, PVD and the like. In some embodiments, excess material of the first source/drain electrode 132B and the second source/drain electrode 132S (e.g., material over the top surfaces of the isolation regions 126A and 126B, the second dielectric layer 106B, and the first gate electrode 116) may be removed by a planarization process, such as a CMP, an etchback process, or a combination thereof, or the like. It should be appreciated that while fig. 9 illustrates a particular arrangement of the first and second source/drain electrodes 132B, 132S, the arrangement of the first and second source/drain electrodes 132B, 132S may be reversed in some embodiments.

In fig. 10, isolation region 126A is removed to form opening 136, according to some embodiments. The opening 136 may be formed by an acceptable etch. For example, a patterned mask (not shown) is formed to expose isolation regions 126A, while covering other features of memory array 100. The patterned mask may be formed of a photoresist (e.g., a single layer of photoresist, a triple layer of photoresist, etc.) or a hard mask (e.g., tiN or other suitable mask material that is different from the material of the isolation regions 126A). Removal of isolation region 126A also includes etching isolation region 126A using a dry etch or a wet etch. For example, cl can be used ₂ 、CF ₄ 、CH ₃ F、CH ₂ F ₂ And the like, the isolation region 126A is etched by dry etching. In some embodiments, the etching is anisotropic. Alternatively, in some embodiments, the etching may be isotropic, with the isolation region 126A having a high etch selectivity to the first dielectric layer 106A and the second dielectric layer 106B.

In fig. 11A and 11B, a semiconductor film 140 and a second gate structure 142 are formed in the opening 136 according to some embodiments. Fig. 11A shows a three-dimensional view of the memory array 100. Fig. 11B shows a cross-sectional view of fig. 11A along section A-A' in the x-direction. Semiconductor film 140 may be formed (e.g., conformally) in opening 136, e.g., deposited over bottom portions and sidewalls of first gate dielectric 124. The semiconductor film 140 may be formed of a semiconductor material suitable for providing a channel region of the FET. In some embodiments, the semiconductor film 140 is formed of an oxide semiconductor, such as an indium-based semiconductor material, for example, indium Gallium Zinc Oxide (IGZO), indium Tin Oxide (ITO), indium Gallium Zinc Tin Oxide (IGZTO), zinc oxide (ZnO), or the like. In some embodiments, semiconductor film 140 is formed from a silicon-based semiconductor material, such as polysilicon, amorphous silicon, and the like. Other acceptable semiconductor materials may be used. The material of the semiconductor film 140 may be formed by any acceptable deposition process such as ALD, CVD, PVD and the like. In some embodiments, semiconductor film 140 is formed to a thickness in the range of 3nm to 20 nm.

Next, according to some embodiments, a second gate structure 142 is formed over the semiconductor film 140. For example, a second gate dielectric 144 may be formed (e.g., conformally) over the bottom portion and sidewalls of the semiconductor film 140, and a second gate electrode 146 may be formed over the second gate dielectric 144 and filling the remaining portion of the opening 136. In some embodiments, the second gate dielectric 144 is formed of a high-k dielectric material, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or a combination thereof. In some embodiments, the second gate dielectric 144 is formed from a memory film, such as a ferroelectric film, which may be hafnium oxide, hafnium zirconium oxide, silicon doped hafnium oxide, or the like. However, at least one of the first gate dielectric 124 or the second gate dielectric 144 is formed from a memory film. In some embodiments, the second gate dielectric 144 has a thickness of 0.1nm to 50 nm. The second gate dielectric 144 may be formed by any acceptable deposition process such as ALD or CVD.

The second gate electrode 146 may comprise a material similar to the first gate electrode 116. The second gate electrode 146 may also be formed of a material similar to the first source/drain electrode 132B and the second source/drain electrode 132S. For example, the second gate electrode 146 may include a TiN liner layer and a tungsten main layer. Alternatively, the second gate electrode 146 uses a different material than the first gate electrode 116. In some embodiments, the material selection of the second gate electrode 146 may be more flexible than the first gate electrode 116. The first gate electrode 116 may have a longer length (e.g., longer than the second gate electrode 146), and the use of a material with low resistivity (e.g., tungsten) may reduce the resistance of the first gate electrode 116 and help to improve the performance of the memory array 100. Thus, the work function of transistor 50A may be adjusted by selecting a different material for second gate electrode 146, for example to increase the threshold voltage of transistor 50A and reduce leakage current, rather than changing the material of first gate electrode 116. In some embodiments, the second gate electrode 146 includes Mo, ti, pd, co, cr, cu, ni, ta, pt, au, al, tiW, taN, WN, WCN, or the like, or a combination thereof.

Excess material of the second gate dielectric 144 and the second gate electrode 146 (e.g., material over the top surfaces of the semiconductor film 140, the second dielectric layer 106B, and the first gate electrode 116) may be removed by CMP, an etchback process, or other suitable planarization process. After removal, the top surfaces of semiconductor film 140, second gate dielectric 144, second gate electrode 146, second dielectric layer 106B, first gate dielectric 124, and first gate electrode 116 are coplanar (within process variations) such that they are flush with one another. In a plan view, the semiconductor film 140 and the second gate dielectric 144 may each have a ring shape or the like. Further, the semiconductor film 140 and the second gate dielectric 144 may each have a U shape or the like in a cross-sectional view in the x direction. The second gate electrodes 146 may each include a square, a rounded square, a rectangle, a rounded rectangle, a circle, an oval, or the like in plan view, and are surrounded laterally by at least the second gate dielectric 144 and the semiconductor film 140.

In fig. 12, a bit line 152B, a source line 152S, and a conductive line 152A are formed over the intermediate structure as shown in fig. 11A. According to some embodiments, bit line 152B, source line 152S, and conductive line 152A are electrically coupled to first source/drain electrode 132B, second source/drain electrode 132S, and second gate electrode 146, respectively. In some embodiments, bit line 152B, source line 152S, and conductive line 152A are formed in the same layer, e.g., in the same dielectric layer (not shown). In some embodiments, the bit line 152B, the source line 152S, and the conductive line 152A may be formed in a plurality of dielectric layers (not shown). Although not separately shown in fig. 12, the conductive lines connected to the first gate electrode 116 may also be formed in the same layer (S) as the bit line 152B, the source line 152S, and the conductive line 152A. In some embodiments, a conductive line connected to the first gate electrode 116 may be connected to the top of the first gate electrode 116 and provide an appropriate voltage from the top of the first gate electrode 116, and at least one conductive line may be connected to the bottom of the first gate electrode 116 and provide an appropriate voltage to the first gate electrode 116 from the bottom of the first gate electrode 116 (e.g., from the interconnect structure 102).

In embodiments where the first gate dielectric 124 or the second gate dielectric 144 is a memory film of ferroelectric material, the memory film may be polarized in one of two different directions and the polarization direction may be changed by applying an appropriate voltage difference across the memory film and generating an appropriate electric field. The polarization may be relatively localized (e.g., typically contained within each boundary of the memory cells 50), and a contiguous region of memory film may extend over multiple memory cells 50. The threshold voltage of the corresponding transistor 50A varies according to the polarization direction of a specific region of the memory film, and a digital value (e.g., 0 or 1) may be stored. For example, when a region of the memory film has a first direction of electrical polarization, the corresponding transistor 50A may have a relatively low threshold voltage, and when a region of the memory film has a second direction of electrical polarization, the corresponding transistor 50A may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as a threshold voltage shift. The larger threshold voltage shift makes it easier (e.g., less prone to error) to read the digital value stored in the corresponding memory cell 50.

To perform a write operation to the memory cell 50 in these embodiments, a write voltage is applied across a portion of the memory film corresponding to the memory cell 50. The write voltage may be applied, for example, by applying an appropriate voltage to the corresponding first gate electrode 116, the corresponding second gate electrode 146, the corresponding first source/drain electrode 132B, and the corresponding second source/drain electrode 132S. By applying a write voltage to this portion of the memory film, the polarization direction of the memory film region can be changed. As a result, the corresponding threshold voltage of the corresponding transistor 50A may also switch from a low threshold voltage to a high threshold voltage, and vice versa, and a digital value may be stored in the memory cell 50. Since the first gate electrode 116 and the second gate electrode 146 intersect the first source/drain electrode 132B (e.g., a portion of a bit line) and the second source/drain electrode 132S (e.g., a portion of a source line), each memory cell 50 may be selected for a write operation.

To perform a read operation on the memory cell 50 in such an embodiment, a read voltage (e.g., a voltage difference between a low threshold voltage and a high threshold voltage of the first gate electrode 116 and the second gate electrode 146) is applied to the corresponding first gate electrode 116 and second gate electrode 146. The transistor 50A of the memory cell 50 may be conductive or non-conductive depending on the polarization direction of the corresponding region of the memory film. As a result, bit line 152B may or may not discharge (e.g., ground) through source line 152S, and the digital value stored in memory cell 50 may be determined. Since the first gate electrode 116 and the second gate electrode 146 intersect the first source/drain electrode 132B (e.g., a portion of a bit line) and the second source/drain electrode 132S (e.g., a portion of a source line), each memory cell 50 may be selected for a read operation. In some embodiments, as shown in fig. 11B, each of the first gate electrodes 116 (e.g., a portion of a word line) may be connected to two of the first gate dielectrics 124 (left and right sides of the first gate electrode 116), and the digital values of the two first gate dielectrics 124 may be read independently by providing appropriate voltages to the corresponding second gate electrodes 146. For example, a different voltage may be provided to the second gate electrode 146 on a different side of the first gate electrode 116 and ensure that one transistor 50A is turned off when reading the digital value stored in the first gate dielectric 124 of the other transistor 50A.

One or more interconnect layers (not shown) are formed over the intermediate structure shown in fig. 12. The interconnect layer(s) each include an interconnect in a dielectric layer. The interconnect is electrically coupled to the first gate electrode 116, the bit line 152B, the source line 152S, the conductive line 152A, and the interconnect structure 102 to interconnect the transistor 50A to form a functional memory. The interconnect layer(s) may be formed by a damascene process, such as a single damascene process, a dual damascene process, and the like.

Fig. 13A-13D illustrate cross-sectional views of a memory array 100 along section A-A' as shown in fig. 11A, the memory array 100 having an alternative first gate electrode configuration, in accordance with some embodiments. For example, when the process for forming the sidewall recess 112 is performed by laterally etching the third dielectric layer 108 (as described with reference to fig. 4), the sidewalls of the remaining portion of the third dielectric layer 108 may not be vertical, e.g., inclined. As a result, the sidewalls of the subsequently filled first gate electrode 116 may have a shape that inversely corresponds to the sidewalls of the remaining portion of the third dielectric layer 108. In some embodiments, an anisotropic etch is used to form the openings 136 (as described with reference to fig. 10), which may be performed by aligning the outermost points of the first gate electrode 116, leaving portions of the third dielectric layer 108 on the sidewalls of the first gate electrode 116 as dielectric spacers 108S. In the resulting structure, dielectric spacer 108S may be disposed between first gate electrode 116 and first gate dielectric 124, as shown in fig. 13A-13D.

The shape of the dielectric spacers 108S may be controlled by the etchant and other etching process parameters, such as the temperature and time of the lateral etching process described with reference to fig. 4. For example, the dielectric spacer 108S may have a triangular or triangle-like shape with a wide bottom as shown in fig. 13A, or with a wide top as shown in fig. 13B. In some embodiments where the dielectric spacer 108S has a wide bottom, the electric field provided by the first gate electrode 116 may be localized near the top of the second portion 116B (and the third portion 116C) of the first gate electrode 116. In this way, the speed at which the first gate electrode 116 of fig. 13A generates an electric field across the first gate dielectric 124 may increase when a voltage is transmitted from the interconnect connected to the top of the first gate electrode 116. Alternatively, in some embodiments where the dielectric spacer 108S has a wide top, the electric field provided by the first gate electrode 116 may be localized near the bottom of the second portion 116B (and the third portion 116C) of the first gate electrode 116. In this way, the speed at which the first gate electrode 116 of fig. 13B generates an electric field across the first gate dielectric 124 may increase when a voltage is transmitted from an interconnect (e.g., interconnect structure 102) connected to the bottom of the first gate electrode 116. Fig. 13C and 13D provide different configurations of the first gate electrode 116 and the dielectric spacer 108S for generating localized electric fields at different locations. The configuration of the first gate electrode 116 and the dielectric spacer 108S of fig. 13C and 13D may be formed by adjusting an etching process for forming the sidewall recess 112 by laterally etching the third dielectric layer 108, as described with reference to fig. 4.

Fig. 14A and 14B illustrate cross-sectional views of a memory array 100 along section A-A' as shown in fig. 11A, the memory array 100 having an alternative first gate electrode configuration, in accordance with some embodiments. The first dielectric layer 106A and the second dielectric layer 106B have different thicknesses. For example, in fig. 14A, the thickness of the second dielectric layer 106B may be greater than the thickness of the first dielectric layer 106A, so the second portion 116B and the third portion 116C of the first gate electrode 116 are closer to the bottom of the first gate electrode 116 (than to the top of the first gate electrode 116). In this way, the electric field provided by the first gate electrode 116 may be localized closer to the bottom of the first gate electrode 116 (as compared to the top of the first gate electrode 116). In some embodiments, the speed at which the first gate electrode 116 of fig. 14A generates an electric field across the first gate dielectric 124 may increase when a voltage is transmitted from an interconnect connected to the bottom of the first gate electrode 116. In fig. 14B, the second dielectric layer 106B may be thinner than the first dielectric layer 106A, so the second portion 116B and the third portion 116C of the first gate electrode 116 are closer to the top of the first gate electrode 116 (than to the bottom of the first gate electrode 116). In this way, the electric field provided by the first gate electrode 116 may be localized closer to the top of the first gate electrode 116 (as compared to the bottom of the first gate electrode 116). In some embodiments, the speed at which the first gate electrode 116 of fig. 14B generates an electric field across the first gate dielectric 124 may increase when a voltage is transmitted from an interconnect connected to the top of the first gate electrode 116.

Fig. 15A-15C illustrate cross-sectional views of a memory array 100 along section A-A' as shown in fig. 11A, the memory array 100 having an alternative first gate electrode configuration, in accordance with some embodiments. In some embodiments, the multi-layer stack 104 has more than three dielectric layers, including seven dielectric layers, for example. According to some embodiments, as shown in fig. 15A-15C, dielectric layers 106A-106D formed of a first dielectric material and dielectric layers 108A-108C formed of a second dielectric material are alternately stacked. As a result, the first gate electrode 116 may thus have a plurality of second portions 116B and a plurality of third portions 116C sandwiched between the dielectric layers 106A-106D.

In some embodiments, as shown in fig. 15A, each of the dielectric layers 106A-106D has substantially the same thickness. The electric field generated by the first gate electrode 116 may be uniformly distributed in the thickness direction (e.g., z direction). In some embodiments, the dielectric layers 106A-106D may have different thicknesses. For example, as shown in fig. 15B, the thickness of the dielectric layers 106A-106D may gradually decrease from bottom to top, so that the second portion 116B and the third portion 116C of the first gate electrode 116 are generally closer to the top of the first gate electrode 116 (as compared to the bottom of the first gate electrode 116). In some embodiments, the speed at which the first gate electrode 116 of fig. 15B generates an electric field across the first gate dielectric 124 may increase when a voltage is transmitted from an interconnect connected to the top of the first gate electrode 116. Alternatively, as shown in fig. 15C, the thickness of the dielectric layers 106A to 106D may gradually increase from bottom to top, so the second portion 116B and the third portion 116C of the first gate electrode 116 are closer to the bottom of the first gate electrode 116 as a whole (compared to the top of the first gate electrode 116). In some embodiments, the speed at which the first gate electrode 116 of fig. 15C generates an electric field across the first gate dielectric 124 may increase when a voltage is transmitted from an interconnect (e.g., interconnect structure 102) connected to the bottom of the first gate electrode 116.

Embodiments may realize advantages. According to some embodiments, a vertical FET (e.g., transistor 50A) for a memory array is provided. The vertical FET may provide an increased channel width to enhance the performance of the vertical FET without increasing the footprint of the memory array. The vertical FET may also provide more options to adjust the position of the first gate electrode 116 (e.g., word line) to create a localized electric field on the first gate dielectric 124 (e.g., memory film). The inclusion of the second gate structure 142 may increase the threshold voltage (Vt) of the transistor 50A and provide more options to provide a voltage difference across the memory film of the memory cell 50. The material of the second gate electrode 146 may be selected to adjust the work function instead of changing the material of the first gate electrode 116. The work function of transistor 50A can be adjusted without significantly affecting the performance of the memory array.

In one embodiment, a device includes: a first gate structure over the substrate, the first gate structure comprising a first gate electrode over a first side of a first gate dielectric; a first electrode disposed over a second side of the first gate dielectric opposite the first side; a second electrode disposed over a second side of the first gate dielectric; a second gate structure disposed between the first electrode and the second electrode, the second gate structure comprising a second gate electrode and a second gate dielectric, the second gate dielectric surrounding the second gate electrode at least laterally; and a semiconductor film disposed between the first electrode and the second electrode and surrounding the second gate structure at least laterally, wherein at least one of the first gate dielectric or the second gate dielectric is a memory film. In one embodiment, the first gate electrode includes a first portion between a second portion and a third portion, wherein the first portion has a different thickness than the second portion and the third portion. In one embodiment, the device includes a first dielectric layer disposed below the second portion of the first gate electrode and between the first portion of the first gate electrode and the first gate dielectric. In one embodiment, the device includes a second dielectric layer disposed over the second portion of the first gate electrode and between the first portion of the first gate electrode and the first gate dielectric. In one embodiment, the second gate dielectric extends under the second gate electrode. In one embodiment, the semiconductor film extends under the second gate structure. In one embodiment, the first gate electrode and the second gate electrode are formed of different materials. In one embodiment, the first electrode is electrically coupled to a bit line and the second electrode is electrically coupled to a source line. In one embodiment, the memory film is a ferroelectric film. In one embodiment, the device includes a dielectric spacer disposed between the first gate electrode and the first gate dielectric.

In one embodiment, a device includes: a first gate dielectric extending in a first direction; a word line disposed over and extending in a second direction over a first side of the first gate dielectric, the second direction being perpendicular to the first direction; a first electrode disposed in the second direction over a second side of the first gate dielectric opposite the word line, the first electrode being part of or electrically coupled to a first bit line; a second electrode disposed over a second side of the first gate dielectric, the second electrode being part of or electrically coupled to the first source line; a semiconductor film disposed between the first electrode and the second electrode; and a first gate structure disposed over a portion of the semiconductor film in the first direction such that the portion of the semiconductor film is sandwiched between the first gate dielectric and the first gate structure, wherein top surfaces of the word line and the first gate structure are flush with each other. In one embodiment, the device further includes a third electrode, a fourth electrode, and a second gate structure disposed over a side of the second electrode opposite the first gate structure in the first direction, the third electrode being part of or electrically coupled to a second bit line, the fourth electrode being part of or electrically coupled to a second source line. In one embodiment, the word line includes a first portion sandwiched between a second portion and a third portion, each of the first portion, second portion, and third portion extending along the first gate dielectric in the first direction, the first portion having a different thickness than the second portion and third portion. In one embodiment, the device further includes a first dielectric layer disposed below the second portion of the word line and a second dielectric layer disposed above the second portion of the word line, each of the first and second dielectric layers extending along the first portion of the word line in the first direction and intersecting the third and fourth electrodes. In one embodiment, the second dielectric layer and the top surface of the word line are flush with each other.

In one embodiment, a method of forming a device is provided. The method comprises the following steps: forming a multi-layer stack over a substrate, the multi-layer stack including a first dielectric layer, a second dielectric layer, and a third dielectric layer sandwiched between the first dielectric layer and the second dielectric layer, the third dielectric layer having a different material than the first dielectric layer and the second dielectric layer; forming a first trench extending through the multi-layer stack; recessing sidewalls of the second dielectric layer from the first trench to form sidewall recesses between the first dielectric layer and the second dielectric layer; forming a conductive line in the first trench and the sidewall recess; removing a portion of the first dielectric layer, a portion of the second dielectric layer, and at least a portion of the third dielectric layer to form a second trench adjacent the conductive line; forming a first gate dielectric in the second trench; and forming a first electrode, a second electrode, a semiconductor film, and a gate structure over the first gate dielectric and in the second trench, the semiconductor film and the gate structure being disposed between the first electrode and the second electrode. In one embodiment, the method further comprises forming isolation regions over the first gate dielectric and in the second trench prior to forming the first electrode, the second electrode, the semiconductor film, and the gate structure. In one embodiment, the method further comprises performing a first removal for removing a first portion of the isolation region to form an opening for forming the first electrode and the second electrode. In one embodiment, the method further comprises performing a second removal for removing a second portion of the isolation region to form an opening for forming the semiconductor film and the gate structure, wherein the first removal and the second removal are performed separately. In one embodiment, the third dielectric layer is completely removed when the second trench is formed.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1 is a semiconductor device, comprising: a first gate structure over the substrate, the first gate structure comprising a first gate electrode over a first side of a first gate dielectric; a first electrode disposed over a second side of the first gate dielectric opposite the first side; a second electrode disposed over a second side of the first gate dielectric; a second gate structure disposed between the first electrode and the second electrode, the second gate structure comprising a second gate electrode and a second gate dielectric, the second gate dielectric surrounding the second gate electrode at least laterally; and a semiconductor film disposed between the first electrode and the second electrode and surrounding the second gate structure at least laterally, wherein at least one of the first gate dielectric or the second gate dielectric is a memory film.

Example 2 is the device of example 1, wherein the first gate electrode comprises a first portion between a second portion and a third portion, wherein the first portion has a different thickness than the second portion and the third portion.

Example 3 is the device of example 2, further comprising a first dielectric layer disposed below the second portion of the first gate electrode and between the first portion of the first gate electrode and the first gate dielectric.

Example 4 is the device of example 2, further comprising a second dielectric layer disposed over the second portion of the first gate electrode and between the first portion of the first gate electrode and the first gate dielectric.

Example 5 is the device of example 1, wherein the second gate dielectric extends under the second gate electrode.

Example 6 is the device of example 1, wherein the semiconductor film extends under the second gate structure.

Example 7 is the device of example 1, wherein the first gate electrode and the second gate electrode are formed of different materials.

Example 8 is the device of example 1, wherein the first electrode is electrically coupled to a bit line and the second electrode is electrically coupled to a source line.

Example 9 is the device of example 1, wherein the memory film is a ferroelectric film.

Example 10 is the device of example 1, further comprising a dielectric spacer disposed between the first gate electrode and the first gate dielectric.

Example 11 is a semiconductor device, comprising: a first gate dielectric extending in a first direction; a word line disposed over and extending in a second direction over a first side of the first gate dielectric, the second direction being perpendicular to the first direction; a first electrode disposed in the second direction over a second side of the first gate dielectric opposite the word line, the first electrode being part of or electrically coupled to a first bit line; a second electrode disposed over a second side of the first gate dielectric, the second electrode being part of or electrically coupled to the first source line; a semiconductor film disposed between the first electrode and the second electrode; and a first gate structure disposed over a portion of the semiconductor film in the first direction such that the portion of the semiconductor film is sandwiched between the first gate dielectric and the first gate structure, wherein top surfaces of the word line and the first gate structure are flush with each other.

Example 12 is the device of example 11, further comprising a third electrode, a fourth electrode, and a second gate structure disposed over a side of the second electrode opposite the first gate structure in the first direction, the third electrode being part of or electrically coupled to a second bit line, the fourth electrode being part of or electrically coupled to a second source line.

Example 13 is the device of example 12, wherein the word line includes a first portion sandwiched between a second portion and a third portion, each of the first portion, the second portion, and the third portion extending along the first gate dielectric in the first direction, the first portion having a different thickness than the second portion and the third portion.

Example 14 is the device of example 13, further comprising a first dielectric layer disposed below the second portion of the word line and a second dielectric layer disposed above the second portion of the word line, each of the first and second dielectric layers extending along the first portion of the word line in the first direction and intersecting the third and fourth electrodes.

Example 15 is the device of example 14, wherein top surfaces of the second dielectric layer and the word line are flush with each other.

Example 16 is a method of forming a semiconductor device, the method comprising: forming a multi-layer stack over a substrate, the multi-layer stack including a first dielectric layer, a second dielectric layer, and a third dielectric layer sandwiched between the first dielectric layer and the second dielectric layer, the third dielectric layer having a different material than the first dielectric layer and the second dielectric layer; forming a first trench extending through the multi-layer stack; recessing sidewalls of the second dielectric layer from the first trench to form sidewall recesses between the first dielectric layer and the second dielectric layer; forming a conductive line in the first trench and the sidewall recess; removing a portion of the first dielectric layer, a portion of the second dielectric layer, and at least a portion of the third dielectric layer to form a second trench adjacent the conductive line; forming a first gate dielectric in the second trench; and forming a first electrode, a second electrode, a semiconductor film, and a gate structure over the first gate dielectric and in the second trench, the semiconductor film and the gate structure being disposed between the first electrode and the second electrode.

Example 17 is the method of example 16, further comprising: isolation regions are formed over the first gate dielectric and in the second trenches prior to forming the first electrode, the second electrode, the semiconductor film, and the gate structure.

Example 18 is the method of example 17, further comprising: a first removal is performed for removing a first portion of the isolation region to form an opening for forming the first electrode and the second electrode.

Example 19 is the method of example 18, further comprising: a second removal is performed for removing a second portion of the isolation region to form an opening for forming the semiconductor film and the gate structure, wherein the first removal and the second removal are performed separately.

Example 20 is the method of example 16, wherein the third dielectric layer is completely removed when forming the second trench.

Claims

1. A semiconductor device, comprising:

a first gate structure over the substrate, the first gate structure comprising a first gate electrode over a first side of a first gate dielectric;

a first electrode disposed over a second side of the first gate dielectric opposite the first side;

A second electrode disposed over a second side of the first gate dielectric;

a second gate structure disposed between the first electrode and the second electrode, the second gate structure comprising a second gate electrode and a second gate dielectric, the second gate dielectric surrounding the second gate electrode at least laterally; and

a semiconductor film disposed between the first electrode and the second electrode and surrounding the second gate structure at least at a side face,

wherein at least one of the first gate dielectric or the second gate dielectric is a memory film.

2. The device of claim 1, wherein the first gate electrode comprises a first portion between a second portion and a third portion, wherein the first portion has a different thickness than the second portion and the third portion.

3. The device of claim 2, further comprising a first dielectric layer disposed below the second portion of the first gate electrode and between the first portion of the first gate electrode and the first gate dielectric.

4. The device of claim 2, further comprising a second dielectric layer disposed over the second portion of the first gate electrode and between the first portion of the first gate electrode and the first gate dielectric.

5. The device of claim 1, wherein the second gate dielectric extends under the second gate electrode.

6. The device of claim 1, wherein the semiconductor film extends under the second gate structure.

7. The device of claim 1, wherein the first gate electrode and the second gate electrode are formed of different materials.

8. The device of claim 1, wherein the first electrode is electrically coupled to a bit line and the second electrode is electrically coupled to a source line.

9. A semiconductor device, comprising:

a first gate dielectric extending in a first direction;

a word line disposed over and extending in a second direction over a first side of the first gate dielectric, the second direction being perpendicular to the first direction;

a first electrode disposed in the second direction over a second side of the first gate dielectric opposite the word line, the first electrode being part of or electrically coupled to a first bit line;

a second electrode disposed over a second side of the first gate dielectric, the second electrode being part of or electrically coupled to the first source line;

A semiconductor film disposed between the first electrode and the second electrode; and

a first gate structure disposed over a portion of the semiconductor film in the first direction such that the portion of the semiconductor film is sandwiched between the first gate dielectric and the first gate structure, wherein top surfaces of the word line and the first gate structure are flush with each other.

10. A method of forming a semiconductor device, the method comprising:

forming a multi-layer stack over a substrate, the multi-layer stack including a first dielectric layer, a second dielectric layer, and a third dielectric layer sandwiched between the first dielectric layer and the second dielectric layer, the third dielectric layer having a different material than the first dielectric layer and the second dielectric layer;

forming a first trench extending through the multi-layer stack;

recessing sidewalls of the second dielectric layer from the first trench to form sidewall recesses between the first dielectric layer and the second dielectric layer;

forming a conductive line in the first trench and the sidewall recess;

removing a portion of the first dielectric layer, a portion of the second dielectric layer, and at least a portion of the third dielectric layer to form a second trench adjacent the conductive line;

Forming a first gate dielectric in the second trench; and

a first electrode, a second electrode, a semiconductor film, and a gate structure are formed over the first gate dielectric and in the second trench, the semiconductor film and the gate structure being disposed between the first electrode and the second electrode.