CN117060996A - Phase error evaluation system of coherent receiving chip - Google Patents
Phase error evaluation system of coherent receiving chip Download PDFInfo
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- CN117060996A CN117060996A CN202311087660.3A CN202311087660A CN117060996A CN 117060996 A CN117060996 A CN 117060996A CN 202311087660 A CN202311087660 A CN 202311087660A CN 117060996 A CN117060996 A CN 117060996A
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- 230000001427 coherent effect Effects 0.000 title claims abstract description 114
- 238000011156 evaluation Methods 0.000 title claims abstract description 30
- 238000012360 testing method Methods 0.000 claims abstract description 26
- 238000012545 processing Methods 0.000 claims abstract description 4
- 230000003287 optical effect Effects 0.000 claims description 105
- 230000010287 polarization Effects 0.000 claims description 32
- 239000013307 optical fiber Substances 0.000 claims description 23
- 239000000835 fiber Substances 0.000 claims description 9
- 230000010355 oscillation Effects 0.000 claims description 9
- 230000008878 coupling Effects 0.000 claims description 8
- 238000010168 coupling process Methods 0.000 claims description 8
- 238000005859 coupling reaction Methods 0.000 claims description 8
- 238000004364 calculation method Methods 0.000 claims description 6
- 238000004891 communication Methods 0.000 abstract description 7
- 238000013461 design Methods 0.000 abstract description 6
- 238000012216 screening Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 210000001503 joint Anatomy 0.000 description 1
- 230000005389 magnetism Effects 0.000 description 1
- 238000003032 molecular docking Methods 0.000 description 1
- 238000003908 quality control method Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
- H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
- H04B10/079—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
- H04B10/0795—Performance monitoring; Measurement of transmission parameters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/61—Coherent receivers
- H04B10/614—Coherent receivers comprising one or more polarization beam splitters, e.g. polarization multiplexed [PolMux] X-PSK coherent receivers, polarization diversity heterodyne coherent receivers
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Abstract
The application discloses a phase error evaluation system of a coherent receiving chip, which comprises: a light source for providing coherent light; and the front-end light path is used for processing the coherent light to output two coherent light beams with time delay. The original design structure of the chip is not required to be changed, the test link is flexible in structure, and the test mode is concise; the evaluation system provided by the application can be used for measuring the phase error in a wafer level or chip level test, namely, the advanced screening is realized before the coherent receiving chip is packaged into the coherent receiving module, so that the risk of overflowing to the coherent receiving module or the coherent communication system can be effectively reduced.
Description
Technical Field
The application relates to the technical field of coherent communication, in particular to a phase error evaluation system of a coherent receiving chip.
Background
Compared with the traditional optical communication system based on direct intensity detection, the coherent optical communication system has the advantages of high spectrum utilization rate, large communication capacity, support of multiple modulation modes and sensitive signal detection. The coherent receiving chip is an essential component of a receiving end of a coherent optical communication system, can demodulate and convert an optical signal into an electric signal, and is convenient for a digital chip to process the signal.
The mixer is one of core optical devices of a coherent receiving chip, the common mode rejection ratio and the phase error are two main performance indexes of the mixer, wherein the common mode rejection ratio can be extracted through a responsivity test result, and the phase error needs to build a special test system. The current phase error testing system needs to change the structural design of the original chip of the coherent receiving chip, so that the complexity of the chip is improved, and additional loss can be caused by adding structures such as crossed waveguides.
Disclosure of Invention
In order to solve the technical problems, the application provides a phase error evaluation system of a coherent receiving chip. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
The application adopts the following technical scheme:
the application provides a phase error evaluation system of a coherent receiving chip, which comprises:
a light source for providing coherent light;
the front-end light path is used for processing the coherent light to output two coherent light beams with time delay, and the front-end light path comprises:
the polarization controller is used for controlling the coherent light output by the light source to output the coherent light with the polarization state required by the test;
and the beam splitting time delay light path is used for splitting the coherent light output by the polarization controller and introducing time delay to the split two beams of light to form two beams of coherent light which are input to the signal light input end and the local oscillation light input end of the coherent receiving chip to be tested and have time delay.
Wherein, the beam-splitting time delay light path includes: and the optical fiber beam splitter is used for dividing the coherent light output by the polarization controller into two paths and introducing time delay to the two split light beams by utilizing the length difference value of the tail fiber of the optical fiber beam splitter.
Wherein, the beam-splitting time delay light path further comprises: and the adjustable optical delay line is arranged on an optical link connected with the optical fiber beam splitter and the coherent receiving chip to be tested and is used for introducing delay to two beams of light output after the optical fiber beam splitter splits.
The number of the adjustable optical delay lines is one, and the adjustable optical delay lines are arranged on an optical link connected with the signal light input end of the to-be-detected coherent receiving chip or an optical link connected with the local oscillation light input end of the to-be-detected coherent receiving chip.
The number of the adjustable optical delay lines is two, and the two groups of the adjustable optical delay lines are respectively arranged on optical links of the optical fiber beam splitter, which are connected with the signal light input end and the local oscillator light input end of the coherent receiving chip to be tested.
The beam splitting delay optical path is a beam splitting delay chip, the beam splitting delay chip is provided with two output ports, the two output ports are of an end face coupling structure, and the distance between the two output ports is equal to the distance between the two input ports of the coherent receiving chip to be detected.
Wherein, the beam splitting delay chip includes: two on-chip waveguides with different beam splitters and optical paths; and the beam splitter splits the coherent light output by the polarization controller, and the split two beams of light are output after passing through the two on-chip waveguides so as to introduce time delay into the split two beams of light.
Wherein, the beam splitting delay chip includes: the optical system comprises a beam splitter, a first optical route and a second optical route, wherein a plurality of on-chip waveguides with mutually different optical paths are arranged between the first optical route and the second optical route; the beam splitter splits the coherent light output by the polarization controller, one path of split light is transmitted in the optical waveguide on the chip and directly output, and the other path of split light is guided to one path of on-chip waveguides with different multipath optical paths after passing through the first optical path and then is output after passing through the second optical path.
Wherein, the polarization controller is integrated at the front end of the beam splitting delay chip.
The phase error evaluation system of the coherent receiving chip further comprises: the system comprises a calculation control device and an electric signal receiving device, wherein the electric signal receiving device acquires an output electric signal of a coherent receiving chip to be detected and transmits the output electric signal to the calculation control device.
The application has the beneficial effects that:
1. the evaluation system provided by the application can be used for measuring the phase error in a wafer level or chip level test, namely, the advanced screening is realized before the coherent receiving chip is packaged into the coherent receiving module, so that the risk of overflowing to the coherent receiving module or the coherent communication system can be effectively reduced.
2. The original design structure of the chip does not need to be changed, the test system is flexible in structure, and the test mode is concise;
drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a phase error evaluation system of a coherent receiving chip according to the present application;
FIG. 2 is a schematic view of a first configuration of the front-end optical path of the present application;
FIG. 3 is a schematic view of a second configuration of the front-end optical path of the present application;
FIG. 4 is a schematic view of a third embodiment of the front-end optical path of the present application;
FIG. 5 is a schematic view of a fourth configuration of the front-end optical path of the present application;
fig. 6 is a schematic diagram of a first configuration of the beam splitting delay chip of the present application;
fig. 7 is a schematic diagram of a second configuration of the beam splitting delay chip of the present application;
fig. 8 is a schematic view of a fifth configuration of the front-end optical path of the present application.
Detailed Description
Embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
As shown in fig. 1, the present application provides a phase error evaluation system of a coherent receiving chip, specifically, a test link constructed by a light source 100, a front-end optical path 200, an electrical signal receiving device 400, a calculation control device 500, and a related photoelectric connection, so as to implement evaluation of a phase error of a coherent receiving chip 300 to be tested. The application aims to provide a test link basic framework which has good adaptability and does not need to introduce extra design phase error evaluation on a coherent receiving chip 300 to be tested. In fig. 1, the dashed arrow lines are control signals, and the solid arrow lines are input light and output electrical signals at the time of evaluation.
The calculation control device 500 controls the light source 100 to provide coherent light, and inputs the coherent light to the front-end light path 200, so as to obtain two coherent light beams with time delay, and the two coherent light beams are respectively input to the signal light input end 310 and the local oscillation light input end 320 of the coherent receiving chip 300 to be measured. The coherent receiving chip 300 to be tested demodulates the input light, and finally outputs multiple paths of electric signals (the electric signals output by the single-polarization coherent receiving chip are generally 4 paths, and the electric signals output by the double-polarization coherent receiving chip are generally 8 paths) to the electric signal receiving device 400. Finally, the electrical signal receiving apparatus 400 transmits the acquired information to the computation control apparatus 500 for processing, and outputs evaluation information of the chip phase error. With respect to the partial configuration of the front-end optical path 200, the computing control device 500 may provide control over the front-end optical path 200.
A light source 100 for providing coherent light. The light source 100 may be a continuous light coherent light source such as a tunable laser capable of adjusting the wavelength of the laser light within a certain range, or a pulse light coherent light source such as a supercontinuum light source capable of broad-spectrum laser within a certain wavelength range.
The front-end optical path 200 is configured to process the coherent light output by the light source 100, so as to output two coherent light beams with a time delay therebetween. Specifically, the front-end optical path 200 splits the input light into two beams, and causes the two beams to experience different optical paths when input to the coherent receiving chip 300 to be measured, thereby generating a time delay that is necessary for evaluating the phase error. However, the magnitude of the introduced delay need not be known when the output signal is subsequently processed and the phase error is evaluated based thereon.
The coherent receiving chip 300 to be tested is a chip to be evaluated, and when the signal light input end 310 and the local oscillator light input end 320 are of an end surface coupling structure, the evaluation system provided by the application can perform chip-level evaluation; when the signal light input end 310 and the local oscillator light input end 320 are in a vertical coupling structure, the evaluation system provided by the application can perform wafer-level or chip-level evaluation.
The electric signal receiving apparatus 400 is configured to obtain an output electric signal of the coherent receiving chip 300 to be tested, and transmit the output electric signal to the computation control apparatus 500. The electrical signal receiving apparatus 400 is a multi-channel source meter, or other electrical signal receiving apparatus with a multi-channel current reading function, and generally, in the chip-level evaluation, a probe card and a cable may be used to connect with a high-frequency signal output welding area of the to-be-tested coherent receiving chip 300.
The computing and control device 500 may be a microcomputer, or may use a single-chip microcomputer or a programmable logic array chip. In the optical path shown in fig. 1, in the part subsequent to the front-end optical path 200, if an optical fiber is used, a polarization maintaining optical fiber should be used.
The front-end optical path 200 includes: polarization controller 210, beam-splitting delay optical path.
The polarization controller is used for controlling the coherent light output by the light source 100 to output the coherent light with the polarization state required by the test, i.e. transverse electricity, transverse magnetism or mixed polarization can be obtained according to the test requirement.
And the beam splitting time delay optical path is used for splitting the coherent light output by the polarization controller and introducing time delay to the split two beams of light to form two beams of coherent light which are input to the signal light input end 310 and the local oscillation light input end 320 of the coherent receiving chip to be tested and have time delay.
As shown in fig. 2, the beam-splitting delay optical path includes: the optical fiber beam splitter 220 is disposed at the output side of the polarization controller 210, and is configured to split the coherent light output by the polarization controller 210 into two paths, and introduce a time delay to the split two beams by using the difference of lengths of the tail fibers of the optical fiber beam splitter. Because the total delay (including the delay introduced outside the coherent receiving chip and the delay existing in the coherent receiving chip) required to be introduced is generally in the order of hundreds of micrometers to millimeters when evaluating the phase error, the tolerance of the length of the tail fiber of the optical fiber beam splitter 220 is in the same order, and therefore the delay existing in the built optical fiber link can be used as the delay introduced by the evaluating system. The front-end optical path 200 shown in fig. 2 has the advantages of simple test link and low cost.
Because the fiber length tolerance of the fiber splitter 220 has randomness, when the fiber length tolerance is a specific value, the introduced delay is at risk of being too large or too small, and thus, the phase error evaluation data may be unfavorable to be extracted from the output electrical signal. Thus, as shown in fig. 3, the beam-splitting delay optical path further includes: the adjustable optical delay line 230 is disposed on an optical link where the optical fiber splitter 220 is connected to the coherent receiving chip 300 to be tested, and is used for introducing delay to two beams of light output after the optical fiber splitter 220 splits.
The coherent light output by the light source 100 is input to the polarization controller 210, and transverse electric, transverse magnetic or mixed polarization can be obtained according to the test requirement, and then is divided into two paths of output by the optical fiber beam splitter 220 (generally, a polarization maintaining beam splitter), wherein one path of the output is directly output, and the other path of the output is output through the adjustable optical delay line 230. In general, the tunable optical delay line 230 may be tested continuously for a plurality of times after a predetermined fixed delay; the control may also be performed by the computation control device 500, and the introduced delay may be adjusted in real time according to the test result. The time delay can be flexibly set, the wavelength interval between peaks and valleys of the subsequently output electric signal can be flexibly adjusted, and the phase error evaluation result can be easily extracted from the electric signal with high precision.
The number of the tunable optical delay lines 230 is one, and the tunable optical delay lines 230 are disposed on an optical link where the optical fiber splitter 220 is connected to the signal optical input end 310 of the coherent receiving chip to be tested, or an optical link where the optical fiber splitter is connected to the local oscillation optical input end 320 of the coherent receiving chip to be tested, and fig. 3 only shows one of these cases.
As shown in fig. 4, the number of the adjustable delay lines 230 is two, and two groups of adjustable delay lines 230 are respectively disposed on optical links of the optical fiber splitter 220 connected to the signal optical input end 310 and the local oscillator optical input end 320 of the coherent receiving chip to be tested. At this time, the front-end optical path 200 includes: a polarization controller 210, a fiber optic beam splitter 220, and two sets of adjustable optical delay lines 230. The adjustable optical delay line 230 which can be controlled by the computing control device 500 in real time or can be continuously used after being adjusted to a fixed value is introduced into both paths of output, and the advantage of the configuration form is that the adjustable optical delay line has the maximum delay adjustment range, thereby being beneficial to conveniently and accurately customizing the wavelength interval between peaks and valleys of the electric signal which is output subsequently.
As shown in fig. 5, the beam-splitting delay optical path is a beam-splitting delay chip, and in this case, the front-end optical path 200 includes: the polarization controller 210 and the beam splitting time delay chip 240, wherein the beam splitting time delay chip 240 is provided with two output ports, the two output ports are of an end face coupling structure, and the distance between the two output ports is equal to the distance between the two input ports of the coherent receiving chip to be tested.
The advantage of the structure shown in fig. 5 is that, when the signal optical input end 310 and the local oscillator optical input end 320 of the subsequent coherent receiving chip both adopt end-face coupling structures, the beam splitting delay chip 240 can be designed to output by adopting end-face coupling structures, the distance between the two output ports is equal to the distance between the two input ports of the coherent receiving chip, and a mode field size conversion structure is optionally introduced as an aid, so that the beam splitting delay chip 240 and the coherent receiving chip 300 to be tested are connected in a butt coupling mode, and the chip butt joint chip can be tested rapidly.
As shown in fig. 6, the beam-splitting delay chip 240 includes: a beam splitter 61 and two on-chip waveguides 62 having different optical paths. The beam splitter 61 splits the coherent light beam output from the polarization controller 210, and the split two light beams are output after passing through the two on-chip waveguides 62, so as to introduce a time delay to the split two light beams. The advantage of this form is that the introduction is simple and easy to use without additional control.
As shown in fig. 7, the beam-splitting delay chip 240 includes: the beam splitter 61, the first optical path 241, and the second optical path 242, and a plurality of on-chip waveguides 62 having mutually different optical paths are provided between the first optical path 241 and the second optical path 242. The beam splitter 61 splits the coherent light output by the polarization controller 210, one path of split light is transmitted in the optical waveguide on the chip and directly output, and the other path of split light is guided to one path of on-chip waveguides 62 with different optical paths after passing through the first optical path 241, and then passes through the second optical path 242 and then output. The optical routing is typically implemented in a mach-zehnder interferometer, a mach-zehnder interferometer network, or a micro-ring resonator array, and is controlled by a computing control device 500. The advantage of this form of construction is that it is compatible with both end-face docking test schemes and the delay introduced by the test is adjustable.
As shown in fig. 8, the polarization controller is integrated at the front end of the beam-splitting delay chip to form a polarization-controlling beam-splitting delay chip 250, and the polarization-controlling beam-splitting delay chip 250 is based on the beam-splitting delay chip shown in fig. 6 or fig. 7, and a polarization-controlling device, such as a polarization filter through which a transverse electric mode or a transverse magnetic mode can pass, is added at the front end.
The beam splitting delay chip 240 and the polarization control beam splitting delay chip 250 in fig. 5 and 8 may be planar optical waveguide circuit (PLC) chips, or silicon-based, silicon-silicon nitride, or group iii-v chips. The chip may be simply packaged at the input, for example, by packaging a pigtail. The packaging may be omitted and light may be directly coupled in by an optical fiber or lens at the time of testing. The output end can package tail fibers with the same length; it may also be preferable to interface directly with the coherent receiving chip 300 to be tested.
The phase error evaluation system, in particular to the construction of an optical test system, enables the phase error to be measured in chip-level test, simultaneously can evaluate the phase error of a coherent receiving chip by introducing time delay through an external light path on the basis of not changing the original chip design of the coherent receiving chip, and can be widely applied to the coherent receiving chip constructed by a mixer based on various principles and structures without adding an optical structure on the chip.
The phase error evaluation system can be used for carrying out quality control in advance before packaging the coherent receiving chips into the coherent receiving module, selecting the chips which cannot meet the requirement of the index of the phase error, and preventing the risk of overlarge phase error from overflowing to the module level. The application meets the requirement of inputting a pair of coherent light with time delay from the chip signal light input end and the local oscillation light input end required by testing the phase error in the forms of external beam splitting and time delay. And the test link is flexible in structure, and the requirements of various coherent receiving chip designs and tests under different equipment bases are provided.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present application should be included in the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. A phase error evaluation system of a coherent receiving chip, comprising:
a light source for providing coherent light;
the front-end light path is used for processing the coherent light to output two coherent light beams with time delay, and the front-end light path comprises:
the polarization controller is used for controlling the coherent light output by the light source to output the coherent light with the polarization state required by the test;
and the beam splitting time delay light path is used for splitting the coherent light output by the polarization controller and introducing time delay to the split two beams of light to form two beams of coherent light which are input to the signal light input end and the local oscillation light input end of the coherent receiving chip to be tested and have time delay.
2. The phase error evaluation system of a coherent receiving chip according to claim 1, wherein the beam-splitting delay optical path comprises: and the optical fiber beam splitter is used for dividing the coherent light output by the polarization controller into two paths and introducing time delay to the two split light beams by utilizing the length difference value of the tail fiber of the optical fiber beam splitter.
3. The phase error evaluation system of a coherent receiving chip according to claim 2, wherein the beam-splitting delay optical path further comprises: and the adjustable optical delay line is arranged on an optical link connected with the optical fiber beam splitter and the coherent receiving chip to be tested and is used for introducing delay to two beams of light output after the optical fiber beam splitter splits.
4. The system for evaluating phase errors of a coherent receiving chip according to claim 3, wherein the number of the adjustable delay lines is one, and the adjustable delay lines are disposed on an optical link connected to a signal optical input terminal of the coherent receiving chip to be tested or an optical link connected to a local oscillation optical input terminal of the coherent receiving chip to be tested.
5. The system for evaluating the phase error of a coherent receiving chip according to claim 3, wherein the number of the adjustable optical delay lines is two, and two groups of the adjustable optical delay lines are respectively arranged on optical links of the optical fiber beam splitter, which are connected with the signal optical input end and the local oscillation optical input end of the coherent receiving chip to be tested.
6. The system for evaluating the phase error of a coherent receiving chip according to claim 1, wherein the beam-splitting delay optical path is a beam-splitting delay chip, the beam-splitting delay chip has two output ports, the two output ports are of an end-face coupling structure, and the distance between the two output ports is equal to the distance between the two input ports of the coherent receiving chip to be tested.
7. The phase error evaluation system of claim 6, wherein the beam splitting delay chip comprises: two on-chip waveguides with different beam splitters and optical paths; and the beam splitter splits the coherent light output by the polarization controller, and the split two beams of light are output after passing through the two on-chip waveguides so as to introduce time delay into the split two beams of light.
8. The phase error evaluation system of claim 6, wherein the beam splitting delay chip comprises: the optical system comprises a beam splitter, a first optical route and a second optical route, wherein a plurality of on-chip waveguides with mutually different optical paths are arranged between the first optical route and the second optical route;
the beam splitter splits the coherent light output by the polarization controller, one path of split light is transmitted in the optical waveguide on the chip and directly output, and the other path of split light is guided to one path of on-chip waveguides with different multipath optical paths after passing through the first optical path and then is output after passing through the second optical path.
9. The system for evaluating the phase error of a coherent receiving chip according to claim 7 or 8, wherein the polarization controller is integrated in a front end of the beam-splitting delay chip.
10. The phase error evaluation system of a coherent receiving chip according to claim 1, further comprising: the system comprises a calculation control device and an electric signal receiving device, wherein the electric signal receiving device acquires an output electric signal of a coherent receiving chip to be detected and transmits the output electric signal to the calculation control device.
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| CN202311087660.3A CN117060996A (en) | 2023-08-28 | 2023-08-28 | Phase error evaluation system of coherent receiving chip |
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| CN202311087660.3A CN117060996A (en) | 2023-08-28 | 2023-08-28 | Phase error evaluation system of coherent receiving chip |
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