CN117060864A

CN117060864A - Neural network-aided physical modeling of envelope features

Info

Publication number: CN117060864A
Application number: CN202310531137.9A
Authority: CN
Inventors: 于弢; C·梅耶
Original assignee: Analog Devices Inc
Current assignee: Analog Devices Inc
Priority date: 2022-05-13
Filing date: 2023-05-12
Publication date: 2023-11-14

Abstract

The present disclosure relates to digital predistortion of neural network-aided physical modeling of envelope features. Systems, devices, and methods related to envelope modulated Digital Predistortion (DPD) are provided. Example devices include: an envelope adjuster circuit for processing the input signal based on the parameterized model to generate an envelope adjustment signal; a Digital Predistortion (DPD) actuator circuit for processing the envelope adjustment signal and the input signal based on DPD coefficients associated with the nonlinear characteristics of the nonlinear component; and a DPD adaptation circuit for updating the DPD coefficients based on a feedback signal indicating an output of the nonlinear component.

Description

Neural network-aided physical modeling of envelope features

Cross Reference to Related Applications

The present application claims the priority and benefit of U.S. patent application Ser. No.17/948,482 entitled "digital predistortion of neural network-aided physical modeling of envelope characteristics" filed on month 9 and 20 of 2022 and U.S. provisional patent application Ser. No.63/341,746 entitled "digital predistortion based on neural network-aided physical model for Power Amplifier drain inductance resonance suppression", filed on month 13 of 2022, the technical disclosures of each of which are fully incorporated herein by reference as if fully set forth below, and for all applicable purposes.

Technical Field

The present disclosure relates generally to electronic devices, and more particularly to Digital Predistortion (DPD).

Background

An RF system is a system that transmits and receives signals in the form of electromagnetic waves in the RF range of about 3 kilohertz (kHz) to 300 gigahertz (GHz). RF systems are commonly used for wireless communications, cellular/wireless mobile technology is a prominent example, but may also be used for wired communications, such as cable television. In both types of systems, the linearity of the various components plays a crucial role.

The linearity of an RF component or system such as an RF transceiver is theoretically well understood. That is, linearity generally refers to the ability of a component or system to provide an output signal that is proportional to an input signal. In other words, if the component or system is perfectly linear, then the relationship of the ratio of the output signal to the input signal is a straight line. This behavior is much more complex to implement in real-life components and systems, and many challenges to linearity must be addressed, often at the expense of some other performance parameters, such as efficiency and/or output power.

The Power Amplifier (PA) is made of inherently non-linear semiconductor material and must operate at relatively high power levels, which is typically the first component to analyze when considering the linear design of an RF system. PA output with nonlinear distortion may result in reduced modulation accuracy (e.g., reduced Error Vector Magnitude (EVM)) and/or out-of-band emissions. Thus, both wireless RF systems (e.g., long Term Evolution (LTE) and millimeter wave or fifth generation (5G) systems) and cable RF systems have stringent PA linearity specifications.

DPD may be used to enhance the linearity of the PA. In general, DPD involves predistortion of a signal input as a PA in the digital domain to reduce and/or eliminate distortion expected to be caused by the PA. Predistortion may be characterized by a PA model. The PA model may be updated based on feedback from the PA (i.e., based on the PA output). The more accurate the PA model is in predicting the distortion that the PA will introduce, the more efficient the predistortion of the input to the PA is in reducing the impact of the amplifier-induced distortion.

Performing DPD in a radio frequency system is not an easy task because various factors affect the cost, quality and robustness of DPD. Physical constraints such as space/surface area and regulations may place further constraints on the requirements or specifications of DPD. As the sampling rate used in the most advanced RF systems continues to increase, DPD becomes particularly challenging and thus trade-offs and originality must be made in designing DPD.

Drawings

In order to provide a more complete understanding of the present disclosure, and features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts, and in which:

FIG. 1A provides a schematic block diagram of an exemplary Radio Frequency (RF) transceiver in which parameterized model-based Digital Predistortion (DPD) may be implemented, according to some embodiments of the present disclosure;

FIG. 1B provides a schematic block diagram of an exemplary indirect learning architecture-based DPD in which a parameterized model-based configuration may be implemented, in accordance with some embodiments of the present disclosure;

FIG. 1C provides a schematic block diagram of an exemplary direct learning architecture-based DPD in which a parameterized model-based configuration may be implemented, in accordance with some embodiments of the present disclosure;

FIG. 2 illustrates an exemplary Power Amplifier (PA) drain inductor resonance effect;

fig. 3 provides a schematic diagram illustrating an exemplary high power PA in which drain inductor resonance may occur;

fig. 4 provides a block diagram illustrating an exemplary neural network aided physical model for pre-compensating PA gain oscillations, according to an embodiment of the present disclosure;

FIG. 5 provides a block diagram illustrating an exemplary neural network assisted envelope adjustment DPD model with mid-term memory envelope features, in accordance with an embodiment of the disclosure;

fig. 6 illustrates a Finite Impulse Response (FIR) impulse response diagram representing PA drain bias feed in accordance with some aspects of the present disclosure;

7A-7B illustrate amplitude and phase diagrams, respectively, of a two-dimensional (2D) look-up table (LUT) according to some aspects of the present disclosure;

FIG. 8 provides a flowchart illustrating an exemplary method for performing DPD in conjunction with parameterized model-based envelope adjustment on target hardware in accordance with some embodiments of the present disclosure;

FIG. 9 provides a flowchart illustrating an exemplary method for training a parameterized model of envelope adjustment, which may be used in connection with DPD operation, according to some embodiments of the present disclosure; and

FIG. 10 provides a block diagram illustrating an exemplary data processing system that may be configured to implement or control at least part of a hardware block configuration using a neural network, according to some embodiments of the present disclosure.

Detailed Description

Overview of the invention

The systems, methods, and devices of the present disclosure each have several innovative embodiments, none of which are solely responsible for the desirable attributes disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the description and the accompanying drawings.

To illustrate DPD using the neural networks presented herein, it may be useful to first understand the phenomena that may play a role in an RF system. The following basic information may be regarded as a basis on which the present disclosure can be properly interpreted. Such information is provided for illustrative purposes only and should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.

As mentioned above, PA is typically the first component to analyze when considering the linear design of RF systems. Having a linear and efficient PA is essential for wireless and wired RF systems. While linearity is also important for small signal amplifiers, such as low noise amplifiers, the challenges of linearity are particularly apparent for PAs, as such amplifiers are often required to produce relatively high output power levels and thus are particularly easy to enter into certain operating conditions where non-linear behavior can no longer be ignored. On the one hand, when an amplifier operates on a signal having a high power level (such operating conditions are often referred to as "saturation operation"), the nonlinear behavior of the semiconductor material used to form the amplifier tends to deteriorate, thereby increasing the amount of nonlinear distortion in its output signal, which is highly undesirable. On the other hand, amplifiers that operate at relatively high power levels (i.e., operate at saturation) typically also operate at their highest efficiency, which is highly desirable. Thus, linearity and efficiency (or power level) are two performance parameters for which an acceptable compromise must generally be found, since improvements in one of these parameters come at the cost of suboptimal another parameter. For this reason, the term "back-off" is used in the art to describe how much the input power (i.e., the power of the signal provided to the amplifier to be amplified) should be reduced to achieve a measure of the desired output linearity (e.g., the back-off may be measured as the ratio between the input power providing the maximum power and the input power providing the desired linearity). Thus, reducing the input power may provide improvements in linearity, but result in reduced efficiency of the amplifier.

Also as described above, DPD may predistort the input of the PA to reduce and/or eliminate distortion caused by the amplifier. To achieve this function, at a high level, DPD involves forming a model of how the PA affects the input signal, defining coefficients of a filter to be applied to the input signal (such coefficients are referred to as "DPD coefficients") in an attempt to reduce and/or eliminate distortion of the input signal caused by the amplifier. In this way, the DPD will attempt to compensate the amplifier to apply an undesirable non-linear modification to the signal to be transmitted by applying a corresponding modification to the input signal to be provided to the amplifier.

The models used in DPD algorithms are typically adaptive models, meaning that they are formed in an iterative process by gradually adjusting coefficients based on a comparison between data input into the amplifier and data output from the amplifier. The estimation of DPD coefficients is based on the acquisition of a finite sequence of input and output data (i.e. the input and output of the PA), commonly referred to as "acquisition", and forms a feedback loop in which the model is adjusted based on analysis of the acquisition. More specifically, the conventional DPD algorithm is based on a Generic Memory Polynomial (GMP) model that includes forming a set of polynomial equations, commonly referred to as "update equations", and searching a broad solution space for an appropriate solution of the equations to update the model of the PA. For this purpose, the DPD algorithm solves an inverse problem, deriving occasional factors for a set of observations from these observations.

Solving the inverse problem in the presence of nonlinear effects can be challenging and can be uncomfortable. In particular, the inventors of the present disclosure realized that GMP-based PA models may have limitations due to the signal dynamics and limited memory depth required to store polynomial data, especially in the case of the ever-increasing sampling rates used in high power PAs present at state of the art RF systems and macro base stations.

Solid state devices that can be used for high frequencies are of great importance in modern semiconductor technology. Due in part to their large band gap and high mobility, III-N based transistors (i.e., transistors using a compound semiconductor material having a first sub-lattice of at least one element from group III of the periodic table (e.g., al, ga, in) and a second sub-lattice of nitrogen (N) as channel materials), such as GaN based transistors, may be particularly advantageous for high frequency applications. In particular, gaN transistors may be used to build PA.

While GaN transistors have desirable characteristics in terms of cut-off frequency and efficiency, their behavior is complicated by an effect known as charge trapping, in which defective sites in the transistor channel trap charge carriers. The density of trapped charge depends to a large extent on the gate voltage, which is generally proportional to the signal amplitude. More complex, the opposite effect may compete simultaneously with the effect of charge trapping. That is, when some charge carriers are trapped by the defect sites, other charge carriers are released from the traps, for example, due to thermal activation. These two effects have distinct time constants: whenever the gate voltage increases, the defective portion may be rapidly filled with the trapped charge, and the release of the trapped charge is slow. The release time constant may be 10 microseconds, up to milliseconds, and this effect is often very pronounced on the time scale of the symbol period of 4G or 5G data, especially for data containing bursts.

Various improvements have been made to DPD operating under 5G wireless communications. For example, to improve the 5G transceiver handling wideband distortion with complex frequency dependent behavior, higher order nonlinear terms are introduced. However, the PA at the macro base station is typically a high power PA (e.g., with an output power of 40 watts (W) or more) so that sufficient area coverage may be provided. These high power PAs may present new challenges. For example, the release of the trapped charge may occur on a faster time scale, e.g., from hundreds of nanoseconds to tens of microseconds. Furthermore, the drain bias of a high power PA may typically be 28-50 volts (V) Direct Current (DC) provided by a bias network with large inductance to maintain a high current draw when transmitting complex waveforms (e.g., broadband signals with high slew rates or fast switching waveforms). A typical drain bias network may use a quarter-wave line/RF short to feed direct low frequency (DC/LF) current while blocking RF with a minimum RF load output by the power transistor. However, when providing an envelope Bandwidth (BW) current pulse to a high power PA, the limited bias feed inductor may oscillate with the drain decoupling capacitor. This oscillation in turn may cause ringing effects at the output of the high power PA. Ringing effects may occur in the form of gain oscillations, which may be nonlinear. In some examples, the memory effect due to drain voltage resonance may last about 4-6 microseconds, which may be much longer than the typical range of DPD (e.g., DPD for 5G transceivers) processing. Furthermore, ringing effects may result in unnecessary out-of-band emissions that fail to meet certain regulations (e.g., as defined by the federal communications commission). Thus, it may be beneficial to mitigate the adverse effects of PA drain inductor resonance.

Various embodiments of the present disclosure provide systems and methods directed to improving one or more of the above-described challenges and/or drawbacks in providing linear and efficient amplifiers (e.g., without limitation, PAs) for RF systems (e.g., without limitation, millimeter wave/5G technology wireless RF systems). In particular, aspects of the present disclosure provide techniques for modeling complex mappings between PA drain voltage and gain oscillations using machine learning (e.g., neural networks) such that ringing effects (or PA gain oscillations) from the PA drain may be mitigated, for example, prior to DPD actuation.

Aspects of the present disclosure provide an apparatus for applying DPD to an input signal of a nonlinear component. The nonlinear component may be a high power PA and may have gain oscillation (or gain variation) problems due to PA drain inductor resonance as described above. To pre-compensate for the gain oscillation, the apparatus may include an envelope adjuster circuit, a DPD actuator circuit, and a DPD adaptation circuit. The envelope adjuster circuit may process an envelope (e.g., amplitude) of the input signal based on the parameterized model to generate an envelope adjustment signal (e.g., a gain oscillation precompensation signal). The DPD actuator circuit may process the envelope adjustment signal and the input signal based on DPD coefficients associated with the non-linear characteristics of the non-linear components. The DPD adaptation circuit may update the DPD coefficients based on a feedback signal indicating the output of the nonlinear component.

In some aspects, the envelope adjuster circuit may include a gain adjustment model associated with the voltage variation of the nonlinear component, and the apparatus may further include a control block (e.g., a hardware control register) to configure the gain adjustment model based on the parameterized model. In some aspects, the gain adjustment model in the envelope adjuster circuit may be based on drain inductor resonance of the nonlinear component. In some aspects, the gain adjustment model in the envelope adjuster circuit may include a look-up table (LUT) generated based on the parameterized model. The LUT may be a two-dimensional (2D) LUT that maps voltage variations of the nonlinear components and an envelope (e.g., instantaneous envelope) of the input signal to gain values.

In some aspects, the drain bias feed of the PA may be modeled by a Finite Impulse Response (FIR). Thus, the envelope adjuster circuit may further comprise a filter (e.g., a FIR filter) upstream of the gain adjustment model, the control block may further configure the filter based on the parameterized model, and the envelope adjuster circuit may further process the envelope of the input signal based on the filter. In some cases, the filter may model at least one of an input signal envelope or an input voltage variation associated with the nonlinear component. In some aspects, the DPD actuator circuit may operate at a sampling rate that samples the input signal, while the filter may operate at a lower sampling rate than the input signal sampling rate (e.g., at a decimated sampling rate so that computational load may be reduced). In this regard, the envelope adjuster circuit may further include a downsampler upstream of the filter and an upsampler downstream of the filter, and the control block may further configure the downsampler and the upsampler based on the parameterized model.

In some aspects, the envelope adjuster circuit may include a first path (signal path) and a second path (signal path) arranged in parallel with the first path. The first path may include a first downsampler, a first filter, a first upsampler, and a first voltage variation and signal envelope to gain mapping table (which may be a 2D LUT mapping voltage variation and signal envelope to gain values). Similarly, the second path may include a second downsampler, a second filter, a second upsampler, and a second voltage variation and signal envelope to gain mapping table (which may be a 2D LUT mapping voltage variation and signal envelope to gain values). The first voltage variation and signal envelope to gain mapping table may be different from the second voltage variation and signal envelope to gain mapping table. Additionally or alternatively, the first and second downsamplers may be based on different downsampling factors. Additionally or alternatively, the first upsampler and the second upsampler may be based on different upsampling factors. Additionally or alternatively, the first filter and the second filter may be different filters (having different filter coefficients).

In some aspects, the parameterized model may be an offline trained neural network. For example, a computer-implemented system may implement a method for training a parameterized model to provide envelope adjustment such that PA gain oscillations caused by PA drain-inductor resonance may be mitigated. A computer-implemented system may receive a data set comprising one or more data pairs, each data pair comprising an input signal and an observation signal associated with a PA (e.g., a high power PA). For example, the input signal and the observed signal may be collected from the target hardware. The computer-implemented system may further train the parameterized model based on the data set. As part of training the parameterized model, the computer-implemented system may update at least one parameter of the parameterized model associated with configuring a plurality of processing units associated with the envelope adjuster circuit. The method may include outputting one or more configurations for a plurality of processing units associated with the envelope adjuster circuit based on the training.

In some aspects, a computer-implemented system may generate a parameterized model. As part of generating the parameterized pattern, the computer-implemented system may generate a mapping between each of a plurality of processing units associated with the envelope adjuster circuit and one of a plurality of differentiable functional blocks.

In some aspects, the envelope adjustment of the nonlinear component may comprise a sequence of operations, wherein the computer-implemented system may further calculate a parameter for each operation in the sequence of operations. In some aspects, calculating the parameter for each operation in the sequence of operations is further based on a back propagation process and a loss function. In some aspects, the operational sequence of envelope adjustment of the nonlinear component may include at least one of a downsampling operation, a filtering operation, an upsampling operation, or a PA drain voltage to gain mapping operation.

The systems, schemes, and mechanisms described herein advantageously use a physical model with the help of a neural network to model drain inductance resonance of a macro base station PA (high power PA). The physical configuration may enable the model to significantly improve DPD performance while maintaining the compactness and interpretability of the model. The disclosed embodiments may also facilitate digital implementations using lightweight components (e.g., processing components). The disclosed embodiments further provide for successful adoption of data-driven methods in traditional modeling spaces, where numerical models such as neural networks bring new perspectives for improving physical models. While the present disclosure is discussed in the context of modeling physical behavior of drain inductance resonance in a high power PA using a neural network and configuring target hardware based on the model to pre-compensate for the behavior, the disclosed techniques may be applicable to modeling any type of physical behavior of a component (e.g., a nonlinear component) and configuring target hardware to compensate for the behavior based on the model.

Example radio frequency Transceiver with DPD arrangement

Fig. 1A provides a schematic block diagram of an exemplary RF transceiver 100 in which parameterized model-based envelope adjustment DPD may be implemented, according to some embodiments of the present disclosure. As shown in fig. 1A, RF transceiver 100 may include DPD circuit 110, transmitter circuit 120, PA130, antenna 140, and receiver circuit 150.

DPD circuit 110 is configured to receive an input signal 102, represented by x, the input signal 102 may be a sequence of digital samples and may be a vector. Generally, as used herein, each lower case bold italic single letter label used in this figure (e.g., labels x, z, y, and y' shown in fig. 1A) refers to a vector. In some embodiments, the input signal 102x may include one or more active channels in the frequency domain, but for simplicity, an input signal having only one channel (i.e., a single frequency range of in-band frequencies) is described. In some embodiments, the input signal x may be a baseband digital signal. DPD circuit 110 is configured to generate an output signal 104, which may be represented by z, based on input signal 102 x. DPD output signal 104z may be further provided to transmitter circuitry 120. To this end, DPD circuit 110 may include a DPD actuator 112 and a DPD adaptation circuit 114. In some embodiments, the actuator 112 may be configured to generate the output signal 104z based on the input signal 102x and the DPD coefficients c calculated by the DPD adaptation circuit 114, as described in more detail below.

The transmitter circuit 120 may be configured to upconvert the signal 104z from a baseband signal to a higher frequency signal, such as an RF signal. The RF signal generated by the transmitter 120 may be provided to the PA130, and the PA130 may be implemented as a PA array including N individual PAs. The PA130 may be configured to amplify the RF signal generated by the transmitter 120 (and thus, the PA130 may be driven by a drive signal based on the output of the DPD circuit 110) and output an amplified RF signal 131, which amplified RF signal 131 may be represented by y (e.g., a vector).

In some embodiments, RF transceiver 100 may be a wireless RF transceiver, in which case it will also include antenna 140. In the context of a radio frequency system, an antenna is a device that serves as an interface between radio waves propagating wirelessly in space and currents moving in metallic conductors used in transmitters, receivers or transceivers. During transmission, the transmitter circuitry of the RF transceiver may provide an electrical signal that is amplified by the PA and an amplified version of the signal is provided to the terminals of the antenna. The antenna may then radiate the energy of the signal from the PA output as a radio wave. Antennas are an important component of all radio devices for radio broadcasting, broadcast television, two-way radio, communication receivers, radar, cell phones, satellite communications and other devices.

An antenna with a single antenna element will typically broadcast a radiation pattern that radiates uniformly in all directions in a spherical wavefront. Phased antenna arrays generally refer to a set of antenna elements that focus electromagnetic energy in a particular direction to produce a main beam, a process commonly referred to as "beamforming". Phased antenna arrays have many advantages over single antenna systems, such as high gain, the ability to perform directional control, and simultaneous communication. As a result, phased array antenna arrays are increasingly frequently used in a variety of different applications, such as mobile/cellular wireless technology, military applications, aircraft radar, automotive radar, industrial radar, and Wi-Fi technology.

In embodiments where RF transceiver 100 is a wireless RF transceiver, amplified RF signal 131y may be provided to antenna 140 and antenna 140 may be implemented as an antenna array comprising a plurality of antenna elements (e.g., N antenna elements). The antenna 140 is configured to wirelessly transmit the amplified RF signal 131y.

In embodiments where RF transceiver 100 is a wireless RF transceiver of a phased antenna array system, RF transceiver 100 may further include a beamformer arrangement configured to alter the input signals provided to the individual PAs of PA array 130 to steer the beam generated by antenna array 140. Such a beamformer arrangement is not specifically shown in fig. 1, as it may be implemented in different ways, for example as an analog beamformer (i.e. modifying the input signals to be amplified by the PA array 130 in the analog domain, i.e. after these signals have been converted from the digital domain to the analog domain), as a digital beamformer (i.e. the input signals to be amplified by the PA array 130 are modified in the digital domain, i.e. before these signals are converted from the digital domain to the analog domain), or as a hybrid beamformer, i.e. the input signals to be amplified by the PA array 130 are modified partly in the digital domain and partly in the analog domain.

Ideally, the amplified RF signal 131y from the PA130 should be only an up-converted and amplified version of the output of the transmitter circuit 120, e.g., up-converted, amplified, and beamformed version of the input signal 102 x. However, as described above, the amplified radio frequency signal 131y may have distortion outside the main signal component. Such distortion may be caused by nonlinearities in the response of the PA 130. As noted above, it may be desirable to reduce such nonlinearities. Thus, the RF transceiver 100 may further include a feedback path (or observation path) that allows the RF transceiver to analyze the amplified RF signal 131y (in the transmission path) from the PA 130. In some embodiments, a feedback path as shown in fig. 1A may be implemented, where a feedback signal 151y' may be provided from PA130 to receiver circuit 150. However, in other embodiments, the feedback signal may be a signal from a sounding antenna element configured to sense a wireless RF signal transmitted by the antenna 140 (not specifically shown in fig. 1A).

Thus, in various embodiments, at least a portion of the output of PA130 or the output of antenna 140 may be provided as feedback signal 151 to receiver circuit 150. The output of the receiver circuit 150 is coupled to the DPD circuit 110, and in particular to the DPD-adaptation circuit 114. In this way, the output signal 151 (y') of the receiver circuit 150 may be provided to the DPD adaptation circuit 114 by the receiver circuit 150, the output signal 151 being a signal based on the feedback signal 151, the feedback signal 151 in turn being indicative of the output signal 131 (y) from the PA 130. The DPD adaptation circuit 114 may process the received signal and update the DPD coefficients applied to the input signal 102x by the DPD actuator circuit 112 to produce the actuator output 104z. A signal based on the actuator output z is provided as an input to the PA130, which means that the DPD actuator output z can be used to control the operation of the PA 130.

According to aspects of the present disclosure, DPD circuit 110 may further include an envelope adjuster circuit 116. As will be discussed in more detail below, the envelope adjuster circuit 116 may be configured based on a parameterized model 170. Envelope adjuster circuit 116 may operate on input signal 102x to mitigate the effects of drain inductor resonance at PA 130 (e.g., as shown in fig. 2). For example, the RF transceiver 100 may be part of a macro base station and the PA 130 may be a high power PA (e.g., providing an output power of greater than about 40W). Parameterized model 170 may be based on a neural network generated and trained offline by parameterized model training system 172 (e.g., a computer-implemented system such as data processing system 2300 shown in FIG. 8), as will be discussed more fully below with reference to FIGS. 2-7. In some aspects, the operation of DPD actuator circuit 112 and DPD adaptation circuit 114 may be modeled as part of the training of parameterized model 170. Further, DPD actuator circuit 112 and/or DPD adaptation circuit 114 may be configured to implement DPD using an indirect learning architecture as shown in fig. 1B or using a direct learning architecture as shown in fig. 1C.

As further shown in fig. 1A, in some embodiments, the transmitter circuit 120 may include a digital filter 122, a digital-to-analog converter (DAC) 124, an analog filter 126, and a mixer 128. In such a transmitter, the predistortion signal 104z may be filtered in the digital domain by a digital filter 122 to generate a filtered predistortion input, i.e., a digital signal. The output of the digital filter 122 may then be converted to an analog signal by the DAC 124. The analog signal generated by DAC124 may then be filtered by analog filter 126. The output of the analog filter 126 may then be up-converted to RF by the mixer 128, and the mixer 128 may receive a signal from the Local Oscillator (LO) 162 to convert the filtered analog signal from the analog filter 126 from baseband to RF. Other methods of implementing the transmitter circuit 120 are possible and are within the scope of this disclosure. For example, in another implementation (not shown in the figures), the output of the digital filter 122 may be directly converted to an RF signal by the DAC124 (e.g., in a direct RF architecture). In such an implementation, the RF signal provided by DAC124 may then be filtered by analog filter 126. Since in this embodiment DAC124 will directly synthesize the RF signal, in such an embodiment mixer 128 and local oscillator 162 shown in fig. 1A may be omitted from transmitter circuit 120.

As further shown in fig. 1A, in some embodiments, the receiver circuit 150 may include a digital filter 152, an analog-to-digital converter (ADC) 154, an analog filter 156, and a mixer 158. In such a receiver, feedback signal 151 may be down-converted to baseband by mixer 158, and mixer 158 may receive a signal from Local Oscillator (LO) 160 (which may be the same or different from local oscillator 160) to convert feedback signal 151 from RF to baseband. The output of mixer 158 may then be filtered by analog filter 156. The output of the analog filter 156 may then be converted to a digital signal by the ADC 154. The digital signal generated by ADC 154 may then be filtered in the digital domain by digital filter 152 to generate a filtered down-converted feedback signal 151y', which may be a sequence of digital values indicative of the output y of PA 130, and may also be modeled as a vector. The feedback signal 151y' may be provided to the DPD circuit 110. Other methods of implementing the receiver circuit 150 are possible and are within the scope of this disclosure. For example, in another implementation (not shown in the figures), the RF feedback signal 151' may be directly converted to a baseband signal by the ADC 154 (e.g., in a direct RF architecture). In such an implementation, the down-converted signal provided by ADC 154 may then be filtered by digital filter 152. Since in this implementation ADC 154 will directly synthesize the baseband signal, in such an embodiment mixer 158 and local oscillator 160 shown in fig. 1A may be omitted from receiver circuit 150.

Further variations of the RF transceiver 100 described above are possible. For example, although frequency up-conversion and frequency down-conversion are described with respect to baseband frequencies, in other embodiments of RF transceiver 100, intermediate Frequencies (IF) may be used instead. The IF may be used in a superheterodyne radio receiver in which the received RF signal is shifted to the IF before final detection of the information in the received signal is completed. Conversion to IF may be useful for several reasons. For example, when several stages of filters are used, they can all be set to a fixed frequency, which makes them easier to build and tune. In some embodiments, the mixer of RF transmitter 120 or receiver 150 may include several such IF conversion stages. In another example, although a single-path mixer is shown in each of the Transmit (TX) path (i.e., the signal path for the signal to be processed by transmitter 120) and the Receive (RX) path (e.g., for the signal to be processed by receiver 150) of RF transceiver 100, TX path mixer 128 and RX path mixer 158 may be implemented as quadrature up-and down-converters, respectively, in which case they each include a first mixer and a second mixer. For example, for RX path mixer 158, the first RX path mixer may be configured to perform down-conversion to generate an in-phase (I) down-converted RX signal by mixing feedback signal 151 and an in-phase component of the local oscillator signal provided by local oscillator 160. The second RX path mixer may be configured to perform frequency down-conversion to generate a quadrature (Q) down-converted RX signal by mixing feedback signal 151 with a quadrature component of the local oscillator signal provided by local oscillator 160, which is a component 90 degrees out of phase with the in-phase component of the local oscillator signal. The output of the first RX path mixer may be provided to an I signal path and the output of the second RX path mixer may be provided to a Q signal path, which may be substantially 90 degrees out of phase with the I signal path. In general, transmitter circuitry 120 and receiver circuitry 150 may use a zero IF architecture, a direct conversion RF architecture, a complex IF architecture, a high (real) IF architecture, or any suitable RF transmitter and/or receiver architecture.

In general, the RF transceiver 100 may be any device/apparatus or system configured to support transmission and reception of signals in the form of electromagnetic waves in the RF range of approximately 3kHz to 300 GHz. In some embodiments, the RF transceiver 100 may be used for wireless communication, for example, in a Base Station (BS) or User Equipment (UE) device of any suitable cellular wireless communication technology, such as global system for mobile communications (GSM), code Division Multiple Access (CDMA), or LTE. In another example, RF transceiver 100 may be used as a BS or UE device for millimeter wave wireless technology (e.g., 5G wireless) or used in, for example, a BS or UE (i.e., high frequency/short wavelength spectrum, e.g., having frequencies in the range between about 20 and 60GHz, corresponding to wavelengths in the range between about 5 and 15 millimeters). In yet another example, the RF transceiver 100 may be used for wireless communication using Wi-Fi technology (e.g., a frequency band of 2.4GHz, corresponding to a wavelength of about 12cm, or a frequency band of 5.8GHz, spectrum, corresponding to a wavelength of about 5 cm), for example, in applications such as desktops, laptops, video game consoles, smartphones, tablets, smarttelevisions, digital audio players, automobiles, printers, and the like. In some implementations, the Wi-Fi enabled device may be, for example, a node in an intelligent system configured to communicate data with other nodes (e.g., intelligent sensors). In yet another example, the RF transceiver 100 may be used for wireless communication using bluetooth technology (e.g., a frequency band from about 2.4 to about 2.485GHz, corresponding to a wavelength of about 12 cm). In other embodiments, the RF transceiver 100 may be used to transmit and/or receive wireless RF signals for purposes other than communication, for example, in an automotive radar system, or in medical applications such as Magnetic Resonance Imaging (MRI). In other embodiments, the RF transceiver 100 may be used for wired communications, such as in a cable television network.

Fig. 1B provides a schematic block diagram of an exemplary indirect learning architecture-based DPD 180 in which parameterized model-based configurations may be implemented, according to some embodiments of the present disclosure. In some aspects, DPD circuit 110 of fig. 1A may be implemented as shown in fig. 1B, and parameterized model training system 172 may train parameterized model 170 to configure DPD circuit 100 for indirect learning based adaptation. For simplicity, the transmitter circuit 120 and the receiver circuit 150 are not shown in fig. 1B, and only the elements related to performing DPD are shown.

For indirect learning, DPD adaptation circuit 114 may use the observed received signal (e.g., feedback signal 151 y') as a reference to predict PA input samples corresponding to the reference. The function used to predict the input samples is called the inverse PA model (for linearizing the PA 130). Once the prediction of the input samples corresponding to the observed data is good (e.g., when the error between the predicted input samples and the predistortion signal 104z meets certain criteria), the estimated inverse PA model is used to predistort the transmit data (e.g., the input signal 102 x) to the PA 130. That is, DPD adaptation circuit 114 may calculate an inverse PA model that is used by DPD actuator circuit 112 to predistort input signal 102 x. To this end, DPD adaptation circuit 114 may observe or capture N PA input samples (from predistortion signal 104 z) and N PA output samples (from feedback signal 151 y'), calculate a set of M coefficients, which may be represented by c, corresponding to the inverse PA model, and update DPD actuator circuit 112 with coefficient c, as indicated by the dashed arrow. In some examples, DPD adaptation circuit 114 may solve for the set of coefficients c using a least squares approximation.

Fig. 1C provides a schematic block diagram of an exemplary direct learning architecture-based DPD 190 in which a parameterized model-based configuration may be implemented, according to some embodiments of the present disclosure. In some aspects, DPD circuit 110 of fig. 1A may be implemented as shown in fig. 1C, and parameterized model training system 172 may train parameterized model 170 to configure the DPD circuit for direct learning. For simplicity, the transmitter circuit 120 and the receiver circuit 150 are not shown in fig. 1B, and only the elements related to performing DPD are shown.

For direct learning, DPD adaptation circuit 114 may use input signal 102X as a reference to minimize the error between the observed received data (e.g., feedback signal 151 y') and the transmitted data (e.g., input signal 102X). In some examples, DPD adaptation circuit 114 may use iterative techniques to calculate a set of M coefficients, which may be represented by c, that are used by DPD actuator circuit 112 to pre-distort input signal 102 x. For example, DPD adaptation circuit 114 may calculate the current coefficient based on the previously calculated coefficient (in the previous iteration) and the current estimated coefficient. The DPD adaptation circuit 114 may calculate coefficients to minimize an error indicative of the difference between the input signal 102x and the feedback signal 151 y'. The DPD adaptation circuit 114 may update the DPD actuator circuit 112 with the coefficient c, as indicated by the dashed arrow.

In some aspects, DPD actuator circuit 112 in either indirect learning-based DPD180 of fig. 1B or direct learning-based DPD 190 of fig. 1C may use a Volterra series or GMP model (which is a subset of a Volterra series) to implement DPD actuation as follows:

z[n]＝∑ _i，j ∑ _k c _ijk f _k (||x[n-i]||)x[n-j]， (1)

wherein z [ n ]]An nth sample, f, representing the predistortion signal 104z _k (-) represents the kth function of the DPD model (e.g. comprising a set of M basis functions), c _ijk Representing a set of DPD coefficients (e.g. for combining a set of M basis functions), x [ n-i]And x [ n-j ]]Representing samples of the input signal 102 delayed by i and j sample numbers, respectively, and x n-i]I represents the sample x [ n-i ]]Is a constant, or amplitude. The values of the sampling delays i and j may in some cases depend on the nonlinear characteristics of the PA 130 that are of interest to predistortion, and x [ n-i ]]And x [ n-j ]]May be referred to as i, j interleaving memory items. Although equation (1) shows that a GMP model is applied to the envelope or amplitude of the input signal 102x, aspects are not limited in this regard. In general, DPD actuator circuit 112 may apply DPD actuation directly or after preprocessing the input signal 102x according to a preprocessing function represented by P ()The preprocessing function may be an amplitude function, an amplitude square, or any suitable function for the input signal 102X.

In some aspects, DPD actuator circuit 112 may use one or more look-up tables (LUTs) to implement equation (1). For example, term Σ _k c _ijk f _k (||x[n-i]I) may be stored in a LUT, where the LUT for i, j interleaved memory terms may be represented by the following equation:

L _i，j (||x[n-i]||)＝∑ _k c _ijk f _k (||x[n-i]||). (2)

thus, operation of DPD actuator circuit 112 may include selecting a first memory item (e.g., x [ n-i ] from input signal 102x]And x [ n-j ]]) And generates a predistortion signal 104z based on the LUT and the selected first memory term as will be discussed more fully below with reference to fig. 3-5. For DPD adaptation using the direct learning architecture shown in fig. 1C, operation of DPD adaptation circuit 114 may include calculating DPD coefficients (e.g., coefficient C _k A set), and updating one or more LUTs based on the calculated coefficients. For DPD adaptation using the indirect learning architecture shown in FIG. 1B, on the other hand, operation of DPD adaptation circuit 114 may include selecting a second memory term (e.g., and selecting y' n-i from feedback signal 151y]And y' [ n-j ]]) Based on the selected second memory item and the basis function f _k The set calculates DPD coefficients (e.g., coefficient c _k A set), and updating one or more LUTs based on the calculated coefficients. As such, DPD circuit 110 may include various circuits such as memory for storing LUTs for various interleaved memory items, multiplexers for memory item selection, multipliers, adders, and various other digital circuits and/or processors for executing instructions to perform DPD operations (e.g., actuation and adaptation).

In accordance with aspects of the present disclosure, parameterized model training system 172 may train parameterized model 170 to configure at least envelope adjuster circuit 116 to mitigate the effects of drain inductor resonance at PA 130. For example, the RF device 100 may be part of a macro base station and the PA 130 may be a high power PA. In some aspects, parameterized model training system 172 may model the operation of DPD actuator circuit 112 and DPD adaptation circuit 114 as part of training parameterized model 170. The mechanisms by which the parameterized model 170 is trained [ e.g., during offline ] and the DPD circuit 110 is operated [ e.g., during online ] according to the trained parameterized model 170 are discussed more fully below with reference to fig. 2-7. For simplicity, FIGS. 2-7 are discussed using the same signal representations as in FIGS. 1A-1C. For example, symbol x may refer to an input signal of a DPD actuator circuit linearizing the PA, symbol z may refer to an output signal (predistortion signal) provided by the DPD, symbol y may refer to an output of the PA, symbol y' may refer to an observed received signal indicative of the output of the PA, and symbol c may refer to DPD coefficients for combining basis functions associated with characteristics or nonlinearities of the PA. In addition, the input signal 102x and the predistortion signal 104z may be referred to as transmission data (TX), and the feedback signal 151y' may be referred to as observation data (ORx).

PA drain inductance resonance effect example

Fig. 2 illustrates an exemplary PA drain inductor resonance effect, for example, at a PA (e.g., PA 130) having a high output power (e.g., > 40W). Fig. 2 shows transient simulation results for a single transistor PA (PA 300 of fig. 3) with drain-inductor resonance behavior, where graph 210 shows the input signal waveform of the PA (e.g., over a wide instantaneous BW of about 280 MHz), and graph 220 shows the output signal waveform of the PA (e.g., RF signal waveform). As shown in graphs 210 and 220, the envelope of the drain voltage oscillates and distorts the output RF waveform. Depending on the size of the decoupling capacitors, the duration and frequency of such resonance may vary. In some cases, this involves a macro PA, rather than a massive multiple-input multiple-output (MIMO) PA, due to a more complex decoupling capacitor network and higher drain current change rate (e.g., denoted dI/dt).

Fig. 3 provides a schematic diagram illustrating an exemplary high power PA 300 (e.g., PA 130), which may be a macro base station PA that provides an output power of greater than about 40W. The input signal at the gate may be a wide BW signal with a high slew rate (e.g., with transient signal rise and transient signal fall). Due to the large output power, the power supply feeding the drain may start resonating, which in turn may inject a modulated long-term waveform at the output, causing ringing or oscillation effects as shown in graph 220 of fig. 2.

In order to solve the PA drain inductance resonance problem with digital assistance, baseband equivalent analysis shows that when the drain voltage resonates, the baseband complex gain oscillates. This can be seen as a step response with a memory depth over the resonance duration. In one example, for a 40W PA, the memory effect may last about 4-6 hours, which is well beyond the typical range handled by DPD used in 5G transceivers.

Example envelope adjustment, DPD

Fig. 4 provides a block diagram illustrating an exemplary neural network aided physical model 400 for pre-compensating PA gain oscillations, according to an embodiment of the present disclosure.

To mitigate the effects of drain voltage resonance with DPD, the gain oscillation can be modeled first. With the envelope induced gain oscillation model, the waveform can then be predistorted by applying inverse gain using model 420 prior to DPD440 (e.g., DPD actuator circuit 112). DPD440 may be a sample rate DPD operating at the sample rate of input signal x (e.g., input signal x 102).

The challenge is to first model the drain inductance resonance behavior accurately and then model the gain oscillation due to drain inductance resonance. Due to the complexity of PA, it may be difficult to derive a fully compact model based on device physics. According to aspects of the present disclosure, modeling of PA drain-inductor resonant behavior may utilize machine learning capabilities that enable data driven modeling with black box neural networks. In one aspect, the FIR filter 454 may be used to represent the impulse response of the PA drain bias feed; then, since PA baseband gain is a function of drain voltage and waveform envelope (e.g., gain_iq=f (Δv_dd, |x|), where gain_iq represents gain of IQ signal, Δv_dd represents PA drain voltage variation, |x| represents amplitude or envelope of input signal x), a two-output multi-layer perceptron (MLP) (neural network) can be used to numerically approximate the mapping (e.g., as shown in fig. 5). In one example, the MLP model may include 3 hidden layers with (16,32,16) neurons, respectively. In general, the MLP model may include any suitable number of hidden layers, and each hidden layer may include any suitable number of neurons. The two components are combined together and the complete model is shown at 402. Additional downsampling 452 and/or upsampling 456 may be included to adjust the nyquist frequency of the FIR filter 454 based on the resonant frequency. The MLP model may output a two-dimensional (2D) LUT 458 representing (envelope, VDS) to gain mapping. In some cases, the 2d LUT 458 may be referred to as a voltage variation and signal envelope to gain mapping table. In one aspect, since the MLP model has 2 inputs and 2 outputs, the conversion from the neural network to the 2d LUT 458 can be accomplished by running a quantization grid through the neural network and using the outputs as the contents of the LUT 458.

In one aspect, the envelope (or amplitude) of the input signal x (e.g., input signal x 102) may be calculated by block 410, and model 420 may operate on the envelope (shown by 412) of the input signal x to pre-compensate or mitigate PA drain inductor resonance effects. The model 420 may output a gain adjustment or gain inversion signal 422. Multiplier 430 may multiply input signal x with gain-inverted signal 422 to provide gain-precompensated signal 432 and provide gain-precompensated signal 432 to DPD440.

In one aspect, the model 420 may be designed and trained using machine learning tools. For example, model 420 may correspond to parameterized model 170 and may be trained by parameterized model training system 172.

In one aspect, the operations shown at 402 may be implemented by the RF transceiver 100 of fig. 1A. Referring to fig. 1A, the envelope adjuster circuit 116 may implement the operations shown at 402. The envelope adjuster circuit 116 may process the envelope of the input signal 102 (to be transmitted by the PA 130) based on the parameterized model to generate an envelope adjustment signal (e.g., a gain oscillation precompensation signal). The DPD actuator circuit 112 may process the envelope adjustment signal and the input signal based on DPD coefficients associated with the nonlinear characteristics of the nonlinear component. The DPD adaptation circuit 114 may update the DPD coefficients based on a feedback signal indicating the output of the nonlinear component.

In some aspects, the RF transceiver 100 may further include a control block (e.g., a hardware register) to configure a gain adjustment model associated with the drain inductor resonance of the PA 130, and the envelope adjuster circuit 116 may process the envelope of the input signal 102 based on the gain adjustment model. In some aspects, the gain adjustment model may include a drain voltage to gain mapping look-up table (LUT) based on the parameterized model. For example, a drain voltage to gain mapping LUT (e.g., 2d LUT 458) may be generated based on the parameterized model.

In some aspects, the drain bias feed of PA 130 may be modeled by an FIR. Thus, the envelope adjuster circuit 116 may further include a filter (e.g., FIR filter 454) upstream of the gain adjustment model (e.g., drain voltage to gain mapping LUT), the control block may further configure the filter based on the parameterized model, and the envelope adjuster circuit 116 may further process the envelope of the input signal 102 based on the filter. In some aspects, DPD actuator circuit 112 may operate at a sampling rate that samples the input signal 102, while the filter may operate at a lower sampling rate (e.g., at a decimating sampling rate) than the input signal sampling rate. In this regard, the envelope adjuster circuit 116 may further include a downsampler (e.g., downsampler 452) upstream of the filter and an upsampler (e.g., upsampler 456) downstream of the filter arranged in a similar manner as shown in fig. 4, and the control block may further configure the downsampler and upsampler based on the parameterized model.

In some aspects of the RF transceiver 100 of fig. 1A, the envelope adjuster circuit 116 may include a first path (signal path) and a second path (signal path), where the second path may be arranged in parallel with the first path. Each of the first path and the second path may implement the operations shown at 402. In this regard, the first path may include a first downsampler (e.g., downsampler 452) upstream of the first filter (e.g., FIR filter 454), a first upsampler (e.g., upsampler 456) downstream of the first filter, and a first mapping table (e.g., a first voltage variation and signal envelope to gain mapping table similar to the 2d LUT 458) arranged as shown in fig. 4. Similarly, the second path may include a second downsampler (e.g., downsampler 452) upstream of the second filter (e.g., FIR filter 454), a second upsampler (e.g., upsampler 456) downstream of the second upsampler, and a second mapping table (e.g., a second voltage variation and signal envelope to gain mapping table similar to the 2d LUT 458) arranged as shown in fig. 4. In some cases, the first mapping table may be different from the second mapping table. Additionally or alternatively, the first and second downsamplers may be based on different downsampling factors. Additionally or alternatively, the first upsampler and the second upsampler may be based on different upsampling factors. Additionally or alternatively, the first filter and the second filter may be different filters (having different filter coefficients).

In other words, in some aspects, the input signal 102 (to be transmitted by the PA 130) may be processed by two or more separate paths (a first path and a second path) for envelope adjustment as discussed herein, where each path may perform envelope adjustment using different sampling factors, different filters, and/or different mapping tables. More specifically, in the first path, the envelope of the first input signal 102 may be processed by a first downsampling, a first filter, and a first upsampler to provide a first processed signal envelope (e.g., modeling gain variation). Further, the first processed signal envelope and the input signal 102 envelope may be mapped to gain values using a first mapping table. In a similar manner, in the second path, the envelope of the first input signal 102 may be processed by a second downsampling, a second filter, and a second upsampler to provide a second processed signal envelope (e.g., modeling gain variation). The second processed signal envelope and the input signal 102 envelope may furthermore be mapped to gain values using a second mapping table. The envelope adjustment signals from each path may then be combined and processed by DPD actuator circuit 112 for predistortion and/or by DPD adaptation circuit 114 for updating the DPD coefficients, as discussed above with reference to fig. 1A-1C.

Learning model parameters from data

To learn the FIR coefficients and NN-based gain mapping, the model 400 of fig. 4 may be implemented using differentiable operations. By automatic differentiation, a single capture from the PA test bench can be performed using gradient descent and back propagation, with end-to-end optimization of these unknown parameters. For example, a Transmit (TX) signal (e.g., input signal x 102) may be input to the high power PA, and the output of the high power PA may be observed and captured, e.g., as an observation signal (ORx) (e.g., signal y' 151). In one example, training in the inverse mode (i.e., from ORx to TX) may be performed using an Adam optimizer with different learning rates for FIR coefficients and MLP.

Fig. 5 provides a block diagram illustrating an exemplary neural network assisted envelope adjustment DPD model 500 with mid-term memory envelope features according to embodiments of the present disclosure. Model 500 provides a more detailed view of model 400. For simplicity, fig. 5 may use the same reference numbers as in fig. 4 to refer to the same elements in fig. 4.

In one aspect, the downsampler 452 and upsampler 456 may be implemented as a half-band (HB) filter decimator and interpolator, respectively. In one aspect, FIR filter 454 is represented by:

∑ _k b[k]|x _DS [n-k]|， (3)

Wherein b [ k ]]Representing FIR coefficients and x _DS Represents the downsampled input signal (input signal x downsampled by downsampler 452), and |x _DS [n-k]I denotes the envelope of the downsampled output signal. In some aspects, downsamplers 452 and 456 may be configured with any suitable downsampling and upsampling factors, for example, to reduce the size (e.g., number of taps) of FIR filter 454. In one example, the FIR filter 454 may have 64 taps, and the selection of up/down sampling factors may be 1x/2x/4x. DPD440 may operate at the sampling rate of input signal x. For example, model 500 may include a model having the characteristics described aboveFor example, each path includes a block 410, a downsampler 452, a filter 454, an upsampler, and a neural network 510 arranged as shown in fig. 5).

In one aspect, a 2-input (env, VDS), 2-output (gain I/Q) neural network 510 may be used to numerically fit the gain map of the 2d LUT 458. Once b k learns the coefficients of DPD440 (e.g., c ijk), least Squares (LS) adaptation may be performed using the autocorrelation and cross correlation matrices constructed using the envelope features.

In one aspect, a single TX-ORX signal pair (e.g., a test data set) on the widest BW under a full power waveform may be captured from target hardware (e.g., using open loop or closed loop).

In one aspect, an optimization tool of the ML framework may be used to perform automatic differentiation of the back-propagation modeling error (DPD model fitted by LS) to calculate gradients over the learnable parameters (e.g., NN weights and FIR coefficients). The back propagation and corresponding automatic differentiation of each block in fig. 5 is shown by the dashed arrows.

In one aspect, random gradient descent (SGD) based optimization may be used to perform small batch updates to the captured data set.

In one aspect, the 2d LUT 458 may have about 256 entries, and a total of 4 LUTs to achieve interpolation in a single clock cycle.

In some aspects, the block 410 (for signal envelope calculation), the downsampler 452, the filter 454, the upsampler 456, the neural network 510, and the DPD440 in the model 500 may be a differentiable functional block and may have a one-to-one correspondence with operations performed at target hardware (e.g., at least some portions of the DPD circuit 110 in the RF transceiver 100 of fig. 1A). For example, the envelope adjuster circuit 116 of fig. 1A may include a signal envelope calculation block, a downsampler, a filter, an upsampler, and a 2D LUT (e.g., corresponding to the neural network 510) arranged in the same manner as shown in the model 500, and the envelope adjuster circuit 116 may be coupled to the DPD actuator circuit 112 and the DPD adaptation circuit 114 (e.g., the DPD440 may model both the DPD actuator circuit 112 and the DPD-adaptation circuit 114) in the same manner as shown in the model 500. To generate the parameterized model 170 (e.g., offline) for configuring the envelope adjuster circuit 116 (for online operation), the parameterized model 170 may be trained using input signal data (shown by x) and desired signals (shown by y) collected from the target hardware.

As shown in fig. 5, block 410 may calculate a signal envelope (amplitude) of the input signal x, and downsampler 452, filter 454, and upsampler 456 may process the signal envelope, and the processed signal envelope (e.g., representing drain voltage variations) and signal envelope may be processed by neural network 510 to provide an output (gain-inverted signal 422 for envelope adjustment). Multiplier 430 may multiply input signal x with gain inversion signal 422 to provide gain precompensation signal 432 (shown as). The gain pre-compensation signal 432 may be provided to the DPD440 for pre-distortion. The processing of the input signal x by block 410, downsampler 452, filter 454, upsampler 456, neural network 510, multiplier 430, and DPD440 may be referred to as forward propagation.

To train the model 500, a Mean Square Error (MSE) loss function may be calculated (e.g.Wherein the method comprises the steps ofMay represent the predistortion signal output by DPD 440). For direct learning DPD, y may represent the difference between the input signal x and the observed signal (e.g., a feedback signal indicating the output of PA 130). For indirect learning DPD, y may represent a desired signal (e.g., an ideal transmission signal). Back propagation (shown by the dashed arrow) may be performed to adjust parameters of downsampler 452, filter 454, upsampler 456, neural network 510, and/or DPD 440. As further shown in fig. 5, as part of the back propagation, the loss function is relative to the gradient of the gain pre-compensation signal 432 (e.g. +. >) Gradient of the loss function with respect to the weight of the neural network 510 (e.g.)>Wherein w is _i Representing the ith weight) and may calculate the gradient of the loss function with respect to the filter 454 coefficients (e.g. +.>Wherein b [ k ]]Representing the kth coefficient). In some aspects, the forward propagation computation and the backward propagation computation may be repeated until the MSE loss function meets a particular threshold.

In some aspects, a computer-implemented system (e.g., system 172 of fig. 1 or system 2300 of fig. 10) may implement a method for training a parameterized model (e.g., parameterized model 170) to provide envelope adjustment such that PA gain oscillations caused by PA drain-inductor resonance may be mitigated. A computer-implemented system may receive a data set comprising one or more data pairs, each data pair comprising an input signal (e.g., signal 102) and an observation signal (e.g., signal 151) associated with a PA (e.g., a high power PA). For example, the input signal and the observed signal may be collected from the target hardware. The computer-implemented system may further train the parameterized model based on the data set. As part of training the parameterized model, the computer-implemented system may update at least one parameter of the parameterized model associated with configuring a plurality of processing units associated with the envelope adjuster circuit. The method may include outputting one or more configurations for a plurality of processing units associated with the envelope adjuster circuit based on the training.

In some aspects, a computer-implemented system may generate a parameterized model. As part of generating the parameterized model, the computer-implemented system may generate a mapping between each of a plurality of processing units associated with the envelope adjuster circuit and one of a plurality of differentiable functional blocks.

In some aspects, the envelope adjustment of the nonlinear component may comprise a sequence of operations, wherein the computer-implemented system may further calculate a parameter for each operation in the sequence of operations. In some aspects, calculating the parameters for each operation in the sequence of operations is further based on a back propagation process and a loss function, e.g., as discussed above with reference to fig. 5. In some aspects, the sequence of operations for envelope adjustment of the nonlinear component may include at least one of a downsampling operation, a filtering operation, an upsampling operation, or a PA drain voltage to gain mapping operation, e.g., as described above with reference to fig. 4-5.

Learned model parameters

Fig. 6 illustrates a FIR impulse response diagram 600 representing PA drain bias feed in accordance with some aspects of the present disclosure. In fig. 6, the x-axis represents the sample index and the y-axis represents the amplitude of any suitable unit. The FIR impulse response shown in graph 600 may be learned using the mechanism described above with reference to fig. 5. Curve 600 is the baseband equivalent resonant behavior of the drain inductor (e.g., at the PA arrangement shown in fig. 3).

Fig. 7A-7B illustrate an amplitude map 710 and a phase map 720, respectively, of a 2D LUT (e.g., 2D LUT 458) generated based on the neural network 510 of fig. 5, in accordance with some aspects of the present disclosure. The neural network 510 may be learned using the mechanisms described above with reference to fig. 5. Curve 710 shows an example learned gain mapping from drain voltage (filtered envelope) and waveform envelope to complex gain. Curve 720 shows an example learned gain mapping from drain voltage (filtered envelope) and waveform envelope to complex phase. Unlike the mainstream black-box large neural network model, even if learning is performed using a data-driven method, the learning component of the physical-based model becomes meaningful and interpretable. This is possible when the model is well in agreement with the underlying physical, so the learned parameters will be those that are physically significant.

Model-based envelope adjustment method of example parameterization

Fig. 8 provides a flowchart illustrating an exemplary method 800 for performing DPD in conjunction with parameterized model-based envelope adjustment on target hardware according to some embodiments of the present disclosure. In some aspects, method 800 may be implemented by a DPD device (e.g., DPD circuit 110, indirectly learned DPD180, and/or directly learned DPD 190) for which a parameterized model is trained. In some aspects, method 800 may be implemented as part of envelope adjustment and DPD as described above. In FIG. 8, each operation is shown once in a particular order, but the operations may be performed in parallel, reordered, and/or repeated as desired

At 802, a digital input signal may be received.

At 804, an envelope adjustment signal may be generated based on the digital input signal, for example, using the envelope adjuster circuit 116 of fig. 1A. Generating the envelope adjustment signal may include mapping an envelope of the input signal and a gain variation associated with the power amplifier (e.g., PA 130) to one or more gain values based on a parameterized model (e.g., parameterized model 170). In some aspects, mapping the envelope of the input signal and the gain variation associated with the power amplifier to one or more gain values may include filtering the input signal using a filter (e.g., filter 454) to generate a filtered signal, wherein coefficients of the filter may be based on a parameterized model. The mapping may further include determining one or more gain values from a two-dimensional lookup table (e.g., LUT 458 generated from neural network 510) based on an envelope (e.g., instantaneous envelope) of the filtered signal and an envelope (e.g., instantaneous envelope) of the input signal. In some aspects, the response (e.g., impulse response) of the filter may be associated with an envelope of the input signal and a gain variation associated with the power amplifier. In some aspects, mapping the envelope of the input signal and the gain variation associated with the power amplifier to one or more gain values may include downsampling the input signal prior to filtering (e.g., using downsampler 452) and upsampling the filtered signal prior to determining the one or more gain values (e.g., using upsampler 456). In some aspects, generating the envelope adjustment signal may further include multiplying the input signal with one or more gain values (e.g., using multiplier 430).

At 806, digital Predistortion (DPD) may be performed on the envelope adjustment signal to generate a predistortion signal (e.g., using DPD actuator circuit 112).

At 808, the predistortion signal may be output, e.g., transmitted by a nonlinear component (e.g., PA 130).

Fig. 9 provides a flowchart illustrating an exemplary method 900 for training a parameterized model (e.g., parameterized model 170) for envelope adjustment, which may be used in connection with DPD operations, according to some embodiments of the present disclosure. Method 900 may be implemented by a computer-implemented system (e.g., parameterized model training system 172 of fig. 1A and/or data processing system 2300 shown in fig. 10). In some aspects, the method 900 may be implemented as part of the offline training shown in fig. 4 and 5. In fig. 9, each operation is shown once in a particular order, but the operations may be performed in parallel, reordered, and/or repeated as desired.

At 902, a data set including one or more data pairs may be received. Each data pair may include an input signal and an observation signal associated with a nonlinear component (e.g., PA 130).

At 904, a parameterized model (e.g., parameterized model 170) associated with envelope adjustment of the nonlinear component (e.g., operation 402) may be trained based on the data set. Training may include updating at least one parameter of a parameterized model associated with configuring a plurality of processing units associated with an envelope adjuster circuit (e.g., envelope adjuster 116).

At 906, one or more configurations of a plurality of processing units associated with the envelope adjuster circuit may be output based on the training.

In some aspects, the method 900 may further include generating a parameterized model, wherein generating may include generating a mapping between each of a plurality of processing units associated with the envelope adjuster circuit and one of a plurality of differentiable functional blocks.

In some aspects, the envelope adjustment of the nonlinear component may include a sequence of operations, and the method 900 may further include calculating a parameter for each operation in the sequence of operations. In some aspects, calculating parameters for each operation in the sequence of operations may be performed further based on the back propagation process and the loss function. In some aspects, the operational sequence of envelope adjustment of the nonlinear component may include power amplifier voltage variation and input signal envelope to gain mapping operations (e.g., processing by the neural network 510 or mapping by the LUT 458). In some aspects, the operational sequence of envelope adjustment of the nonlinear component may include a filtering operation (e.g., processing of filter 454). In some aspects, the sequence of operations for envelope adjustment of the nonlinear component may include a downsampling operation (e.g., the processing of downsampler 452) and an upsampling operation (e.g., the processing of upsampler 456).

In some aspects, outputting one or more configurations at 906 may include outputting information associated with a two-dimensional look-up table (e.g., LUT 458) that maps voltage gain variations and input signal envelopes associated with nonlinear components to gain values. In some aspects, outputting one or more configurations at 906 may include outputting information associated with a filter (e.g., filter coefficients b [ k ] as described above) that models voltage changes of the nonlinear component based on the input signal envelope.

Data processing System example

Fig. 10 provides a block diagram illustrating an exemplary data processing system 2300 that may be configured to implement or control at least part of a hardware block configuration using a neural network, according to some embodiments of the disclosure. In one example, data processing system 2300 can be configured to train a parameterized model (e.g., parameterized model 170) for configuring target hardware using model architecture search techniques (e.g., DNAS) as discussed herein. In another example, data processing system 2300 may be configured to configure DPD hardware based on a configuration provided by a training parameterized model as discussed herein.

As shown in fig. 10, the data processing system 2300 may include at least one processor 2302, such as a hardware processor 2302, coupled to a memory element 2304 through a system bus 2306. In this manner, the data processing system can store program code within memory element 2304. Further, the processor 2302 may execute program code accessed from the memory elements 2304 via the system bus 2306. In one aspect, the data processing system may be implemented as a computer adapted to store and/or execute program code. However, it should be appreciated that the data processing system 2300 may be implemented in the form of any system including a processor and memory capable of performing the functions described in this disclosure.

In some embodiments, the processor 2302 may execute software or algorithms to perform the activities discussed in this disclosure, particularly activities related to using the neural network-assisted envelope adjustment described herein to perform DPD. The processor 2302 may include any combination of hardware, software, or firmware that provides programmable logic, including a microprocessor, digital Signal Processor (DSP), field Programmable Gate Array (FPGA), programmable Logic Array (PLA), application specific Integrated Circuit (IC) (ASIC), or virtual machine processor, as non-limiting examples. The processor 2302 may be communicatively coupled to the memory element 2304, such as in a Direct Memory Access (DMA) configuration, such that the processor 2302 may read from the memory element 2302 or write to the memory element 2303.

In general, memory element 2304 may include any suitable volatile or non-volatile memory technology including Double Data Rate (DDR) Random Access Memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash memory, read-only memory (ROM), optical media, virtual memory areas, magnetic memory or tape memory, or any other suitable technology. Any memory element discussed herein should be construed as being encompassed within the broad term "memory" unless otherwise specified. Information measured, processed, tracked, or transmitted to or from any component of the data processing system 2300 may be provided in any database, register, control list, cache, or storage structure, all of which may be referenced at any suitable time period. Any such storage option may be included in the broad sense of "memory" as used herein. Similarly, any potential processing elements, modules, and machines described herein should be construed as being encompassed within the broad term "processor". Each of the elements shown in this figure, e.g., any of the elements shown in fig. 1A-1C and 4-5 for performing DPD placement by neural network assisted envelope adjustment, may also include suitable interfaces for receiving, transmitting, and/or otherwise communicating data or information in a network environment so that they may communicate with, e.g., data processing system 2300.

In some example implementations, the mechanisms for performing DPD with neural network assisted envelope adjustment as outlined herein may be implemented by logic encoded in one or more tangible media, which may include a non-transitory medium, e.g., embedded logic provided in an ASIC, DSP instructions, software (possibly including object code and source code) to be executed by a processor or other similar machine, etc. In some of these examples, a memory element, such as memory element 2304 shown in fig. 10, may store data or information for the operations described herein. This includes memory elements capable of storing software, logic, code, or processor instructions that are executed to perform the activities described herein. The processor may execute any type of instructions associated with the data or information to implement the operations detailed herein. In one example, a processor, such as the processor 2302 shown in fig. 10, may transform an element or article (e.g., data) from one state or thing to another state or thing. In another example, the activities outlined herein may be implemented with fixed logic or programmable logic (e.g., software/computer instructions executed by a processor), and the elements identified herein could be some type of programmable processor, programmable digital logic (e.g., an FPGA, a DSP, an Erasable Programmable Read Only Memory (EPROM), an Electrically Erasable Programmable Read Only Memory (EEPROM)) or an ASIC that includes digital logic, software, code, electronic instructions, or any suitable combination thereof.

The memory elements 2304 can include one or more physical memory devices, such as local memory 2308 and one or more mass storage devices 2310. Local memory may refer to RAM or other non-persistent memory device that is typically used during actual execution of program code. The mass storage device may be implemented as a hard disk drive or other persistent data storage device. The processing system 2300 may also include one or more caches (not shown) that provide temporary storage of at least some program code in order to reduce the number of times program code must be retrieved from the mass storage device 2310 during execution.

As shown in fig. 10, memory element 2304 may store application 2318. In various embodiments, the application programs 2318 may be stored in the local memory 2308, in one or more mass storage devices 2310, or separately from the local memory and mass storage. It is to be appreciated that the data processing system 2300 can further execute an operating system (not shown in FIG. 10) that can facilitate execution of the applications 2318. An application 2318 implemented in the form of executable program code may be executed by the data processing system 2300, such as by the processor 2302. In response to executing an application, data processing system 2300 may be configured to perform one or more of the operations or method steps described herein.

Alternatively, input/output (I/O) devices, depicted as input devices 2312 and output devices 2314, may be coupled to the data processing system. Examples of input devices may include, but are not limited to, a keyboard, a pointing device such as a mouse, and the like. Examples of output devices may include, but are not limited to, a monitor or display, speakers, and the like. In some embodiments, the output device 2314 may be any type of screen display, such as a plasma display, a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display, an Electroluminescent (EL) display, or any other indicator, such as a dial, barometer, or LED. In some implementations, the system may include a driver (not shown) for the output device 2314. The input and/or output devices 2312, 2314 may be coupled to the data processing system directly or through intervening I/O controllers.

In one embodiment, the input and output devices may be implemented as combined input/output devices (shown in fig. 10 with dashed lines surrounding input device 2312 and output device 2314). An example of such a combined device is a touch sensitive display, sometimes also referred to as a "touch screen display" or simply "touch screen". In such embodiments, input to the device may be provided by movement of a physical object (e.g., a user's stylus or finger) on or near the touch screen display.

Optionally, a network adapter 2316 may also be coupled to the data processing system to enable it to be coupled to other systems, computer systems, remote network devices, and/or remote storage devices through intervening private or public networks. The network adapter may include a data receiver for receiving data transmitted by the system, device, and/or network to the data processing system 2300, and a data transmitter for transmitting data from the data processing system 2300 to the system and/or network. Modems, cable modems and Ethernet cards are examples of the different types of network adapters that may be used with data processing system 2300.

Example

Example 1 includes an apparatus comprising an envelope adjuster circuit to process an input signal based on a parameterized model to generate an envelope adjustment signal; a Digital Predistortion (DPD) actuator circuit for processing the envelope adjustment signal and the input signal based on DPD coefficients associated with the nonlinear characteristics of the nonlinear component; and a DPD adaptive circuit for updating the DPD coefficients based on a feedback signal indicative of the output of the nonlinear component.

In example 2, the apparatus of example 1 may optionally include wherein the nonlinear component comprises a power amplifier, and wherein the parameterized model is associated with drain inductance resonance of the power amplifier.

In example 3, the apparatus of any of examples 1-2 may optionally include, wherein the envelope adjuster circuit includes a gain adjustment model associated with a voltage variation of the nonlinear component; and the apparatus further comprises a control block for configuring the gain adjustment model based on the parameterized model.

In example 4, the apparatus of any of examples 1-3 may optionally include wherein the gain adjustment model in the envelope adjuster circuit is based on a drain inductor resonance of the nonlinear component.

In example 5, the apparatus of any of examples 1-4 may optionally comprise, wherein the gain adjustment model in the envelope adjuster circuit comprises a look-up table (e.g., a 2D LUT) mapping the voltage variations of the nonlinear component and the envelope (e.g., instantaneous envelope) of the input signal to gain values.

In example 6, the apparatus of any of examples 1-5 may optionally include, wherein the envelope adjuster circuit further includes a filter upstream of the gain adjustment model; and the control block configures the filter further based on the parameterized model.

In example 7, the apparatus of any of examples 1-6 may optionally include wherein the filter models at least one of an input signal envelope or an input voltage variation associated with the nonlinear component.

In example 8, the apparatus of any of examples 1-7 may optionally include, wherein the envelope adjuster circuit further includes a downsampler upstream of the filter; and the control block configures the downsampler further based on the parameterized model.

In example 9, the apparatus of any of examples 1-8 may optionally include, wherein the envelope adjuster circuit further includes an upsampler downstream of the filter; and the control block configures the upsampler further based on the parameterized model.

In example 10, the apparatus of any of examples 1-9 may optionally include, wherein the envelope adjuster circuit includes a first path including a first downsampler, a first filter, a first upsampler, and a first voltage variation and signal envelope to gain map; and a second path in parallel with the first path, the second path including a second downsampler, a second filter, a second upsampler, and a second voltage variation and signal envelope to gain mapping table.

In example 11, the apparatus of any of examples 1-10 may optionally include a case where the first filter is different from the second filter.

In example 12, the apparatus of any of examples 1-11 may optionally include wherein the first voltage variation and signal envelope to gain mapping table filter is different from the second voltage variation and signal envelope to gain mapping table.

In example 13, the apparatus of any of examples 1-12 may optionally include, wherein at least one of the first downsampler and the second downsampler is based on a different downsampling factor; or the first upsampler and the second upsampler are based on different upsampling factors.

In example 14, the apparatus of any of examples 1-13 may optionally include, wherein the control block further configures at least one of a look-up table or a memory item selection of the DPD actuator circuit based on the parameterized model.

In example 15, the apparatus of any one of examples 1-14 may optionally include wherein the DPD adaptation circuit updates the DPD coefficients further based on a parameterized model.

In example 16, the apparatus of any of examples 1-15 may optionally include, wherein the parameterized model is trained based on a mapping between each processing unit of the envelope adjuster circuit, the DPD actuator circuit, and the DPD adaptation circuit and a different one of the plurality of differentiable building blocks; and at least one of an input data set collected on the target hardware, an output data set collected in the target hardware.

In example 17, the apparatus of any of examples 1-16 may optionally include wherein the parameterized model used by the envelope adjuster circuit is trained on a plurality of differentiable building blocks using machine learning.

Example 18 includes a method comprising receiving a digital input signal; generating an envelope adjustment signal based on the digital input signal, wherein the generating comprises mapping an envelope of the input signal and a gain variation associated with a power amplifier to one or more gain values based on a parameterized model; performing Digital Predistortion (DPD) on the envelope adjustment signal to generate a predistortion signal; and outputting the predistorted signal.

In example 19, the method of example 18 may optionally include, wherein mapping the envelope of the input signal and the gain variation associated with the power amplifier to the one or more gain values comprises filtering the input signal using a filter to generate a filtered signal, wherein coefficients of the filter are based on the parameterized model; and determining one or more gain values from a two-dimensional look-up table based on the envelope (e.g., instantaneous envelope) of the filtered signal and the envelope (e.g., instantaneous envelope) of the input signal.

In example 20, the method of any of examples 18-19 may optionally include wherein the response of the filter is associated with an envelope of the input signal and a gain variation associated with the power amplifier.

In example 21, the method of any of examples 18-20 may optionally include, wherein mapping the envelope of the input signal and the gain variation associated with the power amplifier to one or more gain values comprises downsampling the input signal prior to filtering; and upsampling the filtered signal prior to determining the one or more gain values.

In example 22, the method of any of examples 18-21 may optionally include, wherein generating the envelope adjustment signal further includes multiplying the input signal with one or more gain values.

Example 23 includes a method comprising receiving, by a computer-implemented system, a data set comprising one or more data pairs, each data pair comprising an input signal and an observation signal associated with a nonlinear component; training a parameterized model associated with envelope adjustment of the nonlinear component based on the dataset, wherein the training includes updating at least one parameter of the parameterized model associated with configuring a plurality of processing units associated with an envelope adjuster circuit; and based on the training, outputting one or more configurations for the plurality of processing units associated with the envelope adjuster circuit.

In example 24, the method of example 23 may optionally include generating a parameterized model, wherein generating includes generating a mapping between each of the plurality of processing units associated with the envelope adjuster circuit and one of the plurality of differentiable functional blocks.

In example 25, the method of any of examples 23-24 may optionally include, wherein the envelope adjustment of the nonlinear component includes a sequence of operations; and the method further includes calculating a parameter for each operation in the sequence of operations.

In example 26, the method of any of examples 23-25 may optionally include calculating parameters for each operation in the sequence of operations further based on the back propagation process and the loss function.

In example 27, the method of any of examples 23-26 may optionally include wherein the sequence of operations of envelope adjustment of the nonlinear component includes power amplifier voltage variation and input signal envelope to gain mapping operations.

In example 28, the method of any of examples 23-27 may optionally include wherein the sequence of operations of envelope adjustment of the nonlinear component includes a filtering operation.

In example 29, the method of any of examples 23-28 may optionally include wherein the sequence of operations of envelope adjustment of the nonlinear component includes a downsampling operation and an upsampling operation.

In example 30, the method of any of examples 23-29 may optionally include wherein outputting the one or more configurations includes outputting information associated with a two-dimensional lookup table that maps voltage gain variations and input signal envelopes associated with the nonlinear components to gain values.

In example 31, the method of any of examples 23-30 may optionally include, wherein outputting the one or more configurations includes outputting information associated with a filter that models voltage changes of the nonlinear component based on the input signal envelope.

Example 32 includes a computer-implemented system (e.g., parameterized model training system 172 and/or data processing system 2300 of fig. 10) comprising one or more non-transitory computer-readable media storing instructions that, when executed by one or more processing units, cause the one or more processing units to perform the method of any of examples 23-31.

Example 33 includes an apparatus comprising means for performing the method of any of examples 18-22.

Example 33 includes an apparatus comprising means for performing the method of any of examples 23-31.

Variants and implementations

Various embodiments of performing DPD with neural network assisted envelope adjustment are explained herein with reference to "input signal of PA" as a driving signal of PA, i.e. a signal generated based on input signal x described herein, the DPD apparatus applying predistortion to input signal x based on DPD coefficients. However, in other embodiments of DPD with neural network assisted envelope adjustment, the "input signal of the PA" may be a bias signal for biasing the N PAs. Thus, embodiments of the present disclosure also contemplate DPD arrangements with neural network assisted envelope adjustment, which are similar to the arrangements described herein and shown in the drawings, except that without modifying the drive signal of the PA, the DPID arrangements with neural network assisted envelope adjustment may be configured to modify the bias signal of the PA, which may be done based on a control signal generated by a DPD adaptation circuit (e.g., the DPD adaptation circuit described herein), wherein the output of the PA is based on the bias signal used to bias the PA. In other aspects of the disclosure, the drive signal and bias signal of the PA may be adjusted as described herein to implement DPD using a neural network.

Although some description is provided herein with reference to PA, in general, the various embodiments of DPD with neural network assisted envelope adjustment presented herein are applicable to amplifiers other than PA, such as low noise amplifiers, variable gain amplifiers, etc., as well as nonlinear electronic components of RF transceivers other than amplifiers (i.e., components that may exhibit nonlinear behavior). Furthermore, although some description is provided herein with reference to millimeter wave/5G technology, in general, the various embodiments of DPD with neural network assisted envelope adjustment set forth herein may be applied to any technology or standard wireless communication system other than millimeter wave/5G, to any wireless RF system other than wireless communication systems, and/or to RF systems other than radio RF systems.

Although embodiments of the present disclosure are described above with reference to the exemplary embodiments shown in fig. 1A-1C, 2-6, 7A-7B, and 8-10, those skilled in the art will appreciate that the various teachings described above are applicable to a variety of other embodiments.

In some cases, the features discussed herein may be applicable to automotive systems, safety critical industrial applications, medical systems, scientific instrumentation, wireless and wired communications, radio, radar, industrial process control, audio and video equipment, current sensing, instrumentation (which may be high precision), and other digital processing-based systems.

In the discussion of the above embodiments, components of the system, such as multiplexers, multipliers, adders, delay taps, filters, converters, mixers, and/or other components, may be readily replaced, substituted, or otherwise modified to accommodate particular circuit requirements. Furthermore, it should be noted that the use of complementary electronics, hardware, software, etc., provides a equally viable option for implementing the teachings of the present disclosure in connection with model-architecture searching employing hardware configurations in a variety of communication systems.

Portions of the various systems for using model architecture search techniques for hardware configurations presented herein may include electronic circuitry that performs the functions described herein. In some cases, one or more portions of the system may be provided by a processor specifically configured to perform the functions described herein. For example, a processor may include one or more specialized components, or may include programmable logic gates configured to perform the functions described herein. The circuit may operate in the analog domain, digital domain, or mixed signal domain. In some cases, the processor may be configured to perform the functions described herein by executing one or more instructions stored on a non-transitory computer-readable storage medium.

In one example embodiment, any number of circuits of the present diagram may be implemented on a board of an associated electronic device. The board may be a universal circuit board that may house various components of the internal electronic system of the electronic device and further provide connectors for other peripheral devices. More specifically, the board may provide an electrical connection through which other components of the system may communicate electrically. Any suitable processor (including DSP, microprocessor, supporting chipset, etc.), computer-readable non-transitory storage element, etc. may be suitably coupled to the board based on particular configuration requirements, processing requirements, computer design, etc. Other components, such as external memory, additional sensors, audio/video display controllers, and peripheral devices may be connected to the board by cables as plug-in cards, or integrated into the board itself. In various embodiments, the functions described herein may be implemented in emulation form as software or firmware running within one or more configurable (e.g., programmable) elements arranged in a structure supporting these functions. The software or firmware that provides the emulation may be provided on a non-transitory computer readable storage medium including instructions that allow the processor to perform these functions.

In another example embodiment, the circuitry of the present diagram may be implemented as a stand-alone module (e.g., a device having associated components and circuitry configured to perform a particular application or function), or as a plug-in module inserted into the particular application hardware of an electronic device. Note that particular embodiments of the present disclosure may be readily included, in part or in whole, in a system on a chip (SOC) package. SOC refers to ICs that integrate components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed signals, and usual RF functions: all of these functions may be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM) in which multiple individual ICs are located within a single electronic package and configured to interact closely with each other through the electronic package.

It must also be noted that all of the specifications, dimensions and relationships outlined herein (e.g., the number of components of the device and/or RF transceiver shown in fig. 1-5 and 10) are provided for purposes of illustration and teaching only. Such information may vary considerably without departing from the spirit of the present disclosure or the scope of the appended claims. It should be appreciated that the system may be combined in any suitable manner. Any of the circuits, components, modules and elements shown in this figure may be combined in a variety of possible configurations, all of which are clearly within the broad scope of this specification, in accordance with similar design alternatives. In the foregoing description, example embodiments have been described with reference to specific processor and/or component arrangements. Various modifications and changes may be made to such embodiments without departing from the scope of the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Note that in many of the examples provided herein, interactions may be described in terms of two, three, four, or more electrical components. However, this is done for clarity and illustration only. It should be appreciated that the system may be combined in any suitable manner. Any of the components, modules, and elements shown in the figures may be combined into various possible configurations, all of which are clearly within the broad scope of this specification, in accordance with similar design alternatives. In some cases, it may be easier to describe one or more functions of a given set of flows by referring to only a limited number of electrical elements. It should be understood that the figures and the circuits taught therewith are readily scalable and can accommodate a large number of components and more complex/complex arrangements and configurations. Thus, the examples provided should not limit the scope of the circuit or inhibit the broad teachings of the circuit as the circuit may be applied to a myriad of other architectures.

Note that in this specification, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in "one embodiment," "an example embodiment," "an embodiment," and "another embodiment," etc., are intended to mean that any such feature is included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment. Furthermore, as used herein, including in the claims, "or" as used in an item list (e.g., an item list beginning with the phrase "at least one" or "one or more") means an inclusive list, such that, for example, a list of [ A, B or at least one of C ] represents a or B or C or AB or AC or BC or ABC (i.e., A, B and C).

Various aspects of the illustrative embodiments are described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term "connected" refers to a direct electrical connection between things that are connected without any intermediate devices/components, while the term "coupled" refers to a direct electrical connection between things that are connected, or an indirect connection through one or more passive or active intermediate devices/components. In another example, the term "circuit" refers to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. Furthermore, as used herein, the terms "substantially," "approximately," and the like may be used in the context of particular values described herein or known in the art to generally refer to within +/-20% of a target value, such as within +/-10% of the target value.

Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained by those skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, modifications, and modifications as falling within the scope of the examples and the appended claims. Note that all optional features of the apparatus described above may also be implemented with respect to the methods or processes described herein, and that details in the examples may be used anywhere in one or more embodiments.

Claims

1. An apparatus, comprising:

an envelope adjuster circuit for processing the input signal based on the parameterized model to generate an envelope adjustment signal;

a Digital Predistortion (DPD) actuator circuit for processing the envelope adjustment signal and the input signal based on DPD coefficients associated with nonlinear characteristics of the nonlinear component; and

a DPD adaptation circuit for updating the DPD coefficients based on a feedback signal indicating the output of the nonlinear component.

2. The apparatus of claim 1, wherein the nonlinear component comprises a power amplifier, and wherein the parameterized model is associated with drain inductor resonance of the power amplifier.

3. The apparatus of claim 1, wherein:

the envelope adjuster circuit includes a gain adjustment model associated with a voltage variation of the nonlinear component; and

the apparatus further comprises:

a control block for configuring the gain adjustment model based on the parameterized model.

4. The apparatus of claim 3, wherein a gain adjustment model in the envelope adjuster circuit is based on drain inductor resonance of the nonlinear component.

5. The apparatus of claim 3, wherein a gain adjustment model in the envelope adjuster circuit comprises a look-up table that maps voltage variations of the nonlinear component and an envelope of the input signal to gain values.

6. A device according to claim 3, wherein:

the envelope adjuster circuit further comprises a filter upstream of the gain adjustment model; and

the control block further configures the filter based on the parameterized model.

7. The apparatus of claim 6, wherein:

the envelope adjuster circuit further comprises a downsampler upstream of the filter; and

the control block further configures the downsampler based on the parameterized model.

8. The apparatus of claim 6, wherein:

the envelope adjuster circuit further comprises an up-sampler downstream of the filter; and

the control block further configures the upsampler based on the parameterized model.

9. The apparatus of claim 1, wherein the envelope adjuster circuit comprises:

a first path comprising a first downsampler, a first filter, a first upsampler, a first voltage variation and a signal envelope to gain map; and

and a second path connected in parallel with the first path, the second path including a second downsampler, a second filter, a second upsampler, and a second voltage variation and signal envelope to gain mapping table.

10. A method, comprising:

receiving a digital input signal;

generating an envelope adjustment signal based on the digital input signal, wherein the generating comprises mapping an envelope of the digital input signal and a gain variation associated with a power amplifier to one or more gain values based on a parameterized model;

performing Digital Predistortion (DPD) on the envelope adjustment signal to generate a predistortion signal; and

outputting the predistortion signal.

11. The method according to claim 10, wherein:

mapping an envelope of the digital input signal and a gain variation associated with a power amplifier to one or more gain values comprises:

filtering the digital input signal using a filter to produce a filtered signal, wherein coefficients of the filter are based on the parameterized model; and

determining the one or more gain values from a two-dimensional look-up table based on an envelope of the filtered signal and an envelope of the digital input signal; and

the generating the envelope adjustment signal further comprises:

the digital input signal is multiplied with the one or more gain values.

12. The method of claim 11, wherein mapping an envelope of the digital input signal and a gain variation associated with a power amplifier to one or more gain values comprises:

Downsampling the digital input signal prior to filtering; and

the filtered signal is up-sampled prior to determining the one or more gain values.

13. A method, comprising:

a computer-implemented system receives a data set comprising one or more data pairs, each data pair comprising an input signal and an observation signal associated with a nonlinear component;

training a parameterized model associated with envelope adjustment of the nonlinear component based on the dataset, wherein the training includes updating at least one parameter of the parameterized model associated with configuring a plurality of processing units associated with an envelope adjuster circuit; and

based on the training, one or more configurations for the plurality of processing units associated with the envelope adjuster circuit are output.

14. The method of claim 13, further comprising:

generating the parameterized model, wherein the generating includes generating a mapping between each of the plurality of processing units associated with the envelope adjuster circuit and one of a plurality of differentiable functional blocks.

15. The method of claim 13, wherein

Envelope adjustment of the nonlinear component comprises a series of operations; and

the method further comprises the steps of:

parameters are calculated for each operation in the sequence of operations.

16. The method of claim 15, wherein the calculating the parameters for each operation in the sequence of operations is further based on a back propagation process and a loss function.

17. The method of claim 15, wherein the operational sequence of envelope adjustment of the nonlinear component comprises:

power amplifier voltage variation and input signal envelope to gain mapping operations.

18. The method of claim 15, wherein the operational sequence of envelope adjustment of the nonlinear component comprises a filtering operation.

19. The method of claim 15, wherein the operational sequence of envelope adjustment of the nonlinear component comprises a downsampling operation and an upsampling operation.

20. The method of claim 13, wherein outputting the one or more configurations comprises:

outputting information associated with a two-dimensional look-up table mapping voltage gain variations and input signal envelopes associated with non-linear components to gain values; and

information associated with a filter modeling voltage variations of the nonlinear component based on an input signal envelope is output.