CN117056149B

CN117056149B - Memory testing method and device, computing equipment and storage medium

Info

Publication number: CN117056149B
Application number: CN202311288330.0A
Authority: CN
Inventors: 张明; 赵清虎; 张旭
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2023-10-08
Filing date: 2023-10-08
Publication date: 2024-02-02
Anticipated expiration: 2043-10-08
Also published as: CN117056149A

Abstract

The embodiment of the specification provides a memory testing method, a device, a computing device and a storage medium, wherein the memory testing method is used for executing a testing process by a microcontroller in response to an enabling instruction, so that the problem that a processor occupies processor resources for a long time due to the fact that the processor executes the testing process is avoided, the performance of the processor is favorably released, and the processor can execute other tasks when testing a memory, so that the system performance when testing the memory is improved. In addition, the memory controller of the memory test method is connected with a plurality of test units, so that the requirement of simultaneously testing memories of the plurality of test units can be met, and the efficiency of memory test is improved.

Description

Memory testing method and device, computing equipment and storage medium

Technical Field

The present disclosure relates to the field of computer application technologies, and in particular, to a memory testing technology in the field of computer application technologies, and more particularly, to a memory testing method, apparatus, computing device, and storage medium.

Background

Memory is typically used to provide storage space for data, and may provide data reading and storage functions. The memory is an important component of a system on Chip (SoC) and other systems, and in the system on Chip, the memory is a key component for storing instructions and related data, so that it is important to check the memory to ensure that the data stored in the memory is correct.

At present, when the memory is checked, the problem of great limitation on the system performance exists.

Disclosure of Invention

The embodiment of the specification provides a memory testing method, a memory testing device, a computing device and a storage medium, wherein a microcontroller responds to an enabling instruction to execute a testing process, so that the problem that a processor occupies processor resources for a long time due to the fact that the processor executes the testing process is avoided, the performance of the processor is favorably released, and the system performance of the memory during testing is improved.

In order to achieve the technical purpose, the embodiment of the specification provides the following technical scheme:

in a first aspect, an embodiment of the present disclosure provides a memory testing method applied to a microcontroller, where the microcontroller is connected to a memory controller, and the memory controller is connected to a plurality of test units, and the test units include a memory, and the memory testing method includes:

in response to the enabling instruction, performing a test procedure;

the test process comprises the following steps: and sending a verification instruction to the memory controller, wherein the verification instruction is used for instructing the memory controller to initialize a plurality of memories and verifying the initialized memories.

In the test process, the microcontroller sends a check instruction to the memory controller to instruct the memory controller to initialize a plurality of memories so as to realize the initialization process, and a processor does not need to traverse each storage unit of the memories and initialize the storage units, so that the problem that the processor occupies processor resources for a long time due to the execution of the test process by the processor is avoided, the performance of the processor is favorably released, and the processor can execute other tasks when testing the memories, thereby improving the system performance when testing the memories. In addition, the memory controller of the memory test method is connected with a plurality of test units, so that the requirement of simultaneously testing memories of the plurality of test units can be met, and the efficiency of memory test is improved.

In one embodiment, the test unit further comprises: an encoder and a decoder;

the check instruction instructs the memory controller to check a plurality of the memories specifically for:

instructing the memory controller to control each encoder to encode a corresponding memory so as to generate and store a check code; and the memory controller is used for instructing the memory controller to control each decoder to decode the data and the check code in the corresponding memory so as to check the memory.

In this embodiment, by arranging the encoder and the decoder in the test unit, the memory controller may instruct each of the encoders to encode the corresponding memories respectively, or instruct each of the decoders to decode the corresponding memories respectively, so that the encoding and decoding operations may be respectively issued to the test unit, without the memory controller executing the encoding and decoding processes for each of the memories, which is beneficial to reducing the performance requirements of the test process on the memory controller, and also beneficial to expanding the number of test units that the memory controller may simultaneously control, and improving the test efficiency.

In one embodiment, the checking instruction instructs the memory controller to control each of the encoders to encode a respective corresponding memory specifically for:

instructing the memory controller to control each encoder to cut the data block of the corresponding memory so as to obtain a plurality of sub data blocks; the data bit width of the sub data block is smaller than the data bit width of the data block;

and encoding each sub data block to obtain a sub check code corresponding to each sub data block.

Since the encoding and decoding of the data block are performed by using a combination circuit such as the encoding logic and the decoding logic, respectively, all the calculations are performed within one beat (for example, the duration of one period of the clock signal), in some cases, the encoding logic and the decoding logic may be too much, which may occupy more logic resources and affect the timing. In this embodiment, by cutting the data block and generating the corresponding sub-check codes for each sub-data block obtained by cutting, the problems of occupying more logic resources and affecting the time sequence due to excessive coding logic and decoding logic in some cases are avoided. For example, in encoding and decoding a block of 512 bits wide as a whole, it may be necessary to integrate more encoding logic and decoding logic to meet the requirements of performing all encoding or decoding computations in one beat. In this embodiment, a possible process of encoding a data block with a bit width of 512 bits may include: in the cutting process, a 512-bit data block is cut into 4 128-bit sub-data blocks, and each sub-data block is respectively encoded during encoding to obtain 4 sub-check codes corresponding to each sub-data block one by one. By the method, coding logic and decoding logic which are required to be set in the process of coding and decoding each sub data block can be greatly reduced, and therefore the problems of occupying more logic resources and affecting time sequence are solved.

In one embodiment, said encoding each of said sub-data blocks comprises:

determining the data bit width of the sub check code according to the data bit width of the sub data block;

sequentially and alternately arranging check bits in the sub check codes and data bits in the sub data blocks to obtain a data column to be encoded; each position in the data column to be encoded is numbered sequentially, the position with the number of the power of 2 is the check bit, and the rest positions are the data bits;

calculating the exclusive or value of the data bit covered by each check bit, and giving the calculation result to the check bit; the N-th check bit coverage number is 2 ^N-1 The data bit of the position, N is an integer greater than 0;

and combining the data bits in the data column to be encoded to obtain the sub data block, and combining the check bits in the data column to be encoded to obtain the sub check code.

In this embodiment, by the above-described parity bit generation method, the data bits in the data block may be covered by a plurality of parity bits, so as to improve the error correction capability of the parity bits. For example, assume that the 1 st parity bit covers all bits numbered odd, the 2 nd parity bit covers all bits numbered a multiple of 2, the 4 th parity bit covers all bits numbered a multiple of 4, and so on, in such a manner that a parity code is generated. Thus, all bits numbered multiples of 4 will be covered by both the 2 nd and 4 th check bits, which is done in order to increase the error correction capability. If only one check bit covers the data bits, then the check bit cannot find an error when an even number of errors occur in the data bits. However, if two check bits cover the data bits, at least one check bit will find an error when an even number of errors occur in the data bits, thereby improving the error correction capability of the check code.

In one embodiment, the verification instruction instructs the memory controller to control each of the decoders to decode the data and the verification code in the corresponding memory, so as to verify the memory specifically for:

instructing the memory controller to control each decoder to calculate a comprehensive check bit according to the data and the check code in the corresponding memory;

if the comprehensive check bit is a first value, no error data exists in the memory; and if the comprehensive check bit is a second value, error data exist in the memory.

In this embodiment, through the data stored in the memory and the corresponding check code, a comprehensive check bit indicating whether there is error data can be calculated, and the judgment result of whether there is error data can be obtained through the value of the comprehensive check bit.

In one embodiment, the check instruction is further configured to instruct the memory controller to control each decoder to query a preset data table when the comprehensive check bit is the second value, obtain a specific position of the error data in the memory, and correct the error data;

The preset data table is used for storing the corresponding relation between the comprehensive check bit and the position in the memory.

In this embodiment, by querying the preset data table, a specific value of the error data in the memory may be simply and quickly located, and the error data may be corrected.

In one embodiment, the checking instruction is further configured to instruct the memory controller to return a flag bit signal indicating that the checking is completed after the testing unit completes the checking of the memory;

the memory testing method further comprises the following steps:

and ending the test process after receiving the marker bit signals representing the completion of the verification of the plurality of test units.

In this embodiment, after the memory controller completes the verification of the memories in the test units, a flag bit signal indicating that the verification of the memories in the test units is completed is returned to the microcontroller, and when the microcontroller receives the flag bit signal indicating that the verification of the test units is completed, the test process can be ended, so that the microcontroller can learn the verification progress of the memories in the test units through the received flag bit signal, and the method has the characteristics of simplicity and easy implementation.

In one embodiment, the initializing the plurality of memories by the check instruction is specifically configured to:

and the memory controller is instructed to generate a bit width signal and an address signal according to the data bit width of each memory, the bit width signal is used for instructing the data bit width of the memory, and the address signal is used for positioning the storage units in the memory.

In this embodiment, the memory controller is instructed to generate the bit width signal and the address signal according to the data bit width of each memory, so that the memory test method can generate corresponding bit width signals and address signals for memories with different sizes, so as to meet the test requirement, and thereby, the adaptability of the memory test method to memories with different sizes is improved.

In a second aspect, an embodiment of the present disclosure provides a memory testing method applied to a memory controller, where the memory controller is connected to a plurality of test units, the test units include a memory, and the memory testing method includes:

and initializing a plurality of memories in response to the verification instruction, and verifying the initialized memories.

In the test process, the memory controller responds to the verification instruction to initialize a plurality of memories so as to realize the initialization process, and the processor does not need to traverse each storage unit of the memories and initialize the storage units, so that the problem that the processor occupies processor resources for a long time due to the execution of the test process by the processor is avoided, the performance of the processor is favorably released, and the processor can execute other tasks when testing the memories, thereby improving the system performance when testing the memories. In addition, the memory controller of the memory test method is connected with a plurality of test units, so that the requirement of simultaneously testing memories of the plurality of test units can be met, and the efficiency of memory test is improved.

In one embodiment, the test unit further comprises: an encoder and a decoder;

the verifying the plurality of memories includes:

controlling each encoder to encode the corresponding memory to generate and store a check code;

and controlling each decoder to decode the data and the check code in the corresponding memory so as to check the memory.

In one embodiment, the controlling each of the encoders to encode a respective corresponding memory includes:

controlling each encoder to cut the data blocks of the corresponding memories so as to obtain a plurality of sub data blocks; the data bit width of the sub data block is smaller than the data bit width of the data block; and encoding each sub data block to obtain a sub check code corresponding to each sub data block.

In one embodiment, said encoding each of said sub-data blocks comprises:

calculating exclusive OR of data bits covered by each check bitA value and giving the calculation result to the check bit; the N-th check bit coverage number is 2 ^N-1 The data bit of the position, N is an integer greater than 0;

In one embodiment, the controlling each decoder to decode the data and the check code in the corresponding memory to check the memory includes:

controlling each decoder to calculate a comprehensive check bit according to the data and the check code in the corresponding memory;

In one embodiment, the memory test method further includes:

after the test unit finishes checking the memory, a flag bit signal representing the completion of checking is obtained, and the flag bit signal is returned to the microcontroller.

In this embodiment, after the memory controller completes the verification of the memory in the test unit, a flag bit signal indicating that the verification is completed is returned to the microcontroller. After the microcontroller receives the marker bit signals representing the completion of the verification of the plurality of test units, the test process can be ended, so that the microcontroller can learn the verification progress of the memories in the test units through the received marker bit signals, and the method has the characteristics of simplicity and easiness.

In one embodiment, the memory testing method further includes:

when the comprehensive check bit is controlled to be a second value, each decoder is controlled to query a preset data table to obtain a specific position of error data in the memory, and the error data is corrected;

In a third aspect, embodiments of the present disclosure provide a memory test device applied to a microcontroller, where the microcontroller is connected to a memory controller, and the memory controller is connected to a plurality of test units, where the test units include a memory, and the memory test device includes:

the first test module is used for responding to the enabling instruction and executing a test process;

In a fourth aspect, embodiments of the present disclosure provide a memory test device applied to a memory controller, where the memory controller is connected to a plurality of test units, the test units include a memory, and the memory test device includes:

and the second test module is used for responding to the verification instruction, initializing a plurality of memories and verifying the initialized memories.

In a fifth aspect, embodiments of the present specification provide a computing device comprising: a microcontroller, a memory controller, and a plurality of test units; the microcontroller is connected with the memory controller, the memory controller is connected with a plurality of test units, and the test units comprise memories;

the microcontroller is configured to: in response to the enabling instruction, performing a test procedure;

the test process comprises the following steps: sending a checking instruction to the memory controller, wherein the checking instruction is used for instructing the memory controller to initialize a plurality of memories; sending a verification instruction to the memory controller;

the memory controller is configured to: and responding to the verification instruction, verifying a plurality of memories, and verifying the initialized memories.

In one embodiment, the number of the memory controllers is plural, and each memory controller corresponds to plural test units;

the test process comprises the following steps: and sending the check instruction and the check instruction to a plurality of memory controllers.

In one embodiment, the test unit further comprises: an encoder and a decoder;

the memory controller is specifically configured to control each encoder to encode a corresponding memory in response to the check instruction, so as to generate and store a check code; and controlling each decoder to decode the data and the check code in the corresponding memory so as to check the memory.

In a sixth aspect, embodiments of the present disclosure provide a computer readable storage medium having a computer program stored thereon, the computer program implementing a memory testing method as described above when executed by a processor.

In a seventh aspect, the present description embodiments provide a computer program product or a computer program, the computer program product comprising a computer program stored in a computer readable storage medium; the processor of the computer device reads the computer program from the computer readable storage medium, and the processor implements the steps of the memory testing method described above when executing the computer program.

According to the technical scheme, the memory test method provided by the embodiment of the specification can be used for executing the test process by the microcontroller in response to the enabling instruction, so that the problem that the processor occupies the processor resources for a long time due to the fact that the processor executes the test process is avoided, the performance of the processor is favorably released, the processor can execute other tasks when testing the memory, and the system performance when testing the memory is improved. In addition, the memory controller of the memory test method is connected with a plurality of test units, so that the requirement of simultaneously testing memories of the plurality of test units can be met, and the efficiency of memory test is improved.

Drawings

In order to more clearly illustrate the embodiments of the present description or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present description, and that other drawings may be obtained according to the drawings provided without inventive effort to a person skilled in the art.

Fig. 1 is a system architecture diagram of a possible application scenario provided in an embodiment of the present disclosure.

Fig. 2 is a system architecture diagram of another possible application scenario provided in one embodiment of the present disclosure.

Fig. 3 is a flow chart of a memory testing method according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of a system according to an embodiment of the present disclosure.

Fig. 5 is a schematic diagram of a process for generating a check code according to an embodiment of the present disclosure.

Fig. 6 is a schematic diagram of another check code generation process according to an embodiment of the present disclosure.

Fig. 7 is a schematic structural diagram of another system according to an embodiment of the present disclosure.

Fig. 8 is a flowchart of another memory testing method according to an embodiment of the present disclosure.

Fig. 9 is a schematic structural diagram of a testing device according to an embodiment of the present disclosure.

Fig. 10 is a schematic structural diagram of another test device according to an embodiment of the present disclosure.

Fig. 11 is a schematic structural diagram of a computing device according to an embodiment of the present disclosure.

Detailed Description

Unless defined otherwise, technical or scientific terms used in the embodiments of the present specification should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present specification belongs. The terms "first," "second," and the like, as used in the embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to avoid intermixing of the components.

Throughout the specification, unless the context requires otherwise, the word "plurality" means "at least two", and the word "comprising" is to be construed as open, inclusive meaning, i.e. as "comprising, but not limited to. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "examples," "particular examples," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present specification. The schematic representations of the above terms do not necessarily refer to the same embodiment or example.

The technical solutions of the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is apparent that the described embodiments are only some embodiments of the present specification, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are intended to be within the scope of the present disclosure.

SUMMARY

Memory is an important component of a system on Chip (SoC) or the like, in which memory is a critical component that stores instructions and related data. Ensuring the normal data storage in the memory has important significance for the normal operation of the system.

In some cases, some large scale integrated circuits may be rendered inoperable by being disturbed. For example, a memory such as RAM (Random Access Memory ) that uses bistable states for storage may suffer from single event upsets, i.e., bit upsets within the memory cell due to the energy of natural particles (e.g., free particles or electromagnetic radiation). This bit flip may cause a data error in the memory, for example, it may cause an originally stored "0" to change to "1", or "1" to change to "0", which may cause some serious consequences: such as causing some control programs to run away (i.e., the control program loses normal control flow and begins executing unexpected instructions or entering an erroneous state), stored critical data errors, etc. Now, as the chip integration increases, the probability of errors increases. In some specific application scenarios, this has become a non-negligible problem. For example, in the field of space electronic application, the probability of single event upset occurrence is greatly increased because the use environment may be a high radiation environment.

Taking SRAM (Static Random-Access Memory) as an example, SRAM is a common Memory, and has advantages of high speed, low power consumption, easy integration, and the like. However, SRAM also has drawbacks such as susceptibility to disturbance and susceptibility to Soft Error. Soft errors refer to non-permanent errors that result from external factors (e.g., radiation, electromagnetic interference, etc.) causing data in a memory cell to be flipped. To improve the reliability of SRAM and like types of memories, soft errors can be detected and corrected by an EDAC (Error Detection And Correction ) mechanism, thereby avoiding data loss or errors. EDAC technology is a technology that utilizes redundant information to enable error detection and correction. Specifically, when writing data, the EDAC technology generates a corresponding check code according to the data, and stores the check code and the data together in the SRAM; when the data is read out, the check code is regenerated according to the data and compared with the check code stored in the SRAM, so that whether an error occurs or not is judged, and corresponding correction is carried out.

It has been found through research that when EDAC technology is used on a memory, an initialization operation may be required on the memory. That is, when the system is powered on or reset, the data and the check code in the storage unit in the memory need to be cleared or set to a preset value, so as to avoid false alarm or error correction caused by the random number. The current method for initializing the memory is software initialization, that is, the memory is initialized by a software program. Specifically, after the system is powered up or reset, a specific initialization software program is executed by the processor, and the program will traverse all the memory cells of the memory and zero out or set the content of the memory to a preset value. However, the inventors have found that the following problems exist by studying the current software initialization method:

1) The software initialization needs to occupy processor resources and time, and during the execution of the software program, the processor cannot execute other tasks;

2) The initialization of the software can be influenced by external factors (such as power supply fluctuation, temperature change and the like) to cause abnormal conditions;

3) Software initialization may be tampered with or corrupted by a malicious attacker resulting in failure.

In order to avoid the above problems, the inventors have further studied and found that a hardware initialization solution can be designed. I.e. the memory is initialized by hardware logic. Specifically, after the system is powered on or reset, a specially designed hardware logic controller performs an operation of resetting or setting the memory to a preset value. The method can avoid the problems of long-term occupation of processor resources, abnormal conditions caused by the influence of external factors, tampered or destroyed software and the like, which are possibly caused by the initialization of the software. Specifically, the hardware initialization scheme may include: executing, by the microcontroller, a test procedure in response to the enable instruction, the test procedure may include: and sending a verification instruction to the memory controller, wherein the verification instruction is used for instructing the memory controller to initialize a plurality of memories and verifying the initialized memories. Therefore, the problem that the processor occupies processor resources for a long time due to the fact that the processor executes the test process is avoided, the performance of the processor is released, other tasks can be executed by the processor when the memory is tested, and therefore the system performance when the memory is tested is improved. In addition, the memory controller of the memory test method is connected with a plurality of test units, so that the requirement of simultaneously testing memories of the plurality of test units can be met, and the efficiency of memory test is improved.

Based on the above conception, the present embodiment provides a memory testing method, and the memory testing method will be described in an exemplary manner with reference to the accompanying drawings.

Example scenario

Referring to fig. 1, fig. 1 illustrates a possible application scenario of the memory testing method provided in the embodiment of the present disclosure, specifically may be a usage scenario of a computing device 100, and in a usage process of the computing device 100, a user may trigger a power-on or reset operation of the computing device 100 by using a key 30. That is, after the user triggers the button 30, the test program 20 is triggered to execute, and the test program 20 enables the system 10 to execute the memory test operation. The key 30 may be an on-off key or a reset key. The system 10 may be a system with memory, such as a system on a chip.

Referring specifically to fig. 2, a system 10 may include a microcontroller 11, a memory controller 12, and a test unit 13, where the microcontroller 11 may include a hardware debug module, and the microcontroller 11 establishes a communication connection with the memory controller 12; the memory controller 12 establishes communication connections with a plurality of test units 13. The test unit 13 may comprise a memory 131. The test program 20 may cause the microcontroller 11 to perform a test procedure by sending an enabling instruction to the microcontroller 11. In some embodiments, the test program 20 may be triggered by other manners, for example, the user may call and execute the test program 20 by means of communication between software during the use of the computing device 100, and the test program 20 does not need to be triggered by the key 30, which is not limited in this specification, as the case may be.

It should be noted that fig. 1 and fig. 2 only show possible application scenarios and system architectures, and in a practical application process, more or fewer structures may be included in the computing device 100, and the system architectures that may perform the memory testing method provided in the embodiments of the present disclosure are not exhaustive, and are specific to the practical situation.

Exemplary method

Taking the application to the microcontroller 11 shown in fig. 2 as an example, an embodiment of the present disclosure provides a memory testing method, where the microcontroller 11 is connected to the memory controller 12, the memory controller 12 is connected to a plurality of test units 13, and the test units 13 include a memory 131, as shown in fig. 3, and the memory testing method includes:

s301: in response to the enabling instruction, performing a test procedure;

In some embodiments, the enabling instructions may be sent to the microcontroller 11 by the external controller 20 in fig. 2, which may enable a debug mode of the microcontroller 11, such that the microcontroller 11 performs a test procedure in the debug mode. In the test process, the microcontroller sends a check instruction to the memory controller to instruct the memory controller to initialize a plurality of memories so as to realize the initialization process, and a processor does not need to traverse each storage unit of the memories and initialize the storage units, so that the problem that the processor occupies processor resources for a long time due to the execution of the test process by the processor is avoided, the performance of the processor is favorably released, and the processor can execute other tasks when testing the memories, thereby improving the system performance when testing the memories. In addition, the memory controller of the memory test method is connected with a plurality of test units, so that the requirement of simultaneously testing memories of the plurality of test units can be met, and the efficiency of memory test is improved.

As described above, the initializing of the plurality of memories by the memory controller may refer to resetting or setting the content stored in each storage unit of the plurality of memories to a preset value (the preset value may be "0" or "1", for example).

In order to reduce the performance requirements of the memory controller 12, in one embodiment of the present disclosure, referring to fig. 4, the test unit 13 further includes: an encoder 132 and a decoder 133;

the check instruction instructs the memory controller 12 to check the plurality of the memories 131 specifically for:

instruct the memory controller 12 to control each of the encoders 132 to encode the respective corresponding memories 131 to generate and store a check code; and for instructing the memory controller 12 to control each decoder 133 to decode the data and the check code in the corresponding memory 131 so as to check the memory 131.

In this embodiment, by providing the encoder 132 and the decoder 133 in the test unit 13, the memory controller 12 may instruct each encoder 132 to encode the corresponding memory 131, or instruct each decoder to decode the corresponding memory 131, so that the encoding and decoding operations may be respectively issued to the test unit 13, without the memory controller 12 executing the encoding and decoding process on each memory 131, which is beneficial to reducing the performance requirement of the test process on the memory controller 12, and also beneficial to expanding the number of test units 13 that the memory controller 12 may simultaneously control, and improving the test efficiency.

In order to avoid the problems of occupying more logic resources and affecting the timing caused by excessive encoding logic and decoding logic, in one embodiment of the present disclosure, the verification instruction instructs the memory controller to control each of the encoders to encode the corresponding memory specifically for:

Referring to fig. 5, fig. 5 shows a possible process of encoding a data block with a bit width of 512 bits in the present embodiment, in the process of cutting, the data block with 512 bits is cut into 4 sub data blocks with 128 bits, and each sub data block is encoded during encoding, so as to obtain 4 sub check codes corresponding to each sub data block one by one. In this way, the problems of occupying more logic resources and affecting the time sequence caused by excessive coding logic and decoding logic can be solved. Specifically, in the process of encoding and decoding the data block, it is necessary to use a combination circuit such as an encoding logic and a decoding logic, and the encoding logic and the decoding logic need to complete all the computations in one beat (for example, the duration of one period of the clock signal), which may cause that in some cases, the encoding logic and the decoding logic may be too much, which may occupy more logic resources and affect the timing. In this embodiment, by cutting the data block and generating the corresponding sub-check codes for each sub-data block obtained by cutting, the problems of occupying more logic resources and affecting the time sequence due to excessive coding logic and decoding logic in some cases are avoided. For example, in encoding and decoding a block of 512 bits wide as a whole, it may be necessary to integrate more encoding logic and decoding logic to meet the requirements of performing all encoding or decoding computations in one beat. In this embodiment, a possible process of encoding a data block with a bit width of 512 bits may include: in the cutting process, a 512-bit data block is cut into 4 128-bit sub-data blocks, and each sub-data block is respectively encoded during encoding to obtain 4 sub-check codes (for example, 8-bit check codes) corresponding to each sub-data block one by one. By the method, the coding logic and decoding logic which are required to be integrated when each sub data block is coded and decoded can be greatly reduced, and therefore the problems of occupying more logic resources and affecting time sequence are solved.

The number of check code bits described above is for illustrative purposes only, and in general, the number and distribution of check codes depends on the ECC (Error Checking and Correcting, error checking and correction) algorithm used, which may include Hamming codes, cyclic redundancy check codes, and BCH codes, among others.

In order to improve the error correction capability of the check bit, in one embodiment of the present specification, the encoding each of the sub data blocks includes:

To simplify the verification process, in one embodiment of the present disclosure, the verification instruction instructs the memory controller to control each decoder to decode the data and the verification code in the corresponding memory, so as to verify the memory specifically for:

Alternatively, the first value and the second value of the comprehensive check bit may be "1" and "0", respectively. In this embodiment, through the data stored in the memory and the corresponding check code, a comprehensive check bit indicating whether there is error data can be calculated, and the judgment result of whether there is error data can be obtained through the value of the comprehensive check bit.

Referring to fig. 6, still taking a possible process of encoding a data block with a bit width of 512 bits as an example, cutting the 512-bit data block may obtain 4 128-bit sub-data blocks, where the 4 sub-data blocks may be sub-data block 1, sub-data block 2, sub-data block 3, and sub-data block 4 respectively; during encoding, the sub-check codes 1, 2, 3 and 4 corresponding to the 4 sub-data blocks are respectively obtained, and the size of the 4 sub-data blocks may be 8 bits, for example. After generating 4 sub-check codes, the sub-check codes and the sub-data blocks can be spliced and stored, so that the sub-check codes and the sub-data blocks are correspondingly stored, and check codes corresponding to data bits in the data blocks can be conveniently found in the subsequent decoding process. For example, in fig. 6, the sub data block 1 corresponds to the sub check code 1, and the check code corresponding to the data bit in the sub data block 1 may be found from the sub check code 1.

In order to implement positioning and correcting of the error data, in an embodiment of the present disclosure, the verification instruction is further configured to instruct the memory controller to control each decoder to query a preset data table when the comprehensive verification bit is a second value, obtain a specific position of the error data in the memory, and correct the error data;

In one embodiment, the process of correcting the error data may be, for example: when the value of the error data is 0, the error data can be corrected to be 1; when the error data has a value of "1", the error data may be corrected to "0".

In one embodiment, referring to fig. 7, the verification instruction is further configured to instruct the memory controller to return a flag bit signal indicating that the verification is completed after the test unit completes the verification of the memory;

The memory testing method further comprises the following steps:

In this embodiment, after the verification of the memory 131 in the test unit 13 is completed, the memory controller 12 returns a flag bit signal indicating that the verification of the memory 131 in the test unit 13 is completed to the microcontroller 11, and when the microcontroller 11 receives the flag bit signals indicating that the verification of the test units 13 is completed, the test process can be ended, so that the microcontroller 11 can learn the verification progress of the memory in each test unit 13 through the received flag bit signals, and the method has the characteristics of simplicity and easy implementation.

In order to improve the adaptability of the test method to memories with different sizes, in one embodiment of the present specification, the initializing the plurality of memories by the verification instruction is specifically used for:

Taking the memory controller 12 shown in fig. 2 as an example, an embodiment of the present disclosure further provides a memory testing method applied to a memory controller, where the memory controller is connected to a plurality of test units, and the test units include a memory, as shown in fig. 8, and the memory testing method includes:

s801: and initializing a plurality of memories in response to the verification instruction, and verifying the initialized memories.

Optionally, the test unit further comprises: an encoder and a decoder;

the verifying the plurality of memories includes:

Optionally, the controlling each encoder to encode a respective corresponding memory includes:

controlling each encoder to cut the data blocks of the corresponding memories so as to obtain a plurality of sub data blocks; the data bit width of the sub data block is smaller than the data bit width of the data block;

Optionally, the encoding each of the sub-data blocks includes:

Optionally, the controlling each decoder to decode the data and the check code in the corresponding memory to check the memory includes:

Optionally, the memory testing method further includes:

Optionally, in one embodiment, the memory testing method further includes:

For the process of initializing a plurality of memories and verifying a plurality of initialized memories by the memory controller in response to the verification instruction, reference may be made to the related description above, which is not repeated herein.

Exemplary apparatus

In an exemplary embodiment of the present disclosure, there is also provided a memory test apparatus, as shown in fig. 9, applied to a microcontroller, the microcontroller being connected to a memory controller, the memory controller being connected to a plurality of test units, the test units including a memory, the memory test apparatus including:

a first test module 901, configured to perform a test procedure in response to an enable instruction;

In another exemplary embodiment of the present disclosure, there is also provided a memory test apparatus, as shown in fig. 10, applied to a memory controller, the memory controller being connected to a plurality of test units, the test units including a memory, the memory test apparatus including:

and the second test module 1001 is configured to initialize a plurality of the memories in response to a verification instruction, and verify the initialized memories.

For specific limitations of the memory test apparatus, reference may be made to the above limitations regarding the memory test method, and detailed descriptions thereof are omitted herein. The modules in the memory test device may be implemented in whole or in part by software, hardware, or a combination thereof. The above modules may be embedded in hardware or independent of the computer device, or may be stored in software in the computer device, so that the processor or the controller may call and execute operations corresponding to the above modules.

Exemplary computing device

Another embodiment of the present application further provides a computing device, referring to fig. 11, and an exemplary embodiment of the present specification further provides a computing device 100, including: a microcontroller 11, a memory controller 12 and a plurality of test units 13; wherein the microcontroller 11 is connected with the memory controller 12, the memory controller 12 is connected with a plurality of the test units 13, and the test units 13 comprise a memory 131;

the microcontroller 11 is configured to: in response to the enabling instruction, performing a test procedure;

the test process comprises the following steps: sending a check instruction to the memory controller 12, where the check instruction is used to instruct the memory controller 12 to initialize a plurality of the memories 131; sending a check instruction to the memory controller 12;

The memory controller 12 is configured to: and responding to the verification instruction, verifying the memories 131, and verifying the initialized memories 131.

In some embodiments, the number of the memory controllers 12 is plural, and each memory controller 12 corresponds to a plurality of the test units 13;

the test process comprises the following steps: the check instruction and the check instruction are sent to a plurality of the memory controllers 12.

In some embodiments, the test unit 13 further comprises: an encoder and a decoder;

the memory controller 12 is specifically configured to, in response to the check instruction, control each of the encoders to encode the corresponding memory 131, so as to generate and store a check code; and controlling each decoder to decode the data and the check code in the corresponding memory 131 so as to check the memory 131.

The system 10 shown in fig. 11 may be a system with storage capability, such as a system on a chip.

For specific possible execution and beneficial effects of the test procedure performed by the microcontroller 11, reference is made to the above description of the memory test method, and the description is omitted here.

Those skilled in the art will appreciate that the architecture shown in fig. 11 is merely a block diagram of some of the architecture associated with the present description and is not limiting of the computing devices to which the present description may be applied, and that a particular computing device may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.

Exemplary computer program product and storage Medium

In addition to the methods and apparatus described above, the memory testing methods provided by the embodiments of the present specification may also be a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform the steps in the memory testing methods according to the various embodiments of the present specification described in the "exemplary methods" section of the present specification.

The computer program product may write program code for performing the operations of embodiments of the present description in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.

Furthermore, the embodiments of the present specification also provide a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor to perform the steps of the memory testing method according to the various embodiments of the present specification described in the "exemplary method" section of the present specification.

Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few implementations of the present description, which are described in more detail and are not to be construed as limiting the scope of the solutions provided by the examples of the present description. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the present description, which is within the scope of the present description. Accordingly, the protection scope of the patent should be determined by the appended claims.

Claims

1. A memory testing method, characterized in that it is applied to a microcontroller, the microcontroller being provided independently of a processor, the microcontroller being connected to a memory controller, the memory controller being connected to a plurality of test units, the test units including a memory, the memory testing method comprising:

in response to the enabling instruction, performing a test procedure in a debug mode; the enabling instruction is used for enabling a debug mode of the microcontroller;

The test process comprises the following steps: sending a verification instruction to the memory controller, wherein the verification instruction is used for instructing the memory controller to initialize a plurality of memories and verifying the initialized memories;

the checking instruction is specifically configured to initialize a plurality of memories:

2. The method of claim 1, wherein the test unit further comprises: an encoder and a decoder;

3. The method of claim 2, wherein the checking instructions instruct the memory controller to control each of the encoders to encode a respective corresponding memory is specifically configured to:

4. The method of claim 3, wherein said encoding each of said sub-data blocks comprises:

5. The method of claim 2, wherein the check instruction instructs the memory controller to control each of the decoders to decode data and check codes in a respective corresponding memory to check the memory, and wherein the checking of the memory is specifically performed by:

6. The method of claim 5 wherein the check instruction is further configured to instruct the memory controller to control each of the decoders to query a preset data table when the comprehensive check bit is a second value, obtain a specific location of the error data in the memory, and correct the error data;

7. The method of claim 1, wherein the check instruction is further configured to instruct the memory controller to return a flag signal indicating that a check is complete after the test unit completes checking the memory;

the memory testing method further comprises the following steps:

8. A memory testing method, applied to a memory controller, the memory controller being connected to a microcontroller, and the memory controller being connected to a plurality of test units, the test units including a memory, the microcontroller being provided independently of a processor, the memory testing method comprising:

responding to a verification instruction, initializing a plurality of memories, and verifying the initialized memories; the verification instruction is an instruction sent to the memory controller by the microcontroller in a debugging mode in response to an enabling instruction;

the initializing of the plurality of memories is specifically used for:

Generating a bit width signal and an address signal according to the data bit width of each memory, and sending the bit width signal and the address signal to the test unit for initialization, wherein the bit width signal is used for indicating the data bit width of the memory, and the address signal is used for positioning a storage unit in the memory.

9. A memory test device for use with a microcontroller, the microcontroller being configured independent of a processor, the microcontroller being coupled to a memory controller, the memory controller being coupled to a plurality of test units, the test units including a memory, the memory test device comprising:

the first test module is used for responding to the enabling instruction and executing a test process in a debugging mode; the enabling instruction is used for enabling a debug mode of the microcontroller;

10. A memory test device for use with a memory controller, the memory controller coupled to a microcontroller and the memory controller coupled to a plurality of test units, the test units including a memory, the microcontroller being configured independent of a processor, the memory test device comprising:

the second test module is used for responding to the verification instruction, initializing a plurality of memories and verifying the initialized memories; the verification instruction is an instruction sent to the memory controller by the microcontroller in a debugging mode in response to an enabling instruction;

the initializing of the plurality of memories is specifically used for:

11. A computing device, comprising: a microcontroller, a memory controller, and a plurality of test units; the microcontroller is connected with the memory controller, the microcontroller is arranged independently of the processor, the memory controller is connected with a plurality of test units, and the test units comprise memories;

the microcontroller is configured to: in response to the enabling instruction, performing a test procedure in a debug mode; the enabling instruction is used for enabling a debug mode of the microcontroller;

the memory controller is configured to: responding to the verification instruction, verifying a plurality of memories, and verifying the initialized memories;

12. The computing device of claim 11, wherein the number of memory controllers is a plurality, each memory controller corresponding to a plurality of the test units;

13. The computing device of claim 11, wherein the test unit further comprises: an encoder and a decoder;

14. A computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and when the computer program is executed by a processor, the memory testing method according to any one of claims 1 to 8 is implemented.