CN117054700A - Integrated circuit testing method and testing system - Google Patents

Integrated circuit testing method and testing system Download PDF

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Publication number
CN117054700A
CN117054700A CN202310880926.3A CN202310880926A CN117054700A CN 117054700 A CN117054700 A CN 117054700A CN 202310880926 A CN202310880926 A CN 202310880926A CN 117054700 A CN117054700 A CN 117054700A
Authority
CN
China
Prior art keywords
integrated circuit
signal input
input part
probe
detection signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310880926.3A
Other languages
Chinese (zh)
Inventor
李友刚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Hua Microelectronics Technology Co ltd
Original Assignee
Chengdu Hua Microelectronics Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu Hua Microelectronics Technology Co ltd filed Critical Chengdu Hua Microelectronics Technology Co ltd
Priority to CN202310880926.3A priority Critical patent/CN117054700A/en
Publication of CN117054700A publication Critical patent/CN117054700A/en
Pending legal-status Critical Current

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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/06Measuring leads; Measuring probes
    • G01R1/067Measuring probes
    • G01R1/06705Apparatus for holding or moving single probes
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals
    • G01R1/0408Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/06Measuring leads; Measuring probes
    • G01R1/067Measuring probes
    • G01R1/073Multiple probes
    • G01R1/07392Multiple probes manipulating each probe element or tip individually
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834Automated test systems [ATE]; using microprocessors or computers
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2886Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G01R31/2887Features relating to contacting the IC under test, e.g. probe heads; chucks involving moving the probe head or the IC under test; docking stations
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2886Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G01R31/2889Interfaces, e.g. between probe and tester
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2893Handling, conveying or loading, e.g. belts, boats, vacuum fingers

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The invention relates to an integrated circuit testing method and an integrated circuit testing system, and relates to an integrated circuit technology, wherein the testing method comprises the following steps: (1) selecting parameters to be tested; (2) Video acquisition is carried out on a test board card carrying a chip to be tested, the positions of expansion contacts of the test board card corresponding to parameters to be tested are identified, the test board card is provided with a preset number of expansion contacts, and the expansion contacts are correspondingly connected with the external connecting ends of the chip to be tested; (3) The mechanical arm moves the detection signal input part corresponding to the parameter to be detected to enable the detection signal input part to be contacted with the identified and determined expansion contact corresponding to the parameter to be detected, so as to establish a test connection relation between the detection signal input part and the chip to be detected; (4) The tester to which the detection signal input part belongs outputs a test signal. By adopting the technology of the invention, the tester can be flexibly replaced without any change on the structure of the tester, and the invention has the characteristics of low cost and high reliability.

Description

Integrated circuit testing method and testing system
Technical Field
The present invention relates to integrated circuit technology, and more particularly to integrated circuit testing technology.
Background
Automated Test Equipment (ATE) is a necessary device for testing integrated circuits to perform IC testing. Typically including computer and software systems, system bus control systems, graphics memory, graphics controllers, timing generators, precision Measurement Units (PMUs), programmable power supplies and test stands, ATE test stands, and the like.
In the prior art, the repeated workload of the design and test of the ATE equipment is large, the ATE test platform is occupied to be longer, the test work is not facilitated, and the ATE equipment is inconvenient to move; if a plurality of ATE are purchased, the purchasing cost is very high, and the conventional company cannot bear a plurality of purchasing costs, and the maintenance and use costs are high.
Disclosure of Invention
The invention aims to solve the technical problem of providing an integrated circuit testing method and an integrated circuit testing system which are applicable to various testers and can be switched quickly.
The technical scheme adopted by the invention for solving the technical problems is that the integrated circuit testing method is characterized by comprising the following steps:
(1) Selecting parameters to be measured;
(2) Video acquisition is carried out on a test board card carrying a chip to be tested, the positions of expansion contacts of the test board card corresponding to parameters to be tested are identified, the test board card is provided with a preset number of expansion contacts, and the expansion contacts are correspondingly connected with the external connecting ends of the chip to be tested;
(3) The mechanical arm moves the detection signal input part corresponding to the parameter to be detected to enable the detection signal input part to be contacted with the identified and determined expansion contact corresponding to the parameter to be detected, so as to establish a test connection relation between the detection signal input part and the chip to be detected;
(4) The tester to which the detection signal input part belongs outputs a test signal.
In the step (3), the mechanical arm determines the Z-direction moving distance through a force feedback algorithm, wherein the Z-direction is a direction perpendicular to the plane where the contact is located (i.e. the surface of the test board where the contact is located).
In the step (3), the spatial position of the feature point is determined by performing video acquisition on the feature point of the detection signal input part.
The detection signal input component is a probe, the characteristic point is a contact end of the probe, in the step (3), the actual position of the contact end of the probe is determined through an edge recognition algorithm, the X direction and the Y direction of the contact end of the probe are adjusted to be coincident with the X direction and the Y direction of the corresponding expansion contact, and then Z direction movement is carried out to enable the Z direction position of the contact end of the probe to be coincident with the Z direction position of the corresponding expansion contact.
The invention also provides an integrated circuit testing system, which comprises an image acquisition unit and a rack, wherein the rack is provided with a testing board fixing structure, at least one tester fixing structure and at least one mechanical arm, and the mechanical arm comprises a space position adjusting unit and a clamping structure; the image acquisition unit comprises a data output interface.
Further, the system also comprises a communication relay module, wherein the communication relay module is provided with an external communication interface and at least one internal communication interface, the internal communication interface is used for connecting each tester, and the external communication interface is used for communicating with an external computer.
Further, a sealing structure is arranged on the frame, and the mechanical arm and the test board fixing structure are arranged in a sealing cavity of the sealing structure.
By adopting the technology of the invention, the tester can be flexibly replaced without any change on the structure of the tester, and the invention has the characteristics of low cost and high reliability.
Drawings
Fig. 1 is a schematic view of the overall structure of the present invention.
Fig. 2 is a schematic structural view of the test plate.
Fig. 3 is a schematic diagram of the positional relationship of the mechanical arm, the probe, and the test board of the embodiment.
Detailed Description
Marking:
101. probe with a probe tip
102. Mechanical arm
103. Clamping structure
104. Test board
105. Sliding rail
106. Camera head
202. Expansion contact
203. Chip to be tested
204. Chip communication interface
Referring to fig. 1 to 3, the invention provides an integrated circuit testing system, which comprises a camera 106 serving as an image acquisition unit and a rack, wherein a testing board fixing structure, at least one tester fixing structure and at least one mechanical arm are arranged on the rack, the testing board fixing structure and the tester fixing structure are both slot structures, the mechanical arm comprises a space position adjusting unit and a clamping structure, the space position adjusting unit can be a sliding rail and a matched part, and a driving module of the mechanical arm is connected to an external computer through a communication interface; the image acquisition unit comprises a data output interface.
Further, the system also comprises a communication relay module, wherein the communication relay module is provided with an external communication interface and at least one internal communication interface, the internal communication interface is used for connecting each tester, and the external communication interface is used for communicating with an external computer.
Further, a sealing structure is arranged on the frame, so that the frame forms a 4U test cabinet, and the mechanical arm and the test board fixing structure are arranged in a sealing cavity of the sealing structure.
Fig. 2 shows a simplified test board suitable for a 20 pin chip with pins directed one by one to each expansion contact, thereby converting a dense pin interface into spatially dispersed expansion contacts for accurate contact with probes.
Fig. 3 shows the positional relationship between a robot arm holding a probe and a test board, the robot arm being free to move in space above the test board.
The invention also provides an integrated circuit testing method, which comprises the following steps:
(1) Selecting parameters to be tested, such as voltage between specific two pins of the FPGA;
(2) And the FPGA to be tested is arranged on the test board, then fixed on the rack through the test board fixing structure, and communication connection is established between the chip communication interface and an external PC so as to perform configuration. Video acquisition is carried out on a test board card carrying an FPGA chip to be tested, the positions of the expansion contacts of the test board card corresponding to parameters to be tested are identified, the test board card is provided with a preset number of expansion contacts, and the expansion contacts are connected with the external connecting ends of the chip to be tested in a corresponding mode;
(3) Selecting a corresponding tester (voltmeter) according to the parameters to be tested, and enabling the mechanical arm to clamp the voltmeter probe to be in contact with the identified and determined expansion contact so as to establish a test connection relationship between the voltmeter probe and the chip to be tested;
(4) The chip is stimulated, and the voltmeter outputs a test signal.
In the step (3), the mechanical arm determines the Z-direction moving distance through a force feedback algorithm, wherein the Z-direction is a direction perpendicular to the plane where the contact is located (i.e. the surface of the test board where the contact is located).
In the step (3), the spatial position of the feature point is determined by performing video acquisition on the feature point of the detection signal input part.
The detection signal input component is a probe, the characteristic point is a contact end of the probe, in the step (3), the actual position of the contact end of the probe is determined through an edge recognition algorithm, the X direction and the Y direction of the contact end of the probe are adjusted to be coincident with the X direction and the Y direction of the corresponding expansion contact, and then Z direction movement is carried out to enable the Z direction position of the contact end of the probe to be coincident with the Z direction position of the corresponding expansion contact. The sliding rail mechanism of the mechanical arm supports the mechanical arm to move in three directions of XYZ in space, and the specific structure belongs to the prior art and is not repeated here.
The invention can flexibly replace the tester, such as an oscilloscope, a code pattern generator and the like, can be freely increased or decreased, does not need to change the tester itself, does not need to replace signal input components such as a probe and the like, and ensures the testing effect.

Claims (7)

1. An integrated circuit testing method, comprising the steps of:
(1) Selecting parameters to be measured;
(2) Video acquisition is carried out on a test board card carrying a chip to be tested, the positions of expansion contacts of the test board card corresponding to parameters to be tested are identified, the test board card is provided with a preset number of expansion contacts, and the expansion contacts are correspondingly connected with the external connecting ends of the chip to be tested;
(3) The mechanical arm moves the detection signal input part corresponding to the parameter to be detected to enable the detection signal input part to be contacted with the identified and determined expansion contact corresponding to the parameter to be detected, so as to establish a test connection relation between the detection signal input part and the chip to be detected;
(4) The tester to which the detection signal input part belongs outputs a test signal.
2. The method of testing an integrated circuit according to claim 1, wherein in the step (3), the mechanical arm determines a Z-direction moving distance by a force feedback algorithm, and the Z-direction is a direction perpendicular to a plane in which the contact points lie.
3. The integrated circuit testing method of claim 1, wherein in the step (3), the spatial location of the feature point is determined by performing video acquisition on the feature point of the probe signal input part.
4. The method of testing an integrated circuit of claim 2, wherein the probing signal input member is a probe, the feature is a contact end of the probe,
in the step (3), the actual position of the contact end of the probe is determined through an edge recognition algorithm, and the X direction and the Y direction of the contact end of the probe are adjusted to be coincident with the X direction and the Y direction of the corresponding extended contact, and then Z direction movement is carried out to ensure that the Z direction position of the contact end of the probe is coincident with the Z direction of the corresponding extended contact.
5. The integrated circuit testing system is characterized by comprising an image acquisition unit and a rack,
the machine frame is provided with a test plate fixing structure, at least one tester fixing structure and at least one mechanical arm, wherein the mechanical arm comprises a space position adjusting unit and a clamping structure;
the image acquisition unit comprises a data output interface.
6. The integrated circuit testing system of claim 5, further comprising a communication relay module having an external communication interface for connecting each tester and at least one internal communication interface for communicating with an external computer.
7. The integrated circuit testing system of claim 5, wherein the frame is provided with a sealing structure, and the mechanical arm and the test plate fixing structure are disposed in a sealing cavity of the sealing structure.
CN202310880926.3A 2023-07-18 2023-07-18 Integrated circuit testing method and testing system Pending CN117054700A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310880926.3A CN117054700A (en) 2023-07-18 2023-07-18 Integrated circuit testing method and testing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310880926.3A CN117054700A (en) 2023-07-18 2023-07-18 Integrated circuit testing method and testing system

Publications (1)

Publication Number Publication Date
CN117054700A true CN117054700A (en) 2023-11-14

Family

ID=88654388

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310880926.3A Pending CN117054700A (en) 2023-07-18 2023-07-18 Integrated circuit testing method and testing system

Country Status (1)

Country Link
CN (1) CN117054700A (en)

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