CN117040494B - Reference clock calibration circuit, calibration method and reference clock frequency multiplier - Google Patents
Reference clock calibration circuit, calibration method and reference clock frequency multiplier Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
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Abstract
The invention provides a reference clock calibration circuit, a calibration method and a reference clock frequency multiplier, which comprise the following steps: the adjusting module is used for adjusting the duty ratio of the accessed reference clock signal; the detection module performs mode conversion on the reference clock signal subjected to adjustment, provides offset configuration, and performs multiple comparisons on the reference clock signal subjected to mode conversion; the calibration module performs an algorithm operation to determine an adjustment direction of the duty cycle and an adjustment direction of the offset configuration based on the results of the multiple comparisons. By mode conversion of the reference clock signal, the offset error and the duty cycle error of the reference clock signal are combined for calibration, so that the error of the reference clock signal is reduced below the duty cycle adjustment stepping precision or the offset adjustment stepping precision, in-band spurious is reduced, and the frequency stability of the output signal of the frequency multiplier is improved. Simple structure, easy and simple to handle, have extensive suitability.
Description
Technical Field
The present invention relates to the field of radio frequency communication design and application technology, and in particular, to a reference clock calibration circuit, a reference clock calibration method, and a reference clock frequency multiplier.
Background
The reference clock multiplier is generally applied to the front end part of a frequency synthesizer (the frequency synthesizer is a key device in modern communication systems, radars and test equipment, and can provide high-precision and high-stability frequency and serve as a local oscillator for driving a mixer of a transceiver), and the reference clock signal is multiplied and then transmitted to a phase detector of a phase-locked loop so as to reduce the frequency division ratio of the phase-locked loop. The advantages are that: compared with equivalent noise introduced by the phase-locked loop, the phase noise of the reference clock frequency multiplier is lower, so that the introduction of the reference clock frequency multiplier can reduce the phase noise of the integral output of the frequency synthesizer.
However, the reference clock frequency multiplier generally requires that the duty ratio of the input clock is close to 50%, and once the duty ratio deviates from 50%, the frequency stability of the output signal of the frequency multiplier is reduced, so that the phase noise of the phase-locked loop using the output signal as the reference clock is further deteriorated, and the in-band spurious of the phase-locked loop is increased, therefore, the duty ratio of the reference clock frequency multiplier needs to be calibrated, the existing calibration operation does not consider the error of the duty ratio detection part in the reference clock frequency multiplier, especially when the duty ratio is close to 50%, the input signal of the duty ratio detection part is weak, and the detection process is easily influenced by factors such as noise, mismatch and the like in the system, so that the calibration accuracy of the duty ratio is extremely limited.
It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a reference clock calibration circuit, a calibration method and a reference clock frequency multiplier, which are used for solving the problem that the duty ratio of the reference clock frequency multiplier in the prior art is very susceptible to factors such as noise and mismatch in a system, so that the calibration accuracy of the duty ratio is very limited.
To achieve the above and other related objects, the present invention provides a reference clock calibration circuit, including at least: the device comprises an adjusting module, a detecting module and a calibrating module, wherein:
the adjusting module is used for adjusting the duty ratio of the accessed reference clock signal;
the first input end of the detection module is connected with the output end of the adjustment module, carries out mode conversion on the reference clock signal which is subjected to adjustment, provides offset configuration, and compares the reference clock signal which is subjected to mode conversion for a plurality of times;
the input end of the calibration module is connected with the output end of the detection module, the first output end of the calibration module is connected with the input end of the adjustment module, the second output end of the calibration module is connected with the second input end of the detection module, and algorithm operation is executed based on the result of multiple comparisons to determine the adjustment direction of the duty ratio and the adjustment direction of the offset configuration.
Optionally, the detection module includes: single-ended to differential unit, switching unit, comparison unit and offset adjustment unit, wherein: the single-ended to differential unit converts an accessed reference clock signal from a single-ended signal to two differential signals with complementary duty ratios and opposite polarities; the input end of the switching unit is connected with the output end of the single-end-to-differential unit, so that two paths of differential signals with different polarities are alternately output, wherein when the two paths of differential signals are in a high level, the switching unit outputs two paths of current signals; the input end of the comparison unit is connected with the output end of the exchange unit, wherein the comparison unit performs charging operation based on two paths of accessed current signals, and further converts the two paths of current signals into two voltage signals for comparison operation; the offset adjustment unit is connected with the input end of the comparison unit and provides an adjusting signal for offset configuration for the input signal of the comparison unit.
Optionally, the switching unit includes: switching device, first switch, second switch and first current source, wherein: the switching device includes: the switching device comprises a first input port, a second input port, a first output port and a second output port, wherein the connection state of the switching device comprises: the first input port is connected with the first output port, and the second input port is connected with the second output port; the first input port is connected with the second output port, and the second input port is connected with the first output port; the first end of the first current source is connected with the working voltage; a first end of the first switch is connected with a second end of the first current source, and a control end of the first switch is connected with a first output port of the switching device; the first end of the second switch is connected with the second end of the first current source, and the control end of the second switch is connected with the second output port of the switching device.
Optionally, the comparing unit includes: the first electric capacity, second electric capacity and comparator, wherein: the first capacitor is connected between the second end of the first switch and the reference ground; the second capacitor is connected between the second end of the second switch and the reference ground; the first input end of the comparator is connected with the second end of the first switch, and the second input end of the comparator is connected with the second end of the second switch.
Optionally, the offset adjustment unit includes P parallel charge pumps, where P is a natural number greater than 1, and P is equal to the number of bits of the adjustment signal for offset configuration.
Optionally, the adjusting module includes a cascade of configurable inverters, wherein Q is a natural number greater than 1 and Q is equal to the number of bits of the duty cycle adjusting signal.
To achieve the above and other related objects, the present invention provides a calibration method, which is implemented based on the reference clock calibration circuit, and the calibration method at least includes:
step 1: setting the bit number of the adjusting signal for offset configuration to be P bit long, and setting the initial value of the adjusting signal for offset configuration to be a median value; setting the bit number of the duty ratio adjusting signal to be Q bit long, setting the initial value of the duty ratio adjusting signal to be a median value, and continuously performing 2 x (2 N -1) a comparison operation, dividing the comparison result into (2) N -1) groups, wherein N is a natural number, each group of comparison results being characterized by an "X 1 X 2 ”，“X 1 "expressed as the result of the comparison prior to polarity exchange," X 2 "represents the comparison result after polarity exchange;
step 2: counting the number of 11, 00, 01 and 10 in the comparison result, and setting a first state register and a second state register with the word length of 2*M bits, wherein M is a natural number greater than 1;
step 3: selecting a first status register when the number and value of "11" and "00" are greater than the number and value of "01" and "10"; when the number of 11's is more than the number of 00's, shifting the first state register by a digital 1 ' and increasing the adjusting signal for offset configuration with the length of P bit; when the number of 11's is smaller than the number of 00's, shifting the first state register by a digital 0 ' and reducing the adjusting signal for offset configuration with the length of P bit; when the number of 11 is equal to the number of 00, reporting errors and returning to the step 1; when the value of the first state register does not reach the locking threshold value, calibrating the offset error and returning to the step 1; ending the calibration when the value of the first status register reaches a locking threshold value, M repeated "01" or repeated "10", a number of times in succession;
step 4: selecting a second status register when the number and value of "11" and "00" are less than the number and value of "01" and "10"; when the number of '01's is larger than the number of '10', shifting the second state register by a digital '1', and increasing the adjusting signal of the duty ratio of the Q bit length; when the number of '01's is smaller than the number of '10', shifting the second state register by a digital '0', and reducing the adjusting signal of the duty ratio of the Q bit length; when the number of '01' is equal to the number of '10', reporting errors and returning to the step 1; when the value of the second state register does not reach the locking threshold value, calibrating the duty ratio error and returning to the step 1; calibration is ended when the value of the second status register reaches a locking threshold value, which is M repeated "01" or repeated "10", a number of times in succession.
To achieve the above and other related objects, the present invention provides a reference clock frequency multiplier, which includes a frequency multiplier and the clock calibration circuit, wherein an input end of the frequency multiplier is connected to an output end of the clock calibration circuit, and the reference clock frequency multiplier supplies a frequency-multiplied reference clock signal to a post-stage circuit.
As described above, the reference clock calibration circuit, the reference clock calibration method and the reference clock frequency multiplier have the following beneficial effects:
1) According to the reference clock calibration circuit, the calibration method and the reference clock frequency multiplier, through mode conversion of the reference clock signal, the self offset error and the duty cycle error are combined for calibration, so that the error of the reference clock signal is reduced below the duty cycle adjustment stepping precision or the offset adjustment stepping precision, in-band spurious emissions are reduced, and the frequency stability of the output signal of the frequency multiplier is improved.
2) The reference clock calibration circuit, the reference clock calibration method and the reference clock frequency multiplier have the advantages of simple structure, simplicity and convenience in operation and wide applicability.
Drawings
Fig. 1 is a schematic diagram of a clock calibration circuit according to the present invention.
Fig. 2 is a schematic diagram of a detection module according to the present invention.
Fig. 3 is a schematic signal diagram of each node of the detection module according to the present invention.
Fig. 4 shows a schematic view of the conditioning module of the present invention.
Fig. 5 is a functional schematic diagram of the clock calibration method of the present invention.
Fig. 6 is a schematic diagram of a reference clock multiplier according to the present invention.
Description of the reference numerals
1-a clock calibration circuit; 11-a regulating module; 12-a detection module; 121-a single-ended to differential unit; 122-an exchange unit; 123-a comparison unit; 124-an offset adjustment unit; 13-a calibration module; 2-frequency doubler; S1-S4.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 6. It should be noted that the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
As shown in fig. 1, the present embodiment provides a clock calibration circuit 1, the clock calibration circuit 1 including: an adjusting module 11, a detecting module 12 and a calibrating module 13, wherein:
as shown in fig. 1, the adjusting module 11 is configured to adjust a duty cycle of the accessed reference clock signal.
Specifically, as an example, as shown in fig. 4, the adjusting module 11 includes Q cascaded inverters INV, where Q is a natural number greater than 1, and Q is equal to the number of bits of the adjusting signal duty_aj < Q:1> of the duty ratio. The inverter INV includes: the PMOS tube P1, the PMOS tube P2, the NMOS tube N1, the NMOS tube N2, the switch S1 and the switch S2, wherein the duty-cycle adjusting signal duty_aj < Q:1> can control the time delay of the adjusting module 11, the opening and closing speeds of the PMOS tube P1 and the NMOS tube N1 are higher, the opening and closing speeds of the PMOS tube P2 and the NMOS tube N2 are lower, and the switch S1 and the switch S2 select the working state of the inverter INV. When the PMOS tube P1 and the NMOS tube N2 are gated by the switch S1 and the switch S2, the falling edge of an input signal (the input signal of the first-stage inverter INV is a reference clock signal) is regulated; when the PMOS transistor P2 and the NMOS transistor N1 are gated by the switches S1 and S2, the rising edge of the input signal is adjusted, and the duty ratio of the reference clock signal is adjusted by the adjustment operations of the rising edge and the falling edge of the input signal. It should be noted that, the adjusting module 11 may also be configured in a gate-level circuit, a combinational logic circuit, etc., and specific configuration is not described herein, so long as the duty ratio of the reference clock signal can be primarily adjusted, any configuration of the adjusting module 11 is applicable, and the embodiment is not limited thereto.
As shown in fig. 1, a first input terminal of the detection module 12 is connected to an output terminal of the adjustment module 11, and performs mode conversion on the reference clock signal subjected to adjustment, provides an offset configuration, and performs multiple comparisons on the reference clock signal subjected to mode conversion.
Specifically, as an example, as shown in fig. 1, the detection module 12 includes: single-ended to differential unit 121, switching unit 122, comparing unit 123 and offset adjustment unit 124, wherein: the single-ended to differential unit 121 converts the access reference clock signal from a single-ended signal to a differential signal with two complementary duty cycles and opposite polarities, where the differential signal includes: signal clkp and signal clkn. It should be noted that, there are many unbalanced circuit structures in the circuit, and the unbalanced circuit structures need to be converted into balanced circuit structures, because the unbalanced circuit structures bring many problems, such as poor electromagnetic compatibility, poor anti-interference capability, and the like; in contrast, balanced circuit structures often have high electromagnetic compatibility and anti-interference capability. More specifically, the single-to-differential unit 121 includes an operational amplifier structure, a balun structure, and a complementary clock line. The balun structure is a passive device, which essentially realizes signal conversion through mutual coupling of induction coils, but the balun structure has a certain limitation, and is not suitable for the low-frequency condition due to certain loss, because of certain attenuation of coupling characteristics in the low-frequency condition. The operational amplifier structure adopts the setting form of the active circuit, which has the amplifying function to the signal, and the peripheral circuit of the operational amplifier structure is more complex than the balun structure, which is suitable for the low frequency condition under the small signal. The complementary clock lines are digital circuits and are formed by two paths of inverters in cascade connection, wherein the specific arrangement forms of the complementary clock lines are not described in detail herein. It should be noted that, the setting form of the single-end-to-differential unit 121 should be selected according to the usage scenario, so long as the electromagnetic compatibility and the anti-interference capability of the reference clock signal can be improved, any setting form of the single-end-to-differential unit 121 is applicable, and the embodiment is not limited thereto.
As shown in fig. 1 and 2, the input end of the switching unit 122 is connected to the output end of the single-end to differential unit 121, so that two differential signals with different polarities (the differential signals include a signal clkp and a signal clkn) are alternately output, wherein when both differential signals are at a high level, the switching unit 122 outputs two current signals, wherein the two current signals include: the signal Io1 and the signal Io2. More specifically, as shown in fig. 2, the switching unit 122 includes: the switching device SW1, the first switch K1, the second switch K2 and the first current source I1, wherein: the connection state of the switching device SW1 includes: the first input port is connected with the first output port, and the second input port is connected with the second output port; the first input port is connected with the second output port, and the second input port is connected with the first output port; the first end of the first current source I1 is connected with the working voltage; a first end of the first switch K1 is connected with a second end of the first current source I1, and a control end of the first switch K1 is connected with a first output port of the switching device SW 1; the first end of the second switch K2 is connected to the second end of the first current source I1, and the control end of the second switch K2 is connected to the second output port of the switching device SW 1.
As shown in fig. 1 and 2, an input terminal of the comparing unit 123 is connected to an output terminal of the switching unit 122, wherein the comparing unit 123 performs a charging operation based on two connected current signals, and further converts the two current signals into two voltage signals for the comparing operation, wherein the two voltage signals include: signal V1 and signal V2. More specifically, as shown in fig. 2, the comparison unit 123 includes: the first capacitor C1, the second capacitor C2 and the comparator CMP, wherein: the first capacitor C1 is connected between the second end of the first switch K1 and the reference ground; the second capacitor C2 is connected between the second end of the second switch K2 and the reference ground; a first input terminal of the comparator CMP is connected to a second terminal of the first switch K1, and a second input terminal of the comparator CMP is connected to a second terminal of the second switch K2. The first switch K1 and the second switch K2 charge the first capacitor C1 and the second capacitor C2 in the comparing unit 123 according to the high level duration and the low level duration of the differential signal, respectively. The switching device SW1 exchanges the signal clkp and the signal clkn, the comparator CMP performs a comparison operation on the accessed signal V1 and the accessed signal V2, and then the accessed signalV1 and the signal V2 are compared again, and the output signal of the comparator CMP is characterized as the signal V O 。
As shown in fig. 1 and 2, the offset adjustment unit 124 is connected to the input terminal of the switching unit 122, and provides the adjustment signal offset_aj < P:1> for offset configuration to the input signal of the comparison unit 123. More specifically, as shown in fig. 2, the offset adjustment unit 124 includes P parallel charge pumps, where P is a natural number greater than 1, and P is equal to the number of bits of the adjustment signal offset_aj < P:1> for offset configuration. It should be noted that fig. 2 shows an equivalent schematic diagram of the offset adjustment unit 124 using a charge pump, and the basic principle of the charge pump is to charge the capacitor, remove the capacitor from the charging circuit to isolate the charged charge, and connect the capacitor to another circuit to transfer the isolated charge. In fig. 2, the isolated charges are transferred by the switching operation of the switch in the offset adjustment unit 124, wherein the adjustment signal offset_aj < P:1> for offset configuration is characterized as a signal flow when the isolated charges are transferred, and the adjustment signal offset_aj < P:1> for offset configuration adjusts the offset voltage at the input terminal of the comparator CMP to reduce the offset error of the detection module 12. Because the first switch K1 and the second switch K2 respectively charge the first capacitor C1 and the second capacitor C2 according to the high-level duration and the low-level duration of the differential signal, the comparator CMP starts working after the charging is finished, and duty ratio comparison information of the reference clock signal is output; further, the switching device SW1 switches the input differential signals (including the signal clkp and the signal clkn), and the adjusting signal offset_aj < P:1> for offset configuration is used to control the injection current of the offset adjusting unit 124 to the input terminal of the comparator CMP in the charging phase (the phase of charging the first capacitor C1 and the second capacitor C2), so as to adjust the voltage of the input terminal of the comparator CMP (i.e. the voltages of the adjusting signal V1 and the signal V2).
Wherein, signal clkp, signal clkn, signal Io1, signal Io2, signal V1, signal V2 and signal V O The timing relationship of (a) is shown in fig. 3, and the specific process will not be described in detail here.
Still further, the detection module 12 may further include a current extraction unit, which is not illustrated in fig. 1 and 2, and is disposed between the output terminal of the switching unit 122 and the input terminal of the comparing unit 123, for fine tuning the output signal of the switching unit 122. It should be noted that the current extraction unit may be configured by a charge pump, so that the current extraction unit and the offset adjustment unit 124 form a symmetrical structure, and further adjust the offset voltage of the input terminal of the comparator CMP.
As shown in fig. 1, an input end of the calibration module 13 is connected with an output end of the detection module 12, a first output end of the calibration module 13 is connected with an input end of the adjustment module 11, a second output end of the calibration module 13 is connected with a second input end of the detection module 12, and algorithm operations are performed to determine an adjustment direction of the duty ratio and an adjustment direction of the offset configuration based on a result of the multiple comparisons, wherein the implementation of the algorithm calibration is as follows:
as shown in fig. 5, this embodiment further provides a calibration method, which is implemented based on the reference clock calibration circuit described in this embodiment, and the clock calibration method includes:
as shown in fig. 5, step S1: setting the bit number of the adjusting signal for offset configuration to be P bit long, and setting the initial value of the adjusting signal for offset configuration to be a median value; setting the bit number of the duty ratio adjusting signal to be Q bit long, setting the initial value of the duty ratio adjusting signal to be a median value, and continuously performing 2 x (2 N -1) a comparison operation, dividing the comparison result into (2) N -1) groups, wherein N is a natural number, each group of comparison results being characterized by an "X 1 X 2 ”，“X 1 "expressed as the result of the comparison prior to polarity exchange," X 2 "is expressed as the result of comparison after polarity exchange. It should be noted that, for convenience of calibration, the comparison result is generally subjected to temporary storage operation, and specific setting of the temporary storage operation is not described here.
As shown in fig. 5, step S2: counting the number of 11, 00, 01 and 10 in the comparison result, and setting a first state register and a second state register with the word length of 2*M bits, wherein M is a natural number greater than 1. It should be noted that the first status register and the second status register perform a shift operation based on the comparison result.
As shown in fig. 5, step S3: selecting a first status register when the number and value of "11" and "00" are greater than the number and value of "01" and "10"; when the number of '11's is greater than the number of '00', the first state register is shifted to register the number '1', and the P bit long adjusting signal offset_aj for offset configuration is used<P:1>An increase; when the number of '11's is smaller than the number of '00', the first state register is shifted to register digital '0', and the P bit long adjusting signal offset_aj for offset configuration is used<P:1>A reduction; when the number of 11 is equal to the number of 00, reporting error and returning to the step S1; when the value of the first status register does not reach the locking threshold value, calibrating the offset error and returning to the step S1; calibration is ended when the value of the first status register reaches a lock threshold value, which is M repeated "01" or repeated "10", a number of times in succession. It should be noted that, if the comparator CMP is normal, the signal clkp and the signal clkn are compared, and then the comparator CMP outputs "0" or "1", the switching device SW1 exchanges the signal clkp and the signal clkn and then compares, and the comparator CMP outputs "1" or "0", then "X" 1 X 2 "shown as" 01 "or" 10", where the source of error is primarily the duty cycle error of the reference clock signal; if "X 1 X 2 When the number and value of "11" or "00" are larger than the number and value of "01" and "10", the error is mainly derived from the offset error of the comparator CMP. By way of example, setting M to 2, the lock threshold may be set to "1010" or "0101", and when the value of the first status register does not reach "1010" or "0101", the misalignment error is calibrated; when the value of the first status register reaches "1010" or "0101" a number of times in succession (for example, four times), the calibration operation for the offset error is ended. Further, M and the locking threshold should be set according to specific usage scenariosThe present embodiment is not limited to this embodiment.
As shown in fig. 5, step S4: selecting a second status register when the number and value of "11" and "00" are less than the number and value of "01" and "10"; when the number of "01" is greater than the number of "10", shifting the second status register by a number "1", and increasing the duty ratio adjusting signal duty_aj < Q:1> of Q bit length; shifting the second status register by a digital "0" and decreasing the duty ratio adjusting signal duty_aj < Q:1> of the Q bit length when the number of "01" is smaller than the number of "10"; when the number of "01" is equal to the number of "10", reporting an error and returning to the step S1; when the value of the second status register does not reach the locking threshold value, calibrating the duty ratio error and returning to the step S1; calibration is ended when the value of the second status register reaches a locking threshold value, which is M repeated "01" or repeated "10", a number of times in succession. As an example, setting M to 2, the lock threshold may be set to "1010" or "0101", and when the value of the second status register does not reach "1010" or "0101", the duty cycle error is calibrated; when the value of the second status register reaches "1010" or "0101" a plurality of times (for example, four times) in succession, the calibration operation for the duty cycle error is ended. Further, the setting of M and the locking threshold should be performed according to a specific usage scenario, which is not limited to this embodiment.
As an example, as shown in fig. 1 and 2, when the adjustment signal for offset_aj < P:1> and the adjustment signal for duty_aj < Q:1> are set to be 5 bits long, the adjustment signal for offset_aj < P:1> is set to be offset_aj <5:1>, the adjustment signal for duty_aj < Q:1> is set to be duty_aj <5:1>, and assuming that the duty error of the reference clock signal is mapped to the input code value of the comparator CMP to be 4.1, the offset error of the comparator itself is 3.5, and the adjustment step lengths of offset_aj <5:1> and duty_aj <5:1> are all 1, the calibration procedure based on the clock calibration method of the present embodiment is as follows:
。
in the initial state, the duty ratio error is 4.1, the offset error is 3.5, and the duty ratio error is calibrated because 4.1 is more than 3.5; after the calibration for the 1 st time, the duty cycle error is 3.1, the offset error is 3.5, and the offset error is calibrated because 3.1 is less than 3.5, and so on, after the calibration for the 7 th time, the duty cycle error is 0.1, the offset error is 0.5, the calibration is continuously carried out for four times, and the absolute value of the duty cycle error and the absolute value of the offset error are kept unchanged each time, namely, the value of the first state register reaches the locking threshold value four times in succession, and the value of the second state register reaches the locking threshold value four times in succession, and the calibration is ended.
It should be further noted that a storage medium may be provided, where the storage medium includes one or more programs, where the programs are used to execute the calibration method, and the manner of setting the storage medium is not described herein in detail.
As shown in fig. 6, the present embodiment further provides a reference clock frequency multiplier, where the reference clock frequency multiplier includes a frequency multiplier 2 and the clock calibration circuit 1 described in this embodiment, an input end of the frequency multiplier 2 is connected to an output end of the clock calibration circuit 1, and the reference clock frequency multiplier supplies the frequency-multiplied reference clock signal to a post-stage circuit, where the output clock signal is the frequency-multiplied reference clock signal. It should be noted that, after the reference clock signal is multiplied, the reference clock signal is transmitted to the phase discriminator of the phase-locked loop, so that the frequency division ratio of the phase-locked loop can be reduced, and the stability and anti-interference performance of the system are improved.
In summary, the reference clock calibration circuit, the calibration method and the reference clock frequency multiplier of the present invention at least include: the device comprises an adjusting module, a detecting module and a calibrating module, wherein: the adjusting module is used for adjusting the duty ratio of the accessed reference clock signal; the first input end of the detection module is connected with the output end of the adjustment module, carries out mode conversion on the reference clock signal which is subjected to adjustment, provides offset configuration, and compares the reference clock signal which is subjected to mode conversion for a plurality of times; the input end of the calibration module is connected with the output end of the detection module, the first output end of the calibration module is connected with the input end of the adjustment module, the second output end of the calibration module is connected with the second input end of the detection module, and algorithm operation is executed based on the result of multiple comparisons to determine the adjustment direction of the duty ratio and the adjustment direction of the offset configuration. According to the reference clock calibration circuit, the calibration method and the reference clock frequency multiplier, through mode conversion of the reference clock signal, the self offset error and the duty cycle error are combined for calibration, so that the error of the reference clock signal is reduced below the duty cycle adjustment stepping precision or the offset adjustment stepping precision, in-band spurious emissions are reduced, and the frequency stability of the output signal of the frequency multiplier is improved. The reference clock calibration circuit, the reference clock calibration method and the reference clock frequency multiplier have the advantages of simple structure, simplicity and convenience in operation and wide applicability.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (7)
1. A reference clock calibration circuit, the reference clock calibration circuit comprising at least: the device comprises an adjusting module, a detecting module and a calibrating module, wherein:
the adjusting module is used for adjusting the duty ratio of the accessed reference clock signal;
the first input end of the detection module is connected with the output end of the adjustment module, carries out mode conversion on the reference clock signal which is subjected to adjustment, provides offset configuration, and compares the reference clock signal which is subjected to mode conversion for a plurality of times;
the input end of the calibration module is connected with the output end of the detection module, the first output end of the calibration module is connected with the input end of the adjustment module, the second output end of the calibration module is connected with the second input end of the detection module, and algorithm operation is executed based on the result of multiple comparisons to determine the adjustment direction of the duty ratio and the adjustment direction of the offset configuration; the detection module comprises: single-ended to differential unit, switching unit, comparison unit and offset adjustment unit, wherein: the single-ended to differential unit converts an accessed reference clock signal from a single-ended signal into two differential signals with complementary duty ratios and opposite polarities; the input end of the switching unit is connected with the output end of the single-end-to-differential unit, so that two paths of differential signals with different polarities are alternately output, wherein when the two paths of differential signals are in a high level, the switching unit outputs two paths of current signals; the input end of the comparison unit is connected with the output end of the exchange unit, wherein the comparison unit performs charging operation based on two paths of accessed current signals, and further converts the two paths of current signals into two voltage signals for comparison operation; the offset adjustment unit is connected with the input end of the comparison unit and provides an adjusting signal for offset configuration for the input signal of the comparison unit.
2. The reference clock calibration circuit of claim 1, wherein: the switching unit includes: switching device, first switch, second switch and first current source, wherein: the switching device includes: the switching device comprises a first input port, a second input port, a first output port and a second output port, wherein the connection state of the switching device comprises: the first input port is connected with the first output port, and the second input port is connected with the second output port; the first input port is connected with the second output port, and the second input port is connected with the first output port; the first end of the first current source is connected with the working voltage; a first end of the first switch is connected with a second end of the first current source, and a control end of the first switch is connected with a first output port of the switching device; the first end of the second switch is connected with the second end of the first current source, and the control end of the second switch is connected with the second output port of the switching device.
3. The reference clock calibration circuit of claim 2, wherein: the comparison unit includes: the first electric capacity, second electric capacity and comparator, wherein: the first capacitor is connected between the second end of the first switch and the reference ground; the second capacitor is connected between the second end of the second switch and the reference ground; the first input end of the comparator is connected with the second end of the first switch, and the second input end of the comparator is connected with the second end of the second switch.
4. The reference clock calibration circuit of claim 1, wherein: the offset adjustment unit comprises P paths of charge pumps connected in parallel, wherein P is a natural number larger than 1, and the number of bits of the P is equal to that of adjustment signals for offset configuration.
5. The reference clock calibration circuit of claim 1, wherein: the regulation module comprises Q cascaded configurable inverters, wherein Q is a natural number greater than 1, and the number of bits of the regulating signals of the Q and the duty ratio is equal.
6. A calibration method based on a reference clock calibration circuit implementation according to any of claims 1-5, characterized in that: the calibration method at least comprises the following steps:
step 1: setting the bit number of the adjusting signal for offset configuration to be P bit long, and setting the initial value of the adjusting signal for offset configuration to be a median value; setting the bit number of the duty ratio adjusting signal to be Q bit long, setting the initial value of the duty ratio adjusting signal to be a median value, and continuously performing 2 x (2 N -1) a comparison operation, dividing the comparison result into (2) N -1) groups, wherein N is a natural number, each group of comparison results being characterized by an "X 1 X 2 ”，“X 1 "expressed as the result of the comparison prior to polarity exchange," X 2 "represents the comparison result after polarity exchange;
step 2: counting the number of 11, 00, 01 and 10 in the comparison result, and setting a first state register and a second state register with the word length of 2*M bits, wherein M is a natural number greater than 1;
step 3: selecting a first status register when the number and value of "11" and "00" are greater than the number and value of "01" and "10"; when the number of 11's is more than the number of 00's, shifting the first state register by a digital 1 ' and increasing the adjusting signal for offset configuration with the length of P bit; when the number of 11's is smaller than the number of 00's, shifting the first state register by a digital 0 ' and reducing the adjusting signal for offset configuration with the length of P bit; when the number of 11 is equal to the number of 00, reporting errors and returning to the step 1; when the value of the first state register does not reach the locking threshold value, calibrating the offset error and returning to the step 1; ending the calibration when the value of the first status register reaches a locking threshold value, M repeated "01" or repeated "10", a number of times in succession;
step 4: selecting a second status register when the number and value of "11" and "00" are less than the number and value of "01" and "10"; when the number of '01's is larger than the number of '10', shifting the second state register by a digital '1', and increasing the adjusting signal of the duty ratio of the Q bit length; when the number of '01's is smaller than the number of '10', shifting the second state register by a digital '0', and reducing the adjusting signal of the duty ratio of the Q bit length; when the number of '01' is equal to the number of '10', reporting errors and returning to the step 1; when the value of the second state register does not reach the locking threshold value, calibrating the duty ratio error and returning to the step 1; calibration is ended when the value of the second status register reaches a locking threshold value, which is M repeated "01" or repeated "10", a number of times in succession.
7. A reference clock multiplier, characterized by: the reference clock frequency multiplier comprises a frequency multiplier and the clock calibration circuit according to any one of claims 1-5, wherein the input end of the frequency multiplier is connected with the output end of the clock calibration circuit, and the reference clock frequency multiplier supplies the frequency-multiplied reference clock signal to a later-stage circuit.
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