CN117038469A - Fan-out packaging structure based on diamond substrate and wafer-level preparation process - Google Patents
Fan-out packaging structure based on diamond substrate and wafer-level preparation process Download PDFInfo
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- CN117038469A CN117038469A CN202311034375.5A CN202311034375A CN117038469A CN 117038469 A CN117038469 A CN 117038469A CN 202311034375 A CN202311034375 A CN 202311034375A CN 117038469 A CN117038469 A CN 117038469A
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- 239000010432 diamond Substances 0.000 title claims abstract description 93
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 title claims abstract description 30
- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 49
- 239000002184 metal Substances 0.000 claims abstract description 49
- 239000000463 material Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 claims abstract description 24
- 238000003466 welding Methods 0.000 claims abstract description 16
- 238000005520 cutting process Methods 0.000 claims abstract description 3
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 238000000465 moulding Methods 0.000 claims description 6
- 238000007789 sealing Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- 238000012858 packaging process Methods 0.000 claims description 3
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- 238000007747 plating Methods 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 238000012536 packaging technology Methods 0.000 claims description 2
- 238000007639 printing Methods 0.000 claims description 2
- 238000005476 soldering Methods 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 9
- 230000017525 heat dissipation Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000007731 hot pressing Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
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- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
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- 229910002804 graphite Inorganic materials 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
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- 229920005989 resin Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
Abstract
The invention discloses a fan-out packaging structure based on a diamond substrate and a wafer-level preparation process, wherein the process comprises the following steps: 1) Temporarily bonding one sides of the pad surfaces of the chips to be packaged to a temporary carrier plate; 2) Preparing metal layers on the back surface of the chip and the diamond surface of the temporary carrier plate respectively, and realizing hot-press bonding through the metal layers after alignment; 3) Carrying out plastic packaging, and thinning the plastic packaging layer until the diamond is exposed; 4) Removing the temporary carrier plate of the chip welding disc surface, and temporarily bonding another temporary carrier plate on one side of the diamond; 5) Manufacturing a rewiring layer and an external connection structure on one side of a chip bonding pad surface; 6) Removing the temporary carrier plate on one side of the diamond, and cutting and scribing; 7) A thermal interface material layer and a heat sink are sequentially formed on one side of the diamond. The invention realizes the application of diamond as a chip radiating substrate by the hot-press bonding technology, and improves the radiating performance of the device; while achieving thinner package sizes and lower thermal resistance through the fan-out package structure.
Description
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a diamond substrate-based fan-out packaging structure and a wafer-level preparation process.
Background
With the continuous development of integrated circuits, miniaturization, high integration and high performance are becoming the development trend of electronic devices, and this puts higher demands on the heat dissipation performance of the electronic devices. As devices generate heat during operation, the temperature of the chip increases as heat builds up, and typically exhibits uneven heat dissipation, causing them to reach excessive temperatures, thereby reducing their performance, reliability and lifetime, with increased power consumption leading to significant "thermal death" problems. Therefore, how to transfer the heat of the hot spot of the chip out quickly and efficiently is a key for ensuring the normal operation of the high-power device.
Some high thermal conductivity heat sink materials will greatly improve the heat dissipation problem of the device if applied in the packaging of semiconductor devices. The most potential light, high-efficiency and long-life high-heat-conductivity materials are carbon-based materials at present, and mainly comprise carbon/carbon composite materials, graphite, graphene and diamond film materials. Among them, diamond is the material with the highest heat conductivity in the natural world known at present. At room temperature, the heat conductivity of diamond can reach 2200W/m.K. In addition, diamond has the advantages of low thermal expansion coefficient, high resistivity, low density, high chemical stability and the like, so that the diamond becomes the most ideal heat dissipation material in the device heat management.
However, due to the chemical inertness of diamond, it is difficult to bond diamond to a chip, and relatively severe process conditions such as high temperature, high pressure and the like are often required to bond diamond to the chip, which greatly limits the application of diamond in the field of advanced packaging.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention provides a fan-out packaging structure based on a diamond substrate and a wafer-level preparation process.
In order to achieve the above object, the technical scheme of the present invention is as follows:
a wafer level preparation process of a fan-out packaging structure based on a diamond substrate comprises the following steps:
step 1, a hot-press bonding process:
1.1, a chip to be packaged is provided with a welding disc surface and an opposite back surface, and a plurality of chips are bonded on a temporary carrier plate in a mode that the welding disc surface faces downwards;
1.2, respectively manufacturing metal layers on the back surface and the diamond surface of a chip to be packaged, aligning the diamond with the back surface of the chip one by one, and performing hot-press bonding through the metal layers to obtain a diamond-chip bonding body;
step 2, fan-out packaging technology:
2.1, carrying out plastic package on the diamond-chip bonding body on the temporary carrier plate, and thinning the plastic package layer to the surface of the exposed diamond to form a recombined wafer;
2.2, removing the temporary carrier plate on the welding disc surface of the chip, and forming another temporary carrier plate on one side of the diamond;
2.3, manufacturing a rewiring layer and an external connection structure on one side of the bonding pad surface of the chip;
2.4, removing the temporary carrier plate on one side of the diamond, and cutting and scribing to form single packaging chips;
2.5A thermal interface material layer and a heat sink are sequentially formed on one side of the diamond surface of the packaged chip.
Optionally, the metal layer includes an adhesion barrier layer and a bonding layer; the adhesion barrier layer is made of Ti, cr, ni, W, mo, zr, nb or one or more of carbon and nitride materials thereof; the bonding layer is In, au, ag, sn, cu, ni, al, ti, cr, pd, pt metal or alloy of several metals or soldering paste made of the metal.
Optionally, the thickness of the adhesion barrier layer is 2 nm-50 μm; the thickness of the bonding layer is 10 nm-200 mu m.
Optionally, the metal layer is formed on the diamond surface and the back of the chip by sputtering, vapor deposition, electroplating, chemical plating or printing. In addition, the metal paste dispensing mode can be adopted. The metal layer is preferably planarized by chemical mechanical polishing.
Optionally, the temperature of the hot-press bonding of the chip and the diamond is 20-500 ℃ and the pressure is 0-20 MPa.
Optionally, the total interface thermal resistance of the bonding interface between the chip and the diamond<1mm 2 K/W. The smaller the interface thermal resistance is, the better the heat conduction effect is, and more preferably, the total interface thermal resistance is<0.3mm 2 ·K/W。
Optionally, the temporary carrier is preferably a carrier wafer.
Optionally, step 2.3 in the fan-out packaging process includes the steps of:
2.3.1 Patterning an insulating layer on one side of the chip bonding pad surface, wherein the insulating layer is provided with a first opening exposing the chip bonding pad;
2.3.2 Manufacturing a metal interconnection layer on the patterned insulating layer, wherein the metal interconnection layer is electrically connected with the chip bonding pad through the first opening;
2.3.3 Solder balls or bumps are manufactured on the metal interconnection layer to form an external connection structure.
Optionally, the plastic layer and the diamond have flush surfaces.
The fan-out packaging structure based on the diamond substrate comprises a packaging body of a chip, wherein the packaging body of the chip comprises the chip, diamond, a metal layer and a plastic layer, and the chip is provided with a welding disc surface and an opposite back surface; the diamond is bonded with the back of the chip through the metal layer; the plastic layer coats the side surfaces of the diamond and the chip; the diamond side of the packaging body is sequentially provided with a thermal interface material layer and a radiator, one side of the chip welding disc surface of the packaging body is provided with a rewiring structure and an external connection structure, the rewiring structure comprises a metal interconnection layer arranged in an insulating layer, and the metal interconnection layer is connected with a bonding pad of the chip and the external connection structure.
The beneficial effects of the invention are as follows:
by adopting the hot-press bonding process, on one hand, good bonding effect can be realized at lower temperature: bonding porosity<10%, bonding strength>6MPa; on the other hand, the bonded sample exhibits excellent heat conduction characteristics: total thermal resistance of diamond-chip bonding interface<1mm 2 K/W. Compared with the prior artThe device with diamond as the radiating substrate has greatly raised radiating capacity and lowered highest junction temperature>10, the problem that the device fails due to overhigh heat during the working process of the device is avoided, and the reliability of the device is improved. Meanwhile, through a fan-out packaging process, the chip and the diamond are bonded through hot pressing, and then wiring and solder ball preparation are carried out, so that the damage to the solder balls during the hot pressing bonding of the chip and the diamond is avoided; and the fan-out packaging structure can realize thinner packaging size and lower thermal resistance and can be used for three-dimensional multi-chip integration.
Drawings
FIG. 1 is a schematic diagram of a wafer level fabrication process of a diamond substrate based fan-out package structure in combination with a temporary carrier;
FIG. 2 is a schematic diagram of die-to-diamond bonding for a wafer level fabrication process of a fan-out package structure based on a diamond substrate of an embodiment;
FIG. 3 is a schematic diagram of a temporary carrier plate peeled after plastic packaging in a wafer level manufacturing process of a fan-out package structure based on a diamond substrate according to an embodiment;
FIG. 4 is a schematic diagram of diamond-to-temporary carrier bonding for a wafer level fabrication process of a fan-out package structure based on a diamond substrate of an embodiment;
FIG. 5 is a schematic diagram of a wafer level fabrication process of a diamond substrate based fan-out package structure of an embodiment forming patterned insulating layers and rewiring layers;
FIG. 6 is a schematic diagram of forming solder balls for a wafer level fabrication process of a diamond substrate based fan-out package structure of an embodiment;
FIG. 7 is a schematic diagram of dicing of a wafer level manufacturing process of a diamond substrate based fan-out package structure of an embodiment;
FIG. 8 is a schematic diagram of a thermal interface material formation process for wafer level fabrication of a diamond substrate based fan-out package structure of an embodiment;
fig. 9 is a schematic diagram of a diamond substrate based fan-out package structure of an embodiment.
Detailed Description
The invention is further explained below with reference to the drawings and specific embodiments. The drawings of the present invention are merely schematic to facilitate understanding of the present invention, and specific proportions thereof may be adjusted according to design requirements. The definition of the context of the relative elements and the front/back of the figures described herein should be understood by those skilled in the art to refer to the relative positions of the elements and thus all the elements may be reversed to represent the same elements, which are all within the scope of the present disclosure.
A wafer level fabrication process for a diamond substrate based fan-out package structure is shown in fig. 1-8.
Referring to fig. 1, a temporary carrier plate S1 is first prepared, including a temporary bonding sheet S1-a and a temporary bonding film S1-b, specifically, the temporary bonding sheet S1-a is covered with the temporary bonding film S1-b, and the material of the temporary bonding sheet S1-a may be a non-conductive material such as ceramic, glass, silicon wafer, etc., preferably a carrier plate wafer; the temporary bonding film S1-b has tackiness and can be removed by heating, light irradiation, or the like. For example, the temporary bonding film S1-b is formed by spin coating, baking, or the like on a wafer to form a glue layer on the surface by using a photosensitive material as a temporary bonding glue. The front surfaces of the chips 1 to be packaged are bonding pad surfaces, namely bonding pads 1a are arranged, first insulating layers 1b are filled between the bonding pads 1a, the first insulating layers 1b are flush with the surfaces of the bonding pads 1a, and the front surfaces of the chips 1 are temporarily bonded on the temporary carrier plate S1 through temporary bonding films S1-b downwards, namely the bonding pads face the temporary carrier plate S1. For convenience of explanation, fig. 1 to 6 take a single chip as an example. After the plastic sealing layer thinning process is completed, the temporary bonding film S1-b is acted by laser with specific wavelength to perform bonding, and the chip and the temporary bonding carrier wafer are separated.
Referring to fig. 2, a diamond 2 with a thickness of 400 μm is provided, a physical vapor deposition process is used to deposit Ti/Ag material with a thickness of 10nm/50nm on the surface of the diamond 2 and the back of the chip 1, wherein the Ti layer is an adhesion barrier layer, the Ag layer is a bonding layer, the diamond 2 and the Ti/Ag material layer of the chip 1 are bonded in one-to-one alignment, the bonding temperature is 250 ℃, the pressure is 6MPa, and the two Ti/Ag material layers are combined to form a metal layer 3 after bonding. Due toThe metal layer 3 is present, and can bond materials by interdiffusion of interface atoms, which can realize high-strength bonding under hot-pressing conditions. The metal layer may be made of one metal such as In, au, ag, sn, cu, ni, al, ti, cr, pd, pt or an alloy containing the same. Total thermal resistance of bonded diamond-chip bonding interface<1mm 2 ·K/W。
Referring to fig. 3, a bonding body between the diamond 2 and the chip 1 is coated on the temporary carrier plate S1 by using a molding material to form a molding layer 4, and the surface of the molding layer 4 is thinned to the surface of the bare diamond to form a reconstituted wafer. The molding layer 4 may be formed of various known molding materials for protecting the semiconductor package apparatus. And (5) peeling the temporary carrier plate S1 by adopting a heating, illumination or external force mode to obtain the plastic package wafer containing the chip and the diamond bonding body.
Referring to fig. 4, a chip is bonded to a diamond side of a diamond bond body on a temporary carrier plate S2, and the temporary carrier plate S2 may have the same or similar structure as the temporary carrier plate S1. And thinning the surface of the plastic layer 4 to the surface of the exposed bonding pad 1a, namely forming the upper surface of the plastic layer 4 which is flush with the upper surface of the first insulating layer 1 b. The plastic package body of the chip is obtained, wherein the plastic package layer 4 is coated on the side surface, the upper surface is exposed out of the surface of the first insulating layer 1b, and the lower surface is exposed out of the surface of the diamond 2.
Referring to fig. 5, a second insulating layer 5 is formed on one side of a pad surface of a plastic package of a chip, and a plurality of first openings are formed by patterning the second insulating layer 5 through a photolithography process, wherein the pads 1a of the chip 1 are exposed at the bottoms of the first openings. The metal is deposited on the surface of the second insulating layer 5 to form a patterned metal interconnection layer 6, and the metal is simultaneously deposited in the first opening, so that the metal interconnection layer 6 is electrically connected with the chip 1 through the bonding pad. The material of the second insulating layer 5 may be an organic material such as resin or PI, or an inorganic insulating material such as silicon oxide or silicon nitride. The material of the metal interconnection layer 6 may be copper metal, aluminum metal, tungsten metal, or the like, which performs a fan-out function for the chip 1.
Referring to fig. 6, solder balls 7 are fabricated on the metal interconnection layer 6. And then, the temporary carrier plate S2 is peeled off, the plastic sealing layer 4 is cut, and the plastic sealing wafer is cut and diced into single packaging chips, as shown in fig. 7.
Referring to fig. 8, a thermal interface material layer 8 (TIM) is formed on the diamond 2 side of the molding compound of the chip, and the thermal interface material layer 8 is used to transfer heat between the diamond 2 and the molding compound 4. The main preparation materials of the thermal interface material TIM are as follows: aluminum nitride (AIN) or zinc oxide (ZnO), or aluminum oxide (Al) 2 O 3 ) Ceramic powder such as Boron Nitride (BN) or aluminum powder, and metal powder.
Referring to fig. 9, a heat sink 9 is bonded to the surface of the thermal interface material layer 8. The heat sink 9 is used to dissipate heat generated by the semiconductor device. The heat sink 9 typically has a fan-shaped structure, a column-shaped structure, or the like.
The obtained fan-out packaging structure based on the diamond substrate comprises a packaging body of a chip, the packaging body of the chip comprises a chip 1, diamond 2, a metal layer 3 and a plastic sealing layer 4, the chip 1 is provided with a welding disc surface and a back surface opposite to the welding disc surface, the welding disc surface is provided with a plurality of welding discs 1a and a first insulating layer 1b filled between the welding discs 1a, the diamond 2 is bonded with the back surface of the chip 1 through the metal layer 3, and the plastic sealing layer 4 coats the diamond 2 and the side surface of the chip 1. The diamond side of the packaging body is sequentially provided with a thermal interface material layer 8 and a radiator 9, one side of the chip bonding surface of the packaging body is provided with a rewiring structure and an external connection structure, the rewiring structure comprises a second insulating layer 5 and a metal interconnection layer 6 arranged in and on the second insulating layer 5, the metal interconnection layer 6 is connected with a bonding pad 1a of the chip 1 and the external connection structure, and the external connection structure is a structure of a solder ball 7. Therefore, heat generated by the chip 1 can rapidly outwards diffuse out through the diamond 2, the thermal interface material layer 8 and the radiator 9 on one side, fan-out packaging is realized through the rewiring structure on the bonding pad of the chip 1 on the other side, and the connecting solder balls are arranged outside the rewiring structure and are not influenced by the preamble processes such as diamond bonding, so that the number of I/O ports is increased, and the problem of damage of the bond diamond to the solder balls is avoided.
The above embodiments are only used to further illustrate a fan-out package structure based on a diamond substrate and a wafer level manufacturing process of the present invention, but the present invention is not limited to the embodiments, and any simple modification, equivalent variation and modification made to the above embodiments according to the technical substance of the present invention falls within the scope of the technical solution of the present invention.
Claims (9)
1. The wafer-level preparation process of the fan-out packaging structure based on the diamond substrate is characterized by comprising the following steps of:
step 1, a hot-press bonding process:
1.1, a chip to be packaged is provided with a welding disc surface and an opposite back surface, and a plurality of chips are bonded on a temporary carrier plate in a mode that the welding disc surface faces downwards;
1.2, respectively manufacturing metal layers on the back surface and the diamond surface of a chip to be packaged, aligning the diamond with the back surface of the chip one by one, and performing hot-press bonding through the metal layers to obtain a diamond-chip bonding body;
step 2, fan-out packaging technology:
2.1, carrying out plastic package on the diamond-chip bonding body on the temporary carrier plate, and thinning the plastic package layer to the surface of the exposed diamond to form a recombined wafer;
2.2, removing the temporary carrier plate on the welding disc surface of the chip, and forming another temporary carrier plate on one side of the diamond;
2.3, manufacturing a rewiring layer and an external connection structure on one side of the bonding pad surface of the chip;
2.4, removing the temporary carrier plate on one side of the diamond, and cutting and scribing to form single packaging chips;
2.5A thermal interface material layer and a heat sink are sequentially formed on one side of the diamond surface of the packaged chip.
2. The wafer level fabrication process of a diamond substrate based fan-out package structure of claim 1, wherein: the metal layer comprises an adhesion barrier layer and a bonding layer; the adhesion barrier layer is made of Ti, cr, ni, W, mo, zr, nb or one or more of carbon and nitride materials thereof; the bonding layer is In, au, ag, sn, cu, ni, al, ti, cr, pd, pt metal or alloy of several metals or soldering paste made of the metal.
3. The wafer level fabrication process of a diamond substrate based fan-out package structure of claim 2, wherein: the thickness of the adhesion barrier layer is 2 nm-50 mu m; the thickness of the bonding layer is 10 nm-200 mu m.
4. The wafer level fabrication process of a diamond substrate based fan-out package structure of claim 1, wherein: the metal layer is formed on the diamond surface and the back of the chip through sputtering, vapor plating, electroplating, chemical plating or printing processes.
5. The wafer level fabrication process of a diamond substrate based fan-out package structure of claim 1, wherein: the temperature of the hot-press bonding of the chip and the diamond is 20-500 ℃ and the pressure is 0-20 MPa.
6. The wafer level fabrication process of a diamond substrate based fan-out package structure of claim 1, wherein: total interface thermal resistance of bonding interface between chip and diamond<1mm 2 ·K/W。
7. The wafer level fabrication process of a diamond substrate based fan-out package structure of claim 1, wherein: step 2.3 in the fan-out packaging process comprises the following steps:
2.3.1 Patterning an insulating layer on one side of the chip bonding pad surface, wherein the insulating layer is provided with a first opening exposing the chip bonding pad;
2.3.2 Manufacturing a metal interconnection layer on the patterned insulating layer, wherein the metal interconnection layer is electrically connected with the chip bonding pad through the first opening;
2.3.3 Solder balls or bumps are manufactured on the metal interconnection layer to form an external connection structure.
8. The wafer level fabrication process of a diamond substrate based fan-out package structure of claim 1, wherein: the molding layer and the diamond have flush surfaces.
9. A fan-out packaging structure based on diamond substrate, its characterized in that: the chip packaging structure comprises a chip packaging body, wherein the chip packaging body comprises a chip, diamond, a metal layer and a plastic sealing layer, and the chip is provided with a welding disc surface and an opposite back surface; the diamond is bonded with the back of the chip through the metal layer; the plastic layer coats the side surfaces of the diamond and the chip; the diamond side of the packaging body is sequentially provided with a thermal interface material layer and a radiator, one side of the chip welding disc surface of the packaging body is provided with a rewiring structure and an external connection structure, the rewiring structure comprises a metal interconnection layer arranged in an insulating layer, and the metal interconnection layer is connected with a bonding pad of the chip and the external connection structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311034375.5A CN117038469A (en) | 2023-08-17 | 2023-08-17 | Fan-out packaging structure based on diamond substrate and wafer-level preparation process |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311034375.5A CN117038469A (en) | 2023-08-17 | 2023-08-17 | Fan-out packaging structure based on diamond substrate and wafer-level preparation process |
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| CN117038469A true CN117038469A (en) | 2023-11-10 |
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| CN202311034375.5A Pending CN117038469A (en) | 2023-08-17 | 2023-08-17 | Fan-out packaging structure based on diamond substrate and wafer-level preparation process |
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| CN (1) | CN117038469A (en) |
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