CN117034820B - Simulation verification method and device, electronic equipment and storage medium - Google Patents
Simulation verification method and device, electronic equipment and storage medium Download PDFInfo
- Publication number
- CN117034820B CN117034820B CN202311090920.2A CN202311090920A CN117034820B CN 117034820 B CN117034820 B CN 117034820B CN 202311090920 A CN202311090920 A CN 202311090920A CN 117034820 B CN117034820 B CN 117034820B
- Authority
- CN
- China
- Prior art keywords
- design
- tested
- reference design
- output
- target
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004088 simulation Methods 0.000 title claims abstract description 53
- 238000012795 verification Methods 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000013461 design Methods 0.000 claims abstract description 289
- 238000012360 testing method Methods 0.000 claims abstract description 134
- 230000005284 excitation Effects 0.000 claims abstract description 58
- 238000012216 screening Methods 0.000 claims description 35
- 230000015654 memory Effects 0.000 claims description 27
- 230000008859 change Effects 0.000 claims description 12
- 230000005540 biological transmission Effects 0.000 description 7
- 230000003247 decreasing effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000013178 mathematical model Methods 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000010295 mobile communication Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
Abstract
The invention relates to the technical field of digital simulation, and discloses a simulation verification method, a simulation verification device, electronic equipment and a storage medium, wherein the simulation verification method comprises the following steps: acquiring a to-be-tested design and a plurality of to-be-tested design parameters of the to-be-tested design; respectively establishing a corresponding reference design model for each to-be-tested design parameter; setting an input stimulus based on the current test requirements; broadcasting input excitation to each reference design model to obtain reference design output corresponding to each reference design model; the invention does not need to reconfigure a new parameter model or recompile when generating the new parameter model, avoids repeatedly establishing a test platform for many times, improves the reusability of the test platform, and further greatly improves the test efficiency.
Description
Technical Field
The invention relates to the technical field of digital simulation, in particular to a simulation verification method, a simulation verification device, electronic equipment and a storage medium.
Background
Digital simulation is the process of building a mathematical model of a load element and using the mathematical model to conduct experiments and studies on a digital computer. The implementation of digital simulation generally comprises three main steps of establishing a mathematical model, establishing a digital simulation model and simulating experiments. In the digital simulation stage, when the design to be tested DUT (Design under test) of the multi-parameter model needs to be tested, if the parameter models with different configurations need to be tested, the parameter parameters of the model to be tested of the DUT need to be changed to be realized, and a new parameter model can be created.
In the related art, the DUT is a static reference model after compiling is completed. Once a new parametric model is generated, the test environment needs to be reconfigured for the parametric model and recompilation is needed, i.e. one test environment can only correspond to, resulting in problems of low test efficiency and low reusability of the test platform.
Disclosure of Invention
In view of the above, the invention provides a simulation verification method, a simulation verification device, an electronic device and a storage medium, so as to solve the problems of low test efficiency and low reusability of a test platform.
In a first aspect, the present invention provides a simulation verification method, including:
Acquiring a to-be-tested design and a plurality of to-be-tested design parameters of the to-be-tested design;
Respectively establishing a corresponding reference design model for each to-be-tested design parameter;
Setting an input stimulus based on the current test requirements;
broadcasting input excitation to each reference design model to obtain reference design output corresponding to each reference design model;
And screening the reference design output based on the input excitation to obtain a target reference design output, wherein the target reference design output is used for representing the output of the design to be tested when the design to be tested parameter is the target design to be tested parameter.
According to the invention, the reference design model is built for the design parameters to be tested, the input excitation is set, the reference design output is obtained by broadcasting the input excitation to the reference design model, and screening is carried out based on the input excitation, so that what output is obtained by the design to be tested under the current design parameters to be tested, when a new parameter model is generated, reconfiguration and recompilation are not needed for the newly added parameter model, repeated building of a test platform is avoided, reusability of the test platform is improved, and further the test efficiency is greatly improved.
In an alternative embodiment, setting the input stimulus based on the current test requirements includes:
Determining an input excitation signal and a selection identifier based on the current test requirement, wherein the selection identifier is used for representing a target to-be-tested design parameter corresponding to the current test requirement;
And selecting the selection mark as a mark signal of the input excitation signal to obtain the input excitation.
In the mode, the selection identifier is added for the input excitation signal, so that the reference design output can be conveniently screened later, and the use experience of a user is further improved.
In an alternative embodiment, filtering the reference design output based on the input stimulus to obtain a target reference design output includes:
determining corresponding target design parameters to be tested based on the input excitation mark signals;
And screening the reference design output of the reference design model corresponding to the target design parameter to be tested to obtain the target reference design output.
In the mode, the reference actual model is screened by using the sign signals, so that the screening difficulty is further reduced, the configuration is closer to the user demand, and the use experience of the user is improved.
In an alternative embodiment, a simulation verification system includes: selecting a selector;
screening the reference design output of the reference design model corresponding to the target design parameter to be tested to obtain the target reference design output, comprising:
connecting each input end of the one-out-of-multiple selector with a reference design output end of the reference design model respectively;
and screening the reference design output of the reference design model corresponding to the target design parameter to be tested by using the one-out-of-many selector to obtain the target reference design output.
In the mode, the screening of the reference design output can be directly realized by adopting the one-out-of-many selector, more compiling processes are not needed, the use difficulty is reduced, and the use experience is improved.
In an alternative embodiment, after screening the reference design output based on the input stimulus to obtain the target reference design output, the method further comprises:
Judging whether to change the test configuration;
when the test configuration is changed, the design parameters to be tested are updated based on the changed test configuration, and the step of establishing a corresponding reference design model for each design parameter to be tested is returned.
In the mode, the design to be tested under different configurations is tested, only the design parameters to be tested are required to be updated, one test environment can correspond to the reference design models with various configurations, repeated compiling or changing of the test environment is not required, and the universality of the test platform is further improved.
In an alternative embodiment, updating the design parameters under test based on the modified test configuration includes:
Judging whether the changed test configuration is changed in the type of the design parameters to be tested;
When the type of the design parameters to be tested is changed in the changed test configuration, adding and/or deleting the design parameters to be tested according to the changed test configuration;
And updating the value of the design parameter to be tested based on the changed test configuration when the changed test configuration does not change the type of the design parameter to be tested.
In the mode, when the design parameters to be tested are increased or decreased, only the reference design model is required to be increased or decreased correspondingly, the test environment is not required to be reset, the test efficiency is improved, and meanwhile the problems that the coverage rate is low and the parameter transmission cannot be linked with the test case are solved.
In an alternative embodiment, all of the reference design models have the same test environment.
In the mode, the same test environment is used, test results of the reference design model corresponding to each design parameter to be tested after compiling are in parallel, so that the collection coverage rate is improved, and meanwhile, parameter transmission and linkage with a test case are realized.
In a second aspect, the present invention provides a simulation verification apparatus, the apparatus comprising:
the design acquisition module is used for acquiring a design to be tested and a plurality of design parameters to be tested of the design to be tested;
The model building module is used for building a corresponding reference design model for each parameter of the to-be-tested design respectively;
The excitation setting module is used for setting input excitation based on the current test requirement;
the excitation broadcasting module is used for broadcasting input excitation to each reference design model to obtain reference design output corresponding to each reference design model;
The target screening module is used for screening the reference design output based on the input excitation to obtain target reference design output, wherein the target reference design output is used for representing the output of the design to be tested when the design parameter to be tested is the target design parameter to be tested.
In a third aspect, the present invention provides an electronic device, comprising: the device comprises a memory and a processor, wherein the memory and the processor are in communication connection, the memory stores computer instructions, and the processor executes the computer instructions, so that the simulation verification method of the first aspect or any implementation mode corresponding to the first aspect is executed.
In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to perform the simulation verification method of the first aspect or any of its corresponding embodiments.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a simulation verification method according to an embodiment of the present invention.
FIG. 2 is a flow chart of another simulation verification method according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a simulation verification system according to an embodiment of the present invention.
FIG. 4 is a flow chart of yet another simulation verification method in accordance with an embodiment of the present invention.
Fig. 5 is a block diagram of a simulation verification apparatus according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the related art, the DUT is a static reference model after compiling is completed. Once a new parametric model is generated, the test environment needs to be reconfigured for the parametric model and recompilation is needed, i.e. one test environment can only correspond to, resulting in problems of low test efficiency and low reusability of the test platform.
In order to solve the above-mentioned problems, in the embodiments of the present application, a simulation verification method is provided for an electronic device, and it should be noted that an execution body of the simulation verification method may be a simulation verification device, and the simulation verification device may be implemented by software, hardware or a combination of software and hardware to form part or all of the electronic device, where the electronic device may be a terminal, a client, or a server, and the server may be a server, or may be a server cluster formed by multiple servers. In the following method embodiments, the execution subject is an electronic device.
The electronic device in the embodiment is suitable for use scenes of testing the design to be tested of the multi-parameter model in a digital simulation stage. According to the simulation verification method provided by the invention, the reference design model is built for the design parameters to be tested, the input excitation is set, the reference design output is obtained by broadcasting the input excitation to the reference design model, and screening is carried out based on the input excitation, so that the output of the design to be tested, which is required by the test, is obtained under the current design parameters to be tested, when a new parameter model is generated, reconfiguration and recompilation of the newly added parameter model are not needed, repeated building of a test platform is avoided, reusability of the test platform is improved, and further the test efficiency is greatly improved.
In accordance with an embodiment of the present invention, a simulated verification method embodiment is provided in which the steps shown in the flowchart of the drawings may be performed in a computer system, such as a set of computer-executable instructions, and, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in an order other than that shown or described herein.
In this embodiment, a simulation verification method is provided, which may be used in the above electronic device, and fig. 1 is a flowchart of the simulation verification method according to an embodiment of the present invention, as shown in fig. 1, where the flowchart includes the following steps:
Step S101, a design to be tested and a plurality of design parameters to be tested of the design to be tested are obtained.
In one example, the design under test is a multi-parameter model, with different configurations being tested by varying the design parameters under test.
Step S102, respectively establishing a corresponding reference design model for each parameter to be tested.
In an example, the reference design model may include designs under test under different design parameters under test.
Step S103, setting input stimulus based on the current test requirement.
In one example, the input stimulus may be a random value or a fixed value, without limitation in the present invention.
Step S104, the input excitation is broadcast to each reference design model, and the reference design output corresponding to each reference design model is obtained.
In one example, the same input stimulus is replicated into a plurality of identical input stimuli, and the identical input stimuli are sent to the reference design models for testing at the same time, so that reference design outputs corresponding to each reference design model are obtained.
Step S105, screening the reference design output based on the input excitation to obtain a target reference design output.
In the embodiment of the invention, the target reference design output is used for representing the output of the design to be tested when the design to be tested parameter is the target design to be tested parameter.
According to the simulation verification method provided by the embodiment, the reference design model is built for the design parameters to be tested, the input excitation is set, the reference design output is obtained by broadcasting the input excitation to the reference design model, and screening is carried out based on the input excitation, so that the output of the design to be tested, which is required by testing, is obtained under the current design parameters to be tested, when a new parameter model is generated, reconfiguration and recompilation of the newly added parameter model are not needed, repeated establishment of a testing platform is avoided, reusability of the testing platform is improved, and testing efficiency is greatly improved.
In this embodiment, a simulation verification method is provided, which may be used in the above electronic device, and fig. 2 is a flowchart of another simulation verification method according to an embodiment of the present invention, as shown in fig. 2, where the flowchart includes the following steps:
Step S201, a design to be tested and a plurality of design parameters to be tested of the design to be tested are obtained. Please refer to step S101 in the embodiment shown in fig. 1 in detail, which is not described herein.
Step S202, respectively establishing a corresponding reference design model for each parameter to be tested. Please refer to step S102 in the embodiment shown in fig. 1 in detail, which is not described herein.
Step S203, setting an input stimulus based on the current test requirement.
Specifically, the step S203 includes:
Step S2031, based on the current test requirement, determines an input excitation signal and a selection identifier, where the selection identifier is used to characterize a target to-be-tested design parameter corresponding to the current test requirement.
Step S2032, obtaining the input excitation by using the selection flag as the flag signal of the input excitation signal.
In one example, the input stimulus is a signal input while testing the design under test, which may be a random or fixed value for testing the design under test. By broadcasting the input stimulus to the input port of each DUT, one input stimulus signal is replicated into multiple copies of the same input stimulus, and simultaneously sent to multiple reference design models for invocation.
In the mode, the selection identifier is added for the input excitation signal, so that the reference design output can be conveniently screened later, and the use experience of a user is further improved.
Step S204, the input excitation is broadcasted to each reference design model to obtain the reference design output corresponding to each reference design model. Please refer to step S104 in the embodiment shown in fig. 1 in detail, which is not described herein.
Step S205, screening the reference design output based on the input excitation to obtain a target reference design output.
Specifically, the step S205 includes:
Step S2051, determining a corresponding target design parameter to be tested based on the input excitation flag signal.
Step S2052, screening the reference design output of the reference design model corresponding to the target design parameter to be tested, and obtaining the target reference design output.
In some alternative embodiments, a simulated verification system includes: one more selector.
The step S2022 includes:
step a1, connecting each input end of the selector with the reference design output end of the reference design model.
And a2, screening the reference design output of the reference design model corresponding to the target design parameter to be tested by using a multiple-choice selector to obtain the target reference design output.
In one example, FIG. 3 is a schematic diagram of a simulation verification system in accordance with an embodiment of the present invention. As shown in fig. 3, before the digital simulation phase, a TOP file dut_top is created in advance, which contains the following parts:
1. And calling the DUT to be tested with different parameters by using different parameters parameter to be tested in the TOP file DUT_TOP, and configuring different parameters to be tested in the calling process.
2. The input stimulus is broadcast to the input port of each DUT. In FIG. 3, one input stimulus is replicated as four identical input stimuli, e.g., CASE_0, CASE_1, etc., and addressed to the invoked 4 reference design models simultaneously.
3. And adding a mux selector, wherein the selector selects the DUT output of the test target to be tested corresponding to the input excitation at the output ports of the DUTs_0 to DUT_N according to the mux mark signal attached to the input excitation. The mux select one selector in fig. 3 is a select one-four selector, which performs one-four selection on the outputs of the four reference design models, and selects the outputs of the target reference design models required for testing in the corresponding reference design models of the first four different design parameters to be tested, parameter_0 through parameter_n, by inputting the mux select identification in the stimulus.
In the mode, the design to be tested under different configurations is tested, only the design parameters to be tested are required to be updated, one test environment can correspond to the reference design models with various configurations, repeated compiling or changing of the test environment is not required, and the universality of the test platform is further improved.
According to the simulation verification method provided by the embodiment, the selection identifier is added for the input excitation signal, so that the reference design output can be conveniently screened later, and the user experience is further improved. The marking signals are used for screening the reference actual model, so that the screening difficulty is further reduced, the configuration of the user requirements is more similar, and the use experience of the user is improved. The design to be tested under different configurations is tested, only the design parameters to be tested are required to be updated, one test environment can correspond to the reference design models with various configurations, repeated compiling or changing of the test environment is not required, and the universality of the test platform is further improved.
In this embodiment, a simulation verification method is provided, which may be used in the above electronic device, and fig. 4 is a flowchart of the simulation verification method according to an embodiment of the present invention, as shown in fig. 4, where the flowchart includes the following steps:
Step S401, a design to be tested and a plurality of design parameters to be tested of the design to be tested are obtained. Please refer to step S201 in the embodiment shown in fig. 2 in detail, which is not described herein.
Step S402, respectively establishing a corresponding reference design model for each parameter to be tested. Please refer to step S202 in the embodiment shown in fig. 2, which is not described herein.
Step S403, setting input stimulus based on current test requirement. Please refer to step S203 in the embodiment shown in fig. 2 in detail, which is not described herein.
Step S404, broadcasting the input excitation to each reference design model to obtain the reference design output corresponding to each reference design model. Please refer to step S204 in the embodiment shown in fig. 2 in detail, which is not described herein.
Step S405, filtering the reference design output based on the input excitation to obtain a target reference design output. Please refer to step S205 in the embodiment shown in fig. 2 in detail, which is not described herein.
In an alternative embodiment, all of the reference design models have the same test environment.
In the mode, the same test environment is used, test results of the reference design model corresponding to each design parameter to be tested after compiling are in parallel, so that the collection coverage rate is improved, and meanwhile, parameter transmission and linkage with a test case are realized.
Specifically, after the above step S405, the simulation verification method further includes:
step S406, it is determined whether to change the test configuration.
Step S407, when the test configuration is changed, the design parameters to be tested are updated based on the changed test configuration, and the step of establishing corresponding reference design models for each design parameter to be tested is returned.
In an example, other configured parameter models are tested, and only a new use case is needed in the DUT_TOP layer, so that a test environment can correspond to the parameter models with various configurations, and only MUX marks are needed to be modified to select the required DUT output, thereby improving the universality of a test platform.
In the mode, the design to be tested under different configurations is tested, only the design parameters to be tested are required to be updated, one test environment can correspond to the reference design models with various configurations, repeated compiling or changing of the test environment is not required, and the universality of the test platform is further improved.
Specifically, after the above step S407, the simulation verification method further includes:
Step S408, determining whether the modified test configuration is changed in the type of the design parameter to be tested.
Step S409, when the modified test configuration changes the type of the design parameter to be tested, adding and/or deleting the design parameter to be tested according to the modified test configuration.
In step S410, when the modified test configuration does not change the type of the design parameter to be tested, the value of the design parameter to be tested is updated based on the modified test configuration.
In one example, the DUT_TOP configures the parameter, uses the same DUT and the same test environment, improves the test efficiency, and solves the problems of coverage rate and failure in parameter transmission to link with the test case.
In the mode, when the design parameters to be tested are increased or decreased, only the reference design model is required to be increased or decreased correspondingly, the test environment is not required to be reset, the test efficiency is improved, and meanwhile the problems that the coverage rate is low and the parameter transmission cannot be linked with the test case are solved.
According to the simulation verification method provided by the embodiment, the design to be tested under different configurations is tested, only the design parameters to be tested are required to be updated, one test environment can correspond to the reference design models with various configurations, repeated compiling or changing of the test environment is not required, and the universality of the test platform is further improved. When the design parameters to be tested are increased or decreased, only the reference design model is required to be correspondingly increased or decreased, the test environment is not required to be reset, the test efficiency is improved, and meanwhile the problems that the coverage rate is low and the parameter transmission cannot be linked with the test case are solved. By using the same test environment, the test results of the reference design model corresponding to each design parameter to be tested after compiling exist in parallel, so that the collection coverage rate is improved, and meanwhile, the parameter transmission and the linkage with the test case are realized.
In this embodiment, a simulation verification device is further provided, and the device is used to implement the foregoing embodiments and preferred embodiments, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The present embodiment provides a simulation verification apparatus, as shown in fig. 5, including:
The design obtaining module 501 is configured to obtain a design to be tested and a plurality of design parameters to be tested of the design to be tested. Please refer to step S101 in the embodiment shown in fig. 1 in detail, which is not described herein.
The model building module 502 is configured to build a corresponding reference design model for each parameter of the to-be-tested design respectively. Please refer to step S102 in the embodiment shown in fig. 1 in detail, which is not described herein.
A stimulus setting module 503 for setting an input stimulus based on the current test requirement; please refer to step S103 in the embodiment shown in fig. 1 in detail, which is not described herein.
And the excitation broadcasting module 504 is configured to broadcast the input excitation to each reference design model, so as to obtain a reference design output corresponding to each reference design model. Please refer to step S104 in the embodiment shown in fig. 1 in detail, which is not described herein.
The target screening module 505 is configured to screen the reference design output based on the input excitation, to obtain a target reference design output, where the target reference design output is used to characterize the output of the design to be tested when the design to be tested parameter is the target design to be tested parameter. Please refer to step S105 in the embodiment shown in fig. 1 in detail, which is not described herein.
In some alternative embodiments, the incentive setting module 503 includes:
the identification determining unit is used for determining an input excitation signal and a selection identification based on the current test requirement, and the selection identification is used for representing a target to-be-tested design parameter corresponding to the current test requirement;
and the input excitation determining unit is used for taking the selection mark as a mark signal of the input excitation signal to obtain the input excitation.
In some alternative embodiments, the target screening module 505 includes:
The target parameter determining unit is used for determining corresponding target design parameters to be detected based on the input excitation sign signals;
And the output screening unit is used for screening the reference design output of the reference design model corresponding to the target design parameter to be tested to obtain the target reference design output.
In some alternative embodiments, a simulated verification system includes: selecting a selector;
the output screening unit includes:
The input/output connection subunit is used for respectively connecting each input end of the one-out-of-multiple selector with a reference design output end of the reference design model;
and the output screening subunit is used for screening the reference design output of the reference design model corresponding to the target design parameter to be tested by utilizing the one-out-of-many selector to obtain the target reference design output.
In some alternative embodiments, the emulation verification device further comprises:
the configuration change judging module is used for judging whether to change the test configuration;
And the parameter updating module is used for updating the design parameters to be tested based on the changed test configuration when the test configuration is changed, and returning to the step of respectively establishing a corresponding reference design model for each design parameter to be tested.
In some alternative embodiments, the method comprises:
The parameter type change judging module is used for judging whether the changed test configuration has the change of the type of the design parameters to be tested;
the parameter increasing and decreasing module is used for increasing and/or deleting the design parameters to be tested according to the changed test configuration when the changed test configuration shows the change of the type of the design parameters to be tested;
And the value updating module is used for updating the value of the design parameter to be tested based on the changed test configuration when the changed test configuration does not change the type of the design parameter to be tested.
In some alternative embodiments, all of the reference design models have the same test environment. Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.
The simulation verification apparatus in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application SPECIFIC INTEGRATED Circuit) Circuit, a processor and a memory that execute one or more software or firmware programs, and/or other devices that can provide the above functions.
The embodiment of the invention also provides electronic equipment, which is provided with the simulation verification device shown in the figure 5.
Referring to fig. 6, fig. 6 is a schematic structural diagram of an electronic device according to an alternative embodiment of the present invention, as shown in fig. 6, the electronic device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the electronic device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple electronic devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 6.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods shown in implementing the above embodiments.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the electronic device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The electronic device also includes a communication interface 30 for the electronic device to communicate with other devices or communication networks.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (9)
1. A simulation verification method applied to a simulation verification system, the method comprising:
Acquiring a to-be-tested design parameter and a plurality of to-be-tested design parameters of the to-be-tested design;
respectively establishing a corresponding reference design model for each design parameter to be tested;
Setting an input stimulus based on the current test requirements;
Broadcasting the input excitation to each reference design model to obtain reference design output corresponding to each reference design model;
Screening the reference design output based on the input excitation to obtain a target reference design output, wherein the target reference design output is used for representing the output of the design to be tested when the design to be tested parameter is a target design to be tested parameter; the step of screening the reference design output based on the input excitation to obtain a target reference design output includes: determining corresponding target design parameters to be tested based on the input excitation sign signals; and screening the reference design output of the reference design model corresponding to the target design parameter to be tested to obtain target reference design output.
2. The method of claim 1, wherein setting the input stimulus based on the current test requirement comprises:
Determining an input excitation signal and a selection identifier based on the current test requirement, wherein the selection identifier is used for representing a target to-be-tested design parameter corresponding to the current test requirement;
and taking the selection mark as a mark signal of the input excitation signal to obtain input excitation.
3. The method of claim 1, wherein the simulation verification system comprises: selecting a selector;
The step of screening the reference design output of the reference design model corresponding to the target design parameter to be tested to obtain the target reference design output comprises the following steps:
Connecting each input end of the one-out-of-multiple selector with a reference design output end of the reference design model respectively;
and screening the reference design output of the reference design model corresponding to the target design parameter to be tested by using the one-out-of-many selector to obtain target reference design output.
4. A method according to any one of claims 1-3, wherein after said screening of said reference design output based on said input stimuli to obtain a target reference design output, said method further comprises:
Judging whether to change the test configuration;
When the test configuration is changed, updating the design parameters to be tested based on the changed test configuration, and returning to the step of establishing a corresponding reference design model for each design parameter to be tested.
5. The method of claim 4, wherein updating the design parameters under test based on the modified test configuration comprises:
Judging whether the changed test configuration is changed in the type of the design parameters to be tested;
When the type of the design parameters to be tested is changed in the changed test configuration, adding and/or deleting the design parameters to be tested according to the changed test configuration;
And updating the value of the design parameter to be tested based on the changed test configuration when the changed test configuration does not change the type of the design parameter to be tested.
6. A method according to any of claims 1-3, characterized in that all reference design models have the same test environment.
7. A simulation verification apparatus, the apparatus comprising:
The design acquisition module is used for acquiring a to-be-tested design and a plurality of to-be-tested design parameters of the to-be-tested design;
The model building module is used for building a corresponding reference design model for each design parameter to be tested;
The excitation setting module is used for setting input excitation based on the current test requirement;
the excitation broadcasting module is used for broadcasting the input excitation to each reference design model to obtain reference design output corresponding to each reference design model;
The target screening module is used for screening the reference design output based on the input excitation to obtain target reference design output, wherein the target reference design output is used for representing the output of the design to be tested when the design parameter to be tested is the target design parameter to be tested; the step of screening the reference design output based on the input excitation to obtain a target reference design output includes: determining corresponding target design parameters to be tested based on the input excitation sign signals; and screening the reference design output of the reference design model corresponding to the target design parameter to be tested to obtain target reference design output.
8. An electronic device, comprising:
A memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the simulated authentication method of any of claims 1 to 6.
9. A computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the simulation verification method of any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311090920.2A CN117034820B (en) | 2023-08-28 | 2023-08-28 | Simulation verification method and device, electronic equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311090920.2A CN117034820B (en) | 2023-08-28 | 2023-08-28 | Simulation verification method and device, electronic equipment and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117034820A CN117034820A (en) | 2023-11-10 |
| CN117034820B true CN117034820B (en) | 2024-06-07 |
Family
ID=88643019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311090920.2A Active CN117034820B (en) | 2023-08-28 | 2023-08-28 | Simulation verification method and device, electronic equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117034820B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021000188A1 (en) * | 2019-06-30 | 2021-01-07 | 瑞声声学科技(深圳)有限公司 | Method and apparatus for presenting motor information, and computer device |
| CN113312879A (en) * | 2021-07-28 | 2021-08-27 | 北京燧原智能科技有限公司 | Chip circuit function verification system, method, device and storage medium |
| CN114139475A (en) * | 2021-12-07 | 2022-03-04 | 上海西井信息科技有限公司 | Chip verification method, system, device and storage medium |
| CN115543797A (en) * | 2022-09-28 | 2022-12-30 | 山东工商学院 | Bus conversion bridge verification method, device, equipment and storage medium based on UVM |
| CN115562982A (en) * | 2022-09-28 | 2023-01-03 | 平头哥(上海)半导体技术有限公司 | Reference model debugging method and device, electronic equipment and storage medium |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20220019894A (en) * | 2020-08-10 | 2022-02-18 | 삼성전자주식회사 | Simulation method for semiconductor manufacturing process and method for manufacturing semiconductor device |
-
2023
- 2023-08-28 CN CN202311090920.2A patent/CN117034820B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021000188A1 (en) * | 2019-06-30 | 2021-01-07 | 瑞声声学科技(深圳)有限公司 | Method and apparatus for presenting motor information, and computer device |
| CN113312879A (en) * | 2021-07-28 | 2021-08-27 | 北京燧原智能科技有限公司 | Chip circuit function verification system, method, device and storage medium |
| CN114139475A (en) * | 2021-12-07 | 2022-03-04 | 上海西井信息科技有限公司 | Chip verification method, system, device and storage medium |
| CN115543797A (en) * | 2022-09-28 | 2022-12-30 | 山东工商学院 | Bus conversion bridge verification method, device, equipment and storage medium based on UVM |
| CN115562982A (en) * | 2022-09-28 | 2023-01-03 | 平头哥(上海)半导体技术有限公司 | Reference model debugging method and device, electronic equipment and storage medium |
Non-Patent Citations (1)
| Title |
|---|
| 标准单元工艺参数提取工具的设计及实现;李训根;罗小华;;微电子学与计算机;20070605(第06期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117034820A (en) | 2023-11-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113312879B (en) | Chip circuit function verification system, method, device and storage medium | |
| CN109302522B (en) | Test method, test device, computer system, and computer medium | |
| CN109582525B (en) | Test code verification method, verification device, equipment and storage medium | |
| CN111159049B (en) | Automatic interface testing method and system | |
| KR101414079B1 (en) | Networked test system | |
| US9772918B2 (en) | Method for connecting an input/output interface of a testing device equipped for testing a control unit | |
| CN107797004B (en) | Digital verification system and method for spacecraft electrical performance test case | |
| CN112541313B (en) | Method and device for configuring trigger expression for logic analysis state | |
| CN114780326B (en) | Cross-platform calibration test method, device and equipment | |
| CN105404574B (en) | Smart card and mobile terminal consistency test method and device | |
| CN115184764A (en) | Chip testing method and device, electronic equipment and storage medium | |
| CN114124694A (en) | Configuration method and configuration device of Internet of things equipment, electronic equipment and medium | |
| CN113376514B (en) | FPGA chip testing method, device, system and storage medium | |
| CN115794641A (en) | Method, device and equipment for making number based on business process and storage medium | |
| CN106201852A (en) | A kind of distributed test method and test system | |
| US20050154949A1 (en) | System for flexible embedded Boundary Scan testing | |
| CN117034820B (en) | Simulation verification method and device, electronic equipment and storage medium | |
| CN109885327A (en) | A kind of method and device upgrading CPLD | |
| CN111506501B (en) | Method and device for generating test instruction set and electronic equipment | |
| CN104679648A (en) | Cross-application automatic testing method | |
| CN116090252A (en) | Matlab-based method, device, equipment and medium for automatically generating input interface model | |
| CN115442266A (en) | Gateway performance testing method and device, storage medium and electronic device | |
| CN108802600A (en) | A kind of integrated circuit verification system and method based on FPGA | |
| CN111294250B (en) | Pressure testing method, device and system | |
| CN112328439A (en) | Stability test method and system for hardware equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |