CN117033301A - Architecture system integrating calculation and storage - Google Patents
Architecture system integrating calculation and storage Download PDFInfo
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- CN117033301A CN117033301A CN202311056953.5A CN202311056953A CN117033301A CN 117033301 A CN117033301 A CN 117033301A CN 202311056953 A CN202311056953 A CN 202311056953A CN 117033301 A CN117033301 A CN 117033301A
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- 238000012545 processing Methods 0.000 claims abstract description 13
- 230000002457 bidirectional effect Effects 0.000 claims abstract description 5
- 238000009432 framing Methods 0.000 claims abstract description 4
- 230000003993 interaction Effects 0.000 claims abstract description 4
- 238000013461 design Methods 0.000 claims abstract description 3
- 238000007726 management method Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 7
- 238000013500 data storage Methods 0.000 claims description 5
- 238000012795 verification Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 2
- 230000004927 fusion Effects 0.000 abstract description 5
- 230000005540 biological transmission Effects 0.000 description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7821—Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The application relates to the technical field of aerospace, and provides a computing and storage integrated design architecture system, which comprises: the processor system is used for calculating and processing the received load information and load data of the aircraft through the processor chip; the memory system is used for framing and storing load data and load information through the memory chip, so that read-write control and bad block management of the second memory chip are realized; and the bridging system is used for connecting the processor system and the memory system to realize bidirectional interaction of the load information of the processor system and the load data and the load information and the load data between the memory system. The application can effectively reduce the weight of the whole aircraft, realize the backup of the data of the memory system with special requirements, and simultaneously improve the fusion calculation capability of the space aircraft system and the on-orbit reconstruction capability of the processor system and the memory system.
Description
Technical Field
The application relates to the technical field of aerospace, in particular to a computing and storage integrated architecture system.
Background
In the design and development of an aerospace vehicle, a space-borne computer realizes tasks such as satellite attitude management and control, on-board telemetry, remote control, program control, high-capacity data management, bus management and the like, and along with the diversity and complexity of the tasks, the aerospace vehicle is required to have high flight orbit, high maneuverability and high processing performance, and the requirements of low weight, high calculation performance, high throughput, high-capacity storage, management and the like are provided for the space-borne computer.
At present, for the processor system and the memory system of the spacecraft, which are two independent physical single machines, the processor system performs data calculation processing, the memory system performs data storage, the cost is high, and the using process is redundant.
Disclosure of Invention
The application aims to provide a calculation and storage integrated architecture system which solves the requirements of high calculation performance, high throughput, large-capacity storage and management of a spaceborne computer of an aerospace vehicle.
To achieve the above object, an object of the present application is to provide a computing and storage integrated architecture system, including:
the processor module is used for calculating and processing the received load information and load data of the aircraft through the processor chip;
the memory module is used for framing and storing the load data and the load information through the memory chip, and the memory module is used for realizing read-write control and bad block management of the second memory chip;
and the bridging module is used for connecting the processor module and the memory module to realize bidirectional interaction of the load information and the load data of the processor module and the load information and the load data of the memory module.
Preferably, the processor module further comprises:
after the processor chip on the processor module receives the clock signal sent by the trigger, the first programmable device operates and processes the load data and the load information in the first memory chip through the internal bus isolation driving circuit and the logic circuit.
Preferably, the first memory chip is mainly used for storing programs, the payload data and the payload information.
Preferably, the memory module includes:
the processor module refreshes the memory module at regular time through the bridging module in a normal state and a power-off state, and the regular refreshing process is that the second programmable device realizes the on-rail reconstruction capability of the aircraft through a regular refreshing chip.
Preferably, the memory module further comprises: and the second programmable device performs read-write control and bad block management on the load data and the load information of the second memory chip device.
Preferably, the second memory chip stores the payload data, the payload information and the verification information.
Preferably, the operation and processing of the load data by the processor module in the normal state includes:
the memory module further comprises a power-on reset circuit, the power-on reset circuit resets the timing refreshing chip after the memory module is powered on, and data of a second memory chip is loaded, wherein the timing refreshing chip performs timing refreshing operation on the second memory chip, the load data and the load information stored in the memory module can be constantly maintained, and the memory module is used as a load single-machine data storage medium to store the load data and the load information.
Preferably, the operation and processing of the load data by the processor module in the power-off state includes:
the processor module reads the current state of the memory module, and after the memory system is powered up, the processor module can transmit the processed data back to the memory module through the bridging module, so that the load data and the load information are backed up.
Preferably, the memory module not only can be used as the load data and the load information storage medium to store the load data and the load information, but also can be used as an extended hard disk of the processor module, and the memory module is accessed through the bridging module to read the load data and the load information for fusion calculation.
Preferably, the bridge module connects the processor module and the memory module, and further includes:
the processor module transmits control signals and clock signals to the memory module through the control bus to read and write the load information and the load data, and transmits the address information of the memory module through the address bus, and transmits the load information and the load data through the data bus after finding out the address information.
Compared with the prior art, the application has the beneficial effects that:
the application provides a computing and storage integrated architecture system, which adopts a bridging module to establish a high-speed data transmission channel between a processor module and a memory module, wherein the processor module can write data into the memory module through the bridging module, and can read any storage space in the memory module to ensure that external input data received by the memory module can be used for fusion computation and other operations of the processor module.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate the application and together with the embodiments of the application, serve to explain the application.
In the drawings:
FIG. 1 is a block diagram of a computing and storage architecture system in accordance with the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments, and that a skilled person may use different methods for each step to achieve the described functions, but such implementation should not be considered to be beyond the scope of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The technical definition related to the embodiment of the application is as follows:
1. a Static Random-Access Memory (SRAM) is one type of Random Access Memory. By "static", it is meant that such memory is constantly maintained for data stored therein as long as it remains powered on. In contrast, data stored in Dynamic Random Access Memory (DRAM) needs to be periodically updated. However, when the power supply is stopped, the data stored in the SRAM is lost (referred to as a volatile memory), unlike a ROM or a flash memory which can store data after power is turned off.
2. A programmable read-only memory (PROM or FPROM) is a computer memory chip, each bit of which determines the data content by the state of a fuse or antifuse. Such a memory is used for permanent storage procedures. PROM differs from narrow ROM (Mask ROM) in that the former can be written as needed after IC fabrication is completed, and the latter is fabricated at the time of lC fabrication-and inside.
3. The charged erasable programmable read-only memory (Electrically Erasable Programmable read only memory, EEPROM) is a memory chip that does not lose data after power failure. The EEPROM may be reprogrammed by erasing the existing information on a computer or on a dedicated device. Typically for plug-and-play applications.
4. The field programmable gate array (Field Programmable Gate Aray, FPGA) is a product of further development based on programmable devices such as PAL (programmable array logic), GAL (general array logic) and the like. The FPGA logic is realized by loading programming data into an internal static memory unit, the value stored in the memory unit determines the logic function of the logic unit and the connection mode between each module or between the module and I/O, and finally determines the functions which can be realized by the FPGA, and the FPGA allows infinite programming.
5. The 1553B data bus has bidirectional output characteristics, high instantaneity and reliability, and main hardware parts comprise a Bus Controller (BC), a Remote Terminal (RT) and an optional Bus Monitor (BM). Typically, these 3 parts are done through 1 Multiplexed Bus Interface (MBI). The MBI may be embedded within a computer for transmission of data.
Examples
The application aims to provide a calculation and storage integrated architecture system, and the method provided by the application can effectively reduce the weight of the whole aircraft, realize the backup of special-demand memory system data, and simultaneously improve the fusion calculation capacity of a spacecraft system and the on-orbit reconstruction capacity of a processor system and a memory system.
Referring to fig. 1, the present embodiment provides a specific embodiment of a computing and storage integrated architecture system, and the specific procedure is as follows:
the processor module is used for calculating and processing the received load information and load data of the aircraft through the processor chip;
the memory module is used for framing and storing load data and load information through the memory chip, and the memory module realizes read-write control and bad block management of the second memory chip, specifically, in the embodiment, the memory module adopts a processing architecture of an FPGA+SDRAM cache, the second memory chip comprises the FPGA as a main control chip, the SDRAM is used as a data cache medium, the FLASH realizes external data storage, and the MRAM is used for storing loop blocks and check information and timing refreshing operation;
more preferably, the FPGA chip adopts XQR V3000-4CG717V of XILINX company or BQR V3000 chip of Beijing microelectronic technology institute; the SDRAM chip adopts a 3D PLUSE 3DSD1G32VS2490SSA75M chip or an European VDSD1G32RS70SS2V75 chip; the FLASH chip adopts a 3D PLUSE 3DFN128G08VS8308SSA00M chip or an European VDFN128G08RS50MS8V25 chip; the MRAM chip adopts 3D PLUSE 3DMR4M08VS4428SSA40M or Europe VDMR4M08RS44SS4V35 chip.
And the bridging module is used for connecting the processor module and the memory module to realize bidirectional interaction of the load information and the load data of the processor module and the load information and the load data between the memory modules.
Preferably, the processor module further comprises:
the processor chip receives the clock signal sent by the trigger, and then the driving circuit and the logic circuit are isolated through the internal bus, the first programmable device operates and processes the load data and the load information in the first memory chip, specifically, in this embodiment, the processor module mainly comprises a processor chip, the first programmable device is mainly an FPGA chip, the first memory chip is mainly an SRAM chip, a PROM chip, an eerom chip, and further comprises a 1553B bus interface chip.
More preferably, the processor chip employs a TSC695F-25SASV device from ATMEL company; the FPGA chip adopts an anti-fuse FPGA chip with high single event upset resistance of Actel company; the SRAM chip adopts a 3DSR16M32CS4511SSA15M device of 3D PLUSE company or a VDSR16M32RS64MS4C12 device of European bit company; PROM chip adopts XQR V16CC44V of XILINX company or B17V16RH device of beijing microelectronics technical institute; the EEPROM chip adopts 3D PLUSE 3DEE8M32CS8163SSA00M or Europe VDEE8M32RS64MS8C250 device.
Preferably, the first memory chip mainly stores programs, load data and load information, specifically, in this embodiment, the processor module uniformly addresses a system memory space, an I/O space and an expansion space according to a chip selection line and an address line expansion module, where the processor chip implements operation, control and management operations of the load data and load information, the external SRAM space is used as a program space and a data space to perform uniform mapping of the memory, and the PROM chip stores a monitor program and the EEPROM chip stores an application program.
Preferably, the memory module includes:
the processor module regularly refreshes the memory module through the bridge module in a normal state and a power-off state, and the process of regularly refreshing is that the second programmable device realizes the on-rail reconstruction capability of the aircraft through the regularly refreshing chip, specifically, in the embodiment, the second programmable device is an FPGA (field programmable gate array) as a main control chip, and the regularly refreshing chip adopts a special regularly refreshing chip BSV2CQRH of Beijing microelectronics research institute to regularly refresh.
Preferably, the memory module further comprises: the second programmable device performs read-write control and bad block management on the load data and load information of the second memory chip device, specifically, in this embodiment, the FPGA uses MRAM for storing the loop block and the verification information.
Preferably, the second memory chip stores payload data, payload information, and verification information.
Preferably, the operation and processing of the load data by the processor module in the normal state includes:
the memory module further comprises a power-on reset circuit, the power-on reset circuit resets the timing refreshing chip after the memory module is powered on, and loads data of the second memory chip, wherein the timing refreshing chip performs timing refreshing operation on the second memory chip, load data and load information stored in the memory module can be constantly kept, and the memory module is used as a load single-machine data storage medium to store the load data and the load information. The power-on reset circuit resets the BSV2CQRH chip, loads the memory module FPGA chip XQR V3000 after the reset is completed, and the BSV2CQRH chip performs timing refresh operation on XQR V3000 when the FPGA loading is completed.
Preferably, the operation and processing of the load data by the processor module in the power-off state includes:
the processor module reads the current state of the memory module, after the memory module is powered up, the processor module can transmit the processed data back to the memory module through the bridge module to realize backup of load data and load information, specifically, in the embodiment, when the aircraft is in an emergency state and needs an emergency state, the processor module reads the current state of the memory module through the bridge module to store, and after the power up is completed, the processor module can transmit the needed data back to the memory module through the bridge module to complete the backup.
Preferably, the memory module can be used as a load data and load information storage medium to store load data and load information, and can be used as an expansion hard disk of the processor module to access the memory module through the bridging module to read the load data and the load information for fusion calculation.
Preferably, the bridge module connects the processor module and the memory module, and further comprises:
the processor module carries out read-write control of load information and load data on the memory module through a control bus transmission control signal and a clock signal, the processor module transmits address information of the memory module through an address bus, and the processor module transmits the load information and the load data through a data bus after finding the address information.
Preferably, the processor module obtains the address information of the memory module through the address bus, transmits the control signal and the clock signal through the control bus after finding the relevant address information and transmits the control signal and the clock signal to the memory module through the bridge module, sets the Ha lt signal of the refresh chip BSV2CQRH to be effective, and the refresh chip BSV2CQRH stops working, and loads the memory module main control FPGA chip XQR V3000 through the control bus connected with the bridge module, and transmits the load information and the load data.
Finally, it should be noted that: the above is only a preferred embodiment of the present application, and the present application is not limited thereto, but it is to be understood that the present application is described in detail with reference to the foregoing embodiments, and modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. A computing and storage integrated architecture system, comprising:
the processor module is used for calculating and processing the received load information and load data of the aircraft through the processor chip;
the memory module is used for framing and storing the load data and the load information through the memory chip, and the memory module is used for realizing read-write control and bad block management of the second memory chip;
and the bridging module is used for connecting the processor module and the memory module to realize bidirectional interaction of the load information and the load data of the processor module and the load information and the load data of the memory module.
2. The computing and storage integrated architecture system of claim 1, wherein the processor module further comprises:
after the processor chip on the processor module receives the clock signal sent by the trigger, the first programmable device operates and processes the load data and the load information in the first memory chip through the internal bus isolation driving circuit and the logic circuit.
3. The computing and storage integrated architecture system of claim 2, wherein the first memory chip is configured to store programs, the payload data, and the payload information.
4. The computing and storage integrated design architecture system of claim 1, wherein the memory module comprises:
the processor module refreshes the memory module at regular time through the bridging system in a normal state and a power-off state, and the regular refreshing process is that the second programmable device realizes the on-rail reconstruction capability of the aircraft through a regular refreshing chip.
5. The computing and storage integrated architecture system of claim 4, wherein the memory module further comprises: and the second programmable device performs read-write control and bad block management on the load data and the load information of the second memory chip device.
6. The computing and storage integrated architecture system of claim 5, wherein the second memory chip stores the payload data, the payload information, and the verification information.
7. The integrated computing and storage architecture system of claim 4, wherein the processor module operating and processing the payload data under normal conditions comprises:
the memory module further comprises a power-on reset circuit, the power-on reset circuit resets the timing refreshing chip after the memory module is powered on, and data of a second memory chip is loaded, wherein the timing refreshing chip performs timing refreshing operation on the second memory chip, the load data and the load information stored in the memory module can be constantly maintained, and the memory module is used as a load single-machine data storage medium to store the load data and the load information.
8. The integrated computing and storage architecture system of claim 4, wherein the processor module operating and processing the payload data in a power-down state comprises:
the processor module reads the current state of the memory module, and after the memory module is powered up, the processor system can transmit the processed data back to the memory module through the bridging system, so that the load data and the load information are backed up.
9. The architecture system with integrated computation and storage according to claim 1, wherein the memory module is capable of storing the load data and the load information as the load data and the load information storage medium, and is capable of being used as an extended hard disk of the processor module, and the memory module is accessed through the bridge module, and the load data and the load information are read and fused for computation.
10. The computing and storage integrated architecture system of claim 1, wherein the bridge module connects the processor module and the memory module, further comprising:
the processor module transmits control signals and clock signals to the memory module through the control bus to read and write the load information and the load data, and transmits the address information of the memory module through the address bus, and transmits the load information and the load data through the data bus after finding out the address information.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311056953.5A CN117033301A (en) | 2023-08-21 | 2023-08-21 | Architecture system integrating calculation and storage |
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| CN202311056953.5A CN117033301A (en) | 2023-08-21 | 2023-08-21 | Architecture system integrating calculation and storage |
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