CN116995067A - On-chip inductor structure and manufacturing method thereof - Google Patents
On-chip inductor structure and manufacturing method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Coils Or Transformers For Communication (AREA)
Abstract
An on-chip inductor structure and a method of fabricating the same, the method of fabricating the same, after providing a substrate, forms a first magnetic layer on a surface of the substrate; forming an inductor on a surface of the intermediate portion of the first magnetic layer; forming a polymer coating over the first magnetic layer; providing an imprinting template, wherein the imprinting template is provided with an imprinting groove which is inwards concave from the lower surface of the imprinting module, and the inner wall of the imprinting groove at least comprises a first part and a second part which surrounds the first part and is connected with the first part, the first part is provided with an arc-shaped surface, and the second part is provided with a flat surface; imprinting the imprinting template on the surface of the polymer coating, and patterning the polymer coating to form a patterned polymer coating; a second magnetic layer is formed on the patterned polymer coating surface. The method well and precisely controls the thickness of the magnetic flux hole between the upper surface of the edge portion of the first magnetic layer and the lower surface of the second magnetic layer formed directly above the edge portion.
Description
Technical Field
The application relates to the field of semiconductors, in particular to an on-chip inductor structure and a manufacturing method thereof.
Background
Inductors are the main components of microelectronic circuits such as switching regulators, radio Frequency (RF) circuits, and electromagnetic interference (electro magnetic interference, EMI) mitigation circuits. As microelectronic devices continue to move toward higher levels of integration and complexity, it becomes important to achieve high inductance within small-sized microelectronic devices. The inductor must be integrated on-die or in-package (on-package) to achieve high performance circuits, but the performance of existing on-die inductor structures remains to be improved.
Disclosure of Invention
Some embodiments of the present application provide a method for manufacturing an on-chip inductor structure, including:
providing a substrate;
forming a first magnetic layer on a surface of the substrate, the first magnetic layer including a middle portion and an edge portion surrounding and connected to the middle portion;
forming an inductor on a surface of the intermediate portion of the first magnetic layer, the inductor including at least one wire line;
forming a polymer coating over the first magnetic layer covering the inductor;
providing an imprint template, wherein the imprint template is provided with an inward concave imprint groove from the lower surface of an imprint module, the inner wall of the imprint groove at least comprises a first part and a second part which surrounds the first part and is connected with the first part, the depth of the first part is larger than that of the second part, the first part is provided with an arc-shaped surface, and the second part is provided with a flat surface;
imprinting the imprinting template on the surface of the polymer coating, patterning the polymer coating to form a patterned polymer coating, wherein the position of a first part of the imprinting template corresponds to the position of a middle part of the first magnetic layer when imprinting is performed, the position of a second part of the imprinting template corresponds to the position of an edge part of the first magnetic layer, and the patterned polymer coating comprises a flat part positioned on the surface of the edge part of the first magnetic layer and a convex part positioned on the surface of the middle part of the first magnetic layer;
a second magnetic layer is formed on the patterned polymer coating surface.
In some embodiments, the imprinting the imprint template onto the surface of the polymer coating further comprises denaturing or curing the polymer coating with a curing means that is either heated and pressurized, or heated, pressurized and uv irradiated, or pressurized and uv irradiated.
In some embodiments, pressure is applied to the imprint template while the imprint template is imprinted on the surface of the polymer coating, and the thickness of the flat portion of the patterned polymer coating is adjusted by adjusting the magnitude of the applied pressure.
In some embodiments, the imprinting technique for imprinting the imprint template onto the surface of the polymer coating includes one or a combination of several of thermal nanoimprinting, ultraviolet nanoimprinting, or microcontact printing.
In some embodiments, the material of the imprint template is polydimethyl-oxy-alkane, perfluoroalkyl polyether, polyurethane acrylate.
In some embodiments, the material of the polymeric coating is polymethyl methacrylate, polyimide, pyrrole resin, or cyclic olefin copolymer; the polymer coating forming process includes spin coating process, spray coating process, physical vapor deposition or chemical vapor deposition.
In some embodiments, the inductor is a spiral inductor or a linear inductor, and when the inductor is a spiral inductor, the wire line is one and spiral; when the inductor is a linear inductor, at least two wire lines are arranged, and at least two wire lines are parallel to each other.
In some embodiments, further comprising: forming a first dielectric layer on a surface of the first magnetic layer before forming an inductor on a surface of a middle portion of the first magnetic layer; a second dielectric layer is formed on the patterned polymer coating surface prior to forming a second magnetic layer on the patterned polymer coating surface.
In some embodiments, the first magnetic layer and the second magnetic layer are each a stacked structure in which magnetic thin film layers and spacers are alternately stacked.
Some embodiments of the application also provide an on-chip inductor structure comprising:
a substrate;
a first magnetic layer on a surface of the substrate, the first magnetic layer including a middle portion and an edge portion surrounding and connected to the middle portion;
an inductor located on a surface of the intermediate portion of the first magnetic layer, the inductor including at least one wire line;
a patterned polymer coating on the first magnetic layer and covering the inductor, the patterned polymer coating including a flat portion on an edge portion surface of the first magnetic layer and a convex portion on a middle portion surface of the first magnetic layer, the patterned polymer coating being formed by imprinting an imprinting stencil on a surface of the polymer coating, the imprinting stencil having an imprinting groove recessed inward from a lower surface of the imprinting module, an inner wall of the imprinting groove including at least a first portion and a second portion surrounding and connected to the first portion, and a depth of the first portion being greater than a depth of the second portion, the first portion having an arcuate surface, the second portion having a flat surface, and a position of the first portion of the imprinting stencil corresponding to a position of the middle portion of the first magnetic layer when imprinting is performed, a position of the second portion of the imprinting stencil corresponding to a position of the edge portion of the first magnetic layer;
a second magnetic layer on the patterned polymer coating surface.
In some embodiments, the pressure is applied to the imprint template while the imprint template is imprinted on the surface of the polymer coating, and the thickness of the flat portion of the patterned polymer coating is adjusted by adjusting the magnitude of the applied pressure.
In some embodiments, the material of the imprint template is polydimethyl-oxy-alkane, perfluoroalkyl polyether, polyurethane acrylate; the patterned polymer coating is made of polymethyl methacrylate, polyimide, pyrrole resin or cycloolefin copolymer.
In some embodiments, the inductor is a spiral inductor or a linear inductor, and when the inductor is a spiral inductor, the wire line is one and spiral; when the inductor is a linear inductor, at least two wire lines are arranged, and at least two wire lines are parallel to each other.
In some embodiments, further comprising: a first dielectric layer on the surface of the first magnetic layer, and the inductor is on the surface of the first dielectric layer; a second dielectric layer positioned between the patterned polymer coating and the second magnetic layer.
In some embodiments, the first magnetic layer and the second magnetic layer are each a stacked structure in which magnetic thin film layers and spacers are alternately stacked.
The on-chip inductor structure and the manufacturing method thereof in the foregoing embodiments of the present application, the manufacturing method forming a first magnetic layer on a surface of a substrate after providing the substrate, the first magnetic layer including a middle portion and an edge portion surrounding and connected to the middle portion; forming an inductor on a surface of the intermediate portion of the first magnetic layer, the inductor including at least one wire line; forming a polymer coating over the first magnetic layer covering the inductor; providing an imprint template, wherein the imprint template is provided with an inward concave imprint groove from the lower surface of an imprint module, the inner wall of the imprint groove at least comprises a first part and a second part which surrounds the first part and is connected with the first part, the depth of the first part is larger than that of the second part, the first part is provided with an arc-shaped surface, and the second part is provided with a flat surface; imprinting the imprinting template on the surface of the polymer coating, patterning the polymer coating to form a patterned polymer coating, wherein the position of a first part of the imprinting template corresponds to the position of a middle part of the first magnetic layer when imprinting is performed, the position of a second part of the imprinting template corresponds to the position of an edge part of the first magnetic layer, and the patterned polymer coating comprises a flat part positioned on the surface of the edge part of the first magnetic layer and a convex part positioned on the surface of the middle part of the first magnetic layer; a second magnetic layer is formed on the patterned polymer coating surface. Patterning the polymer coating by imprinting the imprinting stencil on the surface of the polymer coating to form a patterned polymer coating, wherein the imprinting stencil is provided with an imprinting groove which is concave inwards from the lower surface of the imprinting module, the inner wall of the imprinting groove at least comprises a first part and a second part which surrounds the first part and is connected with the first part, the depth of the first part is larger than that of the second part, the first part is provided with an arc-shaped surface, the second part is provided with a flat surface, so that after imprinting, the patterned polymer coating comprises a flat part positioned on the surface of the edge part of the first magnetic layer and a convex part positioned on the surface of the middle part of the first magnetic layer, the thickness of the flat part of the patterned polymer coating can be well controlled, the thickness of a magnetic flux hole between the upper surface of the edge part of the first magnetic layer and the lower surface of the second magnetic layer which is formed right above the edge part is well and precisely controlled, and the magnetic path is easy to form a magnetic path, the magnetic path is greatly reduced, the saturation effect is greatly reduced, and the magnetic path is greatly the magnetic path is saturated when the magnetic path is greatly reduced; moreover, the radian of the surface of the convex part of the patterned polymer coating can be well and accurately controlled by the radian of the second part of the embossing module, so that the radian of the surface of the convex part of the formed polymer coating can be more gentle, and when the second magnetic layer is formed on the polymer coating later, the coverage rate and thickness uniformity of the second magnetic layer formed on the surface of the convex part of the polymer coating are improved, the thickness of the second magnetic layer formed on the surface of the convex part of the polymer coating at a certain position is prevented from being too thin, and the position reaches the saturation magnetic flux density earlier than other positions, so that the inductor is saturated, and the inductance of the inductor is influenced.
Drawings
Fig. 1-14 are schematic diagrams illustrating a fabrication process of an on-chip inductor structure according to some embodiments of the present application.
Detailed Description
The following describes the embodiments of the present application in detail with reference to the drawings. In describing embodiments of the present application in detail, the schematic drawings are not necessarily to scale and are merely illustrative and should not be taken as limiting the scope of the application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
Some embodiments of the present application first provide a method for manufacturing an on-chip inductor structure, and the foregoing method is described in detail with reference to the accompanying drawings.
Referring to fig. 1, a substrate is provided.
In some embodiments, the base plate includes a semiconductor substrate 22 and an interlayer dielectric layer 24 on a surface of the semiconductor substrate 22.
In some specific embodiments, the material of the semiconductor substrate 22 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide. The semiconductor substrate 22 may also be implanted with certain dopant ions to alter electrical parameters according to design requirements. The semiconductor substrate 22 is further formed with a shallow trench isolation structure (not shown in the figure), where the shallow trench isolation structure is used for isolating adjacent active regions, and the material of the shallow trench isolation structure may be one or more of silicon oxide, silicon nitride, and silicon oxynitride. A semiconductor device is formed in and/or on the active region, the semiconductor device including one or more of a transistor, a resistor, a capacitor, and a diode.
In some embodiments, an interconnect structure 26 is also formed in the interlevel dielectric layer 24 (or in the dielectric layer 24 and on the dielectric layer 24). In a specific embodiment, the interconnect structure 26 includes a metal line, or includes a metal line and a conductive plug connected to the metal line.
In some embodiments, the interlayer dielectric layer 24 may be a single-layer or multi-layer stacked structure, and the corresponding interconnect structure 26 may be a single-layer or multi-layer stacked structure, where each of the interconnect structures is formed in and on the interlayer dielectric layer of the corresponding layer. The material of the interlayer dielectric layer 24 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, carbon, FSG (fluorine doped silicon dioxide), BSG (boron doped silicon dioxide), PSG (phosphorus doped silicon dioxide), BPSG (boron phosphorus doped silicon dioxide) or low dielectric constant (K is less than 2.5). The material of the interconnection structure 26 is one or more of Al, cu, ag, au, pt, ni, ti, tiN, taN, ta, taC, W and WN.
In some embodiments, the substrate further comprises: and a passivation layer 28 formed on the surface of the interlayer dielectric layer 24.
In some embodiments, referring to fig. 2, an underlayer dielectric layer 28 is formed on a portion of the surface of the passivation layer 26 (or the substrate), the underlayer dielectric layer 28 being used for electrical isolation between the subsequently formed first magnetic layer and the substrate. The underlying dielectric layer 28 may be one or more of silicon nitride, silicon carbide, silicon oxide, or silicon oxynitride, and the underlying dielectric layer 28 may be formed by a process including Atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD).
Referring to fig. 3 and 4, a first magnetic layer 30 is formed on a surface of the substrate, the first magnetic layer 30 including a middle portion 11 and an edge portion 12 surrounding the middle portion 11 and connected to the middle portion 11.
The first magnetic layer 30 and the second magnetic layer 46 (refer to fig. 12) formed later form a magnetic shell to encapsulate the later formed inductor, and a continuous magnetic circuit is formed or magnetic coupling is generated between the first magnetic layer 32 and the second magnetic layer 46, so that a wire line in the inductor between the first magnetic layer 32 and the second magnetic layer 46 acts, and the inductance of the inductor is increased.
In some embodiments, the forming of the first magnetic layer 30 includes: forming a first magnetic layer 30 (refer to fig. 3) on the surfaces of the underlayer dielectric layer 28 and the passivation layer 26; the first magnetic layer 30 is patterned to remove the first magnetic layer 30 outside the underlying dielectric layer 28, leaving the first magnetic layer 30 on the surface of the underlying dielectric layer 28.
The first magnetic layer 30 may have a single-layer structure or a multi-layer stacked structure composed of a magnetic material.
In some embodiments, when the first magnetic layer 30 is a multi-layer stacked structure, the first magnetic layer 30 is a stacked structure in which magnetic thin film layers and spacer layers are alternately stacked, and the material of the magnetic thin film layers is a nanocrystalline magnetic alloy or an amorphous magnetic alloy, which may be CoZrTa, coZrTaB, niFe, coP, feBN, coZrO, etc., formed by copper Physical Vapor Deposition (PVD) or the like. The material of the spacer layer may be silicon oxide, cobalt oxide, etc., and is formed by a deposition process such as Physical Vapor Deposition (PVD) or an oxidation process such as plasma oxidation and thermal oxidation. The thickness of the spacer layer is typically 5-10% of the thickness of the magnetic thin film layer.
In other embodiments, the first magnetic layer 30 is a multi-layer stacked structure, and the first magnetic layer 30 is a stacked structure in which magnetic thin film layers of different magnetic materials are alternately stacked, and in a specific embodiment, the first magnetic layer 30 is a stacked structure in which first magnetic thin film layers and second magnetic thin film layers are alternately stacked, and the materials of the first magnetic thin film layers and the second magnetic thin film layers are different magnetic materials.
The first magnetic layer 30 includes a middle portion 11 and an edge portion 12, the edge portion 12 is annular and surrounds the middle portion 11, an inductor is subsequently formed on the middle portion 11 of the first magnetic layer 30, and the thickness of the polymer coating subsequently formed on the edge portion 12 of the first magnetic layer 30 determines the thickness of the smallest magnetic via between the first magnetic layer 30 and the subsequently formed second magnetic layer 46 (refer to fig. 12).
In some embodiments, referring to fig. 5, a first dielectric layer 32 is formed on the surface of the first magnetic layer 30 (and the surface of the passivation layer 26).
The first dielectric layer 32 is used for electrical isolation between the subsequently formed inductor and the first magnetic layer 30. The first dielectric layer 32 on the surface of the first magnetic layer 30 has a flat surface.
In some embodiments, the first dielectric layer 32 material may be a polymer, and specifically may be Polyimide (PI), polybenzoxazole (PBO), or the like. In other embodiments, the first dielectric layer 32 may also be an inorganic dielectric material, and specifically may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride.
Referring to fig. 6, 7 and 8, an inductor 38 is formed on the surface of the intermediate portion 11 of the first magnetic layer 30, the inductor 38 including at least one wire line.
In this embodiment, the inductor 38 is formed on the surface of the first dielectric layer 32 on the surface of the first magnetic layer 30. In other embodiments, the inductor 38 may be formed directly on the surface of the first magnetic layer 30.
In some embodiments, the inductor 38 is formed by a process comprising: forming a seed layer 34 (refer to fig. 6) on the surface of the first dielectric layer 32, wherein the seed layer 34 is formed by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or the like, and the material of the seed layer 34 may be copper, titanium, or the like, or an alloy thereof, or a combination of metals; forming a mask layer 36 (see fig. 7) over the seed layer 34, the mask layer 36 having an opening therein exposing a portion of the surface of the seed layer 34, the shape and location of the opening defining the shape and location of the inductor 38 formed; filling a conductive material in the opening by adopting an electroplating process to form an inductor 38, wherein the inductor 38 at least comprises a wire line, and the conductive material can be copper, titanium, nickel, gold and other metals and alloys thereof or a combination of a plurality of metals; the mask layer and the seed layer on both sides of the wire line are removed (refer to fig. 8).
The inductor 38 is a spiral inductor or a wire inductor, and in some embodiments, when the inductor 38 is a spiral inductor, the wire line is one and spiral; in other embodiments, when the inductor 38 is a linear inductor, at least two of the conductive lines are parallel to each other, and two conductive lines in the inductor 38 are illustrated in fig. 8 as an example.
Referring to fig. 9, a polymer coating 40 is formed on the first magnetic layer 30 to cover the inductor 38.
The polymer coating 40 is subsequently used to form a patterned polymer coating, the topography of the patterned polymer coating surface determines the topography and thickness uniformity of the subsequently formed second magnetic layer, and the thickness of the patterned polymer coating formed on the edge portion 12 of the first magnetic layer 30 determines the thickness of the smallest magnetic via between the first magnetic layer 30 and the subsequently formed second magnetic layer 46 (see fig. 12).
The material of the polymer coating 40 is a thermoplastic or ultraviolet plastic polymer, or a thermosetting or ultraviolet curing polymer, the polymer coating 40 is in a liquid state at normal temperature or by heating, and has high shape plasticity, so that after the imprint template is imprinted on the surface of the polymer coating 40, the polymer coating 40 is denatured or cured by using a specific curing means, thereby reproducing a structural pattern on the imprint template on the polymer coating 40, thereby realizing patterning of the polymer coating 40, by using the specific means, the thickness H1 (refer to fig. 13) of the patterned polymer coating 40 formed on the edge portion 12 of the first magnetic layer 30 can be well and accurately controlled, thereby well and accurately controlling the thickness H2 (refer to fig. 14) of a magnetic flux hole between the upper surface of the edge portion 12 of the first magnetic layer 30 and the lower surface of the second magnetic layer 46 formed directly above the edge portion 12, preventing the magnetic flux hole from being easily generated when the thickness H2 of the magnetic through hole is excessively small, greatly reducing the saturation effect of the magnetic through hole, and greatly reducing the magnetic gap from being generated in the inductor, or greatly reducing the magnetic path loss, and greatly reducing the inductor magnetic path inductance.
In some embodiments, the material of the polymer coating 40 may be polymethyl methacrylate (PMMA), polyimide (PI), pyrrole resin, or cyclic olefin Copolymer (COP), or the like. The polymer coating 40 is formed by a process including spin coating, spray coating, physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD).
In some embodiments, the specific curing means is heat and pressure, or heat, pressure, and ultraviolet light, or pressure, and ultraviolet light.
In some embodiments, the polymer coating 40 covers the substrate surface outside of the first magnetic layer 30 in addition to covering the inductor 38 on the first magnetic layer 30.
Referring to fig. 10 and 11, an imprint template 42 is provided, the imprint template 42 having therein an imprint groove recessed inward from a lower surface of the imprint module 42, an inner wall of the imprint groove including at least a first portion 13 and a second portion 14 surrounding the first portion 13 and connected to the first portion 13, and a depth of the first portion 13 being greater than a depth of the second portion 014, the first portion 13 having an arcuate surface, the second portion 14 having a flat surface; imprinting the imprint template 42 on the surface of the polymer coating 40, patterning the polymer coating to form a patterned polymer coating 40, and performing the imprinting with the first portion 13 of the imprint template 42 in a position corresponding to the position of the intermediate portion 11 of the first magnetic layer 30 and the second portion 14 of the imprint template 42 in a position corresponding to the position of the edge portion 12 of the first magnetic layer 30, the patterned polymer coating 40 comprising the flat portion 17 on the surface of the edge portion 12 of the first magnetic layer 30 and the raised portion 16 on the surface of the intermediate portion 11 of the first magnetic layer 30; after the patterned polymer coating 40 is formed, the imprint template 42 is removed.
The shape of the imprint grooves in the imprint template 42 is exactly the inverse of the shape of the surface of the patterned polymer coating 40.
The imprint template 42 has an imprint groove recessed inward from the lower surface of the imprint module 42, the inner wall of the imprint groove includes at least a first portion 13 and a second portion 14 surrounding the first portion 13 and connected to the first portion 13, and the depth of the first portion 13 is greater than the depth of the second portion 014, the first portion 13 has an arc-shaped surface, and the second portion 14 has a flat surface, so that after imprinting, the patterned polymer coating 40 includes a flat portion 17 located on the surface of the edge portion 12 of the first magnetic layer 30 and a raised portion 16 located on the surface of the middle portion 11 of the first magnetic layer 30, so that the thickness H1 (refer to fig. 13) of the flat portion 17 forming the patterned polymer coating 40 can be well controlled, thereby well and precisely controlling the thickness H2 of the magnetic path between the upper surface of the edge portion 12 of the first magnetic layer 30 and the lower surface of the second magnetic layer 46 formed immediately above the edge portion 12, and thus reducing the saturation effect of the magnetic path, and reducing the magnetic path loss, or reducing the magnetic path saturation effect, and the magnetic path loss, in the case of the magnetic path 2 is greatly reduced, the magnetic path thickness H2 is greatly reduced; moreover, the curvature of the surface of the raised portion 16 of the patterned polymer coating 40 can be well and precisely controlled by the curvature of the second portion 13 of the imprint module 42, so that the curvature of the surface of the raised portion 16 of the patterned polymer coating 40 can be relatively gentle (the inclination angle is less than 50 degrees, and may be specifically 30-45 degrees), and the coverage and thickness uniformity of the second magnetic layer formed on the surface of the raised portion 16 of the patterned polymer coating 40 are improved when the second magnetic layer is subsequently formed on the polymer coating 40, so that the thickness of the second magnetic layer 46 (refer to fig. 12) formed on the surface of the raised portion 16 of the patterned polymer coating 40 is prevented from being too thin at a certain position, so that the saturation magnetic flux density is reached earlier than at other positions, and the inductor 38 is saturated, thereby affecting the inductance of the inductor 38.
In some embodiments, pressure is applied to the imprint template 42 while the imprint template 42 is imprinted on the surface of the polymer coating 40, and the thickness of the flat portion 17 of the patterned polymer coating 40 is adjusted by adjusting the magnitude of the applied pressure.
In an embodiment, the inner wall of the embossing groove of the embossing master 42 may further include a third portion 15 connected to the second portion 14 and surrounding the second portion 14, the third portion 15 having a depth smaller than that of the second portion 14, and the third portion 15 having an inclined surface, and the third portion 15 is located at a position corresponding to a position of a side surface of the first magnetic layer 30 when embossing, so that the patterned polymer coating 40 may be uniformly coated on the side surface of the first magnetic layer 30, so that the subsequently formed second magnetic layer may also be uniformly coated on the surface of the polymer coating 40 on the side surface of the first magnetic layer 30, thereby further improving the performance of forming the on-chip inductor structure.
In some embodiments, the material of the imprint template 42 is polydimethyl-oxy-alkane, perfluoroalkyl polyether, polyurethane acrylate.
In some embodiments, the imprinting technique for imprinting the imprint template 42 onto the surface of the polymer coating 40 includes one or a combination of thermal nanoimprinting, ultraviolet nanoimprinting, or microcontact printing. In some embodiments, the imprinting the imprint template 42 onto the surface of the polymer coating 40 further comprises denaturing or curing the polymer coating 40 with a curing means that is either heated and pressurized, or heated, pressurized and ultraviolet irradiated, or pressurized and ultraviolet irradiated. The pressurization for the curing means and the pressurization for imprinting the imprint template 42 on the surface of the polymer coating 40 may be the same pressurization or different pressurization.
Referring to fig. 12, a second magnetic layer 46 is formed on the surface of the patterned polymer coating 40.
In some embodiments, the second magnetic layer 46 is formed directly on the surface of the patterned polymer coating 40. In other embodiments, the second dielectric layer 44 is formed on the surface of the patterned polymer coating 40 prior to forming the second magnetic layer 46. In some embodiments, the purpose of forming first dielectric layer 32 and second dielectric layer 44 is to increase the dielectric constant of the material between second magnetic layer 46 and first magnetic layer 30.
In some embodiments, further comprising: a third dielectric layer 48 is formed on the surface of the second magnetic layer 46.
The materials and formation processes of the second dielectric layer 44 and the third dielectric layer 48 are the same as those of the first dielectric layer 32. The material and forming process of the second magnetic layer 46 are the same as those of the first magnetic layer 30.
The second magnetic layer 46 is formed to blanket over the first magnetic layer 30, and the second magnetic layer 46 has a length greater than the length of the first magnetic layer 30.
The distance between the upper surface of the edge portion 12 of the first magnetic layer 30 and the lower surface of the second magnetic layer 46 formed directly above the edge portion 12 is the thickness H2 of the magnetic via (refer to fig. 14), the thickness H2 of the magnetic via directly affects the overall performance of the on-chip inductor, when the thickness H2 of the magnetic via is too small, a magnetic saturation phenomenon is easy to occur, when the thickness H2 of the magnetic via is too large, a large air gap is generated in the magnetic circuit, and although hysteresis loss and saturation effect are significantly reduced, self inductance is reduced or inductance of the inductor is reduced. The patterned polymer coating is formed by the method, so that the thickness H1 (refer to fig. 13) of the flat portion 17 of the patterned polymer coating 40 can be well controlled, thereby well and precisely controlling the thickness H2 (refer to fig. 14) of the magnetic flux hole between the upper surface of the edge portion 12 of the first magnetic layer 30 and the lower surface of the second magnetic layer 46 formed right above the edge portion 12, preventing the magnetic saturation phenomenon from being easily generated when the thickness H2 of the magnetic flux hole is too small, and generating a large air gap in the magnetic circuit when the thickness H2 of the magnetic flux hole is too large, and reducing the self-inductance or the inductance of the inductor although remarkably reducing the hysteresis loss and saturation effect, thereby improving the overall performance of the formed on-chip inductor structure.
Some embodiments of the present application also provide an on-chip inductor structure, referring to fig. 12 and 11 in combination, comprising:
a substrate;
a first magnetic layer 30 on a surface of the substrate, the first magnetic layer 30 including a middle portion 11 and an edge portion 12 surrounding the middle portion 11 and connected to the middle portion 11;
an inductor 38 located on a surface of the intermediate portion 11 of the first magnetic layer 30, the inductor 38 comprising at least one wire line;
a patterned polymer coating 40 on the first magnetic layer 30 and covering the inductor 38, the patterned polymer coating 40 comprising a flat portion 17 on a surface of the edge portion 12 of the first magnetic layer 30 and a convex portion 16 on a surface of the middle portion 11 of the first magnetic layer 30, the patterned polymer coating 40 being formed by imprinting an imprinting stamp 42 on the surface of the polymer coating, the imprinting stamp 42 having an imprinting groove recessed inward from a lower surface of the imprinting module, an inner wall of the imprinting groove comprising at least a first portion 13 and a second portion 14 surrounding the first portion 13 and connected to the first portion 13, and a depth of the first portion 13 being greater than a depth of the second portion 14, the first portion 13 having an arcuate surface, the second portion 14 having a flat surface, and a position of the first portion 13 of the imprinting stamp 42 corresponding to a position of the middle portion 11 of the first magnetic layer 30 when imprinting is performed, the second portion 42 having an inner wall including at least a first portion 13 and a second portion 14 surrounding the first portion 13 and having a depth greater than a depth of the second portion 14, the first portion 14 having a position of the imprinting stamp 30 corresponding to a position of the middle portion 12 of the imprinting stamp;
a second magnetic layer 46 on the surface of the patterned polymer coating 40.
In some embodiments, the pressure is applied to the imprint template 42 while the imprint template 42 is imprinted on the surface of the polymer coating, and the thickness of the flat portion 17 of the patterned polymer coating 40 is adjusted by adjusting the magnitude of the applied pressure.
In some embodiments, the material of the imprint template 42 is polydimethyl-oxy-alkane, perfluoroalkyl polyether, polyurethane acrylate; the material of the patterned polymer coating 40 is polymethyl methacrylate, polyimide, pyrrole resin or cyclic olefin copolymer.
In some embodiments, the inductor 38 is a spiral inductor or a wire inductor, and when the inductor 38 is a spiral inductor, the wire line is one and spiral; when the inductor 38 is a linear inductor, at least two wire lines are provided, and at least two wire lines are parallel to each other.
In some embodiments, further comprising: a first dielectric layer 32 on a surface of the first magnetic layer 30, the inductor 38 being on a surface of the first dielectric layer 32; a second dielectric layer 44 positioned between the patterned polymer coating 40 and the second magnetic layer 46.
In some embodiments, the first magnetic layer 30 and the second magnetic layer 46 are stacked structures in which magnetic thin film layers and spacers are alternately stacked.
It should be noted that the terms "comprising" and "having" and variations thereof herein are intended to cover a non-exclusive inclusion. The terms "first," "second," and the like are used to distinguish similar objects and not necessarily to describe a particular order or sequence unless otherwise indicated by context, it should be understood that the data so used may be interchanged where appropriate. In addition, the embodiments of the present application and the features in the embodiments may be combined with each other without collision. In addition, in the above description, descriptions of well-known components and techniques are omitted so as to not unnecessarily obscure the present application. In the foregoing embodiments, each embodiment is mainly described for the differences from the other embodiments, and the same/similar parts between the embodiments need to be referred to (or referred to) each other.
Although the present application has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present application by using the methods and technical matters disclosed above without departing from the spirit and scope of the present application, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present application are within the scope of the technical matters of the present application.
Claims (15)
1. A method of fabricating an on-chip inductor structure, comprising:
providing a substrate;
forming a first magnetic layer on a surface of the substrate, the first magnetic layer including a middle portion and an edge portion surrounding and connected to the middle portion;
forming an inductor on a surface of the intermediate portion of the first magnetic layer, the inductor including at least one wire line;
forming a polymer coating over the first magnetic layer covering the inductor;
providing an imprint template, wherein the imprint template is provided with an inward concave imprint groove from the lower surface of an imprint module, the inner wall of the imprint groove at least comprises a first part and a second part which surrounds the first part and is connected with the first part, the depth of the first part is larger than that of the second part, the first part is provided with an arc-shaped surface, and the second part is provided with a flat surface;
imprinting the imprinting template on the surface of the polymer coating, patterning the polymer coating to form a patterned polymer coating, wherein the position of a first part of the imprinting template corresponds to the position of a middle part of the first magnetic layer when imprinting is performed, the position of a second part of the imprinting template corresponds to the position of an edge part of the first magnetic layer, and the patterned polymer coating comprises a flat part positioned on the surface of the edge part of the first magnetic layer and a convex part positioned on the surface of the middle part of the first magnetic layer;
a second magnetic layer is formed on the patterned polymer coating surface.
2. The method of claim 1, wherein imprinting the imprint template onto the surface of the polymer coating further comprises denaturing or curing the polymer coating with a curing means that is either heated and pressurized, or heated, pressurized and uv-illuminated, or pressurized and uv-illuminated.
3. The method of manufacturing an on-chip inductor structure according to claim 1 or 2, wherein a pressure is applied to the imprint template when the imprint template is imprinted on the surface of the polymer coating, and the thickness of the flat portion of the patterned polymer coating is adjusted by adjusting the magnitude of the applied pressure.
4. The method of manufacturing an on-chip inductor structure according to claim 1 or 2, wherein the imprinting technique of imprinting the imprint template on the surface of the polymer coating comprises one or a combination of several of thermal nanoimprinting, uv nanoimprinting or microcontact printing.
5. The method of manufacturing an on-chip inductor structure according to claim 4, wherein the imprint template is made of polydimethyl-oxy-alkane, perfluoroalkyl polyether, polyurethane acrylate.
6. The method of fabricating an on-chip inductor structure according to claim 1, wherein the material of the polymer coating is polymethyl methacrylate, polyimide, pyrrole resin or cyclic olefin copolymer; the polymer coating forming process includes spin coating process, spray coating process, physical vapor deposition or chemical vapor deposition.
7. The method of manufacturing an on-chip inductor structure according to claim 1, wherein the inductor is a spiral inductor or a linear inductor, and when the inductor is a spiral inductor, the wire line is one and spiral; when the inductor is a linear inductor, at least two wire lines are arranged, and at least two wire lines are parallel to each other.
8. The method of fabricating an on-chip inductor structure of claim 1, further comprising:
forming a first dielectric layer on a surface of the first magnetic layer before forming an inductor on a surface of a middle portion of the first magnetic layer; a second dielectric layer is formed on the patterned polymer coating surface prior to forming a second magnetic layer on the patterned polymer coating surface.
9. The method of manufacturing an on-chip inductor structure according to claim 1, wherein the first magnetic layer and the second magnetic layer are stacked structures in which magnetic thin film layers and spacer layers are alternately stacked.
10. An on-chip inductor structure, comprising:
a substrate;
a first magnetic layer on a surface of the substrate, the first magnetic layer including a middle portion and an edge portion surrounding and connected to the middle portion;
an inductor located on a surface of the intermediate portion of the first magnetic layer, the inductor including at least one wire line;
a patterned polymer coating on the first magnetic layer and covering the inductor, the patterned polymer coating including a flat portion on an edge portion surface of the first magnetic layer and a convex portion on a middle portion surface of the first magnetic layer, the patterned polymer coating being formed by imprinting an imprinting stencil on a surface of the polymer coating, the imprinting stencil having an imprinting groove recessed inward from a lower surface of the imprinting module, an inner wall of the imprinting groove including at least a first portion and a second portion surrounding and connected to the first portion, and a depth of the first portion being greater than a depth of the second portion, the first portion having an arcuate surface, the second portion having a flat surface, and a position of the first portion of the imprinting stencil corresponding to a position of the middle portion of the first magnetic layer when imprinting is performed, a position of the second portion of the imprinting stencil corresponding to a position of the edge portion of the first magnetic layer;
a second magnetic layer on the patterned polymer coating surface.
11. The on-chip inductor structure of claim 10, wherein the pressure is applied to the imprint template while the imprint template is imprinted on the surface of the polymer coating, and wherein the thickness of the planar portion of the patterned polymer coating is adjusted by adjusting the magnitude of the applied pressure.
12. The on-chip inductor structure of claim 11, wherein the material of the imprint template is polydimethyl-oxy-alkane, perfluoroalkyl polyether, polyurethane acrylate; the patterned polymer coating is made of polymethyl methacrylate, polyimide, pyrrole resin or cycloolefin copolymer.
13. The on-chip inductor structure of claim 10, wherein the inductor is a spiral inductor or a wire inductor, and the wire line is one and spiral when the inductor is a spiral inductor; when the inductor is a linear inductor, at least two wire lines are arranged, and at least two wire lines are parallel to each other.
14. The on-chip inductor structure of claim 10, further comprising: a first dielectric layer on the surface of the first magnetic layer, and the inductor is on the surface of the first dielectric layer; a second dielectric layer positioned between the patterned polymer coating and the second magnetic layer.
15. The on-chip inductor structure of claim 10, wherein the first magnetic layer and the second magnetic layer are each a stacked structure in which magnetic thin film layers and spacer layers are alternately stacked.
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