CN116991769A - Data sampling method and device of SPI main interface - Google Patents

Data sampling method and device of SPI main interface Download PDF

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Publication number
CN116991769A
CN116991769A CN202311029955.5A CN202311029955A CN116991769A CN 116991769 A CN116991769 A CN 116991769A CN 202311029955 A CN202311029955 A CN 202311029955A CN 116991769 A CN116991769 A CN 116991769A
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sampling
clock
delay
data
spi
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李术亮
黄钧
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Beijing Ziguang Xinneng Technology Co Ltd
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Beijing Ziguang Xinneng Technology Co Ltd
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Priority to CN202311029955.5A priority Critical patent/CN116991769A/en
Publication of CN116991769A publication Critical patent/CN116991769A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/372—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The application discloses a data sampling method and device of an SPI main interface, wherein the method comprises the following steps: and a plurality of delay lines are inserted into the clock period of the SPI master interface sampling clock, the data signal sampling of the SPI master interface is carried out on the clock edge corresponding to each delay line except the last delay line in the clock period of the sampling clock, a plurality of sampling point data in the clock period of the sampling clock are obtained, and the sampling data corresponding to the clock period of the sampling clock are determined according to the plurality of sampling point data. According to the application, a plurality of delay sampling points are inserted into the clock period of the SPI main interface sampling clock, each delay sampling point corresponds to one clock edge of a preset type, so that the prior SPI main interface sampling clock is subdivided into one clock period, the prior SPI main interface sampling clock has smaller scale (sampling granularity), the accuracy of a sampling result can be further ensured, and the accurate sampling of SPI main interface data such as MISO data is ensured.

Description

Data sampling method and device of SPI main interface
Technical Field
The application belongs to the technical field of SPI communication, and particularly relates to a data sampling method and device of an SPI main interface.
Background
In SPI (Serial Peripheral Interface ) communications, the SPI interface can sample data on either the rising or falling edge of the first or second clock, i.e., 4 sampling modes. In either mode, the master node provides a clock that is used by both the master node and the slave node to sample data.
When the clock frequency is very high, i.e., in the ultra-high speed SPI, the SPI master interface data such as MISO (master SPI data input of fig. 1) cannot be sampled correctly, and how to solve this problem makes the SPI master interface capable of sampling correctly an urgent technical problem in the art.
Disclosure of Invention
Therefore, the application discloses a data sampling method and device for an SPI main interface, which are used for solving the data sampling problem of the SPI main interface in SPI communication and ensuring that data of the SPI main interface such as MISO data can be sampled correctly.
The specific technical scheme is as follows:
a data sampling method of SPI main interface includes:
inserting a plurality of delay sampling points into the clock period of the SPI master interface sampling clock, wherein each delay sampling point corresponds to a clock edge of a preset type;
the data signal sampling of the SPI main interface is carried out on the clock edge corresponding to each delay sampling point in the clock period of the sampling clock, so that a plurality of sampling point data in the clock period of the sampling clock are obtained;
and determining sampling data corresponding to the clock period of the sampling clock according to the plurality of sampling point data.
Optionally, the inserting a plurality of delay sampling points inside the clock period of the sampling clock includes:
setting a plurality of delay units in the clock period of a sampling clock to form a plurality of delay sampling points in the clock period of the sampling clock based on the set plurality of delay units;
wherein each delay unit corresponds to a delay sampling point, and the delay total time of the plurality of delay units is less than one clock cycle.
Optionally, the delay unit includes two inverters connected in series, the inverters including MOS transistors, and the method further includes:
and setting the delay time corresponding to the delay unit by adjusting the width-to-length ratio of the MOS tube in the inverter of the delay unit.
Optionally, sampling the data signal of the SPI master interface at a clock edge corresponding to each delayed sampling point in the clock cycle of the sampling clock, including:
and sampling MISO data signals of the SPI main interface on the clock edge corresponding to each delay unit by using the data sampling unit arranged for each delay unit.
Optionally, the determining, according to the plurality of sampling point data, sampling data corresponding to a clock period of the sampling clock includes:
and carrying out OR operation on the plurality of sampling point data by adopting an operation unit to obtain sampling data corresponding to the clock period of the sampling clock.
Optionally, the method further comprises:
the control unit is used for controlling the working mode of the operation unit so that the operation unit can determine sampling data corresponding to the clock period of the sampling clock according to the corresponding working mode;
the operation unit realizes data signal sampling of the SPI main interface based on different delay sampling points or delay sampling point combinations in different working modes.
A data sampling device for an SPI master interface, comprising:
the delay module is used for inserting a plurality of delay sampling points into the clock period of the SPI master interface sampling clock, and corresponding one preset type clock edge at each delay sampling point;
the sampling module is used for sampling the data signals of the SPI main interface at the clock edge corresponding to each delay sampling point in the clock period of the sampling clock to obtain a plurality of sampling point data in the clock period of the sampling clock;
and the determining module is used for determining sampling data corresponding to the clock period of the sampling clock according to the plurality of sampling point data.
Optionally, the delay module includes a plurality of delay units, and the plurality of delay units are arranged inside the clock period of the sampling clock, so that a plurality of delay sampling points are formed inside the clock period of the sampling clock;
wherein each delay unit corresponds to a delay sampling point, and the delay total time of the plurality of delay units is less than one clock cycle.
Optionally, the delay unit includes two inverters connected in series, the inverters include MOS transistors, and the delay time corresponding to the delay unit is set by adjusting the width-to-length ratio of the MOS transistors in the inverters of the delay unit.
Optionally, the sampling module includes a data sampling unit correspondingly configured for each delay unit; and the sampling module samples MISO data signals of the SPI main interface by utilizing the clock edges corresponding to the corresponding delay units by utilizing the data sampling units.
Optionally, the determining module includes an operation unit, configured to perform an or operation on the plurality of sampling point data, to obtain sampling data corresponding to a clock period of the sampling clock.
Optionally, the device further includes a control unit, configured to control an operation mode of the operation unit, so that the operation unit determines, according to the corresponding operation mode, sampling data corresponding to a clock period of the sampling clock;
the operation unit samples the data signal of the SPI main interface based on different delay sampling points or delay sampling point combinations in different working modes.
As can be seen from the above scheme, the present application discloses a data sampling method and apparatus for an SPI master interface, wherein the method includes: inserting a plurality of delay lines into the clock period of the SPI master interface sampling clock so as to correspondingly obtain a clock edge of a preset type in each delay line; the data signal sampling of the SPI main interface is carried out on the clock edge corresponding to each delay line except the last delay line in the clock period of the sampling clock, so that a plurality of sampling point data in the clock period of the sampling clock are obtained; and determining sampling data corresponding to the clock period of the sampling clock according to the plurality of sampling point data.
According to the application, a plurality of delay sampling points are inserted into the clock period of the SPI main interface sampling clock, each delay sampling point corresponds to one clock edge of a preset type, so that the prior SPI main interface sampling clock is subdivided, has smaller scales (sampling granularity), and the sampling data corresponding to the sampling clock period is determined by integrating the data of the plurality of sampling points with smaller sampling granularity in the SPI main interface sampling clock period, so that the accuracy of a sampling result can be further ensured, and the correct sampling of the SPI main interface data such as MISO data is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described, and it is apparent that the drawings in the following description are only embodiments of the present application, and other drawings may be obtained according to the provided drawings without inventive effort for those skilled in the art.
FIG. 1 is a schematic diagram of communication between SPI master and slave nodes provided by the present application;
FIG. 2 is a schematic diagram of correct sampling of an SPI master node provided by the present application;
FIG. 3 is a schematic diagram of error sampling of an SPI master node provided by the present application;
FIG. 4 is a flowchart of a data sampling method of an SPI main interface provided by the present application;
fig. 5 is a schematic diagram of the composition structure of the delay unit provided by the present application;
FIG. 6 (a) is a schematic diagram of normal sampling at each of 3 delayed sampling points at room temperature provided by the present application;
FIG. 6 (b) is a schematic diagram showing erroneous sampling of a delayed sampling point at a high temperature provided by the present application;
FIG. 7 is a block diagram illustrating an implementation of SPI master interface sampling in an application example provided by the present application;
fig. 8 is a block diagram of a data sampling device of an SPI master interface according to the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The applicant finds that, taking 125MHZ as an example, the whole clock period is 8ns, the data signal setup time and hold time are both about 2ns, and since the double delay (SCLK clock arrives at slave+miso data returns to master) on the transmission path (IC internal+pcb) is also ns level, the ultra-high speed SPI master node often sets a delay sampling function to delay the sampling time by half to one period, even if the delay on the transmission path often has a drift of several ns when the temperature change is large, the temperature change affects the hold time and setup time of the data signal, which is liable to cause the data signal setup time lag, i.e. the data signal is not yet established when the sampling edge (rising edge or falling edge) arrives, which is liable to cause data sampling errors, which also causes the current high speed SPI clock to rarely exceed 50 MHZ.
Referring to fig. 1 in combination, the master node is a master device node where the master SPI is located, and the slave nodes are slave device nodes where the slave SPI is located, which may be referred to as an SPI master node and an SPI slave node, respectively.
Taking the rising edge sampling mode of SPI (cpol=1, high level when clock is idle) as an example, as shown in fig. 2, the SPI master node can normally sample delayed data (MISO) after delaying for half a period. However, when the temperature increases or the data transmission path is longer, MISO data delay increases, the data signal setup time further delays, and normal sampling is not possible after the sampling point is set to delay for half a period, as shown in fig. 3.
Based on the above, the embodiment of the application provides a data sampling method and device for an SPI (serial peripheral interface) main interface, which are used for solving the data sampling problem of the SPI main interface in SPI communication and ensuring that data of the SPI main interface such as MISO (serial peripheral interface) data can be accurately sampled.
Referring to a flowchart of a data sampling method of an SPI master interface shown in fig. 4, the data sampling method of an SPI master interface provided by the present application at least includes:
step 401, a plurality of delay sampling points are inserted into a clock cycle of the SPI master interface sampling clock, and each delay sampling point corresponds to a predetermined type of clock edge.
The SPI main interface is the SPI interface of the SPI main node.
According to the application, a plurality of delay sampling points are inserted into the clock period of the SPI main interface sampling clock, and each delay sampling point corresponds to one clock edge of a preset type, so that the repartition of one clock period of the existing SPI main interface sampling clock is realized, and the clock has smaller scale (sampling granularity).
The SPI interface may sample the data on either the rising or falling edge of the first or second clock, i.e., 4 sampling modes. The predetermined type of clock edge described above may be a rising or falling edge, respectively, depending on the sampling pattern employed. The sampling clock of the SPI master interface may be the first clock or the second clock, which may also depend on the sampling mode used, and the sampling clock may be a clock delayed (for example, delayed by half a clock period) with respect to the SCLK clock, which is set based on the double delay on the transmission path (IC internal+pcb), or may be a clock that is not delayed compared with the SCLK clock, which is not limited, and may be specifically set according to the actual working condition requirement.
Optionally, in the embodiment of the present application, a time interpolation manner is adopted, and a plurality of delay units are set inside a clock cycle of a sampling clock of an SPI master interface, so as to form a plurality of delay sampling points inside the clock cycle of the sampling clock based on the set plurality of delay units.
Wherein each delay unit corresponds to a delay sampling point, and the delay total time of the plurality of delay units is less than one clock cycle. The specific delay time parameter of each delay unit and the number of delay units are not limited, and can be set according to requirements. Illustratively, 3 delay cells are provided within one clock cycle, each of which may be, but is not limited to, 0.34ns in delay.
Referring to fig. 5, each delay unit is composed of two inverters connected in series, the inverters further include MOS transistors, and specifically, delay time corresponding to the delay unit can be set by adjusting the width-to-length ratio of the MOS transistors in the inverters of the delay unit.
Step 402, sampling the data signal of the SPI master interface at the clock edge corresponding to each delay sampling point in the clock cycle of the sampling clock, to obtain a plurality of sampling point data in the clock cycle of the sampling clock.
For a plurality of delay units provided inside the clock period of the sampling clock, the present embodiment sets corresponding data sampling units one-to-one for each delay unit, that is, corresponds to setting corresponding data sampling units one-to-one for each delay sampling point. Optionally, the data sampling unit may be a D-type flip-flop DFF, and the data signal sampling of the clock edge (rising edge or falling edge, depending on the sampling mode) corresponding to the delay sampling point is implemented by using the D-type flip-flop DFF set for each delay sampling point, and specifically, MISO data signal sampling of the SPI master interface may be performed on the clock edge corresponding to the corresponding delay unit.
The MISO is Master input slave output, which is a general signal description of SPI, sampling is a process of data reading, and the data line (rising edge or falling edge) is sampled at the edge of the clock, and the high level reads 1, and the low level reads 0.
Step 403, determining sampling data corresponding to the clock period of the sampling clock according to the plurality of sampling point data.
Specifically, the operation unit may perform an or operation on the plurality of sampling point data to obtain sampling data corresponding to a clock cycle of the sampling clock, for example, perform an or operation on the plurality of MISO sampling point data to obtain MISO sampling data corresponding to the clock cycle.
The theoretical basis for obtaining the sampling data corresponding to the clock period through the processing is described below.
Applicants' research has found that the data change from high to low is fast and a process is needed to flip from low to high (closely related to the slew rate of the drive circuit), if the sampling point is too far ahead, during the data signal setup data 0 will hardly be sampled erroneously, whereas data 1 will often be sampled erroneously to 0 because it does not climb up (flip from low to high).
Based on the above analysis, the embodiment of the present application uses the data of multiple delay sampling points or together (preferably, the first delay sampling point can be advanced to the initial position of the data holding period, i.e. immediately after the data establishment is completed), so as to ensure the correctness of the sampling result when the MISO data signal is further delayed due to the temperature rise.
Illustrating:
assume that 3 delayed sampling points are set in a clock period of a sampling clock: sampling points 1, 2, and 3 are all normal at room temperature, as shown in fig. 6 (a).
At high temperature, as shown in fig. 6 (b), sampling point 1 is in the period of MISO data signal establishment, assuming that the last period MISO is logic 1 and the period is logic 0, the sampling point 1 is turned to 0 at this time, and the sampling point 1 will not be erroneously sampled; assuming that the last cycle MISO is a logical 0 and the present cycle is a logical 1, sample point 1 samples 0, samples 2 and 3 samples 1, three data or together is a 1. That is, sampling and sampling the result or together multiple times in one clock period can ensure the correctness of the sampled result when a further delay of the data signal occurs.
According to the scheme, the data sampling method of the SPI main interface disclosed by the application has the advantages that the delay sampling points are inserted into the clock period of the sampling clock of the SPI main interface, each delay sampling point corresponds to one clock edge of a preset type, the repartition of one clock period of the sampling clock of the existing SPI main interface is realized, the sampling clock has smaller scales (sampling granularity), the sampling data corresponding to the sampling clock period is determined by integrating the data of the sampling points with smaller sampling granularity in the sampling clock period of the SPI main interface, the accuracy of a sampling result can be further ensured, and the correct sampling of the data of the SPI main interface such as MISO data is ensured.
In an alternative embodiment, the data sampling method of the SPI master interface disclosed in the present application may further include the following processes: the control unit is used for controlling the working mode of the operation unit so that the operation unit can determine sampling data corresponding to the clock period of the sampling clock according to the corresponding working mode;
the operation unit realizes data signal sampling of the SPI main interface based on different delay sampling points or delay sampling point combinations in different working modes.
Alternatively, the control unit may be a control register, i.e. the function of the control unit is implemented using the control register, while the selector may be used as an arithmetic unit to provide a determining/arithmetic function for clock cycle sampling data. The control register can be initialized in a software mode, and at least the setting of the working mode required by the selector is completed in the initialization process so as to be used for controlling the working mode of the selector.
Optionally, in addition to setting a plurality of delay units for forming a plurality of delay sampling points in the clock period of the sampling clock, a delay unit may be additionally set after the plurality of delay units in the clock period, so as to generate a clock edge corresponding to the output result of the selector (the selector needs a certain time to perform the processing function corresponding to the operation mode) based on the delay unit, so as to achieve time alignment with the output result of the selector.
Referring to the example of fig. 7, this example employs a class D flip-flop DFF to implement data sampling. 4 delay units TAP 0-TAP 3 are arranged, wherein TAP0, TAP1 and TAP2 respectively correspond to a D-type trigger DFF, the DFF0 uses a clock delayed by TAP0, and the like; the total delay time of TAP0, TAP1, TAP2 is less than one clock cycle. TAP3 is used to generate clock edges corresponding to the output of the selector to achieve time alignment with the output of the selector.
The control register is initialized by software and controls the operation mode of the selector based on the initialization, and the selector can include, but is not limited to, the following operation modes:
0: using only the output of DFF 0;
1: using only the output of DFF 1;
2: using only the output of DFF 2;
3: outputting the results of DFF0 and DFF1 together;
4: the results of DFF0, DFF1, DFF2 are output together or together.
The selector executes the required processing (such as operation processing) according to the working mode and outputs the corresponding result, and optionally, the output result and a clock (such as a clock after TAP3 delay) after the delay of the additionally arranged delay unit are used as sampling data of the clock period to be sent to the subsequent SPI shift register.
In this embodiment, before data enter the shift register, by setting multiple fine delay units (adopting a time interpolation mode) and combining and utilizing the control register and the selector, the sampling delay time and the working mode of the selector can be finely set, so that corresponding (operation) processing can be executed at the selector in combination with the actual sampling working condition, and the result (such as the or operation result of multiple sampling point data) and the corresponding clock thereof are sent into the shift register together, thereby realizing accurate sampling of the clock period of the SPI main interface.
The embodiment of the application also provides a data sampling device of the SPI main interface, the composition structure of which is shown in figure 8, comprising:
a delay module 801, configured to insert a plurality of delay sampling points into a clock period of the SPI master interface sampling clock, and correspond to a predetermined type of clock edge at each delay sampling point;
the sampling module 802 is configured to sample the data signal of the SPI master interface at a clock edge corresponding to each delay sampling point in a clock period of the sampling clock, so as to obtain a plurality of sampling point data in the clock period of the sampling clock;
a determining module 803, configured to determine, according to the plurality of sampling point data, sampling data corresponding to a clock period of the sampling clock.
In an embodiment, the delay module 801 includes a plurality of delay units, and the plurality of delay units are arranged inside a clock period of a sampling clock, so that a plurality of delay sampling points are formed inside the clock period of the sampling clock;
wherein each delay unit corresponds to a delay sampling point, and the delay total time of the plurality of delay units is less than one clock cycle.
In an embodiment, the delay unit includes two inverters connected in series, the inverters include MOS transistors, and the delay time corresponding to the delay unit is set by adjusting the width-to-length ratio of the MOS transistors in the inverters of the delay unit.
In one embodiment, the sampling module 802 includes a data sampling unit correspondingly configured for each delay unit; and the sampling module samples MISO data signals of the SPI main interface by utilizing the clock edges corresponding to the corresponding delay units by utilizing the data sampling units.
In an embodiment, the determining module 803 includes an operation unit, configured to perform an or operation on the plurality of sampling point data, to obtain sampling data corresponding to a clock period of the sampling clock.
In an embodiment, the device further includes a control unit, configured to control an operation mode of the operation unit, so that the operation unit determines, according to the corresponding operation mode, sampling data corresponding to a clock period of the sampling clock;
the operation unit samples the data signal of the SPI main interface based on different delay sampling points or delay sampling point combinations in different working modes.
For the data sampling device of the SPI master interface provided by the embodiment of the present application, the description is relatively simple because it corresponds to the data sampling method of the SPI master interface provided by the method embodiment, and the relevant similarities are only required to refer to the description of the method embodiment, and are not described in detail herein.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
For convenience of description, the above system or apparatus is described as being functionally divided into various modules or units, respectively. Of course, the functions of each element may be implemented in the same piece or pieces of software and/or hardware when implementing the present application.
From the above description of embodiments, it will be apparent to those skilled in the art that the present application may be implemented in software plus a necessary general hardware platform. Based on such understanding, the technical solution of the present application may be embodied essentially or inventive contributing portions thereof in the form of a software product, which may be stored in a storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the embodiments or portions of the embodiments of the present application.
Finally, it is further noted that relational terms such as first, second, third, fourth, and the like are used herein to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application, which are intended to be comprehended within the scope of the present application.

Claims (12)

1. A data sampling method for an SPI master interface, comprising:
inserting a plurality of delay sampling points into the clock period of the SPI master interface sampling clock, wherein each delay sampling point corresponds to a clock edge of a preset type;
the data signal sampling of the SPI main interface is carried out on the clock edge corresponding to each delay sampling point in the clock period of the sampling clock, so that a plurality of sampling point data in the clock period of the sampling clock are obtained;
and determining sampling data corresponding to the clock period of the sampling clock according to the plurality of sampling point data.
2. The method of claim 1, wherein inserting a plurality of delayed sampling points within a clock cycle of a sampling clock comprises:
setting a plurality of delay units in the clock period of a sampling clock to form a plurality of delay sampling points in the clock period of the sampling clock based on the set plurality of delay units;
wherein each delay unit corresponds to a delay sampling point, and the delay total time of the plurality of delay units is less than one clock cycle.
3. The method of claim 2, wherein the delay unit comprises two inverters in series, the inverters comprising MOS transistors, the method further comprising:
and setting the delay time corresponding to the delay unit by adjusting the width-to-length ratio of the MOS tube in the inverter of the delay unit.
4. The method of claim 2, wherein sampling the data signal of the SPI master interface at the clock edge corresponding to each delayed sampling point in the clock cycle of the sampling clock comprises:
and sampling MISO data signals of the SPI main interface on the clock edge corresponding to each delay unit by using the data sampling unit arranged for each delay unit.
5. The method of claim 1, wherein determining sample data corresponding to a clock cycle of the sample clock from the plurality of sample point data comprises:
and carrying out OR operation on the plurality of sampling point data by adopting an operation unit to obtain sampling data corresponding to the clock period of the sampling clock.
6. The method as recited in claim 5, further comprising:
the control unit is used for controlling the working mode of the operation unit so that the operation unit can determine sampling data corresponding to the clock period of the sampling clock according to the corresponding working mode;
the operation unit realizes data signal sampling of the SPI main interface based on different delay sampling points or delay sampling point combinations in different working modes.
7. A data sampling device for an SPI master interface, comprising:
the delay module is used for inserting a plurality of delay sampling points into the clock period of the SPI master interface sampling clock, and corresponding one preset type clock edge at each delay sampling point;
the sampling module is used for sampling the data signals of the SPI main interface at the clock edge corresponding to each delay sampling point in the clock period of the sampling clock to obtain a plurality of sampling point data in the clock period of the sampling clock;
and the determining module is used for determining sampling data corresponding to the clock period of the sampling clock according to the plurality of sampling point data.
8. The apparatus of claim 7, wherein the delay module comprises a plurality of delay cells that are arranged within a clock cycle of a sampling clock such that a plurality of delayed sampling points are formed within the clock cycle of the sampling clock;
wherein each delay unit corresponds to a delay sampling point, and the delay total time of the plurality of delay units is less than one clock cycle.
9. The apparatus of claim 8, wherein the delay unit comprises two inverters connected in series, the inverters comprise MOS transistors, and the delay time corresponding to the delay unit is set by adjusting the width-to-length ratio of the MOS transistors in the inverters of the delay unit.
10. The apparatus of claim 8, wherein the sampling module comprises a data sampling unit provided for each delay unit; and the sampling module samples MISO data signals of the SPI main interface by utilizing the clock edges corresponding to the corresponding delay units by utilizing the data sampling units.
11. The apparatus of claim 7, wherein the determining module includes an operation unit configured to perform an or operation on the plurality of sampling point data to obtain sampling data corresponding to a clock period of the sampling clock.
12. The apparatus according to claim 11, further comprising a control unit configured to control an operation mode of the operation unit, so that the operation unit determines sampling data corresponding to a clock cycle of the sampling clock in the corresponding operation mode;
the operation unit samples the data signal of the SPI main interface based on different delay sampling points or delay sampling point combinations in different working modes.
CN202311029955.5A 2023-08-16 2023-08-16 Data sampling method and device of SPI main interface Pending CN116991769A (en)

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