CN116981262A

CN116981262A - Wafer manufacturing method and wafer

Info

Publication number: CN116981262A
Application number: CN202210436909.6A
Authority: CN
Inventors: 张云森; 李辉辉; 赵超
Original assignee: Beijing Superstring Academy of Memory Technology
Current assignee: Beijing Superstring Academy of Memory Technology
Priority date: 2022-04-19
Filing date: 2022-04-19
Publication date: 2023-10-31

Abstract

The disclosure provides a wafer manufacturing method and a wafer, and relates to the technical field of semiconductors, wherein the wafer manufacturing method comprises the following steps: providing a wafer substrate; forming a first dielectric layer, wherein the first dielectric layer covers the back surface of the wafer substrate; forming a magnetic tunnel junction device layer on the front surface of the wafer substrate; forming a second dielectric layer, wherein the second dielectric layer covers the magnetic tunnel junction device layer to obtain an initial wafer; and carrying out edge etching and back surface cleaning on the initial wafer to obtain the wafer. In the method, before the magnetic tunnel junction device layer is deposited, the first dielectric layer is formed on the back surface of the wafer substrate, so that metal pollution generated in the process of forming the magnetic tunnel junction device layer later and chemical adsorption generated on the back surface of the wafer are avoided, and potential metal pollution generated in the process of depositing the magnetic tunnel junction device layer on the wafer can be effectively removed after subsequent edge etching and back surface cleaning.

Description

Wafer manufacturing method and wafer

Technical Field

The disclosure relates to the field of semiconductor technology, and in particular relates to a wafer manufacturing method and a wafer.

Background

Magnetic random access memory (Magnetic Random Access Memory, MRAM) is considered one of the most promising new types of storage media, with wide application and market prospects in both embedded and free-standing systems, magnetic tunnel junctions (Magnetic Tunnel Junction, MTJ) being the basic memory cell of magnetic random access memory MRAM. In the current fabrication method, the surface state of the back surface of the wafer is unknown prior to deposition of the magnetic tunnel junction layer, which can present a significant challenge to the prevention and control of metal contamination during subsequent wafer formation.

Disclosure of Invention

The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

The disclosure provides a wafer manufacturing method and a wafer.

A first aspect of the present disclosure provides a method for manufacturing a wafer, the method for manufacturing a wafer including:

providing a wafer substrate;

forming a first dielectric layer, wherein the first dielectric layer covers the back surface of the wafer substrate;

forming a magnetic tunnel junction device layer on the front surface of the wafer substrate;

forming a second dielectric layer, wherein the second dielectric layer covers the magnetic tunnel junction device layer to obtain an initial wafer;

And carrying out edge etching and back surface cleaning on the initial wafer to obtain the wafer.

According to some embodiments of the present disclosure, the wafer base includes a substrate and a transistor device layer disposed on the substrate, the first dielectric layer overlying a backside of the substrate, the magnetic tunnel junction device layer overlying the transistor device layer;

the step of performing edge etching and back surface cleaning on the initial wafer comprises the following steps:

the second dielectric layer and the magnetic tunnel junction device layer are etched to expose a front side edge region of the substrate, and the first dielectric layer is etched to expose a back side edge region of the substrate.

According to some embodiments of the present disclosure, the width of the front edge region of the substrate is greater than 1.0 millimeter; and/or the number of the groups of groups,

the width of the back edge region of the substrate is greater than 2.0 millimeters.

According to some embodiments of the present disclosure, the etching gas employed to etch the second dielectric layer, the magnetic tunnel junction device layer, and/or the first dielectric layer comprises a combination of one or more of the following gases:

argon, neon, krypton, xenon, carbon tetrafluoride, sulfur hexafluoride, nitrogen trifluoride, nitrogen, methanol, ammonia, carbon monoxide.

According to some embodiments of the present disclosure, after the etching the second dielectric layer and the magnetic tunnel junction device layer to expose a front side edge region of the substrate and the etching the first dielectric layer to expose a back side edge region of the substrate, the performing edge etching and back side cleaning on the initial wafer further comprises:

and carrying out wet cleaning on the back surface of the first dielectric layer.

According to some embodiments of the present disclosure, the cleaning medium used for wet cleaning the back side of the first dielectric layer includes one or more of the following combinations:

sulfuric acid, hydrogen fluoride, hydrogen chloride, nitric acid, ozonated deionized water, and water.

According to some embodiments of the disclosure, further comprising:

etching the back surface of the first dielectric layer by adopting an undercut process;

and cleaning the first dielectric layer subjected to the undercut process by adopting a jet flow spray physical removal process to obtain the wafer.

According to some embodiments of the present disclosure, the etching solution employed in the undercut process comprises a combination of one or more of the following:

sulfuric acid, hydrogen fluoride, hydrogen chloride, nitric acid, ozonated deionized water, and water;

The jet physical removal process employs a deionized water and nitrogen combination, and/or an isopropyl alcohol and nitrogen combination.

According to some embodiments of the disclosure, the wet cleaning the back side of the first dielectric layer includes:

the back surface of the first dielectric layer is cleaned with a ceric ammonium nitrate solution and/or a nitric acid solution.

According to some embodiments of the present disclosure, the material of the first dielectric layer includes silicon oxide, silicon oxynitride, silicon nitride, and silicon carbide; and/or the number of the groups of groups,

the material of the second dielectric layer includes silicon oxide, silicon oxynitride, silicon nitride, and silicon carbide.

According to some embodiments of the present disclosure, the material of the magnetic tunnel junction device layer includes some or all of the following elements:

nitrogen, oxygen, boron, magnesium, ruthenium, tungsten, titanium, tantalum, iron, cobalt, nickel, vanadium, niobium, chromium, platinum, iridium, molybdenum, hafnium, palladium.

A second aspect of the present disclosure provides a wafer comprising:

the wafer body comprises a wafer substrate, a magnetic tunnel junction device layer and a second dielectric layer which are stacked;

a first dielectric layer located on the back side of the wafer substrate;

The first dielectric layer covers a portion of the back surface of the wafer substrate and exposes a back surface edge region of the wafer substrate.

According to some embodiments of the present disclosure, the wafer base includes a substrate, and a transistor device layer disposed on the substrate, the magnetic tunnel junction device layer overlying the transistor device layer, the second dielectric layer overlying the magnetic tunnel junction device layer.

According to the manufacturing method of the wafer and the wafer, the first dielectric layer is formed on the back surface of the wafer substrate before the magnetic tunnel junction device layer is deposited, so that metal pollution generated in the process of forming the magnetic tunnel junction device layer later and chemical adsorption generated on the back surface of the wafer are avoided, and potential metal pollution generated in the process of depositing the magnetic tunnel junction device layer of the wafer can be effectively removed after subsequent edge etching and back surface cleaning.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to identify like elements. The drawings, which are included in the description, are some, but not all embodiments of the disclosure. Other figures can be obtained from these figures without inventive effort for a person skilled in the art.

FIG. 1 illustrates an electronegative periodic table of elements;

FIG. 2 is a schematic diagram illustrating the formation of metal contamination on the backside of a wafer substrate in accordance with one exemplary embodiment of the prior art;

FIG. 3 is a flow chart illustrating a method of fabricating a wafer according to an exemplary embodiment;

FIG. 4 is a flow chart illustrating a method of fabricating a wafer according to an exemplary embodiment;

FIG. 5 is a flow chart illustrating a method of fabricating a wafer according to an exemplary embodiment;

FIG. 6 is a schematic diagram of a structure of a wafer substrate provided in a method of fabricating a wafer according to an example embodiment;

FIG. 7 is an enlarged view of the structure of the edge region of the wafer substrate of FIG. 6;

fig. 8 is a schematic diagram of a structure after forming a first dielectric in a method for fabricating a wafer according to an exemplary embodiment;

fig. 9 is a schematic diagram of a structure after forming a transistor device layer in a method for fabricating a wafer according to an exemplary embodiment;

FIG. 10 is a schematic diagram of a structure after forming a magnetic tunnel junction device layer in a method of fabricating a wafer according to an example embodiment;

FIG. 11 is a schematic diagram of thermally annealing a magnetic tunnel junction device layer in a method of fabricating a wafer according to an example embodiment;

FIG. 12 is a schematic diagram of an initial wafer resulting from a method of fabricating a wafer according to an exemplary embodiment;

FIG. 13 is a schematic diagram of a structure of an initial wafer with metal contaminants present in the surface in a method of fabricating a wafer according to an example embodiment;

fig. 14 schematically illustrates an enlarged view of an edge region of the initial wafer of fig. 13;

FIG. 15 is a schematic diagram of an etching tool for etching an edge region of an initial wafer in a method of fabricating a wafer according to an exemplary embodiment;

fig. 16 is a schematic diagram of an initial wafer placed in an ion chamber in a method of fabricating a wafer according to an exemplary embodiment;

Fig. 17 illustrates an enlarged view of an edge region of the initial wafer of fig. 16;

FIG. 18 schematically illustrates the initial wafer of FIG. 17 after an edge region has been etched;

FIG. 19 is a schematic view of an initial wafer formed after an edge region is etched in a method of fabricating a wafer according to an exemplary embodiment;

fig. 20 is a schematic diagram of a cleaning apparatus for cleaning a back surface of a first dielectric layer in a method of fabricating a wafer according to an exemplary embodiment;

FIG. 21 is a schematic view of a structure of an initial wafer in contact with a chuck in a cleaning station in a method of fabricating a wafer according to an exemplary embodiment;

fig. 22 exemplarily shows an enlarged view of a in fig. 21;

fig. 23 schematically illustrates a structure of the back surface of the first dielectric layer after an undercut process;

fig. 24 illustrates a schematic diagram of cleaning a first dielectric layer subjected to an undercut process using a jet spray physical removal process;

fig. 25 is a schematic view of a structure of a wafer obtained in a method for manufacturing a wafer according to an exemplary embodiment.

Reference numerals:

10. a wafer; 100. a wafer substrate; 101. the back surface of the wafer substrate; 102. the front surface of the wafer substrate; 103. an edge region of the wafer substrate; 104. an edge region 104 of the initial wafer; 1040. an upper edge; 1041. a lower edge; 1042. an upper inclined plane; 1043. a lower inclined plane; 1044. a top end; 120. a particulate oxide; 130. a metal silicide;

20. Etching machine; 21. a plasma chamber; 22. etching gas (plasma); 23. an upper polar plate; 24. a lower polar plate; 200. a first dielectric layer; 201. a back surface of the first dielectric layer;

30. a cleaning machine; 31. cleaning the cavity; 32. a suction cup; 33. etching solution; 300. a crystal device layer; 400', metal contamination; 500 a second dielectric layer.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be arbitrarily combined with each other.

The magnetic random access memory (Magnetic Random Access Memory, MRAM) takes the spin property of electrons as an information storage medium, has the excellent characteristics of non-volatility, high speed, scratch resistance, low power consumption, high reliability, irradiation resistance and the like, is an outstanding representative of the emerging storage technology, has wide application prospect in embedded and independent systems, and is mainly applied to the scenes of industry, medical treatment, automobiles, storage/network acceleration, wearable, internet of things, aerospace and the like. However, MRAM fabrication processes currently face challenges such as: deposition and etching of magnetic tunnel junctions, prevention and control of metal contamination, and the like.

In order to describe the method of manufacturing the wafer according to the present disclosure in detail, prior to describing the method of manufacturing the wafer according to the present disclosure, a description is first given of a related art related to the method of manufacturing the wafer according to the present disclosure. As shown in fig. 1, the electronegative periodic table of elements is exemplarily shown.

As shown in table 1, examples show the oxidation-reduction potential values of part of the metal elements. The redox potential is used to reflect the macroscopic redox properties exhibited by all materials in aqueous solutions. The higher the redox potential, the more oxidizing, the lower the redox potential, and the more reducing. The positive potential indicates that the solution exhibits a certain oxidizing property, and the negative potential indicates that the solution exhibits a certain reducing property. Chemical oxidation-reduction is an effective method for converting pollutants, and inorganic matters and organic matters are oxidized or reduced and converted into forms which are easy to separate from water through chemical reaction, so that the aim of treatment is fulfilled.

For metals containing electronegativity less than silicon (Si), such as: magnesium (Mg), titanium (Ti), vanadium (V), chromium (Cr), iron (Fe), cobalt (Co), niobium (Nb), hafnium (Hf), tantalum (Ta), etc., and particulate matter and trace amounts of elemental metals formed therefrom are very easily cleaned in a subsequent cleaning process, such as: the cleaning may be performed with a solution such as dilute hydrofluoric acid (dHF). However, for metals containing electronegativity greater than silicon (Si), such as: molybdenum (Mo), tungsten (W), ruthenium Particulate matter formed by (Ru), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt) and the like and trace amounts of metal element substances react with the edge of the wafer and the exposed substrate surface on the back surface, such as Si to generate metal silicide, and the reaction mechanism becomes more obvious when the wafer is subjected to thermal annealing, so that in the subsequent cleaning process, hydrogen Fluoride (HF), nitric acid (HNO) can be adopted for Mo, W, ni and the like which are easy to clean ₃ ) And washing off the solution.

However, as shown in table 1, in which Ru, ir, pt and Pd having low redox potential values are hard to clean substances, a cleaning solution having a very high redox potential is required for particles, traces of metal elements or metal silicide formed of Ru, ir, pt and Pd, etc. However, in the course of actual production, it is difficult to find a reagent capable of dissolving Ru, ir, pt, pd, and the like.

TABLE 1 metallic element redox potential meter

In the current MRAM fabrication process, as shown in fig. 2, a schematic view of forming particles and metal silicide on the back surface of a wafer is schematically shown. Since the material of the back surface 101' of the wafer is unknown before the MTJ film layer is deposited, and may be a silicon layer and/or a dielectric layer, the MTJ memory cell typically contains elements such as ruthenium (Ru) platinum (Pt), iridium (Ir), or palladium (Pd), and after the MTJ is deposited, particles carrying one or more of these metal elements are highly likely to be adsorbed on the back surface and edge of the wafer by physical or chemical adsorption. If Ru, it will appear as ruthenium (Ru) or ruthenium oxide (RuOx), as shown in FIG. 2, for example, as ruthenium oxide (RuOx) as surface particle oxide 120 adsorbed on the back surface 101' of the wafer; when the back surface 101' of the wafer is silicon (Si), the one or more metal elements may react with the exposed Si to form the metal silicide 130, and the metal silicide 130 is formed, so that the particles 120 are adsorbed on the back surface of the wafer by chemical adsorption, and it is difficult to remove the particles 120 and the metal silicide 130 even by lift-off (lift-off) process. If these particles and trace amounts of metal elements are not removed in time, the manufactured chips will be polluted and/or damaged by other processes and measuring machines in production, and the yield is reduced.

In the method for manufacturing the wafer and the wafer provided in the exemplary embodiments of the present disclosure, in the process of forming the wafer, by forming the first dielectric layer on the back surface of the wafer substrate before depositing the magnetic tunnel junction device layer, metal contamination generated in the process of subsequently forming the magnetic tunnel junction device layer is prevented from reacting with the back surface of the wafer to generate metal silicide and metal-containing particles are adhered to the back surface of the wafer through chemical adsorption, so that potential metal contamination generated in the process of depositing the magnetic tunnel junction device layer by the wafer can be effectively removed after subsequent edge etching and back surface cleaning.

In an exemplary embodiment of the present disclosure, a method for manufacturing a wafer is provided, as shown in fig. 3, fig. 3 is a flowchart illustrating a method for manufacturing a wafer according to an exemplary embodiment of the present disclosure, fig. 6 to fig. 25 are schematic views illustrating various stages of the method for manufacturing a wafer, and the method for manufacturing a wafer is described below with reference to fig. 6 to fig. 25.

The wafer is not limited in this embodiment, and a Magnetic Random Access Memory (MRAM) will be described as an example, but the embodiment is not limited thereto, and the wafer in this embodiment may have other structures.

As shown in fig. 3, a method for manufacturing a wafer according to an exemplary embodiment of the present disclosure includes the following steps:

s310, providing a wafer substrate.

Illustratively, as shown in fig. 6, the wafer substrate 100 serves as a support member for the memory for supporting other components disposed thereon, the wafer substrate 100 may be made of a semiconductor material, which may be one or more of silicon, germanium, silicon germanium compounds, and silicon carbon compounds. The wafer substrate 100 may further include a word line (word line) and a bit line (Bitline) (not shown) for transistors.

S320, forming a first dielectric layer, wherein the first dielectric layer covers the back surface of the wafer substrate.

As shown in fig. 6, the wafer substrate 100 has two sides, a back side 101 of the wafer substrate and a front side 102 of the wafer substrate, respectively, in a direction perpendicular to the surface of the wafer substrate 100. The surface below the wafer substrate 100 is the back surface 101 of the wafer substrate, and the surface above the wafer substrate 100 is the front surface 102 of the wafer substrate.

In this step, as shown in fig. 6 and 8, a first dielectric layer 200 may be formed on the surface of the back surface 101 of the wafer substrate by using a process such as chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition (Atomic Layer Deposition, ALD), or a furnace tube, and the first dielectric layer 200 covers the back surface 101 of the wafer substrate as a back surface dielectric film layer to isolate the wafer substrate from contact with foreign substances. In addition, as the first dielectric layer is formed on the back surface of the wafer substrate, in the subsequent process, the back surface of the wafer substrate can only generate physical adsorption with the subsequent potential metal pollution, so that the possibility of chemical adsorption of the metal pollution on the back surface of the wafer substrate is thoroughly eliminated.

The distinction between physisorption and chemisorption is relatively clear. Physical adsorption is caused by van der Waals attraction between molecules, and may be single-layer adsorption or multi-layer adsorption. The physical adsorption process is relatively fast and equilibrium can be reached at the moment of adsorption. The chemisorption is an adsorption caused by the acting force of chemical bonds, is single-layer adsorption, the chemisorption speed is relatively slow, and the chemisorption reaches equilibrium relatively long, so that in order to achieve better isolation effect on metal pollution on the back surface of the wafer substrate, the thickness of the first dielectric layer can be controlled according to actual needs, so as to prevent the metal pollution from penetrating the first dielectric layer to pollute the back surface of the wafer substrate. In one example, the thickness of the first dielectric layer may be controlled in the range of 50nm to 1000nm, without being particularly limited herein.

As a material of the first dielectric layer, a material having good chemical stability may be selected, and in one example, a combination of one or more of silicon oxide (SiOx), silicon oxynitride (SiON), silicon nitride (SiNx), and silicon carbide (SiCx) may be selected as a material forming the first dielectric layer.

S330, forming a magnetic tunnel junction device layer on the front surface of the wafer substrate.

The front side of the wafer substrate may serve as a region for forming a semiconductor device. In this step, as shown in fig. 6 and 10, a magnetic tunnel junction device layer 400 may be formed on the front side 102 of the wafer substrate by sputter deposition, i.e., physical vapor deposition (Physical Vapor Deposition, PVD).

In one example, as shown in fig. 10, the magnetic tunnel junction device layer 400 is a multi-layer film structure, and the step of forming the magnetic tunnel junction device layer 400 may include: and sequentially and upwards superposing and depositing a magnetic tunnel bottom electrode layer, a magnetic tunnel junction main stack layer and a magnetic tunnel junction top electrode layer on the front surface of the wafer substrate.

The magnetic tunnel junction main stack layer comprises a free layer, a barrier layer, a reference layer and a pinning layer for realizing effective pinning of the reference layer, wherein the pinning layer is in a low resistance state when the magnetic moments of the free layer and the reference layer are parallel, and is in a high resistance state when the magnetic moments of the free layer and the reference layer are anti-parallel, and is in a logic "1".

In one example, the material forming the magnetic tunnel junction device layer includes some or all of the following elements: nitrogen (N), oxygen (O), boron (B), magnesium (Mg), ruthenium (Ru), tungsten (W), titanium (Ti), tantalum (Ta), iron (Fe), cobalt (Co), nickel (Ni), vanadium (V), niobium (Nb), chromium (Cr), platinum (Pt), iridium (Ir), molybdenum (Mo), hafnium (Hf), palladium (Pd). In one example, as shown in fig. 11, after deposition of the magnetic tunnel junction device layer 400, the deposited magnetic tunnel junction device layer 400 is selectively thermally annealed to convert the free layer and the reference layer from amorphous states to crystalline, thereby obtaining a magnetic random access memory device having good magnetic and electrical properties.

And S340, forming a second dielectric layer, wherein the second dielectric layer covers the magnetic tunnel junction device layer, and obtaining the initial wafer.

In this step, as shown in fig. 12, after the formation of the magnetic tunnel junction device layer 400 on the front side 102 (shown in fig. 6) of the wafer substrate, the formation of the second dielectric layer 500 on the surface of the magnetic tunnel junction device layer 400 is continued, and the second dielectric layer 500 covers the upper surface of the magnetic tunnel junction device layer 400, thereby obtaining the initial wafer 10' structure.

As shown in fig. 12, the second dielectric layer 500 may be used as a front side dielectric film layer of a wafer substrate and may be used as a sacrificial layer in a subsequent process. A material having good chemical stability may be selected as the second dielectric layer, and in one example, the material of the second dielectric layer 500 includes a combination of one or more of silicon oxide, silicon oxynitride, silicon nitride, and silicon carbide.

The second dielectric layer may be formed by CVD or ALD. In one example, the thickness of the second dielectric layer may be controlled to be formed as needed, for example, the thickness of the second dielectric layer may be controlled to be in the range of 10nm to 100nm, which is not particularly limited.

And S350, performing edge etching and back surface cleaning on the initial wafer to obtain the wafer.

Because the material of the magnetic tunnel junction device layer contains some or all of the metal elements of nitrogen (N), oxygen (O), boron (B), magnesium (Mg), ruthenium (Ru), tungsten (W), titanium (Ti), tantalum (Ta), iron (Fe), cobalt (Co), nickel (Ni), vanadium (V), niobium (Nb), chromium (Cr), platinum (Pt), iridium (Ir), molybdenum (Mo), hafnium (Hf), and palladium (Pd), during the deposition of the magnetic tunnel junction device layer, particles (metal contaminants) carrying these elements may adhere to the peripheral edge region of the initial wafer and the back surface region of the initial wafer, and therefore, it is necessary to treat the edge region of the initial wafer and the back surface region of the initial wafer to effectively remove the metal contamination existing on the surface of the initial wafer, so that a wafer with high surface cleanliness is obtained.

According to the manufacturing method of the wafer, in the process of forming the wafer, the first dielectric layer is formed on the back surface of the wafer substrate before the magnetic tunnel junction device layer is deposited, so that metal pollution generated in the process of forming the magnetic tunnel junction device layer later and chemical adsorption generated on the back surface of the wafer are avoided, and potential metal pollution generated in the process of depositing the magnetic tunnel junction device layer of the wafer can be effectively removed after subsequent edge etching and back surface cleaning. The manufacturing method of the wafer and the wafer in the disclosure effectively remove the potential metal pollution generated in the MRAM forming process, and are very beneficial to the mass production and industrialization promotion of the MRAM.

As shown in fig. 4, a method for manufacturing a wafer according to an exemplary embodiment of the present disclosure includes the following steps:

s410, providing a wafer base, the wafer base including a substrate, and a transistor device layer disposed on the substrate.

In this step, as shown in fig. 9, the wafer base 100 includes a substrate 110 and a transistor device layer 300, and the substrate 110 may be made of a semiconductor material, which may be one or more of silicon, germanium, a silicon germanium compound, and a silicon carbon compound. A transistor device layer 300 is formed on the surface of the substrate 110, wherein the transistor device layer 300 includes a driving transistor, which may be an FDSOI driving transistor, a FinFET driving transistor, a GAA driving transistor, a HKMG/Poly SiON driving transistor, or the like.

S420, forming a first dielectric layer, wherein the first dielectric layer covers the back surface of the wafer substrate.

S430, forming a magnetic tunnel junction device layer on the front surface of the wafer substrate.

In this step, the magnetic tunnel junction device layer overlies the transistor device layer.

Steps S420 to S430 in this embodiment are the same as the implementation of steps S320 to S330 in the above embodiment, and are not described in detail here.

S440, etching the second dielectric layer and the magnetic tunnel junction device layer to expose a front side edge region of the substrate, and etching the first dielectric layer to expose a back side edge region of the substrate.

As shown in fig. 7, an enlarged view of the edge region 103 of the wafer substrate of fig. 6 is schematically illustrated. The Edge region 103 (Wafer Edge) of the Wafer substrate may include an upper Edge 1040 (Top Edge), a lower Edge 1041 (Bottom Edge), an upper Bevel 1042 (Top Edge), a lower Bevel 1043 (Bottom Edge), and a Top 1044 (Apex). As shown in fig. 13, after the initial wafer 10' is formed in step S430, the magnetic tunnel junction device layer 400 is also present at the edge region 104 of the initial wafer, in addition to covering the front region of the wafer substrate. As shown in fig. 14, an enlarged view of the edge region 104 of the initial wafer of fig. 13 is schematically illustrated. As shown in fig. 12-14, after deposition of the magnetic tunnel junction device layer 400 on the front side of the wafer substrate 100, the magnetic tunnel junction device layer 400 may occur in locations other than the front side region of the wafer substrate 100. For example, the magnetic tunnel junction device layer 400 may be present in the region of the edge region 104 of the initial wafer, such as at the location of the upper bevel 1042 of the wafer substrate, at the location of the lower bevel 1043 of the wafer substrate, and possibly at the location of the top 1044 of the wafer substrate, which may cause some metallic contaminants 400' formed from particles such as Ru, ir, pt and Pd to adhere to the edge region 104 of the initial wafer. Therefore, it is necessary to process the edge region of the initial wafer to effectively remove the metal contamination present on the surface of the initial wafer.

In this step, as shown in fig. 15, a schematic diagram of an etching tool for removing metal contamination existing at the edge of the initial wafer is exemplarily shown, and the etching tool 20 includes a plasma chamber 21. As shown in fig. 13-15, the initial wafer 10' may be placed in the etching station 20 and the edge of the initial wafer 10' is etched by the etching station 20, so that the metal contaminants 400' deposited on the edge region 104 of the initial wafer are effectively removed.

Fig. 16 is a schematic view schematically showing a structure in which an initial wafer is placed in a plasma chamber, and fig. 17 is an enlarged view schematically showing an edge region of the initial wafer in an etching machine. As shown in fig. 16-17, the plasma chamber 21 has an etching gas 22, an upper plate 23 and a lower plate 24, the upper plate 23 is opposite to the lower plate 24, the initial wafer 10' is located between the upper plate 23 and the lower plate 24, and the upper plate 23 covers a part of the front surface area of the initial wafer 10', exposing the front surface edge area of the initial wafer 10 '. The lower plate 24 covers a portion of the back surface area of the initial wafer 10 'exposing the back edge area of the initial wafer 10'. The etching gas 22 in the plasma chamber is located at the edge region of the initial wafer 10', and the etching region of the etching gas (plasma) 22 can be controlled by physically adjusting the upper plate 23 and the lower plate 24 to control the width of the front edge region of the initial wafer 10' to be etched and the width of the back edge region of the initial wafer 10 '.

As shown in fig. 18, an enlarged view of the edge region 104 of the initial wafer of fig. 17 is schematically illustrated after etching. As shown in fig. 18, since there is also a transistor device layer 300 on the front side of the initial wafer, the etched width of the front side edge region of the initial wafer 10' may be made different from the etched width of the back side edge region in order to ensure the integrity of the transistor device layer 300.

As shown in fig. 17 and 18, adjusting the upper plate 23 controls the etched width D1 of the front edge region of the initial wafer 10', and sequentially etches the second dielectric layer 500 and the magnetic tunnel junction device layer 400, exposing the front edge region of the substrate 110 with the width D1; the etched width D2 of the back edge region of the initial wafer 10' is controlled, and the first dielectric layer 200 is etched to expose the back edge region of the substrate 110 by the width D2. In one example, the etched width D1 of the front edge region of the initial wafer 10' is equal to the width D1 of the front edge region of the substrate 110, i.e., d1=d1; the width D2 of the etched back edge region of the initial wafer 10' is equal to the width D2 of the back edge region of the substrate 110, i.e., d2=d2.

In one example, the width D1 of the front edge region of the exposed substrate may be controlled to be greater than 1.0 mm and/or the width D2 of the back edge region of the exposed substrate may be controlled to be greater than 2.0 mm after the edge region of the initial wafer 10' is etched. For example, the width D1 of the front edge region of the substrate is 1.2 mm, and the width D2 of the back edge region of the substrate is 2.4 mm, which is not particularly limited herein. As shown in fig. 19, which schematically illustrates the initial wafer after the edge regions are etched, the front edge region of the exposed initial wafer 10' is smaller than the back edge region.

In this embodiment, in the case where the transistor device layer may be completely preserved, the second dielectric layer and the magnetic tunnel junction device layer in the front edge region of the initial wafer may be etched as completely as possible to remove the metal contamination existing in the front edge region of the initial wafer. While etching the front edge region of the initial wafer in the plasma chamber, a portion of the first dielectric layer located at the back edge of the initial wafer may also be etched to expose the back edge region of the substrate, so as to remove metal contamination present at the back edge region of the initial wafer.

In one example, when etching the edge region of the initial wafer, i.e., the second dielectric layer, the magnetic tunnel junction device layer, and/or the first dielectric layer, in the plasma chamber, the etching gas employed may comprise one or a combination of more of the following gases: argon (Ar), neon (Ne), krypton (Kr), xenon (Xe), carbon tetrafluoride (CF) ₄ ) Sulfur hexafluoride (SF) ₆ ) Nitrogen trifluoride (NF) ₃ ) Nitrogen (N) ₂ ) Methanol (CH) ₃ OH), ammonia (NH) ₃ ) Carbon monoxide (CO).

And S450, performing wet cleaning on the back surface of the first dielectric layer to obtain the wafer.

As shown in fig. 9, since the first dielectric layer (backside dielectric layer) 200 is previously deposited on the backside 101 (shown in fig. 6) of the wafer substrate before the formation of the magnetic tunnel junction device layer 400, a metal silicide that exists in a chemisorbed manner is not generated on the backside of the initial wafer 10'. As shown in fig. 19, a schematic diagram of metal contamination still present on the back side of the first dielectric layer after edge etching of the initial wafer 10' is exemplarily shown. Since some of the metal contaminants 400 'formed by the particles such as Ru, ir, pt and Pd are adsorbed on the back surface of the initial wafer by van der waals force after the magnetic tunnel junction device layer 400 is formed, that is, the metal contaminants 400' may be physically adsorbed on the back surface of the first dielectric layer 200, the back surface of the first dielectric layer 200 needs to be cleaned. In this step, the back surface of the first dielectric layer may be treated in a wet cleaning manner to effectively remove the metal contaminants adsorbed on the back surface of the first dielectric layer.

As shown in fig. 20, a schematic view of a cleaning apparatus for removing metal contamination existing on the back surface of the first dielectric layer is exemplarily shown, and the cleaning apparatus may be a cleaning machine 30, in which a plurality of cleaning chambers 31 are provided in the cleaning machine 30 at intervals in a lateral direction and a longitudinal direction, respectively. As shown in fig. 19 and 20, after the edge etching of the initial wafer 10 'is completed, the initial wafer 10' is then placed into the cleaning chamber 31 of the cleaning machine 30 to clean the surface of the first dielectric layer on the back surface of the initial wafer.

As shown in fig. 21, a schematic view of the structure of an initial wafer in contact with a chuck in a cleaning station is schematically shown. As shown in fig. 20 and 21, the cleaning apparatus 30 may fix the initial wafer 10' by using the chuck 32, and the cleaning apparatus 30 may be controlled to clean the back surface 201 of the first dielectric layer by using a cleaning solution (or etching solution), so that metal contaminants deposited on the back surface 201 of the first dielectric layer are effectively removed, thereby obtaining the wafer 10 with metal contaminants removed from the surface, as shown in fig. 25.

In one example, the back side of the first dielectric layer may be wet cleaned using a cleaning solution or etching solution as a cleaning medium, wherein the cleaning medium used for cleaning comprises one or more of the following combinations: sulfuric acid (H) ₂ SO ₄ ) Hydrogen Fluoride (HF), hydrogen chloride (HCl), nitric acid (HNO) ₃ ) Ozonized deionized water (DIO) ₃ ) Water (H) ₂ O), magnesium (Mg), titanium (Ti), vanadium (V), chromium (Cr), iron (Fe), cobalt (Co), niobium (Nb), hafnium (hf) which may be present on the back surface 201 of the first dielectric layer may be washed with a washing solution formed of one or a combination of the above substances(Hf), tantalum (Ta), molybdenum (Mo), tungsten (W), nickel (Ni) and the like, and a trace amount of metal element substances.

In one example, ceric ammonium nitrate [ (NH) may also be used for particles such as ruthenium (Ru), iridium (Ir), palladium (Pd), and platinum (Pt) adsorbed on the back surface of the first dielectric layer and traces of metal elements ₄ ) ₂ Ce(NO ₃ ) ₆ ]And/or nitric acid (HNO) ₃ ) The solution is directly melted off to clean the back surface of the first dielectric layer.

According to an exemplary embodiment of the present disclosure, most of the contents of the present embodiment are the same as those of the foregoing embodiments, and the difference between the present embodiment and the foregoing embodiments is that, referring to fig. 5, the method provided in the present embodiment mainly describes another alternative implementation manner of cleaning the back surface of the first dielectric layer on the basis of the method shown in fig. 4. As shown in fig. 5, the method of the present embodiment may include:

And S510, etching the back surface of the first dielectric layer by adopting an undercut process.

FIG. 22 schematically illustrates an enlarged view of A in FIG. 21, as shown in FIG. 22, with metal contaminants 400' passing through Van der Waals forces F _vdw Adsorbed on the back surface 201 of the first dielectric layer, the etching solution 33 is soaked on the back surface 201 of the first dielectric layer to surround the metal contaminant 400', and the back surface 201 of the first dielectric layer can be etched by using an undercut-Cut process to reduce van der Waals forces of physical adsorption of particles, as shown in FIG. 23, which shows a schematic view of the structure of FIG. 22 after the undercut process, wherein F _vdw1 Less than F _vdw 。

Wherein F is _vdw ＝A ₁₂₃ Rp/(6H ₀ ) ² Wherein A is ₁₂₃ Rp is the radius of the particulate matter (metal contaminant), H, which is the Hamaker constant of the system ₀ Is the distance of the particles from the surface of the first dielectric 201.

In one example, the etching solution employed in the undercut process includes a combination of one or more of the following: sulfuric acid (H) ₂ SO ₄ ) Hydrogen Fluoride (HF), hydrogen chloride (HCl), nitric acid (HNO) ₃ ) Ozonized deionized water (DIO) ₃ ) Water (H) ₂ O)。

And S520, cleaning the first dielectric layer subjected to the undercut process by adopting a jet flow jet physical removal process to obtain the wafer.

In the step, a Jet-Spray (Jet-Spray) physical removal process is utilized to physically remove particles and trace amounts of metal elements on the back surface of the first dielectric layer which are subjected to an undercut process, so that metal pollution on the surface of the wafer is comprehensively and effectively cleaned, and the cleanliness of the surface of the wafer is improved.

As shown in fig. 24, the Jet-Spray physical removal process continues to treat the back surface of the first dielectric layer subjected to the undercut process to remove the metal contaminant 400' on the surface of the first dielectric layer 201 using the liquid ejected from the nozzle at a high speed. Wherein F is _d ＝C _d PπR _p ，F _d C is the Drag Force (dragforce) applied to the particulate matter _d Is F _d Coefficient, P is the percussion pressure, P is the fluid velocity, V _f In relation, rp is the radius of the particulate matter (metal contaminants).

In one example, the jet physical removal process may be implemented using a combination of deionized water and nitrogen, and/or a combination of isopropyl alcohol and nitrogen.

In this embodiment, during the process of the wafer manufacturing method, etching is performed on the edge area of the initial wafer, and cleaning is continuously performed on the back surface of the initial wafer, so as to gradually remove potential metal contamination adsorbed on the back surface of the initial wafer, effectively control the problem of metal contamination of the wafer, improve the yield of the wafer, and facilitate large-scale mass production of MRAM.

In one example, after cleaning the back side of the first dielectric layer, further comprising: the second dielectric layer is removed in preparation for implementation of a subsequent process.

In an exemplary embodiment of the present disclosure, as shown in fig. 25, there is provided a wafer including:

the wafer body comprises a wafer substrate 100, a magnetic tunnel junction device layer 400 and a second dielectric layer 500 which are stacked;

a first dielectric layer 200, the first dielectric layer 200 being located on the back surface of the wafer substrate 100;

the first dielectric layer 200 covers a portion of the back surface of the wafer substrate 100 and exposes a back surface edge region of the wafer substrate 100.

In one example, the material of the magnetic tunnel junction device layer includes some or all of the following elements: nitrogen, oxygen, boron, magnesium, ruthenium, tungsten, titanium, tantalum, iron, cobalt, nickel, vanadium, niobium, chromium, platinum, iridium, molybdenum, hafnium, palladium.

In one example, the material of the first dielectric layer includes silicon oxide, silicon oxynitride, silicon nitride, and silicon carbide; and/or the material of the second dielectric layer includes silicon oxide, silicon oxynitride, silicon nitride, and silicon carbide.

In one example, as shown in fig. 25, the wafer base 100 includes a substrate 110 and a transistor device layer 300 disposed on the substrate 110, the magnetic tunnel junction device layer 400 overlying the transistor device layer 300, and the second dielectric layer 500 overlying the magnetic tunnel junction device layer 400.

According to the wafer provided by the embodiment of the disclosure, the first dielectric layer is formed on the back surface of the wafer substrate, so that the chemical adsorption generated by metal pollution on the back surface of the wafer substrate is thoroughly avoided, and the cleanliness of the wafer surface is improved.

In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

In the description of the present specification, descriptions of the terms "example," "exemplary embodiment," "some embodiments," "illustrative embodiments," "examples," and the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.

It will be understood that the terms "first," "second," and the like, as used in this disclosure, may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another structure.

In one or more of the drawings, like elements are referred to by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The structure obtained after several steps may be depicted in one figure for simplicity. Numerous specific details of the present disclosure, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. The manufacturing method of the wafer is characterized by comprising the following steps of:

providing a wafer substrate;

2. The method of claim 1, wherein the wafer base comprises a substrate and a transistor device layer disposed on the substrate, the first dielectric layer overlying a backside of the substrate, the magnetic tunnel junction device layer overlying the transistor device layer;

3. The method of claim 2, wherein the width of the front edge region of the substrate is greater than 1.0 mm; and/or the number of the groups of groups,

4. The method of claim 2, wherein the etching gas used to etch the second dielectric layer, the magnetic tunnel junction device layer, and/or the first dielectric layer comprises one or more of the following gases:

5. The method of claim 2, wherein after the etching the second dielectric layer and the magnetic tunnel junction device layer to expose a front side edge region of the substrate and etching the first dielectric layer to expose a back side edge region of the substrate, the performing edge etching and back side cleaning on the initial wafer further comprises:

6. The method of claim 5, wherein the cleaning medium used for wet cleaning the back surface of the first dielectric layer comprises one or more of the following:

7. The method of manufacturing a wafer as set forth in claim 5, further comprising:

8. The method of claim 7, wherein the etching solution used in the undercut process comprises one or more of the following:

9. The method of claim 5, wherein wet cleaning the back surface of the first dielectric layer comprises:

10. The method of any one of claims 1 to 9, wherein the material of the first dielectric layer comprises silicon oxide, silicon oxynitride, silicon nitride, and silicon carbide; and/or the number of the groups of groups,

11. The method of any one of claims 1 to 9, wherein the material of the magnetic tunnel junction device layer comprises some or all of the following elements:

12. A wafer, the wafer comprising:

a first dielectric layer located on the back side of the wafer substrate;

13. The wafer of claim 12, wherein the material of the magnetic tunnel junction device layer comprises some or all of the following elements:

14. The wafer of claim 12 or 13, wherein the material of the first dielectric layer comprises silicon oxide, silicon oxynitride, silicon nitride, and silicon carbide; and/or the number of the groups of groups,

15. The wafer of claim 12, wherein the wafer base comprises a substrate, and a transistor device layer disposed on the substrate, the magnetic tunnel junction device layer overlying the transistor device layer, the second dielectric layer overlying the magnetic tunnel junction device layer.