CN116981253A - Method for preparing semiconductor structure and semiconductor structure - Google Patents
Method for preparing semiconductor structure and semiconductor structure Download PDFInfo
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- CN116981253A CN116981253A CN202310998072.9A CN202310998072A CN116981253A CN 116981253 A CN116981253 A CN 116981253A CN 202310998072 A CN202310998072 A CN 202310998072A CN 116981253 A CN116981253 A CN 116981253A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 37
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- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims description 133
- 238000000151 deposition Methods 0.000 claims description 110
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 102
- 230000008021 deposition Effects 0.000 claims description 79
- 229910052757 nitrogen Inorganic materials 0.000 claims description 51
- 239000007789 gas Substances 0.000 claims description 47
- 239000000463 material Substances 0.000 claims description 47
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 34
- 239000000460 chlorine Substances 0.000 claims description 34
- 229910052801 chlorine Inorganic materials 0.000 claims description 34
- 230000008569 process Effects 0.000 claims description 18
- 238000000231 atomic layer deposition Methods 0.000 claims description 15
- 238000000137 annealing Methods 0.000 claims description 11
- 239000002131 composite material Substances 0.000 claims description 11
- 238000013329 compounding Methods 0.000 claims description 6
- 238000005121 nitriding Methods 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 238000002360 preparation method Methods 0.000 abstract description 6
- 238000002955 isolation Methods 0.000 description 15
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 11
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- 229910052710 silicon Inorganic materials 0.000 description 3
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- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 3
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- 229910052719 titanium Inorganic materials 0.000 description 2
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- 238000013022 venting Methods 0.000 description 2
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- 239000012535 impurity Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 229910000457 iridium oxide Inorganic materials 0.000 description 1
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- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure, the method for manufacturing a semiconductor structure includes providing a substrate, the substrate including a plurality of active regions arranged at intervals, a plurality of word line trenches arranged at intervals being provided in the substrate, the word line trenches exposing the active regions; forming a gate dielectric layer, a first conductive layer and a second conductive layer, wherein the gate dielectric layer covers the groove wall of the word line groove, the first conductive layer is positioned on the gate dielectric layer, and the second conductive layer is positioned on the first conductive layer; the first conductive layer and the second conductive layer form a word line together, and the stress of the first conductive layer is larger than that of the second conductive layer. Because the stress of the second conductive layer is smaller than that of the first conductive layer, the deformation of the word line is relieved, and the influence on the performance of the word line and the DRAM is reduced. Therefore, the preparation method of the semiconductor structure and the semiconductor structure can relieve the deformation of the word line and improve the performances of the word line and the DRAM.
Description
Technical Field
The disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the same.
Background
A dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM) is a semiconductor memory that randomly writes and reads data at high speed, and is widely used in data storage devices or apparatuses.
In the related art, a DRAM may include a substrate on which a plurality of repeated memory cells are disposed. Each memory cell may include a transistor having a gate connected to a word line, a source connected to a bit line, and a drain connected to a capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading the data information stored in the capacitor through the bit line or writing the data information into the capacitor through the bit line for storage.
However, the word lines described above are susceptible to deformation, thereby adversely affecting the performance of the word lines and the DRAM.
Disclosure of Invention
The embodiment of the disclosure provides a preparation method of a semiconductor structure and the semiconductor structure, which can relieve the deformation of a word line and improve the performances of the word line and a DRAM.
A first aspect of an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate, wherein the substrate comprises a plurality of active areas which are arranged at intervals, a plurality of word line grooves which are arranged at intervals are formed in the substrate, and the active areas are exposed by the word line grooves; forming a gate dielectric layer, a first conductive layer and a second conductive layer, wherein the gate dielectric layer covers the groove wall of the word line groove, the first conductive layer is positioned on the gate dielectric layer, and the second conductive layer is positioned on the first conductive layer; the first conductive layer and the second conductive layer form a word line together, and the stress of the first conductive layer is larger than that of the second conductive layer.
The method for manufacturing the semiconductor structure provided by the embodiment of the disclosure may include providing a substrate, wherein the substrate includes a plurality of active regions arranged at intervals, a plurality of word line trenches arranged at intervals are formed in the substrate, and the word line trenches expose the active regions; forming a gate dielectric layer, a first conductive layer and a second conductive layer, wherein the gate dielectric layer covers the groove wall of the word line groove, the first conductive layer is positioned on the gate dielectric layer, and the second conductive layer is positioned on the first conductive layer; the first conductive layer and the second conductive layer form a word line together, and the stress of the first conductive layer is larger than that of the second conductive layer. The stress of the second conductive layer is smaller than that of the first conductive layer, namely the stress of the second conductive material layer is smaller than that of the first conductive material layer, so that the stress of the word line material layer is smaller, the deformation of the word line material layer caused by the stress of the word line material layer can be relieved, the deformation of the word line is relieved, the influence on the performance of the word line and the DRAM is reduced, and the product yield is improved.
In one possible embodiment, forming the first conductive layer and the second conductive layer includes:
depositing a first conductive material layer, wherein the first conductive material layer covers the top of the gate dielectric layer and the substrate positioned in the word line trench;
Depositing a second conductive material layer, wherein the second conductive material layer is positioned on the first conductive material layer, and the word line groove is filled with the second conductive material layer;
and removing a part of the first conductive material layer and a part of the second conductive material layer, wherein the reserved first conductive material layer forms a first conductive layer, and the reserved second conductive material layer forms a second conductive layer.
In one possible embodiment, the method of depositing the first conductive material layer comprises atomic layer deposition;
and/or, the method of depositing the second conductive material layer includes continuous flow deposition;
and/or the deposition temperature of the first conductive material layer is greater than the deposition temperature of the second conductive material layer;
and/or, the deposition temperature at which the first conductive material layer is deposited ranges from 500 ℃ to 800 ℃;
and/or the deposition temperature at which the second conductive material layer is deposited is in the range of 350 ℃ to 600 ℃.
By adopting a mixed deposition mode of atomic layer deposition and continuous flow deposition to respectively deposit a first conductive layer and a second conductive layer, the chlorine content of the formed first conductive layer is smaller than that of the second conductive layer, so that the resistivity of the first conductive layer is smaller than that of the second conductive layer, and the stress of the second conductive layer is smaller than that of the first conductive layer, thereby simultaneously reducing the resistivity of the word line and relieving the deformation of the word line.
In one possible embodiment, after forming the first conductive layer and the second conductive layer, the method includes:
nitriding the second conductive layer to form a nitrided conductive layer,
wherein the chlorine content of the nitrided conductive layer is less than the chlorine content of the second conductive layer, and the resistivity of the nitrided conductive layer is less than the resistivity of the second conductive layer.
The chlorine content of the second conductive layer can be reduced by nitriding to reduce the resistivity of the second conductive layer, thereby reducing the resistivity of the word line.
In one possible embodiment, the nitridation process comprises remote plasma nitridation.
In one possible embodiment, before forming the first conductive layer and the second conductive layer, the method includes: placing a substrate in a deposition chamber;
depositing a first layer of conductive material includes: performing a first composite operation in a plurality of cycles, the first composite operation comprising: providing a first metal source to the deposition chamber to form a first metal source layer on top of the gate dielectric layer of the word line trench and the substrate;
first exhausting the gas in the deposition chamber;
providing a first nitrogen source to the deposition chamber, the first nitrogen source reacting with the first metal source layer to form a first conductive material layer;
the gas in the deposition chamber is exhausted a second time.
In one possible embodiment, depositing the second layer of conductive material comprises:
performing a second composite operation in a plurality of cycles, the second composite operation comprising:
simultaneously providing a second metal source and a second nitrogen source to the deposition chamber to form a second conductive material layer;
third exhausting the gas in the deposition chamber;
providing a second nitrogen source to the deposition chamber again, and annealing the second conductive material layer;
and exhausting the gas in the deposition chamber for the fourth time.
In one possible embodiment, the time for providing the first metal source ranges from 0.02s to 0.08s;
and/or the time of the first discharge is in the range of 0.1s to 0.3s;
and/or providing the first nitrogen source and the second discharge for a time in the range of 0.2s to 0.5s;
and/or providing the second metal source and the second nitrogen source, the third bleed and the fourth bleed for a time in the range of 10s to 15s;
and/or, the second nitrogen source is again provided for a time in the range of 30s to 50s;
and/or providing a gas flow rate of the first metal source in the range of 80sccm to 150sccm;
and/or providing a first nitrogen source, a first bleed and a second bleed at a gas flow rate in the range of 3000sccm to 5000sccm;
and/or providing a gas flow rate of the second metal source in the range of 50sccm to 1500sccm;
And/or providing a second nitrogen source, a third bleed, a fourth bleed, and a second nitrogen source again at a gas flow rate in the range of 500sccm to 3000sccm;
and/or depositing the first conductive material layer and depositing the second conductive material layer at a deposition pressure in the range of 5torr to 6torr;
and/or the number of cycles of the first compounding operation ranges from 100 times to 200 times;
and/or the number of cycles of the second compounding operation ranges from 15 times to 20 times.
A second aspect of embodiments of the present disclosure provides a semiconductor structure comprising: the semiconductor device comprises a substrate, a gate dielectric layer and word lines, wherein the substrate comprises a plurality of active areas which are arranged at intervals, and a plurality of word line grooves which are arranged at intervals are formed in the substrate and expose the active areas; the gate dielectric layer covers the groove wall of the word line groove, the word line comprises a first conductive layer and a second conductive layer, the first conductive layer is located on the gate dielectric layer, the second conductive layer is located on the first conductive layer, and the stress of the first conductive layer is larger than that of the second conductive layer.
The semiconductor structure provided by the embodiment of the disclosure may include a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer, where the substrate includes a plurality of active regions arranged at intervals, and a plurality of word line trenches arranged at intervals are formed in the substrate, and the word line trenches expose the active regions; the gate dielectric layer covers the groove wall of the word line groove, the first conductive layer is positioned on the gate dielectric layer, and the second conductive layer is positioned on the first conductive layer; the first conductive layer and the second conductive layer form a word line together, and the stress of the first conductive layer is larger than that of the second conductive layer. The stress of the second conductive layer is smaller than that of the first conductive layer, namely the stress of the second conductive material layer is smaller than that of the first conductive material layer, so that the stress of the word line material layer is smaller, the deformation of the word line material layer caused by the stress of the word line material layer can be relieved, the deformation of the word line is relieved, the influence on the performance of the word line and the DRAM is reduced, and the product yield is improved.
In one possible embodiment, the material of the first conductive layer and/or the material of the second conductive layer comprises a metal nitride;
and/or the resistivity of the first conductive layer is less than the resistivity of the second conductive layer;
and/or the chlorine content of the first conductive layer is smaller than the chlorine content of the second conductive layer;
and/or the first conductive layer has a chlorine content in the range of 1% -5%;
and/or the chlorine content of the second conductive layer is in the range of 10% -20%.
The chlorine content of the formed first conductive layer is smaller than that of the second conductive layer, so that the resistivity of the first conductive layer is smaller than that of the second conductive layer, and the stress of the second conductive layer is smaller than that of the first conductive layer, thereby simultaneously reducing the resistivity of the word line and relieving the deformation of the word line.
The construction of the present disclosure, together with other objects and advantages thereof, will be best understood from the following description of the preferred embodiments when read in connection with the accompanying drawings.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;
fig. 2 is a schematic structural diagram of a substrate provided in an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a gate dielectric layer, a first conductive material layer, and a second conductive material layer after forming according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a structure after forming word lines according to an embodiment of the present disclosure;
FIG. 5a is a scanning electron microscope image of a word line of experimental example one;
FIG. 5b is a scanning electron microscope image of a word line of experimental example two;
FIG. 6 is a box plot between the IMB of a word line and the preparation temperature of a second conductive material layer provided by embodiments of the present disclosure;
FIG. 7 is a schematic illustration of a reaction for depositing a first conductive material layer provided by an embodiment of the present disclosure;
fig. 8 is a schematic diagram of a reaction for depositing a second conductive material layer provided in an embodiment of the present disclosure.
Reference numerals illustrate:
100: a semiconductor structure; 110: a substrate;
111: an active region; 112: an isolation structure;
113: word line trenches; 120: an isolation layer;
130: a gate dielectric layer; 140: a word line;
140a: a word line material layer; 141: a first conductive layer;
141a: a first conductive material layer; 142: a second conductive layer;
142a: and a second conductive material layer.
Detailed Description
In the related art, in a memory employing buried word lines, a DRAM may include a substrate in which word line trenches are provided. In the process of preparing the word line, a gate oxide layer may be formed on the wall of the word line trench, a word line material layer may be formed on the gate oxide layer, and the word line material layer fills the word line trench. Then, the word line material layer is etched, the word line material layer on the top of the substrate is completely removed, and part of the word line material layer in the word line trench is removed, and the remaining word line material layer in the word line trench forms a buried word line. The material of the word line material layer may include titanium nitride (TiN), and the forming method of the word line material layer may include atomic layer deposition (atomic layer deposition, abbreviated as ALD), which has a better step coverage rate.
However, due to the higher deposition temperature of the atomic layer deposition, the formed word line material layer is denser, resulting in greater stress (stress) of the word line material layer, and in addition, as the line width of the transistor becomes smaller, the aspect ratio of the word line trench is greater, the stress of the word line material layer easily causes deformation (such as bending, uneven height, etc.) of the word line material layer, thereby causing deformation of the word line, affecting the performance of the word line and the DRAM, and possibly even affecting the product yield.
The embodiment of the disclosure provides a preparation method of a semiconductor structure and the semiconductor structure, the preparation method of the semiconductor structure can comprise the steps of providing a substrate, wherein the substrate comprises a plurality of active areas which are arranged at intervals, a plurality of word line grooves which are arranged at intervals are formed in the substrate, and the active areas are exposed by the word line grooves; forming a gate dielectric layer, a first conductive layer and a second conductive layer, wherein the gate dielectric layer covers the groove wall of the word line groove, the first conductive layer is positioned on the gate dielectric layer, and the second conductive layer is positioned on the first conductive layer; the first conductive layer and the second conductive layer form a word line together, and the stress of the first conductive layer is larger than that of the second conductive layer. The stress of the second conductive layer is smaller than that of the first conductive layer, namely the stress of the second conductive material layer is smaller than that of the first conductive material layer, so that the stress of the word line material layer is smaller, the deformation of the word line material layer caused by the stress of the word line material layer can be relieved, the deformation of the word line is relieved, the influence on the performance of the word line and the DRAM is reduced, and the product yield is improved.
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
A method for fabricating the semiconductor structure 100 according to the embodiments of the present disclosure will be described below with reference to fig. 1 to 8. Referring to fig. 1, the preparation method may include:
s100: a substrate is provided, wherein the substrate comprises a plurality of active areas which are arranged at intervals, a plurality of word line grooves which are arranged at intervals are formed in the substrate, and the active areas are exposed by the word line grooves.
Referring to fig. 2, first, a substrate 110 is provided. The material of the substrate 110 may include a semiconductor material. The substrate 110 may provide a support foundation for other structural layers on the substrate 110.
The substrate 110 may be provided therein with an isolation structure 112 and a plurality of active regions 111, the plurality of active regions 111 being disposed in the substrate 110 at intervals, and the isolation structure 112 may be used to isolate two adjacent active regions 111. Active region 111 may be used to form a transistor.
The material of the substrate 110 may include, but is not limited to, any one or more of monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium compounds, gallium arsenic compounds, gallium phosphorous compounds, gallium sulfur compounds, and the like, or other materials known to those skilled in the art. The substrate 110 may be a Bulk Silicon (SOI) substrate or a Silicon-on-insulator (Silicon On Insulator, SOI) substrate.
Referring to fig. 2, the process of providing the substrate 110 may include depositing an isolation layer 120 on the substrate 110, and then etching a portion of the isolation layer 120 and a portion of the substrate 110 to form a plurality of word line trenches 113 in the isolation layer 120 and the substrate 110, the word line trenches 113 exposing the active region 111, and the remaining isolation layer 120 may form protection for the substrate 110 covered thereby.
By way of example, the deposition process may include an atomic layer deposition process, a physical vapor deposition process (physical vapor deposition, PVD for short), a chemical vapor deposition process (chemical vapor deposition, CVD for short), or the like. Other structural layers in the embodiments of the present disclosure may also be formed by deposition, which is not described herein. The etching in the embodiments of the present disclosure may include dry etching or wet etching.
S200: forming a gate dielectric layer, a first conductive layer and a second conductive layer, wherein the gate dielectric layer covers the groove wall of the word line groove, the first conductive layer is positioned on the gate dielectric layer, and the second conductive layer is positioned on the first conductive layer; the first conductive layer and the second conductive layer form a word line together, and the stress of the first conductive layer is larger than that of the second conductive layer.
Referring to fig. 4, after forming the word line trench 113, it may include: the gate dielectric layer 130 is formed, and the gate dielectric layer 130 may cover the walls of the word line trenches 113, and the gate dielectric layer 130 may cover at least a portion of the bottom walls of the word line trenches 113 and/or cover at least a portion of the side walls of the word line trenches 113. In other examples, gate dielectric layer 130 may also cover the top of substrate 110, e.g., gate dielectric layer 130 may cover the top surface of spacer layer 120. The embodiments of the present application are described taking the example where the gate dielectric layer 130 covers the walls of the word line trenches 113 and the top of the substrate 110.
For example, the material of the gate dielectric layer 130 may be oxide, and the gate dielectric layer 130 may be formed by oxidation growth, deposition, or the like.
Referring to fig. 4, after forming the gate dielectric layer 130, forming the first conductive layer 141 and the second conductive layer 142 may include forming the first conductive layer 141 to be located on the gate dielectric layer 130 and the second conductive layer 142 to be located on the first conductive layer 141; wherein the first conductive layer 141 and the second conductive layer 142 may be used together to form a target structural layer, for example, the target structural layer may be the word line 140, and the stress of the first conductive layer 141 may be greater than that of the second conductive layer 142. By this arrangement, since the stress of the second conductive layer 142 is smaller than that of the first conductive layer 141, that is, the stress of the second conductive material layer 142a (fig. 3) is smaller than that of the first conductive material layer 141a (fig. 3), the stress of the word line material layer 140a (fig. 3) can be made smaller, the deformation of the word line material layer 140a caused by the stress of the word line material layer 140a can be relieved, the deformation of the word line 140 can be relieved, the influence on the performance of the word line 140 and DRAM can be reduced, and the yield of the product can be improved.
Referring to fig. 3, forming the first and second conductive layers 141 and 142 may include depositing a first conductive material layer 141a on a surface of the gate dielectric layer 130 of the word line trench 113 and a top of the substrate 110, and in an embodiment in which the gate dielectric layer 130 is disposed on top of the substrate 110, the first conductive material layer 141a may cover a surface of the gate dielectric layer 130 in the word line trench 113 and a top surface of the gate dielectric layer 130 on top of the substrate 110, for example, the first conductive material layer 141a may not fill the word line trench 113. The thickness of the first conductive material layer 141a located in the word line trench 113 may be set smaller. Since the stress of the first conductive material layer 141a is large, the deformation of the word line 140 due to the stress of the first conductive material layer 141a can be relieved when the thickness of the first conductive material layer 141a is set small. Then, a second conductive material layer 142a is deposited on the first conductive material layer 141a, for example, the second conductive material layer 142a may fill the word line trench 113. The thickness of the second conductive material layer 142a located in the word line trench 113 may be set to be large. Since the second conductive material layer 142a has a smaller stress, it does not cause the word line 140 to deform, and the stress of the word line material layer 140a can be reduced by providing the second conductive material layer 142a to relieve the deformation of the word line 140 caused by the stress of the word line material layer 140 a. Then, referring to fig. 4, a partial thickness of the first conductive material layer 141a and a partial thickness of the second conductive material layer 142a are removed, the remaining first conductive material layer 141a may form the first conductive layer 141, and the remaining second conductive material layer 142a may form the second conductive layer 142.
For example, the material of the first conductive layer 141 and/or the second conductive layer 142 may include at least one of a metal such as tantalum, titanium, nickel, cobalt, platinum, tungsten, ruthenium, iridium, etc., a metal compound (metal nitride, metal oxide, etc.) such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium oxide, iridium oxide, a semiconductor material such as silicon, germanium, etc. The materials of the first conductive layer 141 and the second conductive layer 142 may be the same or different
The embodiment of the present application is described taking titanium nitride as an example of the first conductive layer 141 and the second conductive layer 142.
The materials of the first conductive layer 141 and the second conductive layer 142 may be the same, and the first conductive layer 141 and the second conductive layer 142 may be formed by different process conditions, and the material characteristics of the first conductive layer 141 and the second conductive layer 142 may be different. For example, the method of depositing the first conductive material layer 141a may include atomic layer deposition having excellent deposition uniformity, and high controllability. The method of depositing the second conductive material layer 142a may include chemical vapor deposition, which has an advantage of a high deposition rate, for example, chemical vapor deposition may include continuous flow deposition (sequential flow deposition, abbreviated as SFD). Wherein the deposition process may be performed in a deposition chamber, i.e., the substrate 110 may be placed in the deposition chamber to deposit various film layers on the substrate 110.
In the process of depositing titanium nitride, a titanium source (e.g., titanium tetrachloride TiCl 4 ) And a nitrogen source (e.g., ammonia NH 3 ) To collectively form titanium nitride. The properties of the deposited titanium nitride may be different at different deposition temperatures, for example, the chlorine content in the titanium nitride may be different. Wherein, when the deposition temperature is higher, the titanium tetrachloride and ammonia react more completely, the chlorine content is lower, the film layer of the titanium nitride is more compact, and the stress is larger. The lower the deposition temperature, the less complete the reaction of titanium tetrachloride and ammonia, the higher the chlorine content, resulting in a looser film of titanium nitride, less stress, and, in addition, the lower the purity of titanium nitride, resulting in a greater resistance of titanium nitride, when the chlorine content is higher.
Illustratively, the deposition temperature of the first conductive material layer 141a may be greater than the deposition temperature of the second conductive material layer 142a, for example, the atomic layer deposition temperature may be greater than the continuous flow deposition temperature, and the first conductive material layer 141a may be deposited by atomic layer deposition, which may result in a lower chlorine content in the first conductive material layer 141a, which is beneficial for reducing the resistivity of the first conductive material layer 141a, while resulting in a higher stress of the first conductive material layer 141a, which may easily result in deformation of the word line 140 if the first conductive material layer 141a is deposited too thick. Therefore, the embodiment of the disclosure forms the second conductive material layer 142a by using continuous flow deposition with a lower temperature, so that the stress of the second conductive material layer 142a is lower, the second conductive material layer 142a does not cause the deformation of the word line 140, and the thickness of the first conductive material layer 141a can be set smaller by forming the second conductive material layer 142a, so that the deformation of the word line 140 caused by the stress of the first conductive material layer 141a can be relieved, that is, the deformation of the word line 140 caused by the stress of the word line material layer 140a can be relieved. That is, the embodiment of the present disclosure may simultaneously reduce the resistivity of the word line 140 and alleviate the deformation of the word line 140 by depositing the first conductive layer 141 and the second conductive layer 142 by means of a mixed deposition of atomic layer deposition and continuous flow deposition, respectively, such that the chlorine content of the first conductive layer 141 is less than the chlorine content of the second conductive layer 142, such that the resistivity of the first conductive layer 141 is less than the resistivity of the second conductive layer 142, and the stress of the second conductive layer 142 is less than the stress of the first conductive layer 141. In addition, since the first conductive layer 141 is closer to the channel structure of the active region 111 than the second conductive layer 142, the first conductive layer 141 has a greater influence on the gate control capability of the transistor, and is advantageous for improving the electrical performance of the transistor when the resistivity of the first conductive layer 141 is smaller. Second, the first conductive layer 141 is dense, so that it has good adhesion, thermal stability and diffusion barrier.
Fig. 5a is a scanning electron microscope image of the word line 140 of experimental example one, in which the first conductive material layer is formed using ALD at 600 c and the second conductive material layer is formed using SFD at 450 c. Fig. 5b is a scanning electron microscope image of the word line 140 of the second experimental example, in which the first conductive material layer and the second conductive material layer are formed by ALD at 600 ℃. The distance d (e.g., d1, d2, and d 3) between two adjacent word lines 140 is relatively close to each other, and d1, d2, and d3 in fig. 5a indicate that the distance between two adjacent word lines 140 is relatively uniform, and the bending degree of the word lines 140 is relatively small, i.e., the bending phenomenon of the word lines 140 can be improved by forming the second conductive material layer using SFD with relatively low temperature. In fig. 5b, the difference between d1, d2 and d3 is larger, which indicates that the uniformity of the distance between two adjacent word lines 140 is worse, and the bending degree of the word lines 140 is larger, that is, the bending phenomenon of the word lines 140 is worse due to the second conductive material layer formed by ALD. For example, forming the second conductive material layer using SFD at a lower temperature may improve the bending phenomenon of the word line 140 by about 30%.
In addition, fig. 6 is a box diagram drawn after measuring the IMB (i.e., height unevenness) of the word line a plurality of times when the deposition temperature of the second conductive material layer is 450 ℃, 530 ℃ and 640 ℃, respectively. As can be seen from fig. 6, when the deposition temperature of the second conductive material layer is 640 ℃, the average value of IMB is 0.79685, when the deposition temperature of the second conductive material layer is 530 ℃, the average value of IMB is 0.48795, and when the deposition temperature of the second conductive material layer is 450 ℃, the average value of IMB is 0.33311. The phenomenon of the uneven height of the word line 140 may be improved by 38.7% and 58% when the deposition temperature of the second conductive material layer is reduced from 640 ℃ to 530 ℃ and 450 ℃ respectively.
The deposition of the first conductive material layer 141a provided by embodiments of the present disclosure is described below.
Referring to fig. 3 and 7, depositing the first conductive material layer 141a (i.e., ALD-TiN) may include performing a first recombination operation in a plurality of cycles, the first recombination operation may include: a first metal source (i.e., tiCl 4 ) To form a first metal source layer on top of the gate dielectric layer 130 of the wordline trench 113 and the substrate 110. Then, the gas in the deposition chamber is exhausted (i.e. purge 1) for the first time, so as to avoid adverse effects of the gas in the deposition chamber on the subsequent reaction of the first nitrogen source and the first metal source layer. A first nitrogen source (i.e., NH 3 ) The first nitrogen source may react with the first metal source layer to form the first conductive material layer 141a (i.e., tiN), and then the gas in the deposition chamber is exhausted (i.e., purge 2) for a second time to avoid the gas in the deposition chamber from adversely affecting the subsequent first recombination operation. ProvidingThe first metal source, the first bleed, the providing of the first nitrogen source, and the second bleed may together form a first compound operation.
The deposition of the second conductive material layer 142a provided by embodiments of the present disclosure is described below.
Referring to fig. 3 and 8, depositing the second conductive material layer 142a (i.e., SFD-TiN) may include performing a second recombination operation over a plurality of cycles, the second recombination operation may include simultaneously providing a second metal source and a second nitrogen source (i.e., tiCl 4 +NH 3 ) To deposit the second conductive material layer 142a (i.e., tiN), then third exhausting (i.e., purge 3) the gas in the deposition chamber to avoid the gas in the deposition chamber from adversely affecting the subsequent annealing process, and then providing a second nitrogen source (i.e., NH) to the deposition chamber again 3 ) And annealing (annealing) the second conductive material layer 142a, wherein the annealing may repair the lattice of the second conductive material layer 142a, and since the annealing is performed in the second nitrogen source environment and no new gas is introduced, new impurities can be prevented from being introduced, which is beneficial to improving the purity of the second conductive material layer 142a, and then the gas in the deposition chamber is discharged (i.e., purge 4) for the fourth time, so as to avoid the adverse effect of the gas in the deposition chamber on the subsequent second recombination operation. For example, providing a second metal source and a second nitrogen source, a third vent, an annealing process, and a fourth vent may collectively form a second composite operation.
Illustratively, the deposition temperature of the first conductive material layer 141a may range from 500 ℃ to 800 ℃, such that the temperature may be avoided from being too low, such that the chlorine content in the first conductive material layer 141a is low, such that the resistivity of the first conductive material layer 141a is low, and such that the temperature may be avoided from being too high, such that the cost may be reduced, such that the impact of other structural layers of the high Wen Duiban conductor structure 100 may be reduced. For example, the deposition temperature at which the first conductive material layer 141a is deposited may be 500 ℃, 600 ℃, 700 ℃, 800 ℃, or any value between 500 ℃ and 800 ℃.
Illustratively, the deposition temperature at which the second conductive material layer 142a is deposited may range from 350 ℃ to 600 ℃, such that the temperature may be avoided from being too low to avoid too low a reaction rate, and the temperature may be avoided from being too high to allow for lower stress of the second conductive material layer 142 a. For example, the deposition temperature at which the second conductive material layer 142a is deposited may be 350 ℃, 450 ℃, 550 ℃, 600 ℃, or any value between 350 ℃ and 600 ℃.
It can be appreciated that the time for providing the first metal source, providing the first nitrogen source, providing the second metal source, providing the second nitrogen source again, and the like is controlled within a proper range, so that the time can be prevented from being too short, sufficient gas can be provided for the processes of deposition, annealing, and the like, the realization of the processes of deposition, annealing, and the like can be facilitated, the overlong time can be avoided, the time can be saved, and the production efficiency can be improved. The time of the repeated discharge (from the first discharge to the fourth discharge) is controlled in a proper range, so that the time is prevented from being too short, redundant gas in the deposition chamber can be sufficiently discharged, the influence of the gas to be discharged on the subsequent process is avoided, the time is prevented from being too long, the time is saved, and the production efficiency is improved. Wherein N can be introduced into 2 To exhaust the excess gas from the deposition chamber.
Illustratively, the time for providing the first metal source may range from 0.02s to 0.08s, for example, the time for providing the first metal source may be 0.02s, 0.04s, 0.05s, 0.08s, or any value between 0.02s and 0.08 s.
Illustratively, the time of the first discharge may range from 0.1s to 0.3s, for example, the time of the first discharge may be 0.1s, 0.2s, 0.3s, or any value between 0.1s and 0.3 s.
Illustratively, the time for providing the first nitrogen source and the second bleed may range from 0.2s to 0.5s, for example, the time for providing the first nitrogen source and the second bleed may be 0.2s, 0.3s, 0.4s, 0.5s, or any value between 0.2s and 0.5 s. The times at which the first nitrogen source and the second bleed are provided may be the same or may be different.
Illustratively, the second metal source and the second nitrogen source, the third bleed, and the fourth bleed may be provided for a time in the range of 10s-15s, e.g., the second metal source and the second nitrogen source, the third bleed, and the fourth bleed may be provided for a time in the range of 10s, 11s, 12s, 13s, 14s, 15s, or any number in the range of 10s-15 s. The time for providing the second metal source and any two of the second nitrogen source, the third bleed, and the fourth bleed may be the same or may be different.
Illustratively, the time to again provide the second nitrogen source may range from 30s to 50s, and the time to again provide the second nitrogen source may range from 30s, 35s, 40s, 45s, 50s, or any number between 30s to 50 s.
It can be appreciated that the gas flow rates of the first metal source, the first nitrogen source, the second metal source, the second nitrogen source and the second nitrogen source are controlled within a proper range, so that the gas flow rate is prevented from being too small, the speed of the deposition, annealing and other processes is facilitated to be increased, and the gas flow rate is prevented from being too large, so that the waste of the gas is avoided. The gas flow rate of the multiple times of discharge (from the first discharge to the fourth discharge) is controlled in a proper range, so that the gas flow rate is prevented from being too small, gas can be discharged relatively quickly, the discharge efficiency is relatively high, the gas flow rate is prevented from being too large, and the energy consumption during discharge is reduced.
Illustratively, the gas flow rate at which the first metal source is provided may range from 80sccm to 150sccm, for example, the gas flow rate at which the first metal source is provided may be 80sccm, 100sccm, 120sccm, 150sccm, or any value between 80sccm and 150 sccm.
Illustratively, the gas flow rates providing the first nitrogen source, the first vent, and the second vent may range from 3000sccm to 5000sccm, for example, the gas flow rates providing the first nitrogen source, the first vent, and the second vent may be 3000sccm, 3500sccm, 4000sccm, 4500sccm, 5000sccm, or any number between 3000sccm and 5000 sccm. The gas flow rates providing any two of the first nitrogen source, the first bleed, and the second bleed may be the same or may be different.
Illustratively, the gas flow rate at which the second metal source is provided may range from 50sccm to 1500sccm, for example, the gas flow rate at which the second metal source is provided may be 50sccm, 100sccm, 500sccm, 800sccm, 1000sccm, 1500sccm, or any number between 50sccm and 1500 sccm.
Illustratively, the gas flow rate at which the second nitrogen source is provided, the third bleed, the fourth bleed, and the second nitrogen source is again provided may range from 500sccm to 3000sccm, e.g., the gas flow rate at which the second nitrogen source is provided, the third bleed, the fourth bleed, and the second nitrogen source is again provided may be 500sccm, 1000sccm, 1500sccm, 2000sccm, 2500sccm, 3000sccm, or any value between 500sccm and 3000 sccm. The gas flow rates for any two of providing the second nitrogen source, third venting, fourth venting, and re-providing the second nitrogen source may be the same or may be different.
For example, the deposition pressure for depositing the first conductive material layer 141a and depositing the second conductive material layer 142a may range from 5torr to 6torr, so that the deposition pressure may be maintained in a low state, and adverse effects on the film quality due to excessive air pressure may be avoided. For example, the deposition pressure for depositing first conductive material layer 141a and depositing second conductive material layer 142a may be 5torr, 5.5torr, 6torr, or any value between 5torr and 6 torr. The deposition pressure at which the first conductive material layer 141a and the second conductive material layer 142a are deposited may be the same, or may be different.
Illustratively, the number of cycles of the first composite operation may range from 100 to 200 such that the thickness of the first conductive material layer 141a is within a desired thickness range. For example, the number of cycles of the first compounding operation may be 100, 120, 150, 200, or any number between 100 and 200.
Illustratively, the number of cycles of the second compounding operation may range from 15 times to 20 times such that the thickness of the second conductive material layer 142a is within a desired thickness range. For example, the number of cycles of the second compounding operation may be 15, 17, 20, or any number between 15 and 20.
In some embodiments, after forming the first conductive layer 141 and the second conductive layer 142, it may include: the second conductive layer 142 is nitrided to form the second conductive layer 142 into a nitrided conductive layer. After the nitriding treatment, at least a portion of chlorine in the second conductive layer 142 may be removed so that the chlorine content of the nitrided conductive layer is smaller than the chlorine content of the second conductive layer 142, so that the resistivity of the nitrided conductive layer is smaller than the resistivity of the second conductive layer 142, i.e., the chlorine content of the second conductive layer 142 may be reduced by the nitriding treatment to reduce the resistivity of the second conductive layer 142, thereby reducing the resistivity of the word line 140. Since a portion of the thickness of the second conductive material layer 142a has been etched before the nitridation process, the aspect ratio of the second conductive layer 142 formed by the remaining second conductive material layer 142a is reduced, and even if the stress of the second conductive layer 142 is increased due to the reduction of the chlorine content of the second conductive layer 142, the word line 140 is not deformed.
Illustratively, the nitridation process may include remote plasma nitridation (remote plasma nitridation, simply RPN), which may be effective to reduce the chlorine content of the second conductive layer 142, e.g., may remove 90% or more of the chlorine in the second conductive layer 142.
Illustratively, the chlorine content of the first conductive layer 141 may range from 1% to 5%, which may be avoided from being too small to reduce the difficulty of preparing the first conductive layer 141, and may be avoided from being too large, such that the resistivity of the first conductive layer 141 is small. For example, the chlorine content of the first conductive layer 141 may be any value between 1%, 2%, 3%, 4%, 5%, or 1% -5%.
Illustratively, the chlorine content of the second conductive layer 142 may range from 10% to 20%, which may be avoided from being too small, such that the stress of the second conductive layer 142 is small, and which may be avoided from being too large, such that the resistivity of the second conductive layer 142 is prevented from being too large. For example, the chlorine content of the second conductive layer 142 may be any value between 10%, 12%, 15%, 17%, 20%, or 10% -20%.
The following describes a semiconductor structure 100 provided by embodiments of the present disclosure.
The semiconductor structure 100 provided in the embodiments of the present disclosure may be manufactured by using the manufacturing method of the semiconductor structure 100 in the above embodiments. The semiconductor structure 100 may be applied to a memory, which may include, for example, a DRAM, a phase change random access memory (phase change random access memory, abbreviated PRAM), a magnetoresistive random access memory (magnetoresistive random access memory, abbreviated MRAM), or the like. Embodiments of the present disclosure will be described with reference to the application of semiconductor structure 100 to a DRAM.
Referring to fig. 4, semiconductor structure 100 may include a substrate 110, and substrate 110 may provide a support foundation for other structural layers on substrate 110. For example, the substrate 110 may be provided therein with an isolation structure 112 and a plurality of active regions 111 disposed at intervals, and the isolation structure 112 may be used to isolate two adjacent active regions 111. Active region 111 may be used to form a transistor.
For example, referring to fig. 4, the top of the substrate 110 may be covered with an isolation layer 120 for protecting the substrate 110, for example, the isolation layer 120 may prevent the active region 111 covered thereby from being oxidized by exposure to a process environment, resulting in electrical degradation of the active region 111, for example, the material of the isolation layer 120 may include silicon oxide.
For example, referring to fig. 4, the substrate 110 may have a plurality of word line trenches 113 disposed therein at intervals, the word line trenches 113 exposing the active region 111. For example, an isolation layer 120 may be disposed on the substrate 110, and then a portion of the isolation layer 120 and a portion of the substrate 110 may be etched, thereby forming a word line trench 113 exposing the active region 111.
For example, referring to fig. 4, the semiconductor structure 100 may include a gate dielectric layer 130 and a word line 140, the gate dielectric layer 130 may cover a wall of the word line trench 113, the word line 140 may include a first conductive layer 141 and a second conductive layer 142, the first conductive layer 141 may be on the gate dielectric layer 130, the second conductive layer 142 may be on the first conductive layer 141, and a stress of the first conductive layer 141 may be greater than a stress of the second conductive layer 142. By this arrangement, since the stress of the second conductive layer 142 may be smaller than the stress of the first conductive layer 141, that is, the stress of the second conductive material layer 142a (fig. 3) is smaller than the stress of the first conductive material layer 141a (fig. 3), the stress of the word line material layer 140a (fig. 3) is smaller, the deformation of the word line material layer 140a caused by the stress of the word line material layer 140a can be relieved, thereby relieving the deformation of the word line 140, reducing the influence on the performance of the word line 140 and DRAM, and improving the yield of the product.
It should be noted that, the numerical values and the numerical ranges related to the embodiments of the present disclosure are approximate values, and may have a certain range of errors under the influence of the manufacturing process, and those errors may be considered to be negligible by those skilled in the art.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a plurality of active areas which are arranged at intervals, a plurality of word line grooves which are arranged at intervals are formed in the substrate, and the active areas are exposed by the word line grooves;
forming a gate dielectric layer, a first conductive layer and a second conductive layer, wherein the gate dielectric layer covers the groove wall of the word line groove, the first conductive layer is positioned on the gate dielectric layer, and the second conductive layer is positioned on the first conductive layer;
Wherein the first conductive layer and the second conductive layer together form a word line, and the stress of the first conductive layer is greater than the stress of the second conductive layer.
2. The method of manufacturing a semiconductor structure as claimed in claim 1, wherein,
forming the first conductive layer and the second conductive layer includes:
depositing a first conductive material layer, wherein the first conductive material layer covers the top of the gate dielectric layer and the substrate in the word line trench;
depositing a second conductive material layer on the first conductive material layer, wherein the second conductive material layer fills the word line trench;
and removing part of the first conductive material layer and part of the second conductive material layer, wherein the reserved first conductive material layer forms the first conductive layer, and the reserved second conductive material layer forms the second conductive layer.
3. The method of manufacturing a semiconductor structure according to claim 2, wherein,
the method of depositing the first conductive material layer includes atomic layer deposition;
and/or, the method of depositing the second conductive material layer comprises continuous flow deposition;
And/or the deposition temperature of depositing the first conductive material layer is greater than the deposition temperature of depositing the second conductive material layer;
and/or, a deposition temperature at which the first conductive material layer is deposited ranges from 500 ℃ to 800 ℃;
and/or the deposition temperature at which the second conductive material layer is deposited is in the range of 350 ℃ to 600 ℃.
4. A method of fabricating a semiconductor structure according to any one of claims 1 to 3, comprising, after forming the first conductive layer and the second conductive layer:
nitriding the second conductive layer to form a nitrided conductive layer,
wherein the chlorine content of the nitrided conductive layer is less than the chlorine content of the second conductive layer, and the resistivity of the nitrided conductive layer is less than the resistivity of the second conductive layer.
5. The method of fabricating a semiconductor structure of claim 4, wherein the nitridation process comprises remote plasma nitridation.
6. A method of fabricating a semiconductor structure according to claim 2 or 3, wherein prior to forming the first and second conductive layers comprises: placing the substrate in a deposition chamber;
depositing the first conductive material layer includes: performing a first composite operation in a plurality of cycles, the first composite operation comprising: providing a first metal source to the deposition chamber to form a first metal source layer on top of the gate dielectric layer of the word line trench and the substrate;
Exhausting the gas in the deposition chamber for the first time;
providing a first nitrogen source to the deposition chamber, the first nitrogen source reacting with the first metal source layer to form the first conductive material layer;
and exhausting the gas in the deposition chamber for the second time.
7. The method of claim 6, wherein depositing the second conductive material layer comprises:
performing a second composite operation in a plurality of cycles, the second composite operation comprising:
simultaneously providing a second metal source and a second nitrogen source to the deposition chamber to form the second conductive material layer;
third exhausting the gas in the deposition chamber;
providing the second nitrogen source to the deposition chamber again, and annealing the second conductive material layer;
and exhausting the gas in the deposition chamber for the fourth time.
8. The method of manufacturing a semiconductor structure as claimed in claim 7, wherein,
providing the first metal source for a time in the range of 0.02s to 0.08s;
and/or the time of the first discharge is in the range of 0.1s to 0.3s;
and/or providing the first nitrogen source and the second bleed for a time in the range of 0.2s to 0.5s;
And/or providing the second metal source and the second nitrogen source, the third bleed and the fourth bleed for a time in the range of 10s-15s;
and/or, the second nitrogen source is provided again for a time in the range of 30s to 50s;
and/or providing a gas flow rate of the first metal source in a range of 80sccm to 150sccm;
and/or providing a gas flow rate of the first nitrogen source, the first discharge, and the second discharge in a range of 3000sccm to 5000sccm;
and/or providing a gas flow rate of the second metal source in the range of 50sccm to 1500sccm;
and/or providing the second nitrogen source, the third bleed, the fourth bleed, and providing the second nitrogen source again at a gas flow rate in the range of 500sccm to 3000sccm;
and/or depositing the first conductive material layer and the second conductive material layer at a deposition pressure in the range of 5torr to 6torr;
and/or the number of cycles of the first composite operation ranges from 100 times to 200 times;
and/or the number of cycles of the second compounding operation ranges from 15 times to 20 times.
9. A semiconductor structure, comprising: the semiconductor device comprises a substrate, a gate dielectric layer and word lines, wherein the substrate comprises a plurality of active areas which are arranged at intervals, a plurality of word line grooves which are arranged at intervals are formed in the substrate, and the active areas are exposed by the word line grooves;
The gate dielectric layer covers the groove wall of the word line groove, the word line comprises a first conductive layer and a second conductive layer, the first conductive layer is located on the gate dielectric layer, the second conductive layer is located on the first conductive layer, and the stress of the first conductive layer is larger than that of the second conductive layer.
10. The semiconductor structure of claim 9, wherein the semiconductor structure comprises a silicon nitride layer,
the material of the first conductive layer and/or the material of the second conductive layer comprises a metal nitride;
and/or the resistivity of the first conductive layer is less than the resistivity of the second conductive layer;
and/or the chlorine content of the first conductive layer is less than the chlorine content of the second conductive layer;
and/or the first conductive layer has a chlorine content in the range of 1% -5%;
and/or the chlorine content of the second conductive layer is in the range of 10% -20%.
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