CN116980258A - OOK and BPSK modulated transmitter applied to high-speed wireless communication - Google Patents
OOK and BPSK modulated transmitter applied to high-speed wireless communication Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
- H04L25/03834—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using pulse shaping
- H04L25/03847—Shaping by selective switching of amplifying elements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
- H04L25/03834—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using pulse shaping
- H04L25/03853—Shaping by digital methods other than look up tables or up/down converters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/20—Modulator circuits; Transmitter circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B2001/0408—Circuits with power amplifiers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B2001/0491—Circuits with frequency synthesizers, frequency converters or modulators
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Abstract
The invention discloses a transmitter for OOK and BPSK modulation applied to high-speed wireless communication, which comprises: the device comprises a modulation module, a pulse shaping module, a delay locking ring, a digital power amplifier and an injection locking ring oscillator, wherein the pulse shaping module is in signal connection with the modulation module; the modulation module comprises a logic circuit and a decoding module, wherein the decoding module is in signal connection with the digital power amplifier; the injection locking ring oscillator comprises a pulse generating module, a 4 frequency divider, a numerical control ring oscillator connected with the pulse generating module in a signal mode, a frequency estimating module connected with the 4 frequency divider in a signal mode and a 32 frequency divider connected with the frequency estimating module in a signal mode, wherein the numerical control ring oscillator and the 32 frequency divider are connected with a digital power amplifier in a signal mode; the clocks of the transmitters are each provided by a phase locked loop. According to the invention, the low power consumption characteristic and the high data rate characteristic are simultaneously satisfied, and the transmission bandwidth is adjustable.
Description
Technical Field
The invention relates to the technical field of wireless communication and integrated circuits, in particular to an OOK and BPSK modulated transmitter applied to high-speed wireless communication.
Background
The federal communications commission in the united states specifies that UWB signals need to satisfy one of the following conditions: the absolute bandwidth of the transmitted signal is greater than 500MHz or the relative bandwidth is greater than 20% of the center frequency of the signal. The spectrum specification of the transmitted signal is specified, and the maximum output power spectral density is-41.3 dBm/MHz. The architecture of the transmitter to generate the pulse signal thus affects the spectral utilization, power consumption, transmit power and energy efficiency of the overall transmitter.
Conventional IR-UWB transmitters can be like continuous wave communication transmitters, generate pulses in baseband, convert to radio frequency signals by a mixer, and transmit through a linear power amplifier. The architecture is shown in fig. 1, firstly, a narrow pulse generating module generates a narrow pulse according to baseband data, then, the narrow pulse moves a frequency spectrum to a carrier frequency generated by a local oscillator through a mixer, the carrier frequency is transmitted by a power amplifier, and finally, a corresponding UWB signal is obtained. The WB transmitter can also generate transmitting pulse through a pulse control oscillator, firstly baseband data generates an oscillator control signal through a switch signal generating module, then the control signal controls the oscillator to generate pulse, the pulse is transmitted by a power amplifier, and finally a corresponding UWB signal is obtained.
There are always high frequency carrier oscillators and mixers in the up-conversion based UWB transmitter architecture, which can lead to an increase in static power consumption of the circuit, while the high frequency oscillator circuit generally adopts an inductor-capacitor architecture, which occupies a larger circuit area, so that the complexity of the circuit design becomes high and the cost increases.
UWB transmitter frame structure based on pulse control oscillator adopts the chip area of LC carrier oscillator big, is difficult to start the shake fast under low-power consumption design, consequently can't realize high data rate communication.
Technical terms: delay Loop Lock, DLL; an injection locked ring oscillator Injection Locked Ring Oscillator, ILRO; digital power amplifier Digital Power Amplifier, DPA; numerical control ring oscillator Digital Control Ring Oscillator, DCRO
Disclosure of Invention
In view of the shortcomings in the prior art, the invention aims to provide an OOK and BPSK modulated transmitter applied to high-speed wireless communication, and simultaneously meets the characteristics of low power consumption and high data rate, and the transmission bandwidth is adjustable. To achieve the above objects and other advantages and in accordance with the purpose of the invention, there is provided a transmitter for OOK and BPSK modulation applied to high-speed wireless communication, comprising:
the device comprises a modulation module, a pulse shaping module, a delay locking ring, a digital power amplifier and an injection locking ring oscillator, wherein the pulse shaping module is in signal connection with the modulation module;
the modulation module comprises a logic circuit and a decoding module, wherein the decoding module is in signal connection with the digital power amplifier;
the injection locking ring oscillator comprises a pulse generating module, a 4 frequency divider, a numerical control ring oscillator connected with the pulse generating module in a signal mode, a frequency estimating module connected with the 4 frequency divider in a signal mode and a 32 frequency divider connected with the frequency estimating module in a signal mode, wherein the numerical control ring oscillator and the 32 frequency divider are connected with a digital power amplifier in a signal mode;
the clocks of the transmitters are each provided by a phase locked loop.
Preferably, the modulation module is used for generating baseband pulses and data modulation information, realizing OOK and BPSK modulation, and the baseband pulses are sent to the pulse shaping module to generate transmitting pulses.
Preferably, the pulse shaping module includes a delay unit that is calibrated on-chip by a delay locked loop before the transmitter is operating normally, and after modulation is completed, the pulse shaping module provides a multiphase signal to the digital power amplifier to control the output pulse width.
Preferably, the injection locked ring oscillator provides an injection clock through a phase locked loop, the injection locked ring oscillator output signal will be locked on the 8 th harmonic of the injection clock, providing a radio frequency carrier for the digital power amplifier; and the injection locked ring oscillator is calibrated by the frequency estimation module prior to injecting the clock such that the oscillation frequency of the digital controlled ring oscillator is close to the radio frequency carrier frequency required by the transmitter.
Preferably, the pulse shaping module adopts an analog delay line based on an FIR filter, the pulse shaping module comprises a delay line formed by multistage delay units and a digital power amplifier, and multiphase control signals output by the FIR filter are added at the digital power amplifier to obtain the envelope of the radio frequency transmitting signal.
Preferably, the injection locked ring oscillator comprises an injection pulse generating module and a numerical control ring oscillator; the digitally controlled ring oscillator includes a plurality of current starved pseudo-differential inverters.
A transmitter usage method of OOK and BPSK modulation applied to high speed wireless communication, comprising the steps of:
s1, before a transmitter works, firstly, a DLL adjusts the delay of a pulse shaping module by inputting a reference clock Cal_clk, and simultaneously, a pulse generating module of ILRO generates an injection pulse Inj by injecting the clock Inj_clk;
s2, before pulse Inj is injected, DCRO carries out self-oscillation to generate an oscillation signal LO, the LO signal is subjected to 32 frequency division and is sent to a frequency estimation module, and meanwhile, an injection clock inj_clk is sent to the frequency estimation module after 4 frequency division;
s3, the frequency estimation module outputs a frequency control word Freq_code <9:0> to control the free oscillation frequency of the DCRO;
s4, after the frequency estimation module finishes working, injecting a pulse signal Inj to the DCRO module to generate a stable radio frequency carrier LO, and sending the stable radio frequency carrier LO to the DPA module;
s5, performing OR operation on the DATA DATA and the modulation mode control word Mod in the modulation module, performing AND operation on the output signal, the pulse width control clock clk_rule and the pulse repetition frequency PRF to obtain a modulation signal Dpulse, and sending the modulation signal Dpulse to the pulse shaping module;
s6, generating 8-phase pulse signals PSP <8:1> according to the input modulation signals Dpulse by the pulse shaping module, and finally sending the 8-phase pulse signals PSP <8:1> to the DPA module;
s7, the decoding module generates SCR and SCRB signals according to the pulse repetition frequency PRF and the DATA DATA and sends the SCR and SCRB signals to the DPA module;
s8, the DPA generates a UWB radio frequency signal DPA_OUT according to the input signal.
Compared with the prior art, the invention has the beneficial effects that: the transmission bandwidth is adjustable, and the two transmission bandwidths of 1.1GHz and 2.2GHz are provided. The ILRO is used for providing radio frequency carrier for the transmitter, so that the area is saved and the power consumption is low. And meanwhile, the modulation signal passes through an analog delay line based on an FIR filter to generate a baseband waveform with output power spectral density meeting FCC MASK. The transmitter thus has both low power consumption and high data rate characteristics. Has high data rate characteristic, and the highest data rate can reach 499.2Mb/s. The power consumption of the whole transmitter is only 5.9mW, and the energy efficiency is 11.8pJ/bit under the highest data transmission rate.
Drawings
Fig. 1 is an overall architecture of an OOK and BPSK modulated transmitter applied to high speed wireless communication according to the present invention;
fig. 2 is a timing diagram of a modulation module logic of a transmitter for OOK and BPSK modulation applied to high speed wireless communication in accordance with the present invention;
fig. 3 is a schematic circuit diagram of a pulse shaping module of an OOK and BPSK modulated transmitter for high speed wireless communication in accordance with the present invention;
fig. 4 is a schematic and timing diagram of the ILRO circuit of an OOK and BPSK modulated transmitter applied to high speed wireless communication according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-4, a transmitter for OOK and BPSK modulation for high speed wireless communication, comprising: the device comprises a modulation module, a pulse shaping module, a delay locking ring, a digital power amplifier and an injection locking ring oscillator, wherein the pulse shaping module is in signal connection with the modulation module;
the modulation module comprises a logic circuit and a decoding module, wherein the decoding module is in signal connection with the digital power amplifier;
the injection locking ring oscillator comprises a pulse generating module, a 4 frequency divider, a numerical control ring oscillator connected with the pulse generating module in a signal mode, a frequency estimating module connected with the 4 frequency divider in a signal mode and a 32 frequency divider connected with the frequency estimating module in a signal mode, wherein the numerical control ring oscillator and the 32 frequency divider are connected with a digital power amplifier in a signal mode;
the clocks of the transmitters are each provided by a phase locked loop.
The modulation module generates baseband pulse and data modulation information, and can realize OOK and BPSK modulation. The baseband pulse generated by the modulation module is sent to a pulse shaping module for generating a transmit pulse. Before the transmitter operates properly, the delay units in the pulse shaping module need to be calibrated on-chip by the DLL to meet the output pulse width requirements. After modulation is complete, the pulse shaping module provides a multiphase signal to the DPA to control the output pulse width. The phase locked loop provides the ILRO with an injection clock whose output signal will be locked on the 8 th harmonic of the injection clock, thereby providing the DPA with a radio frequency carrier. To achieve this, the ILRO needs to be calibrated by a frequency estimation module before injecting the clock to bring the oscillation frequency of the DCRO close to the radio frequency carrier frequency required by the transmitter.
Modulation module circuit as can be seen from fig. 1, where DATA is the transmit DATA, PRF is the pulse repetition frequency, mod is used to control the modulation mode. The principle of operation is shown in fig. 2, where the logic circuit is mainly used to generate baseband pulses DPulse and to vary the pulse width of DPulse according to the frequency of the clock clk_rule. When clk_rule is 499.2MHz, the DPulse output pulse width is about 1ns; the output pulse width is about 0.5ns when it is 998.4 MHz.
The decoding module outputs Pseudo-random binary sequences (PRBS) in OOK mode, i.e., SCR and SCRB, at the same frequency as the PRF for selecting carrier phases. The SCR and SCRB may thus randomly vary the carrier phase in OOK mode, which smoothes the discrete spectral energy in the output spectrum and maximizes the output PSD if FCC regulations are met. In the BPSK mode, SCR and SCRB outputted by the decoding module are phase information.
The pulse shaping module circuit is shown in fig. 3, and the pulse shaping module adopts an analog delay line based on an FIR filter, so that the pulse shaping module circuit has a simple structure and low power consumption. The circuit consists of a delay line formed by multistage delay units and DPA, and multiphase control signals output by the filter are added at the DPA to obtain the envelope of the radio frequency transmitting signal. The analog delay unit adopts an inverter-based architecture, and the number of the NMOS capacitor arrays NM0-NM125 connected is controlled through thermometer codes B <62:0>, so that delay time is controlled. The capacitor array is 63 groups in total, and the upper and lower two form a group, so that the charge and discharge time on the signal path is matched. The design concatenates 16 delay cells (τ=62.6 ps), wherein the output signals of 8 delay cells are connected to DPA cells, respectively, and the pulse width is selected by PW, and when pw= '1', dpulse pulse width is 1ns, CLK1,3, # 15 is selected to output a multiphase signal, the delay interval is 2τ, resulting in an output pulse width of about 2ns, as shown in fig. 3. When pw= '0', dpulse pulse width is 0.5ns, CLK1,2 is selected, 8 is the output multiphase signal, delay interval is τ, and output pulse width is about 1ns. The designed delay unit covers a certain delay range, and meanwhile, the robustness of the delay circuit is improved through on-chip DLL loop calibration, and the transmitting pulse with accurate pulse width is generated.
The injection locked ring oscillator comprises an injection pulse generation module and a DCRO, wherein the DCRO consists of 2 pseudo-differential inverters with current starvation and has the frequency f DCRO =1/(8×td), where td is the delay of the pseudo-differential inverter, the delay can be adjusted by a 10-bit digitally controlled current-steering digital-to-Analog Converter (CS-DAC). The pseudo-differential inverters constituting the current starvation of DCRO are shown in fig. 4, with INP and INN as inputs and OUTP and OUTN as outputs. Since the inverters consisting of PM0-1 and NM0-1 on the signal path have the potential for deadlock, the cross-coupled pair consisting of PM2-3 and NM2-3 is used to prevent the oscillation loop from entering a deadlock state. The cross-coupled pair size needs to be large enough to prevent the DCRO from getting into a deadlock condition and from oscillating. The size should not be too large, which would lead to power consumption and increased noise. Thus need to be consideredIn both cases, the appropriate dimensions are chosen.
The pulse generation module generates narrow pulses Inj with the same frequency and 40-100ps pulse width according to the frequency of the injection clock inj_clk (499.2 MHz or 998.4 MHz) and sends the narrow pulses Inj into the DCRO. If the pulse width of Inj is too wide or too narrow, the circuit may not be locked, so the pulse width is controlled within a certain range. Careful design is also required for the dimensions of the implant transistor M0, which has the same effect as the pulse width of Inj, determining the implant strength. M1 is load matched and is the same size as M0. The ILRO locks the frequency at the 8 th harmonic of the Inj frequency, i.e. the two center carrier frequencies of the design, 3993.6MHz and 7987.2MHz, depending on the Inj frequency. As can be seen from the timing diagram in fig. 4, the output phase of DCRO is periodically realigned with a clean reference clock edge to suppress long-term noise of the DCRO circuit, optimizing for phase noise that DCRO itself is not ideal. Because of the low figure of merit of DCRO, the circuit can be started and stabilized quickly, while the injection locking technique can be phase locked instantaneously, so ILRO can be turned off when no pulse is transmitted, further reducing circuit power consumption.
The whole transmitter using method is as follows: before the transmitter operates, the DLL first adjusts the delay of the pulse shaping module according to the input reference clock Cal_clk. Meanwhile, the pulse generation module of the ILRO generates the injection pulse Inj according to the injection clock inj_clk. Before the pulse Inj is injected, the DCRO performs self-oscillation to generate an oscillation signal LO, the LO signal is subjected to 32 frequency division and is sent to a frequency estimation module, and meanwhile, an injection clock inj_clk is sent to the frequency estimation module after being subjected to 4 frequency division. The frequency estimation module outputs a frequency control word freq_code <9:0> to control the free oscillation frequency of the DCRO. After the frequency estimation module finishes working, the injection pulse signal Inj is input to the DCRO module to generate a stable radio frequency carrier LO and sent to the DPA module. For the modulation module, the DATA DATA and the modulation mode control word Mod are OR-operated, the output signal is AND-operated with the pulse width control clock clk_rule and the pulse repetition frequency PRF to obtain a modulation signal Dpulse, and the modulation signal Dpulse is sent to the pulse shaping module. The pulse shaping module generates 8-phase pulse signals PSP <8:1> according to the input modulation signals Dpulse, and finally sends the 8-phase pulse signals PSP <8:1> to the DPA module. The decoding module generates SCR and SCRB signals based on the pulse repetition frequency PRF and the DATA and sends the SCR and SCRB signals to the DPA module. The DPA generates a UWB radio frequency signal dpa_out from the input signal.
The number of devices and the scale of processing described herein are intended to simplify the description of the invention, and applications, modifications and variations of the invention will be apparent to those skilled in the art.
Although embodiments of the present invention have been disclosed above, it is not limited to the details and embodiments shown and described, it is well suited to various fields of use for which the invention would be readily apparent to those skilled in the art, and accordingly, the invention is not limited to the specific details and illustrations shown and described herein, without departing from the general concepts defined in the claims and their equivalents.
Claims (7)
1. A transmitter for OOK and BPSK modulation for high speed wireless communication, comprising:
the device comprises a modulation module, a pulse shaping module, a delay locking ring, a digital power amplifier and an injection locking ring oscillator, wherein the pulse shaping module is in signal connection with the modulation module;
the modulation module comprises a logic circuit and a decoding module, wherein the decoding module is in signal connection with the digital power amplifier;
the injection locking ring oscillator comprises a pulse generating module, a 4 frequency divider, a numerical control ring oscillator connected with the pulse generating module in a signal mode, a frequency estimating module connected with the 4 frequency divider in a signal mode and a 32 frequency divider connected with the frequency estimating module in a signal mode, wherein the numerical control ring oscillator and the 32 frequency divider are connected with a digital power amplifier in a signal mode;
the clocks of the transmitters are each provided by a phase locked loop.
2. The OOK and BPSK modulated transmitter of claim 1 wherein the modulation module is configured to generate baseband pulses and data modulation information to effect OOK, BPSK modulation, the baseband pulses being sent to the pulse shaping module to generate transmit pulses.
3. A OOK and BPSK modulated transmitter for high speed wireless communication as defined in claim 2 wherein the pulse shaping module includes a delay unit which is calibrated on-chip by a delay locked loop prior to normal operation of the transmitter, and wherein after modulation is complete, the pulse shaping module provides a multi-phase signal to the digital power amplifier to control the output pulse width.
4. A OOK and BPSK modulated transmitter for high speed wireless communication as defined in claim 3 wherein the injection locked ring oscillator provides an injection clock through a phase locked loop, the injection locked ring oscillator output signal to be locked at the 8 th harmonic of the injection clock, providing a radio frequency carrier for the digital power amplifier; and the injection locked ring oscillator is calibrated by the frequency estimation module prior to injecting the clock such that the oscillation frequency of the digital controlled ring oscillator is close to the radio frequency carrier frequency required by the transmitter.
5. The OOK and BPSK modulated transmitter for high speed wireless communication of claim 4 wherein the pulse shaping module employs an analog delay line based on an FIR filter, the pulse shaping module comprising a delay line of multiple delay cells and a digital power amplifier, the polyphase control signals output by the FIR filter being summed at the digital power amplifier to obtain the envelope of the radio frequency transmit signal.
6. The OOK and BPSK modulated transmitter for high speed wireless communication of claim 1, wherein the injection locked ring oscillator comprises an injection pulse generation module and a digitally controlled ring oscillator; the digitally controlled ring oscillator includes a plurality of current starved pseudo-differential inverters.
7. A method of using an OOK and BPSK modulated transmitter for high speed wireless communication as defined in claim 1, comprising the steps of:
s1, before a transmitter works, firstly, a DLL adjusts the delay of a pulse shaping module by inputting a reference clock Cal_clk, and simultaneously, a pulse generating module of ILRO generates an injection pulse Inj by injecting the clock Inj_clk;
s2, before pulse Inj is injected, DCRO carries out self-oscillation to generate an oscillation signal LO, the LO signal is subjected to 32 frequency division and is sent to a frequency estimation module, and meanwhile, an injection clock inj_clk is sent to the frequency estimation module after 4 frequency division;
s3, the frequency estimation module outputs a frequency control word Freq_code <9:0> to control the free oscillation frequency of the DCRO;
s4, after the frequency estimation module finishes working, injecting a pulse signal Inj to the DCRO module to generate a stable radio frequency carrier LO, and sending the stable radio frequency carrier LO to the DPA module;
s5, performing OR operation on the DATA DATA and the modulation mode control word Mod in the modulation module, performing AND operation on the output signal, the pulse width control clock clk_rule and the pulse repetition frequency PRF to obtain a modulation signal Dpulse, and sending the modulation signal Dpulse to the pulse shaping module;
s6, generating 8-phase pulse signals PSP <8:1> according to the input modulation signals Dpulse by the pulse shaping module, and finally sending the 8-phase pulse signals PSP <8:1> to the DPA module;
s7, the decoding module generates SCR and SCRB signals according to the pulse repetition frequency PRF and the DATA DATA and sends the SCR and SCRB signals to the DPA module;
the DPA generates a UWB radio frequency signal dpa_out from the input signal.
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