CN116979959B - Phase-locked loop, chip and electronic equipment - Google Patents
Phase-locked loop, chip and electronic equipment Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses a phase-locked loop, a chip and electronic equipment, wherein the phase-locked loop comprises a phase discriminator, a phase detector and a phase detector, wherein the phase discriminator is used for detecting the phase difference between an output clock and a reference clock of the phase-locked loop and converting the phase difference into control voltage; an oscillator for outputting an output clock of the phase-locked loop according to the control voltage; a phase noise cancellation circuit; the phase noise cancellation circuit includes: a voltage-controlled delay device and a phase difference voltage converter comprising a first capacitor; the phase difference voltage converter is used for converting the phase difference into voltage and storing the converted voltage in a first capacitor; the voltage-controlled delayer is used for generating a delay signal opposite to the phase difference according to the output voltage of the phase difference voltage converter and the output clock control, and enabling the output clock to overlap the delay signal so as to offset the phase difference. The phase noise of the phase-locked loop can be well removed.
Description
Technical Field
The present invention relates to, but not limited to, the field of communications technologies, and in particular, to a phase locked loop, a chip, and an electronic device.
Background
A phase locked loop (Phase Locked Loop, PLL) is mainly used to keep the phases of the reference signal and the output signal constant. The method is widely applied to circuits such as filtering, frequency synthesis, modulation and demodulation, signal detection and the like.
The phase-locked loop circuit can obtain multipath clock output with higher speed and fixed phase relation with the reference clock by multiplying the input reference clock. In modern communication circuits, the importance of the clock is more ubiquitous. In radio frequency communications, radio signals are transmitted strictly according to a specific frequency. In both radio frequency receiver and transmitter systems, therefore, a clock generation circuit, known as a frequency synthesizer, is required to generate an accurate clock signal. Also in wired communication systems, such as optical fiber communication, and in communication systems with metallic conductors as carriers, digital signals are modulated to a frequency, and accurate clock generation and recovery circuits are very important components in such systems.
The main indexes of the phase-locked loop include phase noise, spurious, power consumption, area, frequency locking range, phase margin and the like. Wherein phase noise is a very important indicator of the measurement of the phase-locked loop. Therefore, it is desirable to reduce the phase noise of the pll to improve the phase noise performance of the pll.
Disclosure of Invention
An aspect of the present invention provides a phase locked loop, which can cancel phase noise of the phase locked loop to improve phase noise performance of the phase locked loop.
The phase-locked loop provided by the invention comprises: the phase discriminator is used for detecting the phase difference between the output clock of the phase-locked loop and the reference clock and converting the phase difference into control voltage; an oscillator for outputting an output clock of the phase-locked loop according to the control voltage; a phase noise cancellation circuit; the phase noise cancellation circuit includes: a voltage-controlled delay device and a phase difference voltage converter comprising a first capacitor; the phase difference voltage converter is used for converting the phase difference into voltage and storing the converted voltage in the first capacitor; the voltage-controlled delayer is used for generating a delay signal opposite to the phase difference according to the output voltage of the phase difference voltage converter and the output clock control, and enabling the output clock to overlap the delay signal so as to offset the phase difference.
In a preferred embodiment of the present invention, the phase difference voltage converter includes: the first P-type switching tube P1, the second N-type switching tube N2, the third N-type switching tube N3 and the first capacitor CS1;
the gate/base electrode of the first P-type switching tube P1 is connected with a reset signal RSTB, the source/emitter electrode of the first P-type switching tube P1 is connected with a power supply voltage VDD, the drain/collector electrode of the first P-type switching tube P1 is grounded through a first capacitor CS1, and the drain/collector electrode of the first P-type switching tube P1 is connected with the drain/collector electrode of a third N-type switching tube; the grid/base electrode of the third N-type switch tube N3 is connected with the phase difference, and the source electrode/emitter electrode of the third N-type switch tube N3 is grounded through the second N-type switch tube.
In a preferred embodiment of the present invention, the phase difference voltage converter further includes: the switch S1 and the second capacitor CS2, both ends of the switch S1 are connected with the drain electrode/collector electrode of the first P-type switching tube, and the second capacitor CS2 is connected between the drain electrode/collector electrode of the first P-type switching tube and the ground, so that when the switch S1 is closed, the first voltage on the first capacitor is transmitted to the second capacitor.
In a preferred embodiment of the present invention, the reset signal controls the first P-type switching tube to be closed, so that the switch S1 is opened when the first capacitor is charged; after the first capacitor is discharged, the switch S1 is closed, so that the first voltage on the first capacitor is transmitted to the second capacitor.
In a preferred embodiment of the present invention, the voltage controlled delay comprises: the first current source, the second P-type switching tube P2, the third P-type switching tube P3, the comparator, the fourth N-type switching tube N4, the fifth N-type switching tube N5, the third capacitor CPNC and the buffer;
one end of the first current source is connected with a power supply voltage VDD, and the other end of the first current source is connected with a source electrode/emitter electrode of the second P-type switching tube P2; the drain electrode/collector electrode of the second P-type switching tube P2 sequentially passes through a third P-type switching tube P3 and a third capacitor CPNC and then is grounded, and the grid electrode/base electrode of the second P-type switching tube P2 is electrically connected with a first control signal; the inverting input end of the comparator is connected with the output end of the phase difference voltage converter, the positive input end of the comparator is connected with the drain electrode/collector electrode of the third P-type switching tube P3, and the output end of the comparator is connected with the grid electrode/base electrode of the third P-type switching tube P3; the input end of the buffer is grounded after passing through a fifth N-type switching tube N5 and a fourth N-type switching tube N4 in sequence, and the input end of the buffer is connected with one end of the third capacitor; the grid electrode/base electrode of the fifth N-type switching tube N5 is connected with the output clock; the output end of the buffer is the output end of the voltage-controlled delay device.
In a preferred embodiment of the present invention, further comprising: the second current source and the first N-type switch tube N1, one end of the second current source is connected with the power supply voltage, the other end of the second current source is grounded through the first N-type switch tube, and the current on the first N-type switch tube N1 forms mirror current with the discharge current of the first capacitor and the discharge current of the third capacitor.
In a preferred embodiment of the present invention, the ratio of the capacitance values of the first capacitor CS1 and the second capacitor CS2 is fixed.
In a preferred embodiment of the present invention, the phase-locked loop further includes a frequency divider connected between the output clock and the phase detector for dividing the output clock, the phase difference being a phase difference between a divided clock output from the frequency divider and a reference clock; the phase noise cancellation circuit further includes a phase difference sampler for acquiring a phase difference between the divided clock and a reference clock and outputting the phase difference to the phase difference voltage converter.
In a preferred embodiment of the present invention, further comprising: and the charge pump and the low-pass filter are sequentially connected between the phase discriminator and the oscillator.
The invention also provides a phase noise cancellation method of the phase-locked loop, the phase-locked loop comprises: a phase noise cancellation circuit, the phase noise cancellation circuit comprising: a phase difference voltage converter including a first capacitor for converting a phase difference between an output clock of a phase-locked loop and a reference clock into a voltage and storing the converted voltage in the first capacitor; and a voltage controlled retarder electrically connected to the phase difference voltage converter; the method comprises the following steps:
Detecting the phase difference between an output clock of the phase-locked loop and a reference clock and converting the phase difference into a control voltage;
controlling an oscillator of a phase-locked loop to output an output clock of the phase-locked loop according to the control voltage;
converting a phase difference between an output clock of a phase-locked loop and a reference clock into a voltage and storing the converted voltage in the first capacitor;
generating a delay signal opposite to the phase difference according to the output voltage of the phase difference voltage converter and the output clock, and enabling the output clock to overlap the delay signal so as to offset the phase difference.
In a preferred embodiment of the present invention, the converting the phase difference between the output clock of the phase locked loop and the reference clock into a voltage and storing the converted voltage in the first capacitor includes: controlling a power supply voltage to charge the first capacitor until the voltage value on the first capacitor is the voltage value of the power supply voltage; and controlling the discharge of the first capacitor according to the phase difference so as to convert the phase difference into voltage, and storing the converted voltage in the first capacitor.
In a preferred embodiment of the present invention, the phase difference voltage converter further includes a second capacitor converting the phase difference into a voltage and storing the converted voltage in the first capacitor, and further includes: the upper polar plates of the first capacitor and the second capacitor are electrically connected by control, so that the first voltage on the first capacitor is transmitted and stored in the second capacitor.
In a preferred embodiment of the present invention, the voltage controlled delay device includes a third capacitor and a buffer having an input terminal electrically connected to the third capacitor, the generating a delay signal opposite to the phase difference according to an output voltage of the phase difference voltage converter and the output clock control, and the superimposing the delay signal by the output clock includes:
controlling to charge the third capacitor;
comparing whether the voltage on the third capacitor is larger than the output voltage of the phase difference voltage converter, if so, stopping charging the third capacitor, and if not, continuing charging the third capacitor;
and when the output clock is at a high level, discharging the third capacitor, connecting the voltage on the third capacitor into the buffer, outputting a high level by the voltage-controlled delay if the voltage on the third capacitor is lower than the inversion voltage of the buffer, and outputting a low level by the voltage-controlled delay if the voltage on the third capacitor is higher than the inversion voltage of the buffer.
The invention also provides a chip comprising a phase locked loop as claimed in any one of the preceding claims.
The invention also provides an electronic device comprising a phase locked loop as claimed in any one of the preceding claims.
The phase-locked loop provided by the invention forms a phase noise cancellation circuit through the phase difference voltage converter and the voltage-controlled delay device, and further converts the phase difference between the output clock and the reference clock of the phase-locked loop into voltage through the phase difference voltage converter and stores the converted voltage in the first capacitor. The voltage-controlled delay device controls the delay signal generated by the opposite phase difference according to the output voltage and the output clock of the phase difference voltage converter, and the output clock of the phase-locked loop is enabled to overlap the delay signal, so that the output clock of the phase-locked loop can be offset after overlapping the delay signal. The phase difference voltage converter converts the phase difference into voltage and stores the voltage on the capacitor, and outputs corresponding voltage to control the voltage-controlled delay device to generate a signal opposite to the phase difference, and the output clock is combined to control to generate a delay signal opposite to the phase difference, so that after the output clock output by the oscillator of the phase-locked loop enters the voltage-controlled delay device, the phase difference can be counteracted, and further the phase noise performance of the phase-locked loop is greatly improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a phase locked loop according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a phase-locked loop according to another embodiment of the present invention;
FIG. 3 is a circuit diagram of a phase noise cancellation circuit of a phase locked loop provided by the embodiment of FIG. 2;
FIG. 4 is a waveform diagram of the phase locked loop in the embodiment shown in FIGS. 3 and 2;
fig. 5 is a flowchart of a phase noise cancellation method according to an embodiment of the present invention;
fig. 6 is a flowchart of a phase noise cancellation method according to another embodiment of the present invention.
In the figure: 10. a phase detector; 20. an oscillator; 30. a phase difference sampler; 31. a phase difference voltage converter; 32. a voltage controlled retarder; 12. a charge pump; 13. a low pass filter;
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The Phase-Locked Loop (PLL) provided by the embodiment of the invention can be widely applied in a plurality of fields, including but not limited to the following application fields:
communication system: PLLs are used for clock recovery, modem, timing recovery, etc. in digital and analog communication systems.
Audio processing: PLL's may be used in digital audio processors, clock recovery in audio devices, jitter suppression, etc.
Video processing: PLL's can be used in digital video processors, clock recovery in video devices, jitter suppression, and the like.
And (3) power management: the PLL may be used in clock synchronization, frequency synthesis, etc. in a power management chip to improve the energy efficiency of the system.
Testing and measuring: PLLs can be used in testing and measuring equipment for frequency synthesis, clock recovery, etc. to improve equipment performance and accuracy.
A sensor: PLLs may be used for clock synchronization, signal conditioning, etc. in certain sensor systems.
Other applications: the PLL is also widely applied to fields and products such as radar, satellite communication, radar high-definition image processing, radar SAR imaging, optical fiber communication, airborne radar and the like.
The PLL may be applied to, but is not limited to, the following: digital televisions, digital audio processors, frequency modulated radios, GPS receivers, digitizer, mixers, radio frequency synthesizers, mobile telephones, wireless local area networks, power management chips, and the like.
In the following description, for the purpose of providing a thorough understanding of the present invention, detailed structures and steps are presented in order to illustrate the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.
Referring to fig. 1, the phase-locked loop provided by the present invention includes: phase detector 10, oscillator 20, and a phase noise cancellation circuit for canceling the phase noise of the phase locked loop. The phase detector 10 is configured to detect a phase difference between an output clock of the phase-locked loop and a reference clock and convert the phase difference into a control voltage; an oscillator 20 outputting an output clock of the phase-locked loop according to the control voltage; the phase noise cancellation circuit includes: the voltage-controlled delay 32 and the phase difference voltage converter 31 including the first capacitor. The phase detector 10 and the oscillator 20 can form a traditional phase-locked loop, and the phase noise cancellation circuit can remove the phase noise of the phase-locked loop.
Specifically, since the phase difference voltage converter 31 converts the phase difference into a voltage and stores the voltage in a capacitor (i.e., the first capacitor), the output voltage of the phase difference voltage converter 31 includes the phase difference information, and the output voltage including the phase difference information is transmitted to the voltage-controlled delay 32; to control the operation of the voltage controlled delay 32. The voltage-controlled delay 32 generates a signal opposite to the above-described phase difference based on the output voltage of the phase difference voltage converter 31, and generates a delayed signal opposite to the phase difference in conjunction with the output clock control. That is, the voltage-controlled delay 32 may combine the voltage stored on the first capacitor and the output clock output from the oscillator 20 to generate a delayed signal opposite to the phase difference. Therefore, the phase difference can be canceled out after the output clock from the oscillator 20 enters the voltage-controlled delay 32 and the delay signal is superimposed. In summary, the phase difference between the sampled reference clock and the output clock of the phase-locked loop is converted into a voltage signal, and the voltage signal is stored in the capacitor. The voltage signal then controls the voltage controlled delay circuit to produce a delay opposite the sampling phase difference. When the output clock of the phase-locked loop passes through the voltage-controlled delay circuit of the feedforward circuit, the phase error between the output clock and the reference clock can be reduced, and further the phase noise performance of the phase-locked loop is greatly improved.
In a preferred embodiment of the present invention, the phase difference voltage converter 31 in the phase noise cancellation circuit includes: the first P-type switching tube P1, the second N-type switching tube N2, the third N-type switching tube N3 and the first capacitor CS1; the gate/base electrode of the first P-type switching tube P1 is connected with a reset signal RSTB, the source/emitter electrode of the first P-type switching tube P1 is connected with a power supply voltage VDD, the drain/collector electrode of the first P-type switching tube P1 is grounded through a first capacitor CS1, and the drain/collector electrode of the first P-type switching tube P1 is connected with the drain/collector electrode of a third N-type switching tube; the grid/base electrode of the third N-type switch tube N3 is connected with the phase difference, and the source electrode/emitter electrode of the third N-type switch tube N3 is grounded through the second N-type switch tube. Therefore, the first capacitor can be controlled to be charged by controlling the on-off state of the first P-type switching tube P1. The third N-type switching tube N3 is grounded through the second N-type switching tube N2, one end of the first capacitor is connected with the third N-type switching tube N3, and the other end of the first capacitor is grounded, so that the on-off of the third N-type switching tube N3 can be controlled through the phase difference, the first capacitor can be controlled to be discharged, and the voltage on the first capacitor can contain the information of the phase difference. Therefore, the output voltage including the phase difference information can be led out to the voltage-controlled delay 32 by taking one end of the first capacitor as the output terminal of the phase difference voltage converter 31, so as to control the operation of the voltage-controlled delay 32. The phase difference voltage converter 31 with the structure has a simple circuit structure, can quickly and accurately convert the phase difference of the phase-locked loop into voltage information, and is used for charging the first capacitor, wherein the power supply is preferably the power supply voltage VDD of the phase-locked loop, so that the existing resources of the phase-locked loop can be further reused, the circuit structure is further simplified, and the interference and the error are reduced. In addition, the voltage converted by the phase difference is stored in the first capacitor, and the voltage-controlled delay device 32 can be controlled to generate a delay signal through the voltage on the first capacitor, so that the phase difference can be counteracted when the delay signal is overlapped by the output clock.
Referring to fig. 2, 3, and 4, fig. 2 is a schematic structural diagram of a phase-locked loop according to another embodiment of the present invention; FIG. 3 is a circuit diagram of a phase noise cancellation circuit of a phase locked loop provided by the embodiment of FIG. 2; fig. 4 is a waveform diagram of the phase locked loop in the embodiment shown in fig. 3 and 2. In this embodiment, the phase difference voltage converter 31 further includes: the switch S1 and the second capacitor CS2, both ends of the switch S1 are connected with the drain electrode/collector electrode of the first P-type switching tube, and the second capacitor CS2 is connected between the drain electrode/collector electrode of the first P-type switching tube and the ground, so that when the switch S1 is closed, the first voltage on the first capacitor is transmitted to the second capacitor. By adding S1 and the second capacitor CS2, the interference of the phase difference voltage converter 31 to the voltage-controlled delay 32 during sampling can be reduced, and jitter can be reduced.
In this embodiment, the voltage controlled delay 32 includes: the first current source I1, the second P-type switching tube P2, the third P-type switching tube P3, the comparator, the fourth N-type switching tube N4, the fifth N-type switching tube N5, the third capacitor CPNC and the buffer. One end of the first current source I1 is connected with the power supply voltage VDD, and the other end of the first current source I1 is connected with the source/emitter of the second P-type switching tube P2; the drain electrode/collector electrode of the second P-type switching tube P2 sequentially passes through a third P-type switching tube P3 and a third capacitor CPNC and then is grounded, and the grid electrode/base electrode of the second P-type switching tube P2 is electrically connected with a first control signal; the inverting input end of the comparator is connected with the output end of the phase difference voltage converter 31, the forward input end of the comparator is connected with the drain electrode/collector electrode of the third P-type switching tube P3 and the input end of the buffer, and the output end of the comparator is connected with the grid electrode/base electrode of the third P-type switching tube P3; the input end of the buffer is grounded after passing through a fifth N-type switching tube N5 and a fourth N-type switching tube N4 in sequence, and the input end of the buffer is connected with one end of the third capacitor; the grid electrode/base electrode of the fifth N-type switching tube N5 is connected with the output clock; the output of the buffer is the output of the voltage controlled delay 32. In this embodiment, the buffer is formed of two inverters.
The oscillator 20 in the phase locked loop is typically a Voltage controlled oscillator (Voltage-controlled oscillator VCO). Although each module of the phase locked loop produces noise, the voltage controlled oscillator 20 tends to consume the greatest power consumption and is the greatest source of noise. The phase noise of the voltage controlled oscillator 20 is a high pass filter by the signal loop of the phase locked loop. Therefore, in order to obtain a higher phase noise filtering effect, it is necessary to increase the phase path bandwidth of the phase locked loop. However, the increase in bandwidth further worsens the spurious performance of the reference clock, reduces the phase margin of the loop, and even destabilizes the phase locked loop. The phase-locked loop provided by the invention adopts an open loop feedforward phase noise cancellation mode, and phase noise high-pass filtering with high bandwidth is realized in an open loop, so that clock spurious can not be introduced into the phase-locked loop provided by the invention, and the problems of clock spurious and loop stability can be avoided.
However, to achieve better open loop feedforward cancellation of phase noise, it is often necessary to calibrate the gain of the phase noise cancellation. Otherwise, the feedforward phase noise cancellation effect is obviously reduced along with the influence of factors such as process manufacturing, temperature change, power supply voltage change and the like. Therefore, preferably, the phase-locked loop provided by the present invention further includes: the second current source I2 and the first N-type switch tube N1, one end of the second current source I2 is connected with the power supply voltage, the other end of the second current source I2 is grounded through the first N-type switch tube, and the current on the first N-type switch tube N1, the discharging current of the first capacitor and the discharging current of the third capacitor form mirror currents. In this way, the gain of the phase noise cancellation circuit in the phase-locked loop can be more stable within a fixed range, and the gain of the phase noise cancellation circuit does not need to be calibrated, or the process of calibrating the gain is reduced. Further preferably, the ratio of the capacitance values of the first capacitor CS1 and the second capacitor CS2 is fixed. The gain of the phase noise cancellation circuit in the phase-locked loop can be completely fixed, and the gain of the phase noise cancellation circuit is not required to be calibrated at all. (for specific reasons, see the following detailed description of the working principle and working procedure of the phase-locked loop), the phase-locked loop provided by the invention may have at least the following advantages: the gain calibration algorithm is reduced or even avoided from being added, so that a series of negative effects are brought to the phase-locked loop, a chip where the phase-locked loop is located, an electronic device where the phase-locked loop is located and the like (for example, the complexity of design is increased, the area and the power consumption of the chip are increased, the convergence of the complex calibration algorithm brings about the reduction of the robustness of the system, the calibration algorithm needs longer calibration time, and the fast-changing power supply voltage interference cannot be dealt with). Therefore, the phase-locked loop provided by the invention can realize constant gain without calibrating gain, so as to realize better phase noise cancellation, and further improve the phase noise performance of the phase-locked loop.
Referring to fig. 4, in a preferred embodiment of the present invention, the phase locked loop further includes: and a frequency divider connected between the output clock and the phase detector 10 for dividing the output clock. Among them, the frequency divider is an important part of the phase-locked loop circuit, and functions to reduce the frequency of the input signal to a frequency range that can be handled by the phase-locked loop. By means of the frequency divider the frequency of the input signal can be reduced so that it can be correctly received and processed by the phase locked loop. In addition, the frequency divider can also provide phase information of the input signal, so that the phase-locked loop can accurately lock the frequency and the phase of the input signal. By comparing the input signal with a reference signal, the phase locked loop can achieve accurate control of the frequency and phase of the input signal. In this embodiment, the phase difference obtained by the phase detector 10 is the phase difference between the divided clock div_out and the reference clock ref_clk output by the frequency divider, which is also within the protection scope of the present invention. The phase noise cancellation circuit further comprises a phase difference sampler 30 for acquiring a phase difference between the divided clock and a reference clock and outputting the phase difference to the phase difference voltage converter 31. Therefore, the phase difference obtained by the phase difference voltage converter 31 in the phase-locked loop provided by the invention can be the phase difference obtained by the phase detector 10, or can be the phase difference obtained by the phase difference sampler 30 in the phase noise cancellation circuit. The noise cancellation circuit is provided with the phase difference sampler 30, so that the circuit structure of the phase-locked loop can be more flexible, and the phase-locked loop is suitable for more types of phase-locked loops and can be suitable for more electronic circuits and electronic devices.
Further preferably, the phase-locked loop provided by the present invention further includes: and a charge pump 12 and a low pass filter 13 connected in turn between the phase detector 10 and the oscillator 20. The charge pump 12 converts the voltage signal output by the phase detector 10 into a current signal, and then the current signal is further filtered by the low-pass filter 13, so that the noise of the phase-locked loop is smaller and the performance is better.
The following describes the working principle and working procedure of the phase-locked loop according to the present invention in detail with reference to fig. 2, 3, and 4:
the phase detector 10 of the phase-locked loop collects the phase difference between the divided clock output from the frequency divider and the reference clock, and converts the phase difference into a control voltage to control the operation of the oscillator 20, and the oscillator 20 outputs the output clock of the phase-locked loop according to the control voltage. The phase difference between the divided clock and the reference clock, and the phase difference between the output clock output from the oscillator 20 and the reference clock are substantially the same and are within the scope of the present invention. The output clock pll_out enters the phase detector 10 after being divided by the frequency divider, and the frequency of the output clock pll_out is N times the frequency division clock div_out, where N is the frequency division ratio of the frequency divider.
The phase difference sampler 30 in the phase noise cancellation circuit is implemented by an and gate to compare the phases of the reference clock and the divided clock output by the divider, so as to obtain the phase difference between the reference clock and the divided clock, where the phase difference is output in the form of a pulse signal (i.e., the pulse signal sam_out in fig. 3). On the one hand, when the reset signal connected to the control end of the first P-type switching tube P1 is enabled, the first P-type switching tube P1 is turned on, and then the power supply voltage VDD charges the first capacitor CS1 until the voltage value on the first capacitor CS1 is VDD, and since the lower electrode plate of the first capacitor is grounded, that is, the voltage of the upper electrode plate of the first capacitor is VDD, the reset signal turns off the first P-type switching tube. Then, when the rising edge of the pulse signal sam_out corresponding to the phase difference comes, the third N-type switching tube and the second N-type switching tube are triggered to be turned on, and the first capacitor CS1 discharges. The phase difference sampler 30 controls the on time of the third N-type switching transistor N3 through the pulse width of the pulse signal sam_out, thereby controlling the discharging of the first capacitor CS1 and controlling the voltage on the first capacitor CS 1. Therefore, the voltage information on the first capacitor includes the information of the phase difference and is stored on the first capacitor. When the switch S1 is turned on by the control signal ph_sam1 of the switch S1, the voltage information on the first capacitor is transferred to the second capacitor CS2 by the charge sharing principle, and the second voltage VCS2 on the second capacitor is used as the output voltage of the phase difference voltage converter 31 to control the voltage-controlled delay 32. When the control signal pnc_chap of the second P-type switching transistor in the voltage-controlled delay 32 and the output signal cmp_out of the comparator are at low level at the same time, the current source i_cha charges the third capacitor CPNC, and the voltage on the third capacitor CPNC increases continuously. When the voltage on the third capacitor CPNC increases to exceed the second voltage VCS2 connected to the inverting input terminal of the comparator, cmp_out outputs a high voltage, and thus the third P-type switching transistor P3 is turned off. Through the above operation, the voltage VCS2 on the second capacitor is copied to the capacitor CPNC. When the rising edge of the output clock pll_out passes through the voltage-controlled delay 32, its rising edge triggers the fifth N-type switching transistor N5 to turn on, and the current i_pnc discharges the third capacitor CPNC. When the voltage VCPNC on the third capacitor drops below the inverting Voltage (VTRIG) of the buffer, the buffer outputs a high level. Thus, the voltage-controlled delay unit 32 can control generation of a delay signal opposite to the phase difference based on the output voltage of the phase difference voltage converter 31 and the output clock, and superimpose the delay signal on the output clock to cancel the phase difference.
In a further preferred embodiment of the present invention, it is possible to achieve a constant gain of the phase noise cancellation circuit without the need to calibrate the gain, thereby avoiding a series of problems caused by introducing a gain calibration algorithm. The reason for this is roughly described as follows: as shown in fig. 4, after the phase-locked loop is locked, the phase difference sampler 30 performs phase sampling on the frequency division clock div_out output from the frequency divider, and the phase difference sampler 30 outputs a pulse sam_out. The pulse width of SAM OUT (Δtsam OUT) at this time includes a fixed delay time Δtdc and a random time error Δterr introduced by device noise or interference of the phase locked loop circuit. The calculation formula of Δtsam_out is as follows:
ΔtSAM_OUT=Δtdc+Δterr （1）；
the output div_out of the frequency divider is directly driven and divided by pll_out. Thus, the phase error of pll_out is directly transmitted to div_out. Phase-difference sampling of div_out is equivalent to phase-difference sampling of pll_out. Alternatively, the phase error may be obtained by dividing the time error by the center frequency of the output clock of the phase locked loop and multiplying by 2pi. Since the locked phase-locked loop center frequency is constant with pi and the phase error is equivalent to the time error, canceling the time error is equivalent to canceling the phase error.
When the reset signal RSTB is at a low level, the first P-type switching transistor P1 is turned on, and the upper plate voltage of the capacitor CS1 is further charged to be equal to the power supply voltage VDD. After that, the output pulse sam_out containing the phase difference discharges the first capacitor CS1 by controlling the switching time of the third N-type switching transistor N3, and the sampled voltage value after the first capacitor CS1 is discharged is VCS1, which has the following calculation formula:
VCS1=VDD-（ΔtSAM_OUT×I_SAM）/CS1 （2）；
because Δtsam_out includes time error information Δterr of pll_out, VCS1 also includes information of Δterr.
When the ph_sam1 is enabled effectively, the first capacitor CS1 is connected to the second capacitor CS2, so as to perform capacitor sharing, and the calculation formula of the voltage VCS2 on the upper plate of the second capacitor CS2 is as follows:
VCS2= VCS1×CS1/(CS1+CS2)（3）；
when the voltage VCPNC on the third capacitor is less than VCS2, the output cmp_out of the comparator is low. When PNC_CHAB and CMP_OUT are both low voltage, the current source I_CHA charges the third capacitor CPNC, when the voltage VCPNC of the upper polar plate of the third capacitor CPNC exceeds VCS2, the output CMP_OUT of the comparator is high level, the third P-type switching tube P3 is closed, and the charging is stopped. The voltage VCPNC is theoretically equal to VCS 2. However, real comparators have offset voltage and output delay. The VCPNC actual voltage calculation formula is as follows:
VCPNC= VOS_CMP+Δtdelay×I_CHA/CPNC+VCS2（4）；
Where vos_cmp is the offset voltage of the comparator, Δtdelay is the output delay of the comparator, i_cha is the current charged by the current source in the voltage-controlled delay 32, and CPNC is the capacitance value of the third capacitor. However, the offset voltage vos_cmp of the comparator and the output delay Δtdelay of the comparator are fixed errors, and only a fixed time difference is introduced to the output pnc_bufout of the feedforward phase noise cancellation circuit, so that random phase noise is not introduced.
As shown in fig. 3, when the pll_out has a time error Δterr with respect to the reference clock ref_clk, since div_out is obtained by pll_out triggering and frequency division, the same time error Δterr occurs at the rising edge of div_out. When the rising edge of pll_out passes through the voltage-controlled delay 32, its rising edge triggers the fifth N-type switching transistor N5 to turn on, and the current i_pnc discharges the third capacitor CPNC. When the voltage of the VCPNC is lower than the inversion Voltage (VTRIG) of the buffer, the buffer outputs a high level.
Assuming that the rising edge of the phase-noise-free PLL output signal occurs at times T1, T2, and T3, the actual pll_out rising edge occurs at times t1+Δter1, t2+Δter2, t3+Δter3, where Δter1, Δter2, and Δter3 are the temporal noise of pll_out at times T1, T2, and T3, respectively. After time T2, the output of the voltage-controlled delay 32, i.e. the output of the buffer, outputs the first output rising edge time (TPNC 2) of the signal pnc_bufout as follows:
TPNC2= T2+Δterr2+ (VCPNC_T2-VTRIG)/I_PNC（5）；
Wherein vcpnc_t2 is the upper plate voltage of the third capacitor CPNC at time T2.
The vcpnc_t2 is calculated by the following general formulas (1), (2), (3), (4), (5):
VCPNC_T2= VOS_CMP+Δtdelay×I_CHA/CPNC+VDD-（Δtdc+Δterr1)×I_SAM×CS1/(CS1+CS2)（6）；
all the fixed constants in equation (6) are set to 0 because they will only introduce a constant phase difference to the output pnc_bufout of the phase noise cancellation circuit, not introduce random phase noise. At the time of TPNC2, the time noise of pnc_bufout is tpnc2_err, and the calculation formula is as follows:
TPNC2_err= Δterr1×I_SAM×CS1/(CS1+CS2)/I_PNC-Δterr2（7）；
for the low frequency part noise of the output clock pll_out, Δter1≡Δter2. The gain of the feedforward phase noise cancellation circuit is defined as:
PNC_GAIN= I_SAM×CS1/(CS1+CS2)/I_PNC（8）；
in the formula (8), CS1 is a capacitance value of the first capacitor, CS2 is a capacitance value of the second capacitor, i_sam is a discharge current of the first capacitor, and i_pnc is a discharge current of the third capacitor. When the GAIN PNC _ gain=1, at the moment TPNC2,
TPNC2_err=Δterr1-Δterr2（9）；
at the moment TPNC2, the pll_outoriginal noise Δterr2 is subtracted by Δterr1. Similarly, at time TPNC3, pll_out original noise Δterr3 is subtracted by Δterr1. By subtracting Δter1 in the time domain, the feedforward cancellation circuit equivalently performs high-pass filtering on the phase noise of the output clock pll_out.
As can be seen from the formula (8), the gain of the phase noise cancellation circuit is related to the ratio i_sam/i_pnc of the two discharge currents and the ratio CS 1/(cs1+cs2) of the capacitance values. Referring to fig. 3, since the first, second, and fourth N-type switching transistors N1, N2, and N4 form a current mirror circuit, the ratio i_sam/i_pnc of the two discharge currents is fixed. The first capacitor CS1 and the second capacitor CS2 provided by the invention can be generated by the same type capacitor device, so that the ratio of the capacitance values of the first capacitor CS1 and the second capacitor CS2 is fixed, and the ratio of CS 1/(CS 1+CS 2) is further fixed, so that the gain of the phase-locked loop provided by the invention can be a fixed value, and the gain of the phase-locked loop provided by the invention can be kept unchanged under the influence of factors such as manufacturing process variation, power supply voltage variation, temperature variation and the like without calibrating the gain, and further the phase noise performance of the phase-locked loop is improved.
In the phase-locked loop provided by the invention, each switch tube can be various electronic components capable of playing a role of switching, for example, can be a triode or a field effect tube. The buffer may be implemented by an inverter. In an embodiment of the present invention, the capacitor in the phase difference voltage converter 31 is only the first capacitor, in which case, the upper plate of the first capacitor is led out of the output end of the phase difference voltage converter 31 and is electrically connected to the input end of the voltage-controlled delay 32 (i.e. the inverting input end of the comparator in the voltage-controlled delay 32), and the lower plate of the first capacitor is grounded. Therefore, the output voltage of the phase difference voltage converter 31, i.e. the voltage VCS1 across the first capacitor, i.e. the voltage across the upper plate of the first capacitor, can be used to control the operation of the voltage controlled delay 32. Further preferably, the phase difference voltage converter 31 further includes a second capacitor CS2 and a switch S1, wherein two ends of the switch S1 are respectively connected to an upper plate of the first capacitor and an upper plate of the second capacitor, and a lower plate of the second capacitor is grounded. When the first capacitor CS1 is charging, the switch S1 may be turned off. After the first capacitor CS1 and the second capacitor CS are shared, the switch S1 may be turned off, so that the voltage-controlled delay 32 is not affected to generate a corresponding delay signal according to the phase difference information stored in the second capacitor CS, and the front end continuous acquisition phase difference is not affected, so that the phase noise cancellation can be continuously performed, the influence of the front end circuit on the back end circuit during operation can be reduced, particularly the interference to the voltage-controlled delay 32 during the phase difference sampling is reduced, and the jitter of the phase-locked loop is further reduced.
The invention also provides a phase noise cancellation method, which is suitable for a phase-locked loop, wherein the phase-locked loop comprises: a phase noise cancellation circuit, the phase noise cancellation circuit comprising: a phase difference voltage converter 31 including a first capacitor for converting a phase difference between an output clock of a phase locked loop and a reference clock into a voltage and storing the converted voltage in the first capacitor; and a voltage-controlled retarder 32 electrically connected to the phase difference voltage converter 31; the method comprises the following steps:
s10, detecting the phase difference between an output clock of a phase-locked loop and a reference clock and converting the phase difference into control voltage;
s20, controlling an oscillator of the phase-locked loop to output an output clock of the phase-locked loop according to the control voltage;
s30, converting the phase difference between the output clock of the phase-locked loop and the reference clock into voltage and storing the converted voltage in a first capacitor;
s40, generating a delay signal opposite to the phase difference according to the output voltage of the phase difference voltage converter and the output clock control, and enabling the output clock to overlap the delay signal so as to offset the phase difference.
Compared with the traditional phase-locked loop working process, the phase noise cancellation process is mainly added, phase noise cancellation is realized through feedforward, specifically, the obtained phase difference between the output clock and the reference clock of the phase-locked loop is converted into a voltage signal, and the voltage converted by the phase difference is stored in the first capacitor, so that dynamic adjustment can be performed according to the real-time phase difference, and a delay signal opposite to the phase difference can be generated in real time according to the voltage signal (namely the output voltage of the phase difference voltage converter 31) stored in the first capacitor and the output clock, and the phase difference can be cancelled by superposing the delay signal when the output clock enters the voltage-controlled delay 32, thereby greatly improving the phase noise performance of the phase-locked loop. It should be noted that, the execution sequence of the phase noise cancellation method provided by the present invention is not limited to the sequence shown in the above steps.
In a preferred embodiment of the present invention, the step S30 includes: step S31, controlling the power supply voltage to charge the first capacitor until the voltage value on the first capacitor is the voltage value of the power supply voltage; step S32, controlling the discharge of the first capacitor according to the phase difference so as to convert the phase difference into voltage, and storing the converted voltage in the first capacitor; the step S32 further includes a step S33: the upper polar plates of the first capacitor and the second capacitor are electrically connected by control, so that the first voltage on the first capacitor is transmitted to the second capacitor and stored in the second capacitor. Step S40 includes: controlling to charge the third capacitor; comparing whether the voltage on the third capacitor is larger than the output voltage of the phase difference voltage converter 31, if so, stopping charging the third capacitor, and if not, continuing charging the third capacitor; the voltage-controlled delay 32 receives the output clock and discharges the third capacitor when the output clock is at a high level, and the voltage on the third capacitor is connected to the buffer, if the voltage on the third capacitor is lower than the inversion voltage of the buffer, the voltage-controlled delay 32 outputs a high level, and if the voltage on the third capacitor is higher than the inversion voltage of the buffer, the voltage-controlled delay 32 outputs a low level.
Referring to fig. 2-6 specifically, the reset signal RSTB is controlled to be at a low level, so that the switching tube P1 is closed to charge the first capacitor CS1 by the power supply voltage VDD, and since the lower plate of the first capacitor CS1 is grounded, until the voltage VCS1 of the upper plate of the first capacitor reaches the value of VDD, the reset signal RSTB is controlled to be at a high level, so that the switching tube P1 is opened to stop charging the first capacitor CS 1; when the pulse signal sam_out containing the phase difference is at a high level, the trigger switch tube N3 is turned on to realize discharging of the first capacitor CS1, and since the time is equivalent to the phase difference, the pulse width of the pulse signal sam_out controls the discharging time of the first capacitor CS1 and thus controls the voltage on the first capacitor CS1, so that the voltage VCS1 on the first capacitor contains the phase difference between the output clock and the reference clock, and the voltage information containing the phase difference is stored on the first capacitor CS 1; the control signal ph_sam1 controls the switch S1 to be turned on, so that the first capacitor CS1 and the second capacitor CS2 are connected to perform charge sharing, and the voltage VCS1 on the first capacitor is further transferred to the second capacitor to form a second voltage VCS2 and stored in the second capacitor, so that the second voltage VCS2 on the second capacitor also includes the information of the phase difference; the control signal pnc_chap controls the switch tube P2 to be turned on, and the voltage value of VCS2 starts to be lower, so that the comparator outputs a low level, and the P-type switch tube P3 is turned on, so that the third capacitor CPNC is charged by VDD, during which the comparator compares whether the voltage on the third capacitor is greater than the output voltage of the phase difference voltage converter 31 (in this embodiment, the output voltage of the phase difference voltage converter 31 refers to the second voltage VCS2 on the second capacitor, and in some embodiments, only the first capacitor stores the phase difference in the phase difference voltage converter 31, the output voltage refers to the first voltage VCS1 on the first capacitor), and if not, the switch tube P3 is continuously turned on to continuously charge the third capacitor, until the voltage on the third capacitor is greater than VCS2, the switch tube P3 is controlled to be turned off to stop charging the third capacitor. (this process may enable the second voltage of the phase difference voltage converter 31, which includes the phase difference, to be copied to the third capacitor of the voltage-controlled delay 32); the output clock pll_out is connected to one input terminal of the voltage-controlled delay 32, when the output clock pll_out is at a high level, the switching tube N5 is triggered to be turned on, the switching tube N5 and the switching tube N4 are both turned on, and the discharging to the ground is realized, that is, the third capacitor is discharged, and the voltage on the third capacitor is connected to the buffer, if the voltage on the third capacitor is lower than the inversion voltage of the buffer, the voltage-controlled delay 32 outputs a high level, and if the voltage on the third capacitor is higher than the inversion voltage of the buffer, the voltage-controlled delay 32 outputs a low level. In this process, a delay signal opposite to the phase difference is formed, and the output clock input to the voltage-controlled delay 32 overlaps the delay signal, so that the phase difference can be cancelled, and thus phase noise can be cancelled.
The phase-locked loop provided by the embodiment of the invention can be applied to various fields, such as the AI field, for example, an analog-digital hybrid AI vision chip which is realized based on a sense-in-computation integrated technology architecture and comprises the phase-locked loop provided by the invention has better phase noise performance and lower power consumption and higher energy efficiency ratio. The corresponding AI vision chip can be applied to automatic driving, AR, VR and laser radar, and can also be widely applied to a series of application fields such as smart phones, tablet computers, wearable electronic equipment, intelligent household electronic products, industry or medical treatment or battery power supply.
The invention provides a chip which comprises any one of the phase-locked loops. For example, the chip can be applied to a high-speed interface chip, a wireless communication chip, a wired communication chip, a wearable main control chip, a mobile phone main control chip, an AR/VR main control chip and the like.
The chip provided by the embodiment of the invention comprises but is not limited to the following chips:
digital signal processing chip: including digital signal processors, digital audio processors, etc.
And a communication chip: including modems, radio frequency transceivers, baseband processors, etc.
Analog signal processing chip: including analog signal processors, analog converters, etc.
And a power management chip: including power managers, power controllers, and the like.
Test and measurement chip: including test and measurement equipment, data collectors, etc.
Other application chips: including sensors, embedded systems, etc.
The invention also provides electronic equipment comprising any one of the phase-locked loops. The corresponding electronic device is for example: smart phones, tablet computers, wearable electronic equipment, smart home electronics, AR, VR, lidar, automobiles, etc. For another example:
digital television set top box and digital television: PLL chips are often used in digital television set-top boxes and digital televisions for clock recovery, synchronization, frequency synthesis, and the like.
Wireless local area network routers and network switches: PLL chips are commonly used in wireless lan routers and network switches for clock synchronization, frequency synthesis, and the like.
A mobile communication device: PLL chips are often used in mobile communication devices for frequency synthesis, clock synchronization, etc.
Digital audio processor and fm radio: PLL chips are often used in digital audio processors and fm radios for clock recovery, frequency synthesis, jitter suppression, and the like.
Optical fiber communication apparatus: PLL chips are often used in fiber optic communications devices for clock recovery, frequency synthesis, synchronization, and the like.
Radar and satellite communication devices: PLL chips are often used in radar and satellite communication devices for frequency synthesis, synchronization, etc.
Data collector and test equipment: PLL chips are often used in data collectors and test equipment for frequency synthesis, clock synchronization, etc.
Power manager and power controller: PLL chips are often used in power managers and power controllers for clock synchronization, frequency synthesis, and the like.
In addition to the above devices, there are many other fields of application in which PLL chips are used, such as aerospace, automotive electronics, medical devices, industrial controls, etc.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.
Claims (16)
1. A phase locked loop, comprising:
The phase discriminator is used for detecting the phase difference between the output clock of the phase-locked loop and the reference clock and converting the phase difference into control voltage;
an oscillator for outputting an output clock of the phase-locked loop according to the control voltage; and
A phase noise cancellation circuit;
the phase noise cancellation circuit includes: a voltage-controlled delay device and a phase difference voltage converter comprising a first capacitor;
the phase difference voltage converter is used for converting the phase difference into voltage and storing the converted voltage in the first capacitor;
the voltage-controlled delayer is used for generating a delay signal opposite to the phase difference according to the output voltage of the phase difference voltage converter and the output clock control, and enabling the output clock to overlap the delay signal so as to offset the phase difference; the voltage-controlled delay device comprises a third capacitor and a buffer with an input end electrically connected with the third capacitor, the voltage-controlled delay device controls the third capacitor to discharge according to the output voltage of the output clock and the phase difference voltage converter, if the voltage on the third capacitor is lower than the inversion voltage of the buffer, the voltage-controlled delay device outputs a high level, and if the voltage on the third capacitor is higher than the inversion voltage of the buffer, the voltage-controlled delay device outputs a low level.
2. The phase locked loop of claim 1, wherein the phase difference voltage converter comprises: the first P-type switching tube P1, the second N-type switching tube N2, the third N-type switching tube N3 and the first capacitor CS1;
the gate/base electrode of the first P-type switching tube P1 is connected with a reset signal RSTB, the source/emitter electrode of the first P-type switching tube P1 is connected with a power supply voltage VDD, the drain/collector electrode of the first P-type switching tube P1 is grounded through a first capacitor CS1, and the drain/collector electrode of the first P-type switching tube P1 is connected with the drain/collector electrode of a third N-type switching tube; the grid/base electrode of the third N-type switch tube N3 is connected with the phase difference, and the source electrode/emitter electrode of the third N-type switch tube N3 is grounded through the second N-type switch tube.
3. The phase locked loop of claim 2, wherein the phase difference voltage converter further comprises: the switch S1 and the second capacitor CS2, both ends of the switch S1 are connected with the drain electrode/collector electrode of the first P-type switching tube, and the second capacitor CS2 is connected between the drain electrode/collector electrode of the first P-type switching tube and the ground, so that when the switch S1 is closed, the first voltage on the first capacitor is transmitted to the second capacitor.
4. The phase-locked loop of claim 3 wherein the reset signal controls the first P-type switching tube to be closed to charge the first capacitor, the switch S1 being opened; after the first capacitor is discharged, the switch S1 is closed, so that the first voltage on the first capacitor is transmitted to the second capacitor.
5. The phase locked loop of any one of claims 1-4, wherein the voltage controlled delay comprises: the first current source, the second P-type switching tube P2, the third P-type switching tube P3, the comparator, the fourth N-type switching tube N4, the fifth N-type switching tube N5, the third capacitor CPNC and the buffer;
one end of the first current source is connected with a power supply voltage VDD, and the other end of the first current source is connected with a source electrode/emitter electrode of the second P-type switching tube P2; the drain electrode/collector electrode of the second P-type switching tube P2 sequentially passes through a third P-type switching tube P3 and a third capacitor CPNC and then is grounded, and the grid electrode/base electrode of the second P-type switching tube P2 is electrically connected with a first control signal; the inverting input end of the comparator is connected with the output end of the phase difference voltage converter, the forward input end of the comparator is connected with the drain electrode/collector electrode of the third P-type switching tube P3 and the input end of the buffer, and the output end of the comparator is connected with the grid electrode/base electrode of the third P-type switching tube P3; the input end of the buffer is grounded after passing through a fifth N-type switching tube N5 and a fourth N-type switching tube N4 in sequence, and the input end of the buffer is connected with one end of the third capacitor; the grid electrode/base electrode of the fifth N-type switching tube N5 is connected with the output clock; the output end of the buffer is the output end of the voltage-controlled delay device.
6. The phase-locked loop of claim 5, further comprising: the second current source and the first N-type switch tube N1, one end of the second current source is connected with the power supply voltage, the other end of the second current source is grounded through the first N-type switch tube, and the current on the first N-type switch tube N1 forms mirror current with the discharge current of the first capacitor and the discharge current of the third capacitor.
7. A phase locked loop as claimed in claim 3, wherein the ratio of the capacitance values of the first capacitor CS1 and the second capacitor CS2 is fixed.
8. The phase locked loop of claim 1, further comprising a divider coupled between the output clock and the phase detector for dividing the output clock, the phase difference being a phase difference between a divided clock output by the divider and a reference clock; the phase noise cancellation circuit further includes a phase difference sampler for acquiring a phase difference between the divided clock and a reference clock and outputting the phase difference to the phase difference voltage converter.
9. The phase-locked loop of claim 1, further comprising: and the charge pump and the low-pass filter are sequentially connected between the phase discriminator and the oscillator.
10. A phase noise cancellation method of a phase locked loop, wherein the phase locked loop comprises: a phase noise cancellation circuit, the phase noise cancellation circuit comprising: a phase difference voltage converter including a first capacitor for converting a phase difference between an output clock of a phase-locked loop and a reference clock into a voltage and storing the converted voltage in the first capacitor; the voltage-controlled delay device is electrically connected with the phase difference voltage converter and comprises a third capacitor and a buffer with an input end electrically connected with the third capacitor; the method comprises the following steps:
detecting the phase difference between an output clock of the phase-locked loop and a reference clock and converting the phase difference into a control voltage;
controlling an oscillator of a phase-locked loop to output an output clock of the phase-locked loop according to the control voltage;
converting a phase difference between an output clock of a phase-locked loop and a reference clock into a voltage and storing the converted voltage in the first capacitor;
generating a delay signal opposite to the phase difference according to the output voltage of the phase difference voltage converter and the output clock, and enabling the output clock to overlap the delay signal so as to offset the phase difference; the voltage-controlled delay device controls the third capacitor to discharge according to the output clock and the output voltage of the phase difference voltage converter, if the voltage on the third capacitor is lower than the inversion voltage of the buffer, the voltage-controlled delay device outputs a high level, and if the voltage on the third capacitor is higher than the inversion voltage of the buffer, the voltage-controlled delay device outputs a low level.
11. The method of claim 10, wherein converting the phase difference between the output clock of the phase locked loop and the reference clock into a voltage and storing the converted voltage in the first capacitor, comprises:
controlling a power supply voltage to charge the first capacitor until the voltage value on the first capacitor is the voltage value of the power supply voltage;
and controlling the discharge of the first capacitor according to the phase difference so as to convert the phase difference into voltage, and storing the converted voltage in the first capacitor.
12. The method according to claim 10 or 11, wherein the phase difference voltage converter further comprises a second capacitor, after converting the phase difference into a voltage and storing the converted voltage in the first capacitor, further comprising: the upper polar plates of the first capacitor and the second capacitor are electrically connected by control, so that the first voltage on the first capacitor is transmitted to the second capacitor and stored in the second capacitor.
13. The method of claim 12, wherein the generating a delay signal opposite the phase difference from the output voltage of the phase difference voltage converter and the output clock control and superimposing the delay signal with the output clock comprises:
Controlling to charge the third capacitor;
comparing whether the voltage on the third capacitor is larger than the output voltage of the phase difference voltage converter, if so, stopping charging the third capacitor, and if not, continuing charging the third capacitor;
the voltage-controlled delay receives the output clock and discharges the third capacitor when the output clock is at a high level, and the voltage on the third capacitor is connected to the buffer.
14. The method of claim 13, wherein a ratio of the discharge current of the first capacitor to the discharge current of the third capacitor is a fixed value.
15. A chip comprising a phase locked loop as claimed in any one of claims 1 to 9.
16. An electronic device comprising a phase locked loop as claimed in any one of claims 1 to 9.
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