CN116978943A - Enhanced semiconductor device and preparation method thereof - Google Patents
Enhanced semiconductor device and preparation method thereof Download PDFInfo
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- CN116978943A CN116978943A CN202311182237.1A CN202311182237A CN116978943A CN 116978943 A CN116978943 A CN 116978943A CN 202311182237 A CN202311182237 A CN 202311182237A CN 116978943 A CN116978943 A CN 116978943A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 95
- 238000002360 preparation method Methods 0.000 title abstract description 10
- 230000004888 barrier function Effects 0.000 claims abstract description 107
- 239000012159 carrier gas Substances 0.000 claims abstract description 86
- 239000000758 substrate Substances 0.000 claims description 62
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 39
- 230000006911 nucleation Effects 0.000 claims description 27
- 238000010899 nucleation Methods 0.000 claims description 27
- 150000001875 compounds Chemical class 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 18
- 239000004047 hole gas Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 239000013078 crystal Substances 0.000 claims description 10
- 239000000969 carrier Substances 0.000 claims description 9
- 238000000407 epitaxy Methods 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 387
- 108091006146 Channels Proteins 0.000 description 211
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 49
- 229910002601 GaN Inorganic materials 0.000 description 47
- 238000005530 etching Methods 0.000 description 13
- 239000000463 material Substances 0.000 description 13
- 230000008569 process Effects 0.000 description 11
- 230000010287 polarization Effects 0.000 description 6
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical group [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7788—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The application relates to an enhanced semiconductor device and a preparation method thereof, belongs to the technical field of semiconductors, and is used for providing a vertical semiconductor device which has good performance and can meet the normally-off requirement. The enhanced semiconductor device comprises a channel layer, a first barrier layer, a second barrier layer, a first electrode, a second electrode and a third electrode, wherein the first barrier layer is obtained by epitaxial growth from a first vertical interface of the channel layer; the second barrier layer is obtained by epitaxial growth from a second vertical interface of the channel layer; the vicinity of the interface between the channel layer and the first barrier layer in the channel layer comprises a first carrier gas and a second carrier gas which are interrupted in the vertical direction; the third electrode is provided directly or indirectly on the second barrier layer and covers the semiconductor layer region where the first carrier gas and the second carrier gas are interrupted. The enhanced semiconductor device provided by the embodiment of the application has the advantages of low on-resistance, good switching characteristic and safe use.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to an enhanced semiconductor device and a preparation method thereof.
Background
III-V compounds are important semiconductor materials, such as AlN, gaN, inN, alP, gaAs and compounds of these materials, such as AlGaN, inGaN, alInGaN, etc. Because III-V compound has advantages of direct band gap, wide band gap, high breakdown field intensity, etc., III-V compound semiconductor represented by GaN is widely used in the fields of light emitting device, power electronics, radio frequency device, etc.
III-V compounds are a class of polar semiconductor materials. There is a fixed polarization charge at the surface of the polar semiconductor or at the interface of two different polar semiconductors. The presence of these fixed polarization charges can attract mobile carriers such as electrons or holes, thereby forming a two-dimensional electron gas (2 DEG) or a two-dimensional hole gas (2 DHG), and has a higher surface charge density. Meanwhile, the effect of ion scattering and the like of the two-dimensional electron gas or the two-dimensional hole gas is greatly reduced because doping of the semiconductor material is not needed, so that the semiconductor material has higher mobility.
Most of the III-V compound semiconductor devices commonly used in the industry are depletion type lateral power devices, and lateral type power devices face some key problems, such as: the presence of a spike electric field at the gate or drain causes the device to breakdown in advance; in order to meet the requirements of high-power devices, the area of the devices has to be increased sharply along with the increase of power; from the point of view of safety of circuit applications, enhancement mode devices are safer than depletion mode devices. There is a need for an enhanced vertical device that overcomes the performance problems associated with the lateral devices and meets the safety requirements of circuit applications.
Disclosure of Invention
Aiming at the technical problems in the prior art, the application provides an enhanced semiconductor device and a preparation method thereof, which are used for providing a vertical semiconductor device with good performance and capability of meeting the normally-off requirement.
In order to solve the technical problem, according to one aspect of the present application, there is provided an enhanced semiconductor device including a channel layer, a first barrier layer, a second barrier layer, a first electrode, a second electrode, and a third electrode. The channel layer comprises a first vertical interface and a second vertical interface with opposite crystal directions; the first barrier layer is obtained by epitaxial growth from the first vertical interface of the channel layer; the second barrier layer is obtained by epitaxial growth from the second vertical interface of the channel layer; the channel layer is provided with a first barrier layer, a second barrier layer and a first channel layer, wherein the channel layer is provided with a first carrier gas and a second carrier gas which are interrupted in the vertical direction near the interface between the channel layer and the first barrier layer, and the first carrier gas and the second carrier gas are two-dimensional hole gas or two-dimensional electron gas; the channel layer, the first barrier layer and the second barrier layer are respectively semiconductor layers of III-V compounds; the first electrode is provided on the channel layer corresponding to a first carrier gas; the second electrode is provided on the channel layer corresponding to a second carrier gas; the third electrode is directly or indirectly provided on the second barrier layer and covers the semiconductor layer region where the first carrier gas and the second carrier gas are interrupted, and a conductive path can be formed between the first electrode and the second electrode when a voltage is applied to the third electrode.
Optionally, the channel layer includes at least a first channel layer, a second channel layer, and a third channel layer sequentially from top to bottom, carriers near an interface between the second channel layer and the first barrier layer in the second channel layer are depleted, a first carrier gas is included near an interface between the first channel layer and the first barrier layer in the first channel layer, and a second carrier gas is included near an interface between the third channel layer and the first barrier layer in the third channel layer; when the first channel layer is of an N type, the second channel layer is of a P type and the third channel layer is of an N type, the first carrier gas in the first channel layer and the second carrier gas in the third channel layer are two-dimensional electron gas; when the first channel layer is P-type, the second channel layer is N-type and the third channel layer is P-type, the first carrier gas in the first channel layer and the second carrier gas in the third channel layer are two-dimensional hole gas.
Optionally, the channel layer further comprises a voltage resistant layer between the second channel layer and the third channel layer or in the third channel layer, the voltage resistant layer being an unintentionally doped group III-V compound or a carbon or iron doped group III-V compound.
Optionally, the region on the first vertical interface side includes an etched region for physically breaking an electrical connection path of the first carrier gas in the first channel layer and the second carrier gas in the third channel layer.
Optionally, the first electrode is provided on top of the channel layer corresponding to the first carrier gas, forming an ohmic contact with the channel layer.
Optionally, the first electrode extends inward from the top of the channel layer into the region where the first carrier gas and the second carrier gas are interrupted.
Optionally, the second electrode is provided at a bottom of the channel layer corresponding to the second carrier gas, and forms an ohmic contact with the channel layer.
Optionally, the enhanced semiconductor device further includes a substrate, the substrate includes a first mesa and a second mesa having a height difference, and a substrate step side connecting the first mesa and the second mesa has six-axis symmetry; correspondingly, the channel layer is obtained by epitaxy from the side surface of the substrate step.
Optionally, the enhanced semiconductor device further includes a nucleation layer, the nucleation layer is obtained by epitaxy from the side surface of the substrate step, and the channel layer is obtained by epitaxy with the nucleation layer as a core; or the substrate step side surface epitaxial growth method comprises the steps of obtaining a nucleation layer from the substrate step side surface epitaxial growth, obtaining a buffer layer by taking the nucleation layer as a core epitaxial growth, and obtaining the channel layer from the buffer layer epitaxial growth.
According to another aspect of the present application, there is also provided a method for manufacturing an enhanced semiconductor device, comprising the steps of:
providing a channel layer, wherein the channel layer comprises a first vertical interface and a second vertical interface with opposite crystal directions;
obtaining a barrier layer from the epitaxial growth of the outer surface of the channel layer, wherein a first barrier layer is obtained from the epitaxial growth of the first vertical interface, and a second barrier layer is obtained from the epitaxial growth of the second vertical interface;
the channel layer is provided with a first barrier layer, a second barrier layer and a first channel layer, wherein the channel layer is provided with a first carrier gas and a second carrier gas which are interrupted in the vertical direction near the interface between the channel layer and the first barrier layer, and the first carrier gas and the second carrier gas are two-dimensional hole gas or two-dimensional electron gas; the channel layer, the first barrier layer and the second barrier layer are respectively semiconductor layers of III-V compounds;
providing a first electrode on the channel layer corresponding to a first carrier gas;
providing a second electrode on the channel layer corresponding to a second carrier gas; and
a third electrode is provided directly or indirectly on the second barrier layer, the third electrode covering a region of the semiconductor layer corresponding to the interruption of the first and second carrier gases, the third electrode being capable of forming a conductive path between the first and second electrodes upon application of a voltage.
Optionally, when providing a channel layer, sequentially providing a third channel layer, a second channel layer and a first channel layer from bottom to top, wherein carriers near the interface between the second channel layer and the first barrier layer in the second channel layer are depleted, wherein first carrier gas is included near the interface between the first channel layer and the first barrier layer in the first channel layer, and second carrier gas is included near the interface between the third channel layer and the first barrier layer in the third channel layer;
when the first channel layer is of an N type, the second channel layer is of a P type and the third channel layer is of an N type, the first carrier gas in the first channel layer and the second carrier gas in the third channel layer are two-dimensional electron gas;
when the first channel layer is P-type, the second channel layer is N-type and the third channel layer is P-type, the first carrier gas in the first channel layer and the second carrier gas in the third channel layer are two-dimensional hole gas.
The application realizes the enhanced semiconductor device, and the electrode for controlling the conduction of the device is provided on the side surface of the semiconductor layer far away from the carrier gas, thereby avoiding the damage of the etching process to the carrier gas when the electrode is provided, effectively reducing the on-resistance, leading the device to have good switching characteristics and being safer in use. In addition, the vertical structure of the device is realized, so that the integration density of the device can be effectively improved, the preparation process is simplified, and the production cost can be effectively reduced.
Drawings
Preferred embodiments of the present application will be described in further detail below with reference to the attached drawing figures, wherein:
fig. 1 is a schematic view of the structure principle of a longitudinal section of an enhanced semiconductor device according to a first embodiment of the present application;
fig. 2 is a flowchart of a method of manufacturing an enhanced semiconductor device according to a first embodiment of the present application;
fig. 3 is a schematic view of the structural principle of a longitudinal section of a substrate according to a first embodiment of the present application;
fig. 4 is a schematic view of the structure of a longitudinal section of an epitaxial channel layer 1 on a substrate according to an embodiment of the present application;
fig. 5 is a schematic view of the structure of a longitudinal section after epitaxy of the channel layer 1 and the barrier layer 2 on the substrate according to an embodiment of the application;
FIG. 6 is a schematic view of the structural principle of a longitudinal section of a device provided with electrodes according to an embodiment of the present application;
fig. 7 is a schematic view of the structure principle of a longitudinal section of an enhanced semiconductor device according to a second embodiment of the present application;
fig. 8 is a schematic view of the structure principle of a longitudinal section of an enhanced semiconductor device according to a third embodiment of the present application;
FIG. 9 is a schematic view in the direction A of FIG. 8;
fig. 10 is a schematic view of the structure of a longitudinal section of an enhanced semiconductor device in accordance with another alternative etching mode of the third embodiment of the present application;
fig. 11 is a schematic view of the structure of a longitudinal section of an enhanced semiconductor device in accordance with a further alternative etching mode of the third embodiment of the present application;
fig. 12 is a schematic view showing the structure of a longitudinal section of an enhanced semiconductor device in accordance with still another alternative etching mode of the third embodiment of the present application;
fig. 13 is a flowchart of the fabrication of an enhanced semiconductor device according to a fourth embodiment of the present application;
fig. 14 is a schematic view of the structure of a semiconductor device of the fourth embodiment of the present application, in which a longitudinal section of a semiconductor layer on a side surface of a channel layer 1 is removed;
fig. 15 is a schematic longitudinal sectional view of an enhanced semiconductor device according to a fourth embodiment of the present application when a barrier layer 2 is epitaxially grown;
fig. 16 is a schematic view of the structure principle of a longitudinal section of an enhanced semiconductor device structure according to a fourth embodiment of the present application;
fig. 17 is a schematic view of the structure principle of a longitudinal section of an enhanced semiconductor device according to a fifth embodiment of the present application;
fig. 18 is a schematic view of the structure of a longitudinal section of another enhanced semiconductor device according to the fifth embodiment of the present application;
fig. 19 is a schematic structural view of a longitudinal section of a semiconductor device according to an application embodiment of the present application;
fig. 20 is a flowchart of the preparation of a semiconductor device according to an application embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments of the application. In the drawings, like reference numerals describe substantially similar components throughout the different views. Various specific embodiments of the application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the application. It is to be understood that other embodiments may be utilized or structural, logical, or electrical changes may be made to embodiments of the present application.
The application provides an enhanced semiconductor device, which comprises a channel layer, a first barrier layer, a second barrier layer, a first electrode, a second electrode and a third electrode, wherein the channel layer comprises a first vertical interface and a second vertical interface with opposite crystal directions, the first barrier layer is obtained by epitaxial growth on the first vertical interface of the channel layer, and the second barrier layer is obtained by epitaxial growth on the second vertical interface of the channel layer; the channel layer is provided with a first barrier layer, a second barrier layer and a first channel layer, wherein the channel layer is provided with a first carrier gas and a second carrier gas which are interrupted in the vertical direction near the interface between the channel layer and the first barrier layer, and the first carrier gas and the second carrier gas are either two-dimensional hole gas or two-dimensional electron gas; the channel layer, the first barrier layer and the second barrier layer are respectively semiconductor layers of III-V compounds; the first electrode is provided on the channel layer corresponding to the first carrier gas; the second electrode is provided on the channel layer corresponding to a second carrier gas; the third electrode is provided directly or indirectly on the second barrier layer and covers the semiconductor region corresponding to the interruption of the first carrier gas and the second carrier gas, and is capable of forming a conductive path between the first electrode and the second electrode when a voltage is applied.
As can be seen from the above structure, the enhanced semiconductor device provided by the present application provides carriers in the vertical direction, and the carriers in the vertical direction are off, that is, the first electrode and the second electrode are off when no voltage is applied to the third electrode, and the first electrode and the second electrode are on when the voltage is applied to the third electrode, so that the enhanced device is realized. In addition, the first electrode and the second electrode are respectively arranged on the channel layer provided with the carriers, and the two sections of carriers are vertically distributed up and down, so that the first electrode and the second electrode are vertically distributed up and down in the device, namely the application also provides a vertical device while realizing the enhancement of the device. The third electrode which plays a role of a switch is positioned on the side surface far away from the second vertical polarization interface forming the carrier gas, so that the carrier gas in the channel layer close to the first vertical polarization interface side is not damaged by etching operation in the process of manufacturing the third electrode, and the carrier gas in the device can be fully utilized to realize electric on and off, and the advantages of the device are brought into play to provide good on and off performances.
The channel layer and the barrier layer in the present application are respectively III-V compounds. For example, the material of the channel layer may be gallium nitride (GaN) capable of providing a crystal orientation of [0001] or [000-1]. The material of the barrier layer is gallium aluminum nitride (AlGaN), indium aluminum nitride (AlInN), gallium indium nitride (InGaN), aluminum nitride (AlN), gallium indium aluminum nitride (AlInGaN), or the like.
The enhanced semiconductor device provided by the application is, for example, a HEMT (High Electron Mobility Transistors, high electron mobility transistor) or HHMT (High Hole Mobility Transistors, high hole mobility transistor), the corresponding first electrode and second electrode are respectively a corresponding source electrode or drain electrode, and the third electrode is a gate electrode. The structure of the enhanced semiconductor device and the method for manufacturing the same provided by the application are described in detail below by way of specific examples.
Example 1
Fig. 1 is a schematic view of the structure principle of a longitudinal section of an enhanced semiconductor device according to a first embodiment of the present application. In this embodiment, the enhanced semiconductor device includes an N-type first channel layer 11, a P-type second channel layer 12 and an N-type third channel layer 13 from top to bottom, where the N-type first channel layer 11, the P-type second channel layer 12 and the N-type third channel layer 13 form a channel layer 1, and the material of the channel layer 1 in this embodiment is GaN, so that the first vertical interface of the channel layer 1 has a crystal orientation of [0001], and the second vertical interface has an opposite crystal orientation side, i.e., [000-1]. A first barrier layer 21 is epitaxially formed on the (0001) plane of the channel layer 1, and a second barrier layer 22 is epitaxially formed on the (000-1) plane of the channel layer 1, and the material of the barrier layer in this embodiment is AlGaN. Since GaN and AlGaN belong to the III-V group compounds, there is a fixed polarization charge at the interface of two different III-V group compound polar semiconductors, and thus, in this embodiment, a first two-dimensional electron gas 41 is formed in the channel layer 1 near the interface of the N-type first channel layer 11 and the first barrier layer 21, a second two-dimensional electron gas 42 is formed in the channel layer 1 near the interface of the N-type third channel layer 11 and the first barrier layer 21, and a P-type layer is added in the N-type channel layer, i.e., the P-type second channel layer 12 in this embodiment, a section of two-dimensional electron gas corresponding to the side of the P-type second channel layer 12 is depleted, so that the vertical two-dimensional electron gas with two-section breaks in the channel layer 1 is depleted without applying any voltage: a first two-dimensional electron gas 41 and a second two-dimensional electron gas 42. A first electrode 31 is provided on top of the channel layer 1, i.e. on top of the N-type first channel layer 11. In this embodiment, the first electrode 31 forms an ohmic contact with the top of the N-type first channel layer 11 so as to be electrically connected to the first two-dimensional electron gas 41 therein. Alternatively, the first electrode 31 is electrically connected directly to the first two-dimensional electron gas 41 in the N-type first channel layer 11 by a process method. Similarly, a second electrode 32 is provided at the bottom of the channel layer 1, i.e., the bottom of the N-type third channel layer 13, and the second electrode 32 forms an ohmic contact with the N-type third channel layer 13 or is directly electrically connected to the second two-dimensional electron gas 42. The third electrode 33 is provided on the second barrier layer 22 of the channel layer 1 (000-1) face, and covers a region where the two-dimensional electron gas is interrupted, i.e., the third electrode 33 covers the side face of the P-type second channel layer 12. The third electrode 33 in this embodiment is in schottky contact with the second barrier layer 22 on the (000-1) side of the channel layer 1. Alternatively, an insulating layer is added to the region of the second barrier layer 22 corresponding to the P-type second channel layer 12, and then the third electrode 33 is formed thereon, i.e., the third electrode 33 is in insulating contact with the second barrier layer 22, so that leakage current can be reduced. Since the third electrode serving as the gate electrode is formed on the (000-1) side of the channel layer 1, the present application does not affect the two-dimensional electron gas channel region during electrode fabrication, and thus does not require a process for fabricating the third electrode 33. The third electrode 33 in this embodiment covers the side surface region of the p-type second channel layer 12, and when a voltage is applied, the p-type second channel layer 12 below it attracts electrons by the action of the third electrode 33, thereby forming a current path between the two N-type channel layers.
Fig. 2 is a flowchart of a method for manufacturing an enhanced semiconductor device according to a first embodiment of the present application. In connection with the structure of the enhanced semiconductor device shown in fig. 1, 3 to 6, the manufacturing method comprises the steps of:
in step S11, a channel layer 1 is provided, which includes a first vertical interface and a second vertical interface with opposite crystal orientation.
Step S12, epitaxially growing a barrier layer from the outer surface of the channel layer 1, wherein a first barrier layer 21 is epitaxially grown from the first vertical interface, and a second barrier layer 22 is epitaxially grown from the second vertical interface, wherein the channel layer 1 and the barrier layer are respectively semiconductor layers of III-V compounds.
In step S13, a first electrode 31 is provided on top of said channel layer 1 corresponding to the first two-dimensional electron gas 41.
In step S14, a second electrode 32 is provided on the bottom of the channel layer 1 corresponding to the second two-dimensional electron gas 42.
In step S15, a third electrode 33 is provided on the second barrier layer 22 in correspondence with the region where the first two-dimensional electron gas 41 and the second two-dimensional electron gas 42 are interrupted. The third electrode is capable of forming a conductive path between the first electrode and the second electrode upon application of a voltage.
In providing the channel layer 1 in step S11, in one embodiment, the substrate 5 is first provided and the substrate 5 is patterned to obtain a substrate step. As shown in FIG. 3, FIG. 3 is a schematic view of a longitudinal section of a substrate according to a first embodiment of the present applicationIntent. The substrate 5 includes a first mesa 51 and a second mesa 52 having a height difference, and a substrate step side 53 connecting the first mesa 51 and the second mesa 52 has six-axis symmetry. The substrate 5 in this embodiment may be silicon (Si), sapphire (Al 2 O 3 ) One of materials such as silicon carbide (SiC) and gallium nitride (GaN), when the substrate 5 is GaN, the substrate step side surface 53 is a (0001) or (000-1) surface of GaN; when the substrate 5 is Si, the substrate step side 53 is a (111) face of Si; when the substrate is sapphire, the substrate step side 53 is a (0001) plane of sapphire; when the substrate is SiC, the substrate step side 53 is a (0001) plane or a (000-1) plane of SiC.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a longitudinal section of an epitaxial channel layer 1 on a substrate according to an embodiment of the present application.
After patterning the substrate 5, the first mesa 51 and the second mesa 52 are covered with silicon oxide or the like as an epitaxial mask 54. When the substrate 5 is GaN, the lattice of the substrate 5 is matched with the lattice of the channel layer 1 also using GaN, and the channel layer 1 and the barrier layer can be obtained directly by sequentially and epitaxially on the substrate step side 53. When the substrate 5 is silicon (Si), a nucleation layer 6 may be deposited from the substrate step side 53 at this time, the nucleation layer 6 may be AlN or GaN, and then the channel layer 1 is epitaxially grown from the nucleation layer 6, because the lattice is significantly different from that of the channel layer 1 using GaN. When the substrate 5 is sapphire (Al 2 O 3 ) Or silicon carbide (SiC), the channel layer 1 using GaN may be directly formed on Al 2 O 3 Or nucleation growth on SiC, it may also be preferable to introduce nucleation layer 6 during the process from the standpoint of crystal quality.
Optionally, a buffer layer 7 may be further grown from the nucleation layer 6, and the buffer layer 7 may have a single layer or multiple layers, and may be one or more of AlN, gaN, alGaN, inGaN, alInN and AlGaInN. The channel layer 1 is then epitaxial from the buffer layer 7. The nucleation layer 6 and/or the buffer layer 7 serve to make the channel layer 1 more crystalline.
In the present embodiment, when the channel layer 1 is epitaxially grown, the N-type third channel layer 13, the P-type second channel layer 12, and the N-type first channel layer 11 are sequentially formed from the inner layer to the outer layer. Taking the structure of the figure as an example, the nucleation layer 6 is epitaxially obtained from the substrate step side 53 of the substrate 5, and the nucleation layer 6 may be on part of the side or on all of the side of the substrate step side 53. And then taking the nucleation layer 6 as a core, and under the limitation of a second mesa 52 of the substrate 5, epitaxially growing an N-type third channel layer 13 outwards and upwards in a direction perpendicular to the second mesa 52, then continuing to epitaxially grow a P-type second channel layer 12 outwards and upwards on the outer surface of the N-type third channel layer 13, and then continuing to epitaxially grow an N-type first channel layer 11 outwards and upwards on the outer surface of the P-type second channel layer 12. And then carrying out process treatment on the current epitaxial body, removing the wrapping layers of all the layers on the side to obtain the structure shown in fig. 5, and removing the N-type third channel layer 13, the P-type second channel layer 12 and the N-type first channel layer 11 of the multi-layer wrapping layers on the side to form a channel layer 1, wherein the (0001) plane on the right side is a first vertical interface, and the (000-1) plane on the left side is a second vertical interface. It will be appreciated that the substrate 5 need not be etched in a stepped manner, for example, nucleation may be performed directly on the upper surface of the substrate 5 to provide a nucleation layer 6 and epitaxially grow the buffer layer and the channel layer.
In step S12, referring to fig. 5, fig. 5 is a schematic structural diagram of a longitudinal section after the channel layer 1 and the barrier layer 2 are epitaxially grown on the substrate according to an embodiment of the present application. On the outer surface of the channel layer 1 shown in fig. 4, the barrier layer 2 is epitaxially grown, and at this time, two-dimensional electron gas in the vertical direction, called a first two-dimensional electron gas 41 and a second two-dimensional electron gas 42, is generated in the vertical plane near the barrier layer 2 in the N-type third channel layer 13 and the N-type first channel layer 11 on the (0001) plane of the channel layer 1.
In steps S13 and S14, when the first electrode 31 is provided on the channel layer 1 corresponding to the first carrier gas and the second electrode 32 is provided on the channel layer 1 corresponding to the second carrier gas, the top barrier layer 2 is removed by taking the structure of the channel layer 1 shown in fig. 5 as an example, and the first barrier layer 21 on the (0001) plane of the channel layer 1 and the second barrier layer 22 on the (000-1) plane of the channel layer 1 are obtained. The first electrode 31 forms an ohmic contact with the top of the top N-type first channel layer 11. Naturally, the top barrier layer 2 may not be completely removed, but a region where the first electrode 31 is located may be defined by opening a hole in the top barrier layer 2, and then the first electrode 31 in ohmic contact with the top of the N-type first channel layer 11 may be formed in the region. As for the second electrode 32, after the substrate 5 is removed, the ohmic-contact second electrode 32 may be formed at the bottom of the N-type first channel layer 13 as shown in fig. 1, or the ohmic-contact second electrode 32 may be formed at the side surface of the N-type third channel layer 13 at a position close to the substrate as shown in fig. 6.
In step S15, the third electrode 33 is provided on the second barrier layer 22 of the (000-1) face of the channel layer 1, and the third electrode 33 covers the region of the side face of the P-type second channel layer 12, thereby covering the region where the first two-dimensional electron gas 41 and the second two-dimensional electron gas 42 are interrupted. The third electrode 33 and the second barrier layer 22 may be schottky contacts, or may be insulated contacts formed by adding an insulating layer to reduce leakage current.
Example two
Fig. 7 is a schematic view of the structure principle of a longitudinal section of an enhanced semiconductor device according to a second embodiment of the present application. The structure of the enhancement mode semiconductor device of the present embodiment is substantially the same as that of the first embodiment, and the difference between the enhancement mode semiconductor device and the first embodiment is that the channel layer 1 further includes a voltage-resistant layer 14, and as shown in the figure, the voltage-resistant layer 14 is provided in the middle of the N-type third channel layer 13, and of course, the voltage-resistant layer 14 may also be included between the P-type second channel layer 12 and the N-type third channel layer 13. The voltage-resistant layer is an unintentionally doped III-V compound or a carbon (C) -doped or iron (Fe) -doped III-V compound, such as an unintentionally doped GaN (UID-GaN) or a C/Fe-doped GaN. The withstand voltage layer 14 forms a high-resistance buffer layer in a main current path within the channel layer 1, thereby improving the withstand voltage of the channel layer 1. GaN intrinsic carrier concentration at room temperature is about 1E-10/cm 3 And in order, the material has good high-resistance characteristics. But the epitaxially grown unintentionally doped GaN will have a concentration of 1E15 to 1E17/cm 3 In order to reduce these shallow donor doping of Si or O, high resistance properties can be achieved by doping C or Fe.
Since the principle of electron gas or hole gas generation is that lattice mismatch between a channel layer (GaN) and a barrier layer (AlGaN) generates stress, a piezoelectric polarization effect is generated, and thus a 2DEG or 2DHG is induced. Thus, two-dimensional electron gas is still generated in the pressure-resistant layer 14 near the interface with the first barrier layer 21, and the pressure resistance of the device is improved while realizing an enhanced device.
Example III
Fig. 8 is a schematic structural view of a longitudinal section of an enhanced semiconductor device according to a third embodiment of the present application. In this embodiment, the same structure as that of the first embodiment is not described herein, and the difference between the first embodiment and the second P-type channel layer 12 on the first vertical interface side is that the etching region 121 is provided, and the etching region 121 corresponds to a region where the depth exceeds the two-dimensional electron gas. The first two-dimensional electron gas 41 and the second two-dimensional electron gas 42 are physically disconnected by etching the P-type second channel layer 12 to prevent leakage current that may be generated when the P-type second channel layer 12 is not activated well. The etching region 121 may be large or small, as shown in the figure, and only a through groove with a depth greater than that of the first two-dimensional electron gas 41 is etched on the side surface of the (0001) plane corresponding to the P-type second channel layer 12. Referring to fig. 8 and 9, the etched region 121 is shown as a through groove penetrating the P-type second channel layer 12 in the a-direction schematic view.
In addition to the through trench shown in fig. 8, in an alternative etching manner, as shown in fig. 10, a partial region of the first barrier layer 21 corresponding to the P-type second channel layer 12 may be removed, so that the barrier layer 2 is not present, thereby avoiding the possibility of generating two-dimensional electron gas in the P-type second channel layer 12 due to poor activation effect.
In another alternative etching manner, the region generating the two-dimensional electron gas in the N-type first channel layer 11 is removed as shown in fig. 11, or a partial region of the first barrier layer 21 corresponding to the N-type first channel layer 11 is removed as shown in fig. 12.
By etching these regions, the possibility of generating leakage current in the P-type second channel layer 12 is avoided, further increasing the turn-off performance of the device.
Example IV
Fig. 13 is a flowchart of the fabrication of an enhanced semiconductor device according to a fourth embodiment of the present application. Referring to fig. 14 to 16, the process flow of the enhanced semiconductor device of the present embodiment includes the following steps:
in step S21, a substrate 5 is provided and the substrate 5 is patterned to obtain a substrate step. The substrate 5 in this embodiment is a silicon substrate, and the substrate step side 53 is a (111) plane of Si.
In step S22, an epitaxial mask 54 is provided to cover the first mesa 51 and the second mesa 52.
In step S23, a nucleation layer 6 is deposited from the substrate step side 53, the nucleation layer 6 being GaN.
In step S24, the second P-type GaN layer 17, the N-type GaN layer 16, and the first P-type GaN layer 15 are epitaxially grown in this order from the nucleation layer 6. The nucleation layer 6 is used as a core, and the second P-type GaN layer 17 is epitaxially grown vertically upward from the second mesa 52 under the limitation of the second mesa 52 of the substrate 5, and then the N-type GaN layer 16 and the first P-type GaN layer 15 are epitaxially grown continuously upward. The doping concentration of each GaN layer forming N type or P type in the embodiment can be 1E17-1E20/cm 3 . The aforementioned first P-type GaN layer 15, N-type GaN layer 16, and second P-type GaN layer 17 constitute the channel layer 1. When each semiconductor layer is epitaxially grown, each semiconductor layer coats the semiconductor layer serving as an epitaxy basis, and the thickness of each semiconductor layer in the vertical direction is far greater than the thickness in the transverse direction during epitaxy by controlling the process conditions in the material growth process, such as the V/III ratio, the temperature, the pressure of a reaction chamber and the like.
In step S25, the N-type GaN layer 16 and the first P-type GaN layer 15 on the side surface of the channel layer 1 are removed, and the side surfaces of the second P-type GaN layer 17 and the N-type GaN layer 16 are exposed, and the resulting structure is shown in fig. 14. Fig. 14 is a schematic structural diagram of a semiconductor device according to a fourth embodiment of the present application, in which a vertical cross section of a semiconductor layer on a side surface of a channel layer 1 is removed, and a right side surface of the channel layer 1 is a second vertical interface of a (0001) plane and a left side surface is a first vertical interface of a (000-1) plane.
In step S26, an AlGaN layer is epitaxially grown on the current channel layer 1 as the barrier layer 2, as shown in fig. 15, and fig. 15 is a schematic view of the longitudinal section of the enhanced semiconductor device according to the fourth embodiment of the present application when the barrier layer is epitaxially grown. In the first vertical interface of the (000-1) plane of the left side surface of the channel layer 1, the interfaces of the first and second P-type GaN layers 15 and 17 and the AlGaN layer form first and second two-dimensional hole gases 43 and 44, respectively. The first and second two-dimensional hole gases 43 and 44 are interrupted by the presence of the intermediate N-type GaN layer 16.
In step S27, the top barrier layer 2 is removed to expose the first P-type GaN layer 15, and the first barrier layer 21 on the (000-1) plane on the left side surface of the channel layer 1 and the second barrier layer 22 on the (0001) plane on the right side surface of the channel layer 1 are obtained.
In step S28, a first electrode 31 is prepared on top of the exposed first P-type GaN layer 15. The first electrode 31 forms an ohmic contact with the first P-type GaN layer 15.
In step S29, a second electrode 32 is prepared on the second mesa 52 of the substrate 5 next to the second P-type GaN layer 17. The second electrode 32 forms an ohmic contact with the second P-type GaN layer 17.
In step S30, the third electrode 33 is prepared in the region of the second barrier layer 22 on the (0001) plane on the right side of the channel layer 1 corresponding to the intermediate N-type GaN layer 16. The third electrode 33 forms a schottky contact with the second barrier layer 22. The resulting structure is shown in fig. 16, and fig. 16 is a schematic view of the structure principle of a longitudinal section of an enhanced semiconductor device structure according to a fourth embodiment of the present application.
In this embodiment, the two-dimensional hole gas is used as a current conducting medium, the two-dimensional hole gas in the vertical direction is interrupted by the middle N-type GaN layer 16, and the first electrode 31 and the second electrode 32 are conducted by the third electrode 33 when a voltage is applied, so that an enhanced vertical device is obtained.
In order to avoid leakage current generated by the intermediate N-type GaN layer 16, the region through which the two-dimensional hole gas passes may be etched away by etching, so as to physically interrupt the two-dimensional hole gas, for example, see embodiment three.
Although the fabrication process in this embodiment is described with the first P-type GaN layer 15, the N-type GaN layer 16, and the second P-type GaN layer 17 as channel layers, it should be understood that the fabrication process in this embodiment is also applicable to the channel layer structures in the first to third embodiments.
Example five
In this embodiment, the first electrode 31 of the enhancement semiconductor device extends inwardly from the top of the channel layer into the region where the first and second two-dimensional electron gases 41 and 42 are interrupted, thereby constituting the body electrode of the device. As shown in fig. 17, fig. 17 is a schematic structural diagram of a longitudinal section of an enhanced semiconductor device according to a fifth embodiment of the present application. The extension 311 of the first electrode 31 extends inward into the P-type second channel layer 12 from the top of the N-type first channel layer 11, as shown in fig. 18, and fig. 18 is a schematic structural diagram of another enhanced semiconductor device according to the fifth embodiment of the present application. The extension 311 of the first electrode 31 protrudes inwardly into the N-type GaN layer 16 from the top of the first P-type GaN layer 15. In practical application, the first electrode 31 is connected to zero potential, and since the body electrode is connected to the intermediate layer in the channel layer 1, the charge in the intermediate layer can be derived, thereby realizing stable control of the threshold voltage.
It will be appreciated that although the substrate 5 in the foregoing embodiments is made into a stepped structure at the beginning of the fabrication of the device, the structure is not limited to a stepped structure, or the like, as long as the nucleation layer can be formed on the upper surface of the substrate 5, and the directionality of the growth of the semiconductor layers such as the channel layer and the barrier layer is satisfied. In addition, although the first electrode 31 is prepared on the top of the channel layer 1 and the second electrode 31 is prepared on the side bottom or bottom of the channel layer 1 as referred to in the drawings of the foregoing embodiments, it is understood that the positions of the electrodes are made at any desired positions according to various electrode preparation processes used.
Application examples
Fig. 19 is a schematic view of the structural principle of a longitudinal section of a semiconductor device according to an applied embodiment of the present application. Fig. 20 is a flowchart of the preparation of a semiconductor device according to an application embodiment of the present application. The embodiment provides a complementary semiconductor device, which utilizes the characteristic that 2DEG and 2DHG can be simultaneously generated on two sides of a grown material to synchronously manufacture an HEMT device based on an electron channel and an HHMT device based on a hole channel, so as to form a complementary device. The preparation process is as follows:
in step S31, the silicon substrate 5 is patterned to obtain a trench having a sufficient trench bottom area, and both sidewalls of the trench are Si (111) planes.
And S32, growing a nucleation layer and a buffer layer from each side wall of the groove, and respectively extending the channel layer and the barrier layer from each buffer layer to obtain two semiconductor columns. The left channel layer is an N-type, a P-type and an N-type gallium nitride layer from top to bottom, and the right channel layer is a P-type, an N-type and a P-type gallium nitride layer from top to bottom. The vertical plane of one side of the two channel layers facing each other is a (0001) plane, and the vertical plane of the other opposite side is a (000-1) plane.
In step S33, the first left electrode 31-1 and the first right electrode 31-2 are prepared on top of the two channel layers, respectively, and serve as the source electrodes of the two devices, respectively.
In step S34, the dielectric layer 8 is filled to define the position of the third electrode, as shown in fig. 19.
In step S35, the third left electrode 33-1 is formed on the side of the (000-1) plane of the left device, and the third right electrode 33-2 is formed on the side of the (0001) plane of the right device, as shown in FIG. 19.
In step S36, the second left electrode 32-1 and the second right electrode 32-2 are fabricated.
Two complementary devices integrated on one substrate are obtained through the foregoing steps. It is to be understood that this application embodiment is only an example, and those skilled in the art can flexibly set the specific structure provided in the foregoing embodiments to meet the actual requirements in the application.
The above embodiments are provided for illustrating the present application and not for limiting the present application, and various changes and modifications may be made by one skilled in the relevant art without departing from the scope of the present application, therefore, all equivalent technical solutions shall fall within the scope of the present disclosure.
Claims (11)
1. An enhanced semiconductor device, comprising:
a channel layer including a first vertical interface and a second vertical interface of opposite crystal direction;
a first barrier layer epitaxially grown from the first vertical interface of the channel layer;
a second barrier layer epitaxially grown from the second vertical interface of the channel layer;
the channel layer is provided with a first barrier layer, a second barrier layer and a first channel layer, wherein the channel layer is provided with a first carrier gas and a second carrier gas which are interrupted in the vertical direction near the interface between the channel layer and the first barrier layer, and the first carrier gas and the second carrier gas are two-dimensional hole gas or two-dimensional electron gas; the channel layer, the first barrier layer and the second barrier layer are respectively semiconductor layers of III-V compounds;
a first electrode provided on the channel layer including the first carrier gas;
a second electrode provided on the channel layer including the second carrier gas; and
and a third electrode provided directly or indirectly on the second barrier layer and covering the semiconductor layer region where the first carrier gas and the second carrier gas are interrupted, wherein a conductive path can be formed between the first electrode and the second electrode when a voltage is applied to the third electrode.
2. The enhancement mode semiconductor device of claim 1, wherein the channel layer comprises, in order from top to bottom, a first channel layer in which carriers near the interface of the second channel layer and the first barrier layer are depleted, a second channel layer in which the first carrier gas is included near the interface of the first channel layer and the first barrier layer, and a third channel layer in which the second carrier gas is included near the interface of the third channel layer and the first barrier layer;
when the first channel layer is of an N type, the second channel layer is of a P type and the third channel layer is of an N type, the first carrier gas in the first channel layer and the second carrier gas in the third channel layer are two-dimensional electron gases;
when the first channel layer is P-type, the second channel layer is N-type, and the third channel layer is P-type, the first carrier gas in the first channel layer and the second carrier gas in the third channel layer are two-dimensional hole gas.
3. The enhancement mode semiconductor device of claim 2, wherein the channel layer further comprises a voltage withstanding layer between the second channel layer and the third channel layer or in between the third channel layer.
4. The enhancement mode semiconductor device of claim 2, wherein the region on the first vertical interface side comprises an etched region for physically breaking an electrical connection path of the first carrier gas in the first channel layer and the second carrier gas in the third channel layer.
5. The enhancement mode semiconductor device of claim 1, wherein the first electrode is provided on top of the channel layer corresponding to the first carrier gas, forming an ohmic contact with the channel layer.
6. The enhancement mode semiconductor device of claim 5 wherein said first electrode extends inwardly from a top of said channel layer into an area where said first carrier gas and said second carrier gas are interrupted.
7. The enhancement mode semiconductor device of claim 1, wherein the second electrode is provided at a bottom of the channel layer corresponding to the second carrier gas, forming an ohmic contact with the channel layer.
8. The enhancement mode semiconductor device of claim 1, further comprising a substrate, the substrate comprising a first mesa and a second mesa having a height difference, a substrate step side connecting the first mesa and the second mesa having six-axis symmetry; correspondingly, the channel layer is obtained by epitaxy from the side surface of the substrate step.
9. The enhancement mode semiconductor device of claim 8, further comprising a nucleation layer epitaxially grown from the substrate step side, the channel layer being epitaxially grown with the nucleation layer as a core; or the substrate step side surface epitaxial growth method comprises the steps of obtaining a nucleation layer from the substrate step side surface epitaxial growth, obtaining a buffer layer by taking the nucleation layer as a core epitaxial growth, and obtaining the channel layer from the buffer layer epitaxial growth.
10. A method of fabricating an enhanced semiconductor device, comprising:
providing a channel layer, wherein the channel layer comprises a first vertical interface and a second vertical interface with opposite crystal directions;
obtaining a barrier layer from the outer surface epitaxial growth of the channel layer, wherein a first barrier layer is obtained from the first vertical interface epitaxial growth, and a second barrier layer is obtained from the second vertical interface epitaxial growth;
the channel layer is provided with a first barrier layer, a second barrier layer and a first channel layer, wherein the channel layer is provided with a first carrier gas and a second carrier gas which are interrupted in the vertical direction near the interface between the channel layer and the first barrier layer, and the first carrier gas and the second carrier gas are two-dimensional hole gas or two-dimensional electron gas; the channel layer, the first barrier layer and the second barrier layer are respectively semiconductor layers of III-V compounds;
providing a first electrode on the channel layer including the first carrier gas;
providing a second electrode on the channel layer including the second carrier gas; and
a third electrode is provided directly or indirectly on the second barrier layer, the third electrode covering a semiconductor layer region corresponding to the first carrier gas and the second carrier gas interruption, a conductive path being able to be formed between the first electrode and the second electrode when a voltage is applied to the third electrode.
11. The method for manufacturing the enhanced semiconductor device according to claim 10, wherein when the channel layer is provided, a third channel layer, a second channel layer, and a first channel layer are provided in this order from bottom to top, carriers near an interface between the second channel layer and the first barrier layer in the second channel layer are depleted, the first carrier gas is included near an interface between the first channel layer and the first barrier layer in the first channel layer, and the second carrier gas is included near an interface between the third channel layer and the first barrier layer in the third channel layer;
when the first channel layer is of an N type, the second channel layer is of a P type and the third channel layer is of an N type, the first carrier gas in the first channel layer and the second carrier gas in the third channel layer are two-dimensional electron gases;
when the first channel layer is P-type, the second channel layer is N-type, and the third channel layer is P-type, the first carrier gas in the first channel layer and the second carrier gas in the third channel layer are two-dimensional hole gas.
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