CN116974965A - Relay control method and system based on FPGA and CPLD - Google Patents
Relay control method and system based on FPGA and CPLD Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/372—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot
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Abstract
The application provides a relay control method and a relay control system based on FPGA and CPLD, wherein the control method comprises the following steps: reading control information sent by an upstream module, wherein the control information comprises first control data and a first address; subtracting 1 from the first address to generate a second address; writing the first control data and the first address into the CPLD module; the second address is sent to the CPLD module, and first feedback data corresponding to the second address sent by the CPLD module is read; when the first control data is judged to be consistent with the first feedback data, a confirmation sending signal is sent to the CPLD module, and the CPLD module is controlled to send the first control data to the relay; through the steps, the FPGA module and the CPLD module form a full duplex asynchronous bus communication processing system, so that a control information read-back confirmation function is realized, and the reliability and safety of relay control are improved; the method is applicable to any scene with high requirements on safety and reliability.
Description
Technical Field
The disclosure relates generally to the technical field of buses, and in particular relates to a relay control method and system based on an FPGA and a CPLD.
Background
With the continuous development of digital communication control systems, FPGA/CPLD has been widely used in many fields, and with the continuous maturity of applications, developers have described some universal asynchronous communication buses through hardware description languages, and encapsulated into special buses IP core, which are transplanted into FPGA/CPLD for users, such as UART, CAN bus, EMIF bus, LOCALBUS bus, I2C, SPI, etc., and these special buses have advantages, but also have disadvantages, and cannot be used in some occasions, such as the scene with higher requirements for safety and reliability when controlling relays in some integrated avionics systems, and the above buses cannot fully meet the working requirements.
Disclosure of Invention
In view of the foregoing drawbacks or shortcomings in the prior art, it is desirable to provide a relay control method and system based on an FPGA and a CPLD that can solve the foregoing technical problems.
The first aspect of the application provides a relay control method based on FPGA and CPLD, comprising the following steps:
reading control information sent by an upstream module, wherein the control information comprises first control data and a first address;
subtracting 1 from the first address to generate a second address;
writing the first control data and the first address into a CPLD module;
the second address is sent to the CPLD module, and first feedback data corresponding to the second address sent by the CPLD module is read;
and when the first control data is judged to be consistent with the first feedback data, a confirmation transmission signal is transmitted to the CPLD module, and the CPLD module is controlled to transmit the first control data to the relay.
According to the technical scheme provided by the application, the method further comprises the following steps:
collecting pin state information of the CPLD module for multiple times;
and when the pin state information acquired for multiple times is judged to be consistent, the pin state information is sent to the upstream module.
According to the technical scheme provided by the application, the method further comprises the following steps:
when the pin state information acquired for multiple times is inconsistent, circularly acquiring the pin state information for multiple times;
and when judging that the pin state information acquired for multiple times in a circulating way is inconsistent, generating a fault code and sending the fault code to the upstream module.
According to the technical scheme provided by the application, the control information sent by the upstream module is read, and the method comprises the following steps:
reading a first signal sent by the upstream module;
when the first signal is at a high level, reading control information sent by the upstream module; the first control data is registered in a first data register, and the first address is registered in a first address register; .
According to the technical scheme provided by the application, the first control data and the first address are written into the CPLD module, and the method comprises the following steps:
transmitting a write enable signal, first control data and a first address to the CPLD module;
controlling the write enable signal to be low level, starting a write enable counter, and reading the first control data and the first address by the CPLD module;
and after the write enabling counter is judged to maintain n clock cycles, controlling a first address in the first address register to be cleared, and controlling the write enabling signal to be changed into a high level.
According to the technical scheme provided by the application, the second address is sent to the CPLD module, and the first feedback data corresponding to the second address sent by the CPLD module is read, and the method comprises the following steps:
sending a read enabling signal and a second address to the CPLD module, wherein the second address is registered in a second address register;
controlling the read enabling signal to be low level, starting a read enabling counter, and receiving the second address by the CPLD module, wherein the second address is used for reading first feedback data in the CPLD module;
after judging that the reading enabling counter maintains k/2 clock cycles, reading first feedback data corresponding to the second address sent by the CPLD module, and registering the first feedback data in a second data register;
and after the reading enabling counter is judged to maintain k clock cycles, controlling a second address in the second address register to be cleared, and controlling the reading enabling signal to be changed into a high level.
According to the technical scheme provided by the application, before the second address is sent to the CPLD module and the first feedback data corresponding to the second address sent by the CPLD module is read, the method further comprises the following steps:
sending an interval control signal to the CPLD module;
controlling the interval control signal to be changed into a high level, and starting an interval counter;
and after the interval counter is judged to maintain for x clock cycles, controlling the interval control signal to be low level.
According to the technical scheme provided by the application, when the first control data is judged to be consistent with the first feedback data, a confirmation transmission signal is transmitted to the CPLD module, and the CPLD module is controlled to transmit the first control data to the relay, and the method comprises the following steps:
judging whether the first control data is consistent with the first feedback data;
transmitting an acknowledgement transmission signal to the CPLD;
controlling the confirmation transmitting signal to be high level, and starting a confirmation transmitting counter;
controlling the CPLD module to send the first control data to the relay;
and after the confirmation sending counter is judged to maintain j clock cycles, controlling the first control data in the first data register and the first feedback data in the second data register to be cleared, and controlling the confirmation sending signal to be changed into a low level.
The second aspect of the present application provides a relay control system based on FPGA and CPLD, comprising:
the CPLD module is connected with the relay;
the FPGA module is connected with the upstream module and the CPLD module;
the FPGA module is configured to:
reading control information sent by the upstream module, wherein the control information comprises first control data and a first address;
subtracting 1 from the first address to generate a second address;
writing the first control data and the first address into a CPLD module;
the second address is sent to the CPLD module, and first feedback data corresponding to the second address sent by the CPLD module is read;
and when the first control data is judged to be consistent with the first feedback data, a confirmation transmission signal is transmitted to the CPLD module, and the CPLD module is controlled to transmit the first control data to the relay.
The application has the beneficial effects that:
the application provides a relay control method and a relay control system based on FPGA and CPLD, wherein the control method comprises the following steps: the FPGA module reads control information sent by the upstream module, wherein the control information comprises first control data and a first address; the FPGA module subtracts 1 from the first address to generate a second address; the FPGA module writes the first control data and the first address into a CPLD module; the FPGA module sends the second address to the CPLD module, and reads first feedback data corresponding to the second address, which is sent by the CPLD; when the FPGA module judges that the first control data is consistent with the first feedback data, the FPGA module sends a confirmation sending signal to the CPLD module to control the CPLD module to send the first control data to a relay; through the steps, the FPGA module and the CPLD module form a full duplex asynchronous bus communication processing system, so that a control information read-back confirmation function is realized, and the reliability and safety in relay control are improved; meanwhile, the speed block and the speed of the transmission data of the FPGA module and the CPLD module are adjustable; the method is applicable to any scene with high requirements on safety and reliability.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:
FIG. 1 is a flow chart of a relay control method based on FPGA and CPLD in the present application;
FIG. 2 is a schematic diagram of a relay control system based on an FPGA and a CPLD in the present application;
FIG. 3 is a schematic diagram of the operational timing of the FPGA and CPLD control relays;
fig. 4 is a schematic diagram of the operation timing sequence for collecting pin status information of the CPLD module.
In the figure: 1. an upstream module; 2. an FPGA module; 3. a CPLD module; 4. and a relay.
Detailed Description
The application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be noted that, for convenience of description, only the portions related to the application are shown in the drawings.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
Example 1
Please refer to fig. 1, which is a flowchart of a relay control method based on FPGA and CPLD, provided by the present application, comprising the following steps:
s100: reading control information sent by an upstream module, wherein the control information comprises first control data and a first address;
the present solution is implemented by FPGA module 2, an FPGA (Field-Programmable Gate Array) which is a programmable logic device, an integrated circuit, with a high degree of flexibility and reconfigurability. As shown in fig. 2, the FPGA module 2 is connected with the upstream module 1 and the CPLD module 3, and the CPLD module 3 is connected with the relay 4; the FPGA module 2 and the CPLD module 3 form a full duplex asynchronous bus communication processing system for transmitting data between the upstream module 1 and the relay 4;
in this embodiment, the upstream module 1 is an upper computer in the integrated avionics system, and the upper computer is configured to send control information to the relay 4 to control the switch of the relay 4;
the CPLD (Complex Programmable Logic Device) module 3 is a programmable logic device and is used for realizing the function of a digital logic circuit; the CPLD consists of a series of programmable logic gates and registers, and also contains programmable internal connection routing; unlike FPGA, CPLD has a smaller resource size, and is suitable for implementing medium-scale logic circuits; the CPLD is suitable for application scenes which have low requirements on logic scale but need high reliability and real-time performance. They generally have low power consumption, high reliability and small size;
in this embodiment, optionally, the reading the control information sent by the upstream module includes the following steps:
reading a first signal sent by the upstream module;
when the first signal is at a high level, reading control information sent by the upstream module; the first control data is registered in a first data register, and the first address is registered in a first address register;
in this embodiment, the FPGA module 2 and the CPLD module 3 are connected by an address line with a width of 16 bits and a data line with a width of 16 bits, and a 32-bit register is defined inside the FPGA module 2; the first data register and the first address register are arranged in the FPGA module 2, the first data register is a 16-bit data register, and the first address register is a 16-bit address register; the upstream module 1 sends a first signal to the FPGA module 2, where the first signal is at a high level, that is, the FPGA module 2 detects that the first signal is a valid signal, the FPGA module 2 reads control information sent by the upstream module 1 and stores the control information into a defined 32-bit register, registers low 16-bit data in the 32-bit register as the first control data in the first data register, and registers high 16-bit data in the 32-bit register as the first address in the first address register; when transmitting data, the data and the address need to be transmitted separately, so that the FPGA module 2 can correctly identify and access the memory unit, and meanwhile, the data and the address can be transmitted separately, so that the data transmission efficiency can be improved.
S200: subtracting 1 from the first address to generate a second address;
in this scheme, in order to prevent misoperation when the CPLD module 3 receives and transmits data, the first address is subtracted by 1 to generate a second address, and the second address is stored in a second address register of the FPGA module 2, where the second address register is a 16-bit address register;
s300: writing the first control data and the first address into a CPLD module;
in this embodiment, optionally, writing the first control data and the first address into the CPLD module includes the following steps:
transmitting a write enable signal, first control data and a first address to the CPLD module;
controlling the write enable signal to be low level, starting a write enable counter, and reading the first control data and the first address by the CPLD module;
after the write enabling counter is judged to maintain n clock cycles, controlling a first address in the first address register to be cleared, and controlling the write enabling signal to be changed into a high level;
wherein: the FPGA module 2 sends a write enable signal, first control data and a first address to the CPLD module 3, controls the write enable signal to be low level, the CPLD module 3 detects that the write enable signal is low level, and the CPLD module 3 reads the first control data and the first address and registers in a third data register and a third address register in the CPLD module 3 respectively; when the write enable signal changes to a low level, the FPGA module 2 starts a write enable counter, determines that the write enable counter maintains n clock cycles (the clock cycle maintained by the write enable counter is determined by the connected clock signal, and the clock cycle of the write enable counter matches the clock cycle of the FPGA module 2), and writes the first control data into the CPLD module 3, and at this time, controls the first address in the first address register to clear, so as to facilitate the next transmission of control information, and controls the write enable signal to change to a high level, thereby completing writing the first control data into the CPLD module 3.
S400: the second address is sent to the CPLD module, and first feedback data corresponding to the second address sent by the CPLD module is read;
in this embodiment, optionally, the sending the second address to the CPLD module, and reading the first feedback data sent by the CPLD module and corresponding to the second address, includes the following steps:
sending a read enabling signal and a second address to the CPLD module, wherein the second address is registered in a second address register;
controlling the read enabling signal to be low level, starting a read enabling counter, and receiving the second address by the CPLD module, wherein the second address is used for reading first feedback data in the CPLD module;
after judging that the reading enabling counter maintains k/2 clock cycles, reading first feedback data corresponding to the second address sent by the CPLD module, and registering the first feedback data in a second data register;
after judging that the read enabling counter maintains k clock cycles, controlling a second address in the second address register to be emptied, and controlling the read enabling signal to be changed into a high level;
the FPGA module 2 sends a read enable signal and a second address to the CPLD module 3, controls the read enable signal to be changed to a low level, the CPLD module 3 detects that the read enable signal is changed to a low level, the CPLD module 3 receives the second address, and simultaneously, the FPGA module 2 starts the read enable counter, determines that the read enable counter maintains k/2 clock cycles (the clock cycle maintained by the read enable counter is determined by the connected clock signal, and the clock cycle of the read enable counter is matched with the clock cycle of the FPGA module 2), and the FPGA module 2 reads first feedback data corresponding to the second address sent by the CPLD module 3, registers the first feedback data in the second data register (reads the first feedback data in the middle of the clock cycle maintained by the read enable counter, and the read first feedback data is stable); the second data register is a 16-bit register; after judging that the reading enabling counter maintains k clock cycles, the FPGA module 2 finishes reading the first feedback data, controls the second address in the second address register to be emptied, facilitates next transmission of control information, and controls the reading enabling signal to be changed into a high level.
S500: and when the first control data is judged to be consistent with the first feedback data, a confirmation transmission signal is transmitted to the CPLD module, and the CPLD module is controlled to transmit the first control data to the relay.
In this embodiment, optionally, when it is determined that the first control data is consistent with the first feedback data, a confirmation sending signal is sent to the CPLD module, and the CPLD module is controlled to send the first control data to the relay, including the following steps:
judging whether the first control data is consistent with the first feedback data;
transmitting an acknowledgement transmission signal to the CPLD module;
controlling the confirmation transmitting signal to be high level, and starting a confirmation transmitting counter;
controlling the CPLD module to send the first control data to the relay;
after judging that the confirmation sending counter maintains j clock cycles, controlling first control data in the first data register and first feedback data in the second data register to be emptied, and controlling the confirmation sending signal to be changed into a low level;
after receiving the first feedback data sent by the CPLD, the FPGA module 2 determines that the first control data is consistent with the first control data, and then sends a confirmation sending signal to the CPLD module 3, controls the confirmation sending signal to become high level, starts the confirmation sending counter, and the confirmation sending counter is arranged in the FPGA module 2; meanwhile, the CPLD module 3 sends the first control data to the relay 4, and the relay 4 is switched according to the first control data; after the confirmation sending counter is judged to maintain j clock cycles (the clock cycle maintained by the confirmation sending counter is determined by the connected clock signal, and the clock cycle of the confirmation sending counter is matched with the clock cycle of the FPGA module 2), the first control data in the first data register and the first feedback data in the second data register are controlled to be emptied, so that the control information can be conveniently transmitted next time; and simultaneously, controlling the confirmation sending signal to be changed into a low level, and completing the transmission of one-time control information.
Working principle: the full duplex asynchronous bus communication processing system is formed by the FPGA module 2 and the CPLD module 3, so that the control information read-back confirmation function is realized, and the reliability and safety of the relay 4 in control are improved; meanwhile, the speed block and the speed of the transmission data of the FPGA module 2 and the CPLD module 3 are adjustable; the method is applicable to any scene with high requirements on safety and reliability.
In some embodiments, before the second address is sent to the CPLD module and the first feedback data corresponding to the second address sent by the CPLD module is read, the method further includes the following steps:
sending an interval control signal to the CPLD module;
controlling the interval control signal to be changed into a high level, and starting an interval counter;
and after the interval counter is judged to maintain for x clock cycles, controlling the interval control signal to be low level.
Specifically, before the second address is sent to the CPLD module 3 and the first feedback data corresponding to the second address sent by the CPLD module 3 is read, the FPGA module 2 sends an interval control signal to the CPLD module 3, and the FPGA module 2 controls the interval control signal to become high level and starts an interval counter; after the FPGA module 2 determines that the interval counter maintains x clock cycles (the clock cycle maintained by the interval counter is determined by the connected clock signal, and the clock cycle of the interval counter is matched with the clock cycle of the FPGA module 2), the interval control signal is controlled to be low level; and a time interval is arranged between the reading and writing of the data by the FPGA module 2, so that errors of the first feedback data read back by the CPLD module 3 by the FPGA module 2 are prevented.
For the convenience of understanding of those skilled in the art, in this embodiment, as shown in fig. 3, the operation timing diagrams of the FPGA and the CPLD control relay 4 are shown in the drawings: clk is a local clock, valid is a first signal, data is control information, wr_data is a first data register, wr_addr is a first address register, rd_addr is a second address register, wr_en is a write enable signal, blank is an interval control signal, rd_en is a read enable signal, rd_data is a second data register, tx_en is an acknowledge transmit signal;
the FPGA module 2 reads a first signal valid sent by the upstream module 1; when the first signal valid is at a high level, reading control information data sent by the upstream module 1, wherein the control information data comprises first control data and a first address, the first control data is registered in a first data register wr_data, and the first address is registered in a first address register wr_addr;
further, subtracting 1 from the first address to generate a second address, and storing the second address in a second address register rd_addr of the FPGA module 2;
further, a write enable signal wr_en, first control data and a first address are sent to the CPLD module 3; controlling the write enable signal wr_en to be low level, starting a write enable counter, and reading the first control data and the first address by the CPLD module 3; after the write enable counter maintains 40 clock cycles, controlling a first address in the first address register wr_addr to be cleared, and controlling the write enable signal wr_en to be changed into a high level;
further, an interval control signal blank is sent to the CPLD module 3; controlling the interval control signal blank to be high level, and starting an interval counter; after the interval counter maintains for 20 clock cycles, the interval control signal blank is controlled to be low level;
further, a read enable signal rd_en and a second address are sent to the CPLD module 3, and the second address is registered in a second address register rd_addr; controlling the read enable signal rd_en to be low level, starting a read enable counter, and receiving the second address by the CPLD module 3; after the reading enabling counter maintains 20 clock cycles, reading first feedback data corresponding to the second address sent by the CPLD module 3, and registering the first feedback data in a second data register rd_data; after the reading enabling counter maintains 40 clock cycles, controlling a second address in the second address register rd_addr to be cleared, and controlling the reading enabling signal rd_en to be changed into a high level;
further, when the first control data is judged to be consistent with the first feedback data; transmitting an acknowledgement transmission signal tx_en to the CPLD module 3; controlling the confirmation transmission signal tx_en to be changed to a high level, and starting a confirmation transmission counter; controlling the CPLD module 3 to send the first control data to the relay 4; after the acknowledge transmitting counter is maintained for 20 clock cycles, the first control data in the first data register wr_data and the first feedback data in the second data register rd_data are controlled to be cleared, and the acknowledge transmitting signal tx_en is controlled to be low level.
In certain embodiments, the method further comprises the steps of:
collecting pin state information of the CPLD module for multiple times;
and when the pin state information acquired for multiple times is judged to be consistent, the pin state information is sent to the upstream module.
Specifically, the pin state of the CPLD module 3 is determined by the pin state of the relay 4, so that the pin information of the relay 4 can be reflected in real time by collecting the pin state information of the CPLD module 3;
in this embodiment, the FPGA module 2 collects pin state information of the CPLD module 3 by using a periodic collection method, the FPGA module 2 detects a read data signal of a pin of the CPLD module 3 in real time, when detecting that the read data signal is an effective signal (i.e., the read data signal becomes low level), pulls up a collection control signal, the FPGA module 2 starts a collection counter to perform cycle counting, the cycle count period can be adjusted according to the actual collection condition (the clock period maintained by the collection counter is determined by the connected clock signal, and the clock period of the collection counter is matched with the clock period of the FPGA module 2), and after reaching an adjustable period, the collection counter is controlled to clear and accumulated again; meanwhile, after the adjustable cycle number is reached, the FPGA module 2 respectively sends three collection signals to the CPLD module 3, and the FPGA module 2 collects pin state information of the CPLD module 3 three times; further comparing the pin state information of the CPLD module 3 acquired for three times, and when the FPGA module 2 judges that the pin state information acquired for three times is consistent, packaging the pin state information and sending the packaged pin state information to the upstream module 1;
for the convenience of understanding of those skilled in the art, in this embodiment, as shown in fig. 4, a schematic diagram of a working time sequence for collecting pin state information of the CPLD module 3 is shown, where clk is a local clock, en is a read data signal, flag_plus is a collection control signal, flag_r1 is a first collection signal, flag_r2 is a first collection signal, and flag_r3 is a first collection signal;
after the FPGA module 2 and the CPLD module 3 start to work, the FPGA module 2 starts to detect the read data signal en, and after the read data signal en is detected to be an effective signal, the pin state information indicating the CPLD module 3 can be collected, at this time, the collection control signal flag_plus is pulled up and kept, and meanwhile, a collection counter is started to perform cycle counting, in this embodiment, 5us is one cycle, and after 5us is counted, the collection counter is cleared and restarted; meanwhile, after 5us is over, pulling up a first acquisition signal flag_r1, the FPGA module 2 starts to acquire the pin state information of the CPLD module 3, starts a first counter, maintains 12000 clocks, and then pulls down the first acquisition signal flag_r1, and starts to extract the level state of the pin of the CPLD module 3 when the first counter counts 6000; further pulling up a second acquisition signal flag_r2, wherein the FPGA module 2 starts to acquire the pin state information of the CPLD module 3, starts a second counter, maintains 12000 clocks, and then pulls down the second acquisition signal flag_r2, and starts to extract the level state of the pin of the CPLD module 3 when the second counter counts 6000; further pulling up a third acquisition signal flag_r3, starting acquiring pin state information of the CPLD module 3 by the FPGA module 2, starting a third counter, maintaining 12000 clocks, pulling down the third acquisition signal flag_r3, and starting extracting the level state of the pin of the CPLD module 3 when the third counter counts 6000; and when judging that the pin state information acquired for three times is consistent, packaging the pin state information and sending the packaged pin state information to the upstream module 1.
In certain embodiments, the method further comprises the steps of:
when the pin state information acquired for multiple times is inconsistent, circularly acquiring the pin state information for multiple times;
and when judging that the pin state information acquired for multiple times in a circulating way is inconsistent, generating a fault code and sending the fault code to the upstream module.
Specifically, when the FPGA module 2 determines that the pin state information collected three times is inconsistent, three cycles (the pin state information of the CPLD module 3 is collected three times in one cycle) are continuously repeated, and when the values collected three cycles are determined to be inconsistent, the FPGA module 2 generates a fault code and sends the fault code to the upstream module 1, so that the upstream module 1 can conveniently cut off the control of the relay 4.
Example 2
Please refer to fig. 2, which is a schematic diagram of a relay 4 control system based on FPGA and CPLD, according to the present application, comprising:
the CPLD module 3 is connected with the relay 4;
the FPGA module 2 is connected with the upstream module 1 and the CPLD module 3;
the FPGA module 2 is configured to:
reading control information sent by the upstream module 1, wherein the control information comprises first control data and a first address;
subtracting 1 from the first address to generate a second address;
writing the first control data and the first address into the CPLD module 3;
the second address is sent to the CPLD module 3, and first feedback data corresponding to the second address sent by the CPLD module 3 is read;
and when the first control data is judged to be consistent with the first feedback data, a confirmation transmission signal is transmitted to the CPLD module 3, and the CPLD module 3 is controlled to transmit the first control data to the relay 4.
Specifically, this embodiment has been described in detail in embodiment 1 as a specific implementation of embodiment 1, and the principle of the implementation is substantially the same as that in embodiment 1, and will not be explained here too much.
The above description is only illustrative of the preferred embodiments of the present application and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the application referred to in the present application is not limited to the specific combinations of the technical features described above, but also covers other technical features formed by any combination of the technical features described above or their equivalents without departing from the inventive concept. Such as the above-mentioned features and the technical features disclosed in the present application (but not limited to) having similar functions are replaced with each other.
Claims (9)
1. A relay control method based on FPGA and CPLD is characterized by comprising the following steps:
reading control information sent by an upstream module, wherein the control information comprises first control data and a first address;
subtracting 1 from the first address to generate a second address;
writing the first control data and the first address into a CPLD module;
the second address is sent to the CPLD module, and first feedback data corresponding to the second address sent by the CPLD module is read;
and when the first control data is judged to be consistent with the first feedback data, a confirmation transmission signal is transmitted to the CPLD module, and the CPLD module is controlled to transmit the first control data to the relay.
2. The relay control method based on the FPGA and the CPLD according to claim 1, further comprising the steps of:
collecting pin state information of the CPLD module for multiple times;
and when the pin state information acquired for multiple times is judged to be consistent, the pin state information is sent to the upstream module.
3. The relay control method based on the FPGA and the CPLD according to claim 2, further comprising the steps of:
when the pin state information acquired for multiple times is inconsistent, circularly acquiring the pin state information for multiple times;
and when judging that the pin state information acquired for multiple times in a circulating way is inconsistent, generating a fault code and sending the fault code to the upstream module.
4. The relay control method based on the FPGA and the CPLD according to claim 1, wherein the step of reading the control information sent by the upstream module includes the steps of:
reading a first signal sent by the upstream module;
when the first signal is at a high level, reading control information sent by the upstream module; the first control data is registered in a first data register, and the first address is registered in a first address register.
5. The relay control method based on FPGA and CPLD as set forth in claim 4, wherein writing said first control data and first address into the CPLD module comprises the steps of:
transmitting a write enable signal, first control data and a first address to the CPLD module;
controlling the write enable signal to be low level, starting a write enable counter, and reading the first control data and the first address by the CPLD module;
and after the write enabling counter is judged to maintain n clock cycles, controlling a first address in the first address register to be cleared, and controlling the write enabling signal to be changed into a high level.
6. The relay control method based on the FPGA and the CPLD according to claim 1, wherein the sending the second address to the CPLD module, and reading the first feedback data corresponding to the second address sent by the CPLD module, includes the following steps:
sending a read enabling signal and a second address to the CPLD module, wherein the second address is registered in a second address register;
controlling the read enabling signal to be low level, starting a read enabling counter, and receiving the second address by the CPLD module, wherein the second address is used for reading first feedback data in the CPLD module;
after judging that the reading enabling counter maintains k/2 clock cycles, reading first feedback data corresponding to the second address sent by the CPLD module, and registering the first feedback data in a second data register;
and after the reading enabling counter is judged to maintain k clock cycles, controlling a second address in the second address register to be cleared, and controlling the reading enabling signal to be changed into a high level.
7. The relay control method based on the FPGA and the CPLD according to claim 1, further comprising the steps of, before sending the second address to the CPLD module and reading the first feedback data corresponding to the second address sent by the CPLD module:
sending an interval control signal to the CPLD module;
controlling the interval control signal to be changed into a high level, and starting an interval counter;
and after the interval counter is judged to maintain for x clock cycles, controlling the interval control signal to be low level.
8. The relay control method based on FPGA and CPLD of claim 6, wherein when it is determined that the first control data is consistent with the first feedback data, a confirmation transmission signal is transmitted to the CPLD module, and the CPLD module is controlled to transmit the first control data to the relay, comprising the steps of:
judging whether the first control data is consistent with the first feedback data;
transmitting an acknowledgement transmission signal to the CPLD;
controlling the confirmation transmitting signal to be high level, and starting a confirmation transmitting counter;
controlling the CPLD module to send the first control data to the relay;
and after the confirmation sending counter is judged to maintain j clock cycles, controlling the first control data in the first data register and the first feedback data in the second data register to be cleared, and controlling the confirmation sending signal to be changed into a low level.
9. A relay control system based on FPGA and CPLD is characterized by comprising:
the CPLD module (3), the said CPLD module (3) connects with said relay (4);
the FPGA module (2) is connected with the upstream module (1) and the CPLD module (3);
the FPGA module (2) is configured to:
reading control information sent by the upstream module (1), wherein the control information comprises first control data and a first address;
subtracting 1 from the first address to generate a second address;
writing the first control data and a first address into a CPLD module (3);
the second address is sent to the CPLD module (3), and first feedback data corresponding to the second address and sent by the CPLD module (3) is read;
and when the first control data is judged to be consistent with the first feedback data, a confirmation transmission signal is transmitted to the CPLD module (3), and the CPLD module (3) is controlled to transmit the first control data to the relay (4).
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