CN116974509A

CN116974509A - Data type conversion method, processor, electronic device and storage medium

Info

Publication number: CN116974509A
Application number: CN202211667800.XA
Authority: CN
Inventors: 任子木
Original assignee: Tencent Technology Shenzhen Co Ltd
Current assignee: Tencent Technology Shenzhen Co Ltd
Priority date: 2022-12-23
Filing date: 2022-12-23
Publication date: 2023-10-31

Abstract

The embodiment of the application discloses a data type conversion method, a processor, electronic equipment and a storage medium, and relates to the fields of computer technology, artificial intelligence and cloud technology. The method comprises the following steps: acquiring source data to be converted, a source data type of the source data and a target data type; determining a shift direction and a shift amount for performing a shift operation on the source data based on the original data type and the target data type; if the shift direction is the target direction, carrying out shift operation of the target direction on the target sequence of the source data according to the shift amount to obtain shifted data; if the shift direction is the opposite direction of the target direction, sequentially performing sequence inversion operation, shift operation of the target direction according to the shift amount and sequence inversion operation on the target sequence of the source data to obtain shifted data; and obtaining target data of the target data type based on the shifted data. By adopting the embodiment of the application, the hardware resource consumption required by the shift operation is reduced.

Description

Data type conversion method, processor, electronic device and storage medium

Technical Field

The present application relates to the field of computer technology, artificial intelligence, and cloud technology, and in particular, to a data type conversion method, a processor, an electronic device, and a storage medium.

Background

With the continuous enrichment of data types, in the process of more and more data operations, operations on data of different data types are involved. When performing operations on data of different data types, the data of different data types are usually converted into data of the same data type, and then the converted data are subjected to operations. It can be seen that it is very critical to transform data of different data types.

In the related art, a data path is generally constructed based on processing units required for converting data of any two different data types, and each data path can perform data conversion operations of the two different data types, namely, the data conversion operations and the data paths are in one-to-one correspondence. Based on the processing mode, when a plurality of data types of different data types need to be operated at the same time, a plurality of data paths are needed, and because the same processing units possibly exist in different data paths, a larger layout area is consumed when the data type conversion equipment is laid out based on the processing mode.

Disclosure of Invention

The embodiment of the application provides a data type conversion method, which aims to solve the problem that in the related art, when data types of a plurality of different data types are required to be converted simultaneously, more data paths are required, so that the layout area of related data type conversion equipment is consumed more.

Correspondingly, the embodiment of the application also provides a processor, electronic equipment, a storage medium and a computer program product, which are used for ensuring the implementation and the application of the method.

In one aspect, an embodiment of the present application provides a data type conversion method, where the method includes:

acquiring source data to be converted, a source data type of the source data and a target data type; the original data type is integer or floating point type, and the target data type is integer or floating point type;

if the source data is determined to be shifted according to the original data type and the target data type, determining the shifting direction and the shifting amount of the source data based on the original data type and the target data type;

if the shift direction is the target direction, carrying out shift operation of the target direction on the target sequence of the source data according to the shift amount to obtain shifted data; if the original data type is integer, the target sequence is the source data; if the original data type is floating point type, the target sequence is the tail number bit of the source data; the target direction is left or right; if the original data type is floating point type, the shifted data also comprises data after modifying the numerical value of the exponent bit of the source data based on the shift quantity;

If the shift direction is the opposite direction of the target direction, sequentially performing sequence inversion operation, shift operation of the target direction according to the shift amount and sequence inversion operation on the target sequence of the source data to obtain shifted data;

and obtaining target data of the target data type based on the shifted data.

In another aspect, an embodiment of the present application provides a processor, including a processor input interface, a shift amount and exponent calculation unit, a shifter, a first sequence inversion unit, a second sequence inversion unit, and a processor output interface;

the processor input interface and the shift quantity are connected with the input interface of the index calculation unit, the shift quantity and the output interface of the index calculation unit are respectively connected with the input interface of the shifter and the input interface of the first sequence inversion unit, the output interface of the first sequence inversion unit is connected with the input interface of the shifter, the output interface of the shifter is respectively connected with the input interface of the second sequence inversion unit and the output interface of the processor, and the output interface of the second sequence inversion unit is connected with the output interface of the processor;

the processor input interface is used for acquiring source data to be converted, the original data type of the source data and the target data type; the original data type is integer or floating point type, and the target data type is integer or floating point type;

A shift amount and index calculation unit for determining a shift direction and shift amount of the source data based on the original data type and the target data type when determining to shift the source data according to the original data type and the target data type; when the shift direction is the target direction, outputting the source data, the shift direction and the shift amount to a shifter; when the shift direction is the opposite direction of the target direction, outputting the source data to the first sequence reversing unit, and outputting the shift direction and the shift amount to the shifter; the target direction is left or right;

the first sequence inversion unit is used for performing sequence inversion operation on the target sequence of the received data to obtain first data and outputting the first data to the shifter; if the original data type is integer, the target sequence is the source data; if the original data type is floating point type, the target sequence is the tail number bit of the source data;

the shifter is used for carrying out shift operation of the target direction on the received data according to the shift amount and the target direction to obtain second data; if the shift direction is the target direction, determining shifted data based on the second data; outputting the second data to the second sequence inversion unit if the shift direction is the opposite direction; if the original data type is floating point type, the shifted data also comprises data after modifying the numerical value of the exponent of the source data based on the shift quantity;

The second sequence inversion unit is used for performing inversion operation on the target sequence of the received data to obtain shifted data;

the processor output interface is used for outputting target data; the target data is derived based on the shifted data.

In another aspect, an embodiment of the present application provides an electronic device, including a processor and a memory, where the processor and the memory are connected to each other;

the memory is used for storing a computer program;

the processor is configured to execute the data type conversion method provided by the embodiment of the application when the computer program is called.

In another aspect, an embodiment of the present application provides a computer readable storage medium storing a computer program that is executed by a processor to implement the data type conversion method provided by the embodiment of the present application.

In another aspect, an embodiment of the present application provides a computer program product, where the computer program product includes a computer program, where the computer program implements a data type conversion method provided by an embodiment of the present application when the computer program is executed by a processor.

In the embodiment of the application, when the shift direction and the shift amount of the shift operation on the source data are determined according to the original data type and the target data type of the source data to be converted, specific shift operation is determined based on the determined shift direction, specifically, if the shift direction is the target direction, the shift operation of the target direction is performed on the target sequence of the source data according to the shift amount, so as to obtain shifted data; if the shift direction is the opposite direction of the target direction, sequentially performing sequence inversion operation, shift operation of the target direction according to the shift amount and sequence inversion operation on the target sequence of the source data to obtain shifted data. The processing operation of normalizing the processing operations in different shift directions into the processing operation in the same shift direction can be realized by a sequence inversion mode, and shifted data are obtained. Since the sequence inversion operation does not increase the additional hardware resource consumption during the actual processing, the hardware resource consumption required during the shift operation can be reduced by this processing method. And further obtains target data of the target data type based on the shifted data, so that data type conversion of the source data can be realized. Therefore, by the data type conversion method provided by the embodiment of the application, the hardware resource consumption of the related data type conversion equipment can be further reduced, namely the layout area consumption of the data type conversion equipment is reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of shaping data provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of floating point shape data according to an embodiment of the present application;

FIG. 3 shows a schematic diagram of a processor provided in the related art;

fig. 4 is a schematic diagram of an application scenario of a data type conversion method according to an embodiment of the present application;

fig. 5 is a schematic flow chart of a data type conversion method according to an embodiment of the present application;

FIG. 6 is a schematic flow chart of a shift operation according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a sign bit expansion operation according to an embodiment of the present application;

FIG. 8 is a schematic diagram of determining reserved bits according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a processor according to an embodiment of the present application;

FIG. 10 is another schematic diagram of a processor provided by an embodiment of the present application;

fig. 11 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The data type conversion method provided by the embodiment of the application can be realized based on artificial intelligence (Artificial Intelligence, AI) technology. For example, the AI processor may be provided with a shift amount and index calculation unit, a shifter for the target direction, a first sequence inversion unit, a second sequence inversion unit, and the like, the shift direction and shift amount of the source data may be determined by the shift amount and index calculation unit, the sequence inversion operation may be performed on the received data by the first sequence inversion unit and the second sequence inversion unit, the shift operation may be performed on the received data in the target direction by the shifter for the target direction, and the like. AI is a theory, method, technique, and application system that utilizes a digital computer or a digital computer-controlled machine to simulate, extend, and extend human intelligence, sense the environment, acquire knowledge, and use knowledge to obtain optimal results. With the research and progress of artificial intelligence technology, the research and application of artificial intelligence technology has been widely developed in a plurality of fields, and it is believed that with the development of technology, the artificial intelligence technology will be applied in more fields and become more and more valuable.

The data type conversion method according to the embodiment of the present application may also be implemented based on Cloud technology (Cloud technology), for example, a data processing process required in determining a shift direction and a shift amount of source data, performing a sequence inversion operation, and performing a shift operation may be implemented by using Cloud technology, and data calculation involved in the data processing process may be implemented by using a Cloud computing (Cloud computing) manner. Cloud technology refers to a hosting technology for unifying serial resources such as hardware, software, network and the like in a wide area network or a local area network to realize calculation, storage, processing and sharing of data. The cloud technology is based on the general names of network technology, information technology, integration technology, management platform technology, application technology and the like applied by the cloud computing business mode, can form a resource pool, and is flexible and convenient as required. Cloud computing technology will become an important support.

It should be noted that, in the alternative embodiment of the present application, when the above embodiment of the present application is applied to a specific product or technology, related data such as related object information (e.g., user image, user nickname, etc.) needs to be licensed or agreed upon in response to the object, and the collection, use and processing of related data needs to comply with related laws and regulations and standards of related countries and regions. That is, in the embodiment of the present application, the data related to the subject is acquired under the approval via the subject's authority and in compliance with the relevant laws and regulations and standards of the country and region.

The technical solutions of the embodiments of the present application and technical effects produced by the technical solutions of the present application are described below by describing several exemplary embodiments. It should be noted that the following embodiments may be referred to, or combined with each other, and the description will not be repeated for the same terms, similar features, similar implementation steps, and the like in different embodiments.

As described above, in the related art, when data type conversion is required for data of a plurality of different data types at the same time, more data paths are required, resulting in larger layout area consumption of the related data type conversion apparatus. In particular, data types may be related to data of multiple data types.

Wherein the different data types may include, but are not limited to integer (int) and floating point (fp), the data corresponding to integer (fixed point number, xxx x 2) ⁰ ) Data corresponding to a floating point type, i.e. floating point type data (i.e. floating point number, expressed in xxx. Yyy 2 x 2 ^e ) Etc. Wherein, floating point type data is composed of three field segments: s-sign, symbol bit; e-exponents, index bits (i.e. xxx. Yyy 2 ^e E) of (a); m-mantissa, mantissa bits (i.e., xxx. Yyy 2 ^e Xxx.yyy) in (a).

For floating point data, the larger the exponent bit is, the larger the data range which can be represented by the floating point data is represented; the more mantissa digits, the higher the accuracy characterizing them.

Because floating point data introduces digits, the dynamic range of data that floating point data can represent is wider than integer data. The dynamic range of data that integer data may represent is smaller than floating point data.

In particular, different data types may be further partitioned based on data bit width (i.e., number of bits, bits), resulting in corresponding subtypes for each data type. For example, the integer can be divided based on the data bit width, resulting in a long integer (32 bit), a short integer (16 bit), an 8bit integer (8 bit), and the like. As shown in fig. 1, integer data corresponding to various sub types may include 32bit int32 (32 bit integer data, long integer data), 16bit int16 (16 bit integer data, short integer data), 8bit int8 (8 bit integer data), and the like.

And the integer can be further divided by a numerical representation range to obtain signed integer and unsigned integer. Correspondingly, integer data may be divided into signed integer data (i.e., signed number) and unsigned integer data (i.e., unsigned number). The most significant bit (MSB, most Significant Bit) of the signed integer data is a sign bit, and if msb=0, the signed number is a positive number; if msb=1, the signed number is negative.

The floating point types may be partitioned based on data bit width to yield single precision floating point types (32 bit), half precision floating point types (16 bit) and Brain precision floating point types (Brain Float or bflot, a digital format optimized for artificial intelligence/deep learning applications). As shown in FIG. 2, floating-point type data corresponding to various sub-types may include 32-bit fp32 (single-precision floating-point number, specifically including 1-bit sign bit [ S (1) ], 8-bit exponent bit [ E (8) ] and 23-bit mantissa bit [ M (23) ]), 16-bit fp16 (half-precision floating-point number, specifically including 1-bit sign bit [ S (1) ], 5-bit exponent bit [ E (5) ] and 10-bit mantissa bit [ M (10) ]), and 16-bit bp16 (Brain Float16 or BFLoat16, brain-precision floating-point number, specifically including 1-bit sign bit [ S (1) ], 8-bit exponent bit [ E (8) ] and 7-bit mantissa bit [ M (7) ]).

Based on the data types described above, data type conversion operations that may be involved in performing data type conversion in particular may include, but are not limited to, converting single precision floating point numbers to half precision floating point numbers (fp32_to_fp16), converting single precision floating point numbers to long integer numbers (fp32_to_int 32), converting long integer numbers to single precision floating point numbers (int 32_to_fp32), converting short integer numbers to half precision floating point numbers (int 16_to_fp16), and the like.

After converting the data type, the data operations performed may include, but are not limited to, signed integer operations, unsigned integer operations, floating point operations, and the like. When the integer data needs to be operated, the fixed-point operation is usually needed to be performed on the integer data in advance, namely, the integer data is expanded into data with an execution bit width, but the hardware implementation of the integer data is simpler.

As shown in fig. 3, when a processor implemented by a data type conversion method in the related art performs data type conversion operation between different types, hardware resources required for each data type conversion operation are typically instantiated as a data path (such as "fp32_to_fp16", "fp32_to_int32", "int32_to_fp32", "int16_to_fp16", etc. in fig. 3, each corresponding to a data path), and then a mux (multiplexer) is used to select a data path corresponding to the current input data (data_in), and perform data type conversion on the input data through the data path, so as to obtain a data converted result (data_out). The data type conversion operation and the data paths are in one-to-one correspondence, and the data paths are completely independent.

When performing data type conversion operations based on the processor shown in fig. 3, as the number of data type conversion operations supported by the processor increases, the number of corresponding data paths increases, and naturally, the larger the area required for hardware resources on the processor to perform the data type conversion operations, that is, the more hardware resources are consumed; in addition, with the increase of data paths, the fan-out of the input data is larger, more buffers (timing controllers) are needed to be inserted in the rear end implementation process of the processor, so that the problem of larger fan-out of the input data is solved, but the problem also causes that the layout and the wiring in the processor are complex, and as only one multiplexer exists, different data type conversion operations cannot be processed in parallel through the processor, so that when multiple data type conversion operations are needed, the timing requirements cannot be met, the data processing process is slow, and the like.

In addition, although the data parallelism (i.e., the number of computations that can be performed in parallel in the same clock cycle) of the processor is continuously increasing, the parallelism of a single core of the high-performance processor can reach 128 paths (i.e., data processing can be performed through 128 paths at the same time), but if the hardware resource consumption required by each data path is high, the parallel processing efficiency is also affected. Therefore, how to reduce the hardware resource consumption required by each path of data path and reduce the corresponding hardware resource area is also a technical problem to be solved in the field.

In view of at least one of the foregoing technical problems or needs to be improved in the related art, an embodiment of the present application provides a data type conversion method, a processor, an electronic device, a storage medium, and a computer program product, so as to reduce hardware resource consumption of the related data type conversion device, that is, reduce layout area consumption of the data type conversion device, and improve data processing efficiency.

The video processing method according to the embodiment of the application can be applied to any scene needing data type conversion, and can include but is not limited to specific application scenes such as image classification, image recognition and the like in image processing application scenes.

Taking image recognition as an example, in general, the image (i.e., source data) is integer data, for example, int8 integer data, and image recognition can be performed based on bp16 floating point data by converting the int8 integer data into bp16 floating point data.

Fig. 4 is a schematic structural diagram of a data type conversion system to which an embodiment of the present application is applicable. As shown in fig. 4, the system 40 may include a terminal 401 and an application server 402, where the terminal 401 and the application server 402 may be directly or indirectly connected through a wired or wireless communication manner, and the embodiment of the present application is not limited thereto.

The terminal 401 may be any data collection device, and the terminal 401 obtains source data, and sends the source data, a primary data type of the source data, and a target data type to the application server 402, and obtains target data obtained by the application server 402 after performing data type conversion on the source data based on the source data, the primary data type of the source data, and the target data type, so as to perform subsequent processing operations based on the target data. The application server 402 may perform data type conversion on the source data based on the source data, the original data type of the source data, and the target data type, and transmit the converted target data to the terminal 401.

The terminal 401 (may also be referred to as a User terminal or User Equipment (UE)) may be, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, a wearable electronic device (e.g., a smart watch), a vehicle-mounted terminal, a smart home appliance (e.g., a smart television), an AR (Augmented Reality) or a Virtual Reality)/VR (Virtual Reality) device, etc.

The application server 402 may be an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, or may be a cloud server or a server cluster based on cloud computing services, such as providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDNs (Content Delivery Network, content delivery networks), big data, artificial intelligence platforms, and the like.

It will be appreciated by those skilled in the art that the above-described terminals or servers are merely examples, and that other terminals or servers that may be present in the present application or in the future are applicable to the present application and are also included within the scope of the present application and are incorporated herein by reference.

An embodiment of the present application provides a data type conversion method, as shown in fig. 5, including:

step S510: acquiring source data to be converted, a source data type of the source data and a target data type; the original data type is integer or floating point type, and the target data type is integer or floating point type.

In this implementation, the source data, i.e., the data whose data type is the original data type. The specific representation may be a multimedia file, such as an image, video, etc., to which embodiments of the present application are not limited.

The original data type is integer or floating point type, and specifically may be the long integer, short integer, 8-bit integer, signed integer, unsigned integer, single-precision floating point type, half-precision floating point type, brain-precision floating point type, etc., which is not limited by the embodiment of the present application. The target data type is integer or floating point type, and may be specifically the long integer, short integer, 8-bit integer, signed integer, unsigned integer, single-precision floating point type, half-precision floating point type, brain-precision floating point type, etc., which is not limited by the embodiment of the present application.

Step S520: if the shift operation is determined to be performed on the source data according to the original data type and the target data type, the shift direction and the shift amount of the source data are determined based on the original data type and the target data type.

As described above, the data ranges indicated by the different data types are different, and when performing the data type conversion operation, it is possible to determine whether to perform the shift operation on the source data based on the data range indicated by the original data type and the data range indicated by the target data type.

When the data range which can be represented by the original data type is the same as the data range which can be represented by the target data type, the source data can be directly used as the target data of the target data type without carrying out shift operation on the source data; when the data range which can be represented by the original data type is different from the data range which can be represented by the target data type, determining that the source data needs to be shifted, and further determining the shifting direction and the shifting amount of the source data based on the original data type and the target data type.

For integer data, since the integer data does not have a exponent, i.e., the exponent is 0, and the integer data is a fixed point number, i.e., the position of the decimal point is fixed, the integer data may be represented as xxx.xxx 2 based on the position of the decimal point in the integer data ⁰ 。

When the integer data is unsigned integer data, the valid data bits of the integer data are all the corresponding data. When the integer data is signed integer data, the valid data bits of the integer data are the data other than the sign bits (i.e., the most significant bits of the integer data) in the integer data.

For floating point data, the position of the decimal point is not fixed, and for the same floating point data, the position of the decimal point in the floating point data is related to the numerical size of the exponent bits of the floating point data. For example, for a decimal floating point number of 2.14, bothCan be represented as 2.14 x 10 ⁰ May also be expressed as 0.214 x 10 ¹ May also be expressed as 21.4x10 ^-1 。

Also, floating point data in a reduced form may be generally represented as 1.Xxx x 2 ^x And typically the most significant bit of the mantissa bits is taken as the implied bit, i.e. "1" is omitted. Thus, when floating point data is represented by binary, "xxx" means mantissa bits after omitting implicit bits of the floating point data, "1" means implicit bits of the floating point data, and "x" means exponent bits of the floating point data. When the floating point data is positive, determining that the sign bit of the floating point data is 1; when the floating point data is negative, the sign bit of the floating point data is determined to be 0.

Based on the description of the integer data and the floating point data above, the source data may be partitioned based on the source data's original data type prior to processing the source data. For example, when the original data type of the source data is integer, determining a sign bit and a valid data bit of the source data; when the original data type of the source data is floating point type, the sign bit, the exponent bit and the mantissa bit of the source data are determined. And further realizes the data type conversion of the source data by adjusting the digits, data bits, mantissa digits and the like corresponding to the original data type and the target data type of the source data.

As an example, if the original data type of the source data is integer, the target data type is floating point type, and the source data is unsigned integer data, the shifted data may be obtained by updating the "exponent bit" corresponding to the source data from "0" to the value of the exponent bit corresponding to the target data type, and shifting the valid data bit of the source data based on the adjustment amount of the exponent bit.

When the value of the exponent corresponding to the target data type is positive, the exponent is larger, the value of the mantissa is required to be reduced correspondingly, and the floating point data usually uses the highest bit of the mantissa as the hidden bit to omit, so that the shift direction for shifting operation can be determined to be left shift, and the shift amount is the adjustment amount +1 of the exponent.

Similarly, when the value of the exponent corresponding to the target data type is a negative number, the exponent bit is reduced, so that the value of the mantissa bit needs to be correspondingly increased, and the floating point data usually uses the highest bit of the mantissa bit as an implicit bit to omit, so that the shift direction for performing the shift operation can be determined to be left shift, and the shift amount is the adjustment amount-1 of the exponent bit.

As another example, if the original data type of the source data is a floating point type, the target data type is integer, and both the exponent and mantissa of the source data are unsigned integer data, the shifted data may be obtained by updating the "exponent" corresponding to the source data to the value of the exponent corresponding to the "0" target data type, and shifting the mantissa of the source data and the implicit bit of the mantissa based on the adjustment amount of the exponent.

When the value of the exponent bit corresponding to the original data type is positive, the exponent bit is reduced, so that the mantissa bit needs to be correspondingly increased, and the floating point data usually uses the highest bit of the mantissa bit as the hidden bit to be omitted, so that the shift direction of shifting operation can be determined to be left shift after the hidden bit of the source data is complemented, and the shift amount is the adjustment amount-1 of the exponent bit.

Similarly, when the value of the exponent corresponding to the original data type is a negative number, the exponent is larger, so that the mantissa is required to be reduced correspondingly, and the highest bit of the mantissa is usually omitted as the hidden bit by the floating point data, so that the shift direction of the shift operation can be determined to be left shift after the hidden bit of the source data is complemented, and the shift amount is the adjustment amount +1 of the exponent.

Step S530: if the shift direction is the target direction, carrying out shift operation of the target direction on the target sequence of the source data according to the shift amount to obtain shifted data; if the original data type is integer, the target sequence is the source data; if the original data type is floating point type, the target sequence is the tail number bit of the source data; the target direction is left or right; if the original data type is floating point type, the shifted data also comprises data after modifying the numerical value of the exponent bit of the source data based on the shift quantity;

if the shift direction is the opposite direction of the target direction, sequentially performing sequence inversion operation, shift operation of the target direction according to the shift amount, and sequence inversion operation on the target sequence of the source data to obtain shifted data.

The target direction is left or right, and in the actual implementation process, the shift operation can be implemented through the shifter. For example, when the target direction is left, the corresponding shifter may be a left shifter. When the target direction is rightward, the corresponding shifter may be a right shifter.

The target sequence of source data is the valid data bits of the source data. It will be appreciated that, as noted above, floating point data will typically omit the most significant bit of the mantissa bits as an implied bit, and if the original data type is a floating point number, the target sequence may be data following the most significant bit "+1" of the mantissa bits actually displayed by the source data.

When the sequence inversion operation is performed, the positions of the low-order data and the high-order data of the data to be processed can be interchanged, namely, the high-order data and the low-order data are ordered, the highest-order data to be processed are used as the lowest-order data after inversion, the lowest-order data to be processed are used as the highest-order data after inversion, and the like, so that the sequence inversion operation of the data to be processed is realized.

For example, after sequence inversion of the data to be processed "11100110", the data "011001111" after sequence inversion can be obtained.

As a specific example, as shown in fig. 6, with the target direction being left, the target sequence of the source data is "1110_0110_0000", the shift direction is right, the shift amount is 4, and for example, the data "0000_1100_0110" can be obtained by directly shifting "1110_0110_0000" by 4 bits. "0000_0110_0111" can be obtained after the sequence inversion operation is performed on "1110_0110_0000"; when "0000_0110_0111" is shifted to the left by 4 bits, data "0110_0111_0000" can be obtained; the data "0000_1100_0110" can be obtained after the sequence inversion operation is performed on "0110_0111_0000".

It can be seen that when the shift direction is the opposite direction to the target direction, the shift operation in the opposite direction is performed directly on the target sequence of the source data by the shift amount, and the sequence inversion operation, the shift operation in the target direction by the shift amount, and the sequence inversion operation are sequentially performed on the target sequence of the source data, which results are the same.

And because the sequence inversion operation only involves the change of the signal line position in the process of hardware implementation, the extra hardware resource consumption is not increased. If the shifters in different directions are respectively arranged, the area occupied by the shifter in the specific data type conversion device is relatively large, and more hardware resources are required to be consumed.

In the embodiment of the application, when the shift direction is the target direction, the shift operation of the target direction is carried out on the target sequence of the source data according to the shift amount, so that shifted data are obtained; when the shift direction is the opposite direction of the target direction, the sequence inversion operation, the shift operation of the target direction according to the shift amount and the sequence inversion operation are sequentially performed on the target sequence of the source data, so that shifted data can be obtained, the shift processing operation of different directions can be realized by only setting the shifter of one target direction and the sequence inversion operation, and the shift operation of different directions is normalized, so that the problem that the area occupied by the shifter in a specific data type conversion device is larger due to the need of setting the shifter of different directions can be avoided, and the chip area is saved.

In the case of the numerical value of the exponent of the source data based on the shift amount, the numerical value of the exponent of the source data should be the corresponding decimal value.

Step S540: and obtaining target data of the target data type based on the shifted data.

As noted above, integer data does not have a exponent bit, floating point data includes a sign bit, a exponent bit, and a mantissa bit, and the mantissa bit is data that does not include an implied bit. Thus, after the shifted data is obtained, the target data can be obtained based on the target data type and the shifted data.

When the target data type is integer, the shifted data can be used as target data.

When the target data type is floating point type data, the target data is determined due to the tail bits related to the shifted data, the hidden bits corresponding to the tail bits, the exponent bits and the corresponding sign bits. Specifically, deleting the highest bit of the mantissa bits related to the shifted data to obtain the mantissa bit of the target data; carrying out corresponding binary conversion on the index bits to obtain index bits of target data; the sign bit of the source data is taken as the sign bit of the target data.

In the embodiment of the application, the shift direction and the shift amount for carrying out shift operation on the source data are determined according to the original data type and the target data type of the source data to be converted. When the shift direction is the target direction, carrying out shift operation of the target direction on the target sequence of the source data according to the shift amount to obtain shifted data; when the shift direction is the opposite direction of the target direction, sequentially performing sequence inversion operation, shift operation of the target direction according to the shift amount, and sequence inversion operation on the target sequence of the source data to obtain shifted data. The processing operation of normalizing the processing operations in different shift directions into the processing operation in the same shift direction can be realized through a sequence inversion mode, shifted data are obtained, and because the sequence inversion operation does not increase extra hardware resource consumption in the actual processing process, the hardware resource consumption required in the shift operation process can be reduced through the method. And further obtains target data of the target data type based on the shifted data, so that data type conversion of the source data can be realized. The hardware resource consumption of the related data type conversion device can be further reduced, that is, the layout area consumption of the data type conversion device is reduced.

In consideration of the actual processing, the data bit width of the source data is generally set to be uniform before the specific data type conversion operation is performed, so as to improve the processing efficiency in the data type conversion process. Based on this, the embodiment of the application also provides the following optional implementation modes:

optionally, if the original data type is integer, the method further includes:

if the data bit width of the source data is not the set bit width, expanding the source data into a sequence with the set bit width according to the value of the sign bit of the source data;

the determining the shift direction and shift amount of the source data based on the original data type and the target data type includes:

if the target data type is a floating point type, determining that the shift amount is the leading zero amount in the sequence with the set bit width, and determining that the shift direction is leftward.

In the actual processing, as shown in fig. 7, when the original data type is signed integer and the data bit width of the source data is not the set bit width, the expanding of the source data into the sequence of the set bit width can be realized by repeating the number of symbols with the interval bit width times at the highest bit of the source data based on the interval bit width between the set bit width and the data bit width and the value of the symbol bit.

When the original data type is unsigned integer and the data bit width of the source data is not the set bit width, the source data can be expanded into a sequence of the set bit width by repeating the number of times of 'the value of the highest bit' at the highest bit of the source data for the interval bit width based on the interval bit width between the set bit width and the data bit width and the value of the highest bit.

Leading zero, a format that displays 0 in front of the number.

As noted above, integer data may be represented as xxx.xxx.2 ⁰ Floating point data may be represented as 1.Xxx 2 ^x In the form of (1) in general, i.e. in practice the most significant bits of the floating point type data are "1" and the integer data are not less than the minimum value of the floating point type data, so that when the original data type is integer and the target data type is floating point type, conversion of the source data from the original data type to the target data type can be achieved by determining the number of leading zeros in the sequence of the set bit width and determining the shift amount as the number of leading zeros and determining the shift direction to the left。

After determining the shift amount and the shift direction, since the floating point data will usually omit the most significant bit of the mantissa bits as the implied bit, when the original data type is integer and the target data type is floating point type, the implied bit of the floating point data needs to be complemented, i.e. the most significant bit "1" is added on the basis of the data after the shift operation, and the exponent bit of the floating point data is determined to be the shift amount +1.

For example, for 8-bit integer data, the integer data can be represented as 00011001, the leading zero number is 3, when the integer data is converted into floating point data, the integer data can be shifted left by 3 bits to obtain 11001000, namely the converted floating point number is represented as 1.1001000 x 2 ⁴ Its mantissa (containing implied bits) is 11001000, exponent bit 4.

In this implementation, if the original data type is a signed integer and the target data type is a floating point type, the absolute value operation may be performed on the source data first, and then the data corresponding to the target data type may be further determined based on the data after the absolute value operation. And determining sign bits of the source data as sign bits in the target data.

In the embodiment of the application, when the source data type of the source data is integer, the data bit width of the source data is set to be uniform bit width based on the value of the sign bit of the source data, so that the processing efficiency in the data type conversion process can be improved.

In addition, by setting the data bit width of the source data to be uniform bit width when the source data type of the source data is integer and determining the subsequent data processing operation based on the target data type, the source data can be preprocessed through the same expanded data bit width operation no matter the target data type, namely the combination of expanded data bit width operation under any target data type is realized, the hardware resources which are required to be set in the data type conversion equipment and correspond to different target data types and are required to realize the expanded data bit width operation are reduced due to the fact that the original data types are the same and the target data types are different, and the layout area consumption related to the expanded data bit width operation in the data type conversion equipment is reduced.

In addition, in this implementation, when the target data type is a floating point type, the shift amount is determined to be the leading zero amount in the sequence with the set bit width, and the shift direction is determined to be the left, the shift direction and the shift amount of the source data can be quickly determined.

Optionally, the floating point type includes at least one first type, and if the original data type is any of the first types, determining the shift direction and the shift amount of the source data based on the original data type and the target data type includes:

if the target data type is integer, determining that the shift amount is the numerical value of the index bit of the source data, and determining that the shift direction is leftward;

if the target data type is another first type, determining a shift amount based on the numerical value of the index bit of the source data and the numerical range of the target index bit corresponding to the target data type; and determining the shift direction based on the original exponent bit value range and the target exponent bit value range corresponding to the original data type.

In this implementation, at least one first type included in the floating point type may be determined based on the above-described division of the floating point type, for example, the first type included in the floating point type may be determined to be a single precision floating point type (fp 32), a half precision floating point type (fp 16), a brain precision floating point type (bp 16), or the like, respectively, based on the bit width of the floating point type data.

As described above, integer data is not smaller than the minimum value of floating point data, the floating point data will omit the most significant bit of the mantissa bit as the hidden bit, when the original data type is floating point type and the target data type is integer, the source data can be converted from the original data type to the target data type by determining the value of the exponent bit in the source data, determining the shift amount as the value of the exponent bit, and determining the shift direction as left, i.e. the decimal point is shifted to the right.

For example, floating point number is 1.1001000×2 ⁴ The mantissa is shifted left by 4 bits to obtain 11001.000X2 ⁰ Binary representations of integer data can be obtainedIs 00011001.

When the original data type is a floating point type and the target data type is a floating point type, if the value of the exponent bit of the source data exceeds the exponent bit value range corresponding to the original data type, that is, the source data is an non-normal number, the conversion of the source data into the protocol data, that is, the conversion of the source data into the floating point type data with a larger data range can be realized by converting the source data from the original data type into the target data type with a larger corresponding exponent bit value range.

The converted data can represent the data corresponding to the source data in a reduced form, and the shift direction can be determined to be leftward by determining the leading zero number in the source data and determining the shift amount as the leading zero number based on the leading zero number.

As an example, if the source data has an irregular number (i.e., contains implicit bits) of 0.000111×2 ^-14 Because fp16 has a smaller data range, fp32 has an exponent minimum of-14, fp32 has an exponent minimum of-126, and the leading zero number of the mantissa of the source data is 4, the mantissa bit can be shifted to the left by 4 bits, and the value of the mantissa bit of the source data can be adjusted to obtain data converted into fp32 of 1.11000×2 ^-18 I.e., mantissa (with implied bit) is 111000 and exponent-18.

When the original data type is a floating point type and the target data type is also a floating point type, if the value of the exponent bit of the source data is not in the range of the target exponent bit value corresponding to the target data type, that is, the source data is required to be converted into floating point type data with smaller corresponding data range, that is, the source data exceeds the data representation range corresponding to the target data type, and the converted data is possibly a non-reduced number. Based on this, the respective shift amounts and shift directions can be determined based on the index value ranges by determining the index values corresponding to the source data and the target data index values corresponding to the target data types.

When the exponent number value corresponding to the source data is smaller than the minimum value of the exponent number range of the target data, the shift amount is determined as the difference between the exponent number value corresponding to the source data and the minimum value, and the shift direction is rightward. When the exponent number value corresponding to the source data is larger than the maximum value of the exponent number range of the target data, determining that the shift amount is the difference value between the exponent number value corresponding to the source data and the minimum value, and the shift direction is leftward.

As an example, if the source data in the form of a reduction number is 1.110000×2 ^-18 Because fp32 represents a larger data range, the minimum index is-126, the minimum index fp16 is-14, fp16 cannot directly represent the value of index-18, the mantissa of fp16 needs to be processed, and the difference between-18 and-14 is 4, the data converted into fp16 can be obtained by right shifting the mantissa digit by 4 bits and adjusting the value of the exponent digit of the source data to be "-14", and the data converted into fp16 is 0.000111 x 2 ^-14 I.e. mantissa (with implied bit) 0000111 and exponent-14.

Based on the above, when the source data type of the source data is any first type, no matter what the target data type is, the sign bit, the exponent bit and the mantissa bit of the source data need to be determined first, and then the subsequent specific data type conversion operation is determined based on the sign bit, the exponent bit and the mantissa bit of the source data.

Specifically, when the original data type is a floating point type, it may be determined in advance whether the source data is a special type such as non-Number (NaN, not a Number, exponent is 1, mantissa is Not 0), infinity (INF, infinity), etc., and when the source data is a special type, it is determined whether the source data is a non-reduction Number, and further it is determined whether the sign bit, the exponent bit, and the mantissa bit of the source data.

In the embodiment of the application, when the source data type of the source data is any first type, the input format (namely the sign bit, the exponent bit and the mantissa bit of the source data) of the source data is determined first, and then the specific data conversion mode is determined based on whether the target data type is integer or floating point type, so that the combination of the input format determining operation of the source data under any target data type can be realized, the hardware resources required for realizing the input format determining operation of the source data corresponding to different target data types are required to be set in the data type conversion equipment due to the fact that the original data type is the same and the target data type is different, and the layout area consumption related to the input format determining operation of the source data in the data type conversion equipment is reduced.

And when the source data type of the source data is any first type and the target data type is integer, determining that the shift amount is the numerical value of the exponent of the source data and the shift direction is left can realize conversion of the data type of the source data from integer to floating point. Determining a shift amount based on the numerical value of the exponent bits of the source data and the range of the numerical values of the target exponent bits corresponding to the target data type by determining the source data type of the source data as any one of the first types and the target data type as another one of the first types; the shift direction is determined based on the original exponent bit value range and the target exponent bit value range corresponding to the original data type, so that the data type of the source data can be converted from a floating point type of one type to a floating point type of another type.

In view of the possible limited transmission bandwidth of the output interface of the data type conversion device, the following alternative implementations are also provided during the actual data type conversion:

the obtaining the target data of the target data type based on the shifted data includes:

determining the data bit width of the shifted data;

if the data bit width is smaller than or equal to the target bit width corresponding to the target data type, obtaining target data based on the shifted data;

if the data bit width is larger than the target bit width, determining low-bit data with the data bit width being the target bit width in the shifted data as reserved data; and obtaining target data based on the reserved data.

In this implementation, when the data bit width is less than or equal to the target bit width corresponding to the target data type, the shifted data may be directly used as the target data.

When the data bit width is larger than the target bit width, after the reserved data (save part) is determined, the reserved data can be directly used as target data, or the reserved data can be processed on the premise that the data bit width is ensured to be the target bit width, and then the processed data is used as target data.

In the actual data type conversion process, when the data bit width is smaller than or equal to the target bit width corresponding to the target data type, the shifted data can be directly used as target data. When the data bit width is larger than the target bit width, the shifted data is processed into target data with the target bit width, so that the output data of the output interface of the data type conversion equipment can be ensured not to exceed the target bit width, and the influence on the data processing structure due to limited transmission bandwidth of the output interface of the data type conversion equipment is avoided.

Specifically, the following optional implementation manner may be adopted, where the reserved data is processed on the premise that the data bit width is ensured to be the target bit width, and the processed data is used as the target data:

the obtaining the target data based on the reserved data includes:

determining the data rounding amount of reserved data based on a preset rounding mode and reject data; discarding the data except the reserved data in the shifted data;

and correcting the reserved data based on the data rounding amount, and obtaining target data based on the corrected reserved data.

As shown in fig. 8, low-bit data having a data bit width of a target bit width among the shifted data may be determined as reserved data, and data other than the reserved data among the shifted data may be determined as discard data (discard part).

In this implementation, the amount of rounding of the data may be determined by performing an or operation on each bit of the discard data, and based on the result of the or operation and a preset rounding mode. The preset rounding mode is the mode of determining the rounding amount of the data.

Specifically, the preset rounding mode may be: if the result of the OR operation is 1, setting the rounding quantity of the data to be 1, namely, the target data is reserved data +1; if the result of the OR operation is 0, the rounding amount of the data is set to 0, namely the target data is reserved data.

When the reserved data is corrected based on the data rounding amount, if the data bit width of the corrected data exceeds the target bit width, the low-bit data having the data bit width of the corrected data that is the target bit width may be directly determined as the target data.

The data rounding amount of the reserved data is determined based on a preset rounding mode and the discarded data, and the reserved data is corrected based on the data rounding amount to obtain target data, so that the target data can be determined on the premise that the bit width of the data is ensured to be the target bit width.

Considering that the target data type is integer and the shifted data may exceed the target data value range corresponding to the target data type, for this purpose, the present application provides the following alternative implementation manner to perform saturation processing on the shifted data:

optionally, if the target data type is integer, obtaining the target data of the target data type based on the shifted data may include:

determining a value of a data bit of the shifted data; if the numerical value of the data bit is in the range of the value of the target data corresponding to the target data type, determining the shifted data as target data; if the numerical value of the data bit is not in the target data value range, determining target data based on the data closest to the shifted data in the target data value range; or alternatively

Determining the data bit width of the shifted data; if the data bit width is smaller than or equal to the target bit width corresponding to the target data type, determining the shifted data as target data; and if the data bit width is larger than the target bit width, determining target data based on low-bit data with the data bit width being the target bit width in the shifted data.

When the value of the data bit is not in the target data value range, taking the target data type as an example of the eight-bit binary signed number, the target data value range corresponding to the target data type is-127 to +127, if the shifted data is 129, the data closest to the shifted data in the target data value range can be determined to be 127, and the target data can be determined to be "01111111". If the shifted data is-129, the data closest to the shifted data in the target data value range can be determined to be-127, and the target data can be determined to be "11111111".

When the data bit width is greater than the target bit width, the method for determining the reserved data based on the above may be specifically referred to, and the target data may be determined based on the low-bit data with the data bit width being the target bit width in the shifted data, which is not described herein. The target bit width may be the same as or different from the set bit width, and may be determined according to actual situations.

It should be noted that, in the actual processing, the target data may be determined by combining two specific manners of determining the target data, that is, the determined target data is located in the target data value range corresponding to the target data type, and the data bit width is also less than or equal to the target bit width corresponding to the target data type.

In the implementation mode, a specific mode for determining target data is determined by determining the numerical value of the data bit of the shifted data and based on whether the numerical value of the data bit is positioned in a target data value range corresponding to the target data type; or, by determining the data bit width of the shifted data and determining a specific manner of determining the target data based on the numerical value size relationship between the data bit width and the target bit width corresponding to the target data type, it is possible to ensure that the target data does not exceed the target data value range corresponding to the target data type, or the data bit width is smaller than or equal to the target bit width corresponding to the target data type, so as to avoid the occurrence of problems such as target data errors caused by the fact that the target data exceeds the target data value range corresponding to the target data type, or the data bit width is larger than the target bit width corresponding to the target data type.

Optionally, if the target data type is a floating point type, obtaining the target data of the target data type based on the shifted data includes:

acquiring a target specification form of a target data type;

and if the target protocol form is a non-protocol form and the shifted data is protocol data, adjusting the shifted data into the data of the target protocol form to obtain target data. For example, if the data corresponding to the target data type is a special type such as non-number (NaN) and Infinity (INF), the shifted data may be adjusted to a corresponding protocol form.

By adjusting the shifted data based on the target specification form of the target data type, the specification form of the target data may be enabled to satisfy the target specification form.

Optionally, the shaping includes at least one second type, and the obtaining the target data of the target data type based on the shifted data includes:

if the target data type is any one of the second types and any one of the second types is the signed type, performing bit inversion operation on the shifted data to obtain target data.

The second type may be in particular a signed type or an unsigned type.

Because the most significant bit of the signed integer data is a sign bit, in this implementation, if the target data type is a signed type, the shifted data may be bit-wise inverted to obtain a result after the bit-wise inversion operation, and the result may be +1-operated to obtain the target data.

When the target data type is signed integer, the bit inversion operation is carried out on the shifted data to obtain the target data, so that the corresponding signed integer data can be obtained under the condition that the actual numerical value of the shifted data is not changed.

It should be noted that, the above is only an example in the data type conversion process, and the processing methods in the embodiments may be combined according to actual situations to obtain a final data type conversion result.

In order to more clearly illustrate the specific effect achieved by the data type conversion method, the real-time example of the present application further describes the data type conversion method by taking a processor as an example of a data type conversion device:

as shown in fig. 9, the processor provided by the embodiment of the application includes a processor input interface, a shift amount and exponent calculating unit, a shifter, a first sequence reversing unit, a second sequence reversing unit, and a processor output interface;

In the actual processing process, the source data to be converted, the original data type of the source data and the target data type can be determined through the data type conversion instruction received by the data interface of the processor.

As described above, when the source data type is a floating point type, it is possible to determine in advance whether the source data is a special type such as non-Number (NaN, not a Number, exponent 1, mantissa 0) or Infinity (INF, infinity), and when the source data is a special type, it is possible to determine whether the source data is a non-reduced Number, and further determine the sign bit, exponent bit, and mantissa bit of the source data.

In the actual processing process, a floating point number input format processing unit (fp input formatter) may be configured to preprocess the source data when the original data type is a floating point type, determine whether the source data is a special type, determine whether the source data is a non-reduced number when the source data is a special type, and further determine sign bits, exponent bits and mantissa bits of the source data.

In a specific implementation process, in order to better realize multiplexing of each unit, a multiplexer may be further connected after the processor input interface, the shift amount and exponent calculation unit and the first sequence inversion unit, and it is determined by the multiplexer whether to perform sequence inversion operation on the target sequence of the source data.

In the embodiment of the application, a processor input interface and a shift amount are set to be connected with an input interface of an index calculation unit (shift amt & expcalc, shift amount & exponent calculation), an output interface of the shift amount and the index calculation unit are respectively connected with an input interface of a shifter and an input interface of a first sequence inversion unit, an output interface of the first sequence inversion unit (first vector invert) is connected with an input interface of a shifter, an output interface of the shifter is respectively connected with an input interface of a second sequence inversion unit and an output interface of the processor, an output interface of the second sequence inversion unit is connected with an output interface of the processor, and a shift direction and a shift amount for shifting source data are determined by performing shift operation according to a primary data type and a target data type of source data to be converted based on operations performed by each unit in the processor. When the shift direction is the target direction, carrying out shift operation of the target direction on the target sequence of the source data according to the shift amount to obtain shifted data; when the shift direction is the opposite direction of the target direction, sequentially performing sequence inversion operation, shift operation of the target direction according to the shift amount, and sequence inversion operation on the target sequence of the source data to obtain shifted data. The processing operation of normalizing the processing operations in different shift directions into the processing operation in the same shift direction can be realized through a sequence inversion mode, shifted data are obtained, and the sequence inversion operation does not increase extra hardware resource consumption in the actual processing process, so that the hardware resource consumption required in the shift operation process can be reduced. And further obtains target data of the target data type based on the shifted data, so that data type conversion of the source data can be realized. The hardware resource consumption of the processor, i.e. the layout area consumption of the processor, can be further reduced.

Optionally, the processor further includes a rounding logic control unit, and the output interface of the shifter and the output interface of the second sequence inversion unit are connected with the output interface of the processor through the rounding logic control unit respectively; a rounding logic control unit for:

determining the data bit width of the shifted data;

The shifted data can be directly used as target data when the data bit width is smaller than or equal to the target bit width corresponding to the target data type through a round logic control unit (round control) in the actual data type conversion process. When the data bit width is larger than the target bit width, the shifted data is processed into target data with the target bit width based on a round mode (round mode), so that the output data of the output interface of the data type conversion equipment can be ensured not to exceed the target bit width, and the influence on the data processing structure due to the fact that the transmission bandwidth of the output interface of the data type conversion equipment is limited is avoided.

Optionally, the above processor further includes a blocking operation unit, and the rounding logic control unit is connected to the processor output interface through the blocking operation unit, and the blocking operation unit is configured to:

In an implementation, the discard data may be ored by a sticky operation unit (stick) to get the rounding amount of the data.

And determining the data rounding amount of the reserved data based on a preset rounding mode and the reject data by the rounding logic control unit, correcting the reserved data based on the data rounding amount to obtain target data, and determining the target data on the premise of ensuring that the data bit width is the target bit width.

Optionally, the processor further includes a sign bit expanding unit and a leading zero detecting unit; the processor input interface is connected with the shift quantity and index calculation unit through the sign bit expansion unit and the leading zero detection unit in sequence;

The sign bit expansion unit is used for outputting the source data to the shift quantity and index calculation unit if the data bit width of the source data is a set bit width when the original data type is integer; if the data bit width of the source data is not the set bit width, expanding the source data into a sequence with the set bit width according to the value of the sign bit of the source data, and outputting the sequence with the set bit width to a shift quantity and index calculating unit;

the leading zero detection unit is used for determining the leading zero quantity in the sequence with the set bit width and outputting the leading zero quantity to the shift quantity and index calculation unit;

the shift amount and exponent calculation unit, when determining a shift direction and shift amount of the source data based on the original data type and the target data type, is to:

and if the target data type is a floating point type, determining that the shift amount is the leading zero amount, and determining that the shift direction is leftward.

As described above, when the original data type is a signed integer and the target data type is a floating point type, it is necessary to determine mantissa bits and exponent bits of the target data type based on the absolute value corresponding to the source data.

And by setting the data bit width of the source data to be uniform bit width when the source data type of the source data is integer, and determining the subsequent data processing operation based on the target data type, the source data can be preprocessed through the same sign bit expansion unit no matter the target data type, namely the combination of expansion data bit width operation under any target data type is realized, the consumption of layout area related to the sign bit expansion unit in the data type conversion equipment is reduced because the original data type is the same and the target data types are different, so that the sign bit expansion unit which corresponds to different target data types and is required for realizing expansion data bit width operation is required to be arranged in the data type conversion equipment.

In addition, in this implementation, when the target data type is a floating point type, the shift direction and the shift amount of the source data can be quickly determined by determining the shift amount to be the leading zero amount in the sequence of the set bit width by the leading zero detection unit (lzd, leading zero detect) and determining the shift direction to be leftward.

Optionally, the processor further includes a floating point number input format processing unit and a leading zero detection unit; the processor input interface is connected with the shift quantity and index calculation unit through the floating point number input format processing unit; the floating point type includes at least one first type;

the floating point number input format processing unit is used for determining the exponent and mantissa of the source data and outputting the exponent and mantissa to the shift quantity and exponent calculating unit;

if the original data type is any first type and the target data type is integer, determining that the shift amount is the numerical value of the digits of the source data, and determining that the shift direction is leftward;

if the original data type is any one type and the target data type is another type, determining a shift amount based on the numerical value of the index bit of the source data and the numerical range of the target index bit corresponding to the target data type; and determining the shift direction based on the original exponent bit value range and the target exponent bit value range corresponding to the original data type.

In the embodiment of the application, when the source data type of the source data is any first type, the input format (namely the sign bit, the exponent bit and the mantissa bit of the source data) of the source data is determined by the floating point number input format processing unit, and then a specific data conversion mode is determined by the shift amount and exponent calculating unit based on whether the target data type is integer or floating point type, so that the combination of 'input format determining operation of the source data' under any target data type can be realized, the problem that hardware resources which are required to be set in the data type converting device and correspond to different target data types and are required to realize the floating point number input format processing unit, shift amount and exponent calculating unit are reduced due to the fact that the original data type is the same and the target data type is different is solved, and the layout area consumption related to the floating point number input format processing unit, the shift amount and the exponent calculating unit in the data type converting device is reduced.

Optionally, the processor further includes a multiplexer, an integer saturation processing unit and a floating point number output format processing unit, the output interface of the shifter and the output interface of the second sequence inversion unit are respectively connected with the input interface of the multiplexer, and the output interface of the multiplexer is respectively connected with the output interface of the processor through the integer saturation processing unit or the floating point number output format processing unit;

The multiplexer is used for outputting the shifted data to the integer saturation processing unit when the target data type is integer; when the target data type is floating point type, outputting the shifted data to a floating point number output format processing unit;

the integer saturation processing unit is used for performing a first operation or a second operation to obtain target data and outputting the target data to the processor output interface; wherein the first operation comprises: determining a value of a data bit of the shifted data; if the numerical value of the data bit is in the range of the value of the target data corresponding to the target data type, determining the shifted data as target data; if the numerical value of the data bit is not in the target data value range, determining target data based on the data closest to the shifted data in the target data value range; the second operation includes: determining the data bit width of the shifted data; if the data bit width is smaller than or equal to the target bit width corresponding to the target data type, determining the shifted data as target data; if the data bit width is larger than the target bit width, determining target data based on low-bit data with the data bit width being the target bit width in the shifted data;

The floating point number output format processing unit is used for acquiring a target protocol form of a target data type; and if the target protocol form is a non-protocol form and the shifted data is protocol data, adjusting the shifted data into the data in the target protocol form to obtain target data, and outputting the target data to the processor output interface.

In the implementation manner, the output interface of the shifter and the output interface of the second sequence inversion unit are respectively connected with the input interface of the multiplexer, the output interface of the multiplexer is respectively connected with the output interface of the processor through the integer saturated processing unit or the floating point number output format processing unit, and the shifted data is processed through the integer saturated processing unit or the floating point number output format processing unit connected with the output interface of the processor based on the target data type, so that the target data is obtained, the combination processing (namely normalization to the same data path) of the processing operation of the shifted data can be realized, the hardware resource consumption required by setting a plurality of data paths due to different target data types is reduced, and the area of the processor is saved.

The integer saturation processing unit is used for determining the numerical value of the data bit of the shifted data, and determining a specific mode for determining the target data based on whether the numerical value of the data bit is positioned in a target data value range corresponding to the target data type; or, the integer saturation processing unit is used for determining the data bit width of the shifted data, and the specific determination mode of the target data is determined based on the numerical value size relation between the data bit width and the target bit width corresponding to the target data type, so that the target data can be ensured not to exceed the target data value range corresponding to the target data type, or the data bit width is smaller than or equal to the target bit width corresponding to the target data type, and the problems of target data errors and the like caused by the fact that the target data exceeds the target data value range corresponding to the target data type, or the data bit width is larger than the target bit width corresponding to the target data type are avoided.

Determining the numerical value of the data bit of the shifted data through the floating point number output format processing unit, and determining a specific mode for determining the target data based on whether the numerical value of the data bit is positioned in a target data value range corresponding to the target data type; or, the floating point number output format processing unit determines the data bit width of the shifted data, and determines a specific determination mode of the target data based on the numerical value size relation between the data bit width and the target bit width corresponding to the target data type, so that the target data can be ensured not to exceed the target data value range corresponding to the target data type, or the data bit width is smaller than or equal to the target bit width corresponding to the target data type, and the problems of target data errors and the like caused by the fact that the target data exceeds the target data value range corresponding to the target data type, or the data bit width is larger than the target bit width corresponding to the target data type are avoided.

Optionally, the processor further includes a bit-wise inverting unit, and the integer includes at least one second type, and the output interface of the shifter and the output interface of the second sequence inverting unit are respectively connected with the output interface of the processor through the bit-wise inverting unit; bit inverting unit for:

And when the target data type is any one of the second types and any one of the second types is the signed type, performing bit reversal operation on the shifted data to obtain target data, and outputting the target data to the processor output interface.

When the target data type is signed integer, the bit inversion unit (bitwise-inv) performs bit inversion operation on the shifted data to obtain target data, so that corresponding signed integer data can be obtained without changing the actual value of the shifted data.

The following describes a normalized processor for performing various data type conversion operations according to an embodiment of the present application with reference to fig. 10:

the connection relation between the units is as follows:

the input data interface (i.e. the processor input interface) is respectively connected with the input interface of the floating point number input format processing unit and the input interface of the fixed point number sign bit expansion unit (i.e. the sign bit expansion unit);

the output interface of the floating point number output format processing unit is respectively connected with the input interface of the leading zero detection unit, the input interface of the shift quantity and index calculation unit and the input interface of the first multiplexer;

The output interface of the fixed point number sign bit expansion unit is respectively connected with the input interface of the leading zero detection unit, the input interface of the absolute value taking operation unit and the input interface of the first multiplexer;

an output interface of the absolute value taking operation unit is connected with an input interface of the first multiplexer;

the output interface of the first multiplexer is respectively connected with the input interface of the first sequence inversion unit and the input interface of the second multiplexer;

the output interface of the leading zero detection unit is connected with the input interface of the shift quantity and index calculation unit;

the output interface of the shift quantity and index calculating unit is respectively connected with the input interface of the second multiplexer and the input interface of the left shifter;

the output interface of the first sequence inversion unit is connected with the input interface of the second multiplexer;

the output interface of the second multiplexer is connected with the input interface of the left shifter;

the output interface of the left shifter is respectively connected with the input interface of the second sequence inversion unit and the input interface of the third multiplexer;

the output interface of the third multiplexer is connected with the input interface of the bit-wise inverting unit;

the high-order data output by the output interface of the bit-wise inverting unit is connected with the input interface of the adder, the low-order data output by the output interface of the bit-wise inverting unit is connected with the input interface of the adhesion operation unit, and the output interface of the bit-wise inverting unit is also connected with the multiplexer;

The input interface of the adder is also input with data 1; the output interface of the adder is connected with the input interface of the fourth multiplexer;

the output interface of the adhesion operation unit is connected with the input interface of the rounding control logic unit;

the input interface of the rounding control logic unit is also input with data 'rounding mode';

the output interface of the rounding control logic unit is connected with the input interface of the fourth multiplexer;

the output interface of the fourth multiplexer is respectively connected with the input interface of the integer saturation unit and the input interface of the floating point number output format processing unit;

the output interface of the integer saturation unit and the output interface of the floating point number output format processing unit are respectively connected with the input interface of the fifth multiplexer;

the output interface of the fifth multiplexer is connected with the output data interface (i.e. the processor output interface).

The actual roles between the units are as follows:

the floating point number input format processing unit is used for determining whether the input data (i.e. source data) is of a special type when the input data is of a floating point type, determining whether the input data is of a non-reduced number when the source data is of a special type, and determining sign bits, exponent bits, tail bits and hidden bits of the tail bits of the input data.

And the fixed point number sign bit expansion unit is used for expanding the data bit width of the integer data into a sequence with a set bit width based on the sign bit of the integer data when the input data is integer.

And the absolute value taking operation unit is used for taking the tail digits of the floating point type data into account as the unsigned digits and carrying out absolute value taking operation on the input data when carrying out the conversion operation from signed integer type to floating point type data.

The leading zero detection unit is used for detecting leading zero of the data output by the fixed point number sign bit expansion unit and determining the leading zero quantity in the data output by the fixed point number sign bit expansion module when the conversion operation of converting integer data into floating point data is carried out; and converting the floating point data of the non-normal number into the data type of the floating point data, detecting leading zeros of the data output by the floating point input format processing unit, and determining the leading zeros in the data output by the floating point input format processing unit.

And the shift amount and exponent calculation unit is used for determining the shift direction and the shift amount when the shift operation is required in the conversion operation of converting integer data into the data type of floating point data, the conversion operation of converting floating point data into the data type of floating point data and the conversion operation of converting floating point data into the data type of integer data.

The first multiplexer is used for determining whether to output the data output by the floating point number input format processing unit or the data output by the absolute value taking operation unit to the second multiplexer based on the original data type. The first multiplexer outputs the data output by the floating point number input format processing unit to the second multiplexer when the original data type is floating point type; and when the source data is floating point type, determining to output the data output by the absolute value operation unit to the second multiplexer.

The first sequence reversing unit and the second sequence reversing unit are used for performing sequence reversing operation on the received data when the shifting direction is the opposite direction (rightward in the example) corresponding to the shifter when the shifting operation is needed.

The second multiplexer is configured to determine whether to directly output the data output from the first multiplexer or output the data output from the first sequence inverting unit to the left shifter by based on the shift direction. The second multiplexer outputs the data output by the first multiplexer to the left shifter when the shift direction is leftward; the data outputted from the first sequence inverting unit is outputted to the left shifter when the shift direction is rightward.

And the left shifter is used for performing left shifting operation on the received data based on the shifting quantity and updating the numerical value of the digit when the shifting operation is required.

The third multiplexer is configured to determine whether to directly output the data output from the left shifter or the data output from the second sequence inverting unit to the bit inverting unit by based on the shift direction. The third multiplexer outputs the data output by the left shifter to the bit-wise inverting unit when the shifting direction is leftward; by outputting the data of the output of the second sequence inverting unit to the bit inverting unit when the shift direction is rightward.

The bit inverting unit is used for considering that the mantissa bit of the floating point type data is an unsigned number, when the conversion operation of converting the floating point type data into the signed integer type data is carried out, the mantissa bit of the floating point type data needs to be converted into the signed integer type data, and therefore, when the signed integer type data is positive number or unsigned integer type data, the bit inverting unit does not need to process; and when the signed integer data is negative, performing bit inversion operation on mantissa bits of the floating point data.

And the adhesion operation unit is used for performing OR operation on each bit of data by adhering the low-order discarded data bits in the data output by the bit inverting unit together to obtain discarded bit information with the data bit width of 1 bit.

The rounding control logic determines the manner in which the reserved bits are processed based on the rounding mode and the discard bit information. Wherein the rounding mode may indicate that the reserved bits are incremented by 1 when the discard bit information is 1; when the discarded bit information is 0, the reserved bit is not processed.

The fourth multiplexer is used for determining whether the data after +1 operation is performed on the high-order data output by the bit inverting unit or the high-order data output by the bit inverting unit is directly output based on the output result of the rounding control logic unit. If the rounding amount of the data determined by the rounding control logic unit is 1, the data after +1 operation is required to be output to the high-order data output by the bit inverting unit; if the rounding amount of the data determined by the rounding control logic unit is 0, the high-order data output by the bit inverting unit is directly output.

And the integer saturation processing unit is used for performing saturation processing operation when the output data type (namely the target data type) is integer and the data to be output exceeds the data representation range. Specifically, there are two modes of saturation processing: firstly, the data to be output is saturated to be the maximum value of the data which can be represented; and secondly, directly intercepting the data to be output, and intercepting only low-order effective data for output.

And the floating point number output format process is used for outputting a corresponding data format when the output data type is a floating point type and the floating point type is non-formatted data, namely, special types such as non-number (NaN), infinity (INF) and the like.

The fifth multiplexer determines whether to output the output data of the integer saturation unit or the output data of the floating point number output format processing unit as the target data based on the target data type. The fifth multiplexer outputs the output data of the integer saturation unit to the output data interface as target data when the target data type is integer; when the source data is floating point type, the output data of the floating point number output format processing unit is output as target data.

It can be seen that, based on the processor provided by the embodiment of the present application, units required for operations such as normalizing all data type conversion operations into the same data path, and performing most of hardware resources required in the data type conversion operation process, for example, preprocessing (floating point number output format processing unit, fixed point number sign bit expanding unit, absolute value taking operation unit), shift (leading zero detection unit, shift amount and exponent calculating unit, first sequence reversing unit, left shifter and second sequence reversing unit), rounding (bit-wise reversing unit, adder, adhesion operation unit, rounding control logic unit), post-processing (integer saturation unit, floating point number output format processing unit) and the like in the data path are multiplexed, so that the consumed chip area is smaller, that is, the hardware resource consumption of conversion operation is greatly reduced, and the processor has a higher area-to-area ratio. And through carrying out the normalization data path, the fan-out of the input data data_in can be reduced, and the layout wiring and timing problems in the back-end implementation process are eliminated. And through a sequence inversion mode, all the left shift operation and the right shift operation which are possibly generated are normalized to shift operation in the same target shift direction, so that the hardware resource consumption is further reduced.

Experimental data shows that in a processor implemented in the related art, the area occupied by hardware resources associated with various data type conversion operations in the process is 1350 μm 2. And based on the processor provided by the embodiment of the application, most of hardware resources required in the data type conversion operation process are multiplexed by adopting the synthesis tool design combiner, and the occupied area of the hardware resources associated with various data type conversion operations in the processing is 260 μm < 2 >. The area occupied by hardware resources associated with various data type conversion operations in the processor provided by the embodiment of the application in the processing is 19% of that of the related art.

Moreover, the processor provided by the embodiment of the application can complete calculation by only two stages of pipelines under the 1.5G main frequency, and has higher correlation performance.

The units in the processor of the embodiments of the present application may perform the method provided by the embodiments of the present application, and the implementation principle is similar, and actions performed by the modules in the apparatus of the embodiments of the present application correspond to steps in the method of the embodiments of the present application, and detailed functional descriptions of the modules of the apparatus may be referred to in the corresponding methods shown in the foregoing descriptions, which are not repeated herein.

Based on the same principle as the data type conversion method and the processor provided in the embodiments of the present application, an electronic device (such as a server) is also provided in the embodiments of the present application, where the electronic device may include a memory, a processor, and a computer program stored on the memory, where the processor executes the computer program to implement the method provided in any of the alternative embodiments of the present application.

In the embodiment of the application, the shift direction and the shift amount for carrying out shift operation on the source data are determined according to the original data type and the target data type of the source data to be converted. When the shift direction is the target direction, carrying out shift operation of the target direction on the target sequence of the source data according to the shift amount to obtain shifted data; when the shift direction is the opposite direction of the target direction, sequentially performing sequence inversion operation, shift operation of the target direction according to the shift amount, and sequence inversion operation on the target sequence of the source data to obtain shifted data. The processing operation of normalizing the processing operations in different shift directions into the processing operation in the same shift direction can be realized through a sequence inversion mode, shifted data are obtained, and the sequence inversion operation does not increase extra hardware resource consumption in the actual processing process, so that the hardware resource consumption required in the shift operation process can be reduced. And further obtains target data of the target data type based on the shifted data, so that data type conversion of the source data can be realized. The hardware resource consumption of the electronic device can be further reduced, i.e. the layout area consumption of the electronic device is reduced.

Referring to fig. 11, fig. 11 shows a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in fig. 11, the electronic device 1100 in the present embodiment may include: processor 1101, network interface 1104, and memory 1105, and further, the above-described electronic device 1100 may further include: an object interface 1103, and at least one communication bus 1102. Wherein communication bus 1102 is used to facilitate connection communications among the components. The object interface 1103 may include a Display screen (Display) and a Keyboard (Keyboard), and the optional object interface 1103 may further include a standard wired interface and a wireless interface. Network interface 1104 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface). The memory 1105 may be a high-speed RAM memory or a non-volatile memory (NVM), such as at least one magnetic disk memory. The memory 1105 may also optionally be at least one storage device located remotely from the processor 1101. As shown in fig. 11, an operating system, a network communication module, an object interface module, and a device control application may be included in the memory 1105 as one type of computer-readable storage medium.

In the electronic device 1100 shown in fig. 11, the network interface 1104 may provide network communication functionality; while object interface 1103 is primarily an interface for providing input to objects; and the processor 1101 may be configured to invoke the device control application stored in the memory 1105 to implement:

in some possible embodiments, the processor 1101 is configured to:

it should be appreciated that in some possible embodiments, the processor 1101 may be a central processing unit (central processing unit, CPU), which may also be other general purpose processors, digital signal processors (digital signal processor, DSP), application specific integrated circuits (application specific integrated circuit, ASIC), off-the-shelf programmable gate arrays (field-programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The memory may include read only memory and random access memory and provide instructions and data to the processor. A portion of the memory may also include non-volatile random access memory. For example, the memory may also store information of the device type.

In a specific implementation, the electronic device 1100 may execute, through each functional module built in the electronic device, an implementation manner provided by each step in fig. 5, and specifically, the implementation manner provided by each step may be referred to, which is not described herein again.

The embodiment of the present application further provides a computer readable storage medium, where a computer program is stored and executed by a processor to implement the method provided by each step in fig. 5, and specifically, the implementation manner provided by each step may be referred to, which is not described herein.

The computer readable storage medium may be the data type conversion apparatus provided in any one of the foregoing embodiments or an internal storage unit of the electronic device, for example, a hard disk or a memory of the electronic device. The computer readable storage medium may also be an external storage device of the electronic device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash card (flash card) or the like, which are provided on the electronic device. The computer readable storage medium may also include a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (random access memory, RAM), or the like. Further, the computer-readable storage medium may also include both an internal storage unit and an external storage device of the electronic device. The computer-readable storage medium is used to store the computer program and other programs and data required by the electronic device. The computer-readable storage medium may also be used to temporarily store data that has been output or is to be output.

Embodiments of the present application provide a computer program product comprising a computer program for executing the method provided by the steps of fig. 5 by a processor.

The terms first, second and the like in the claims and in the description and drawings are used for distinguishing between different objects and not for describing a particular sequential order.

Furthermore, as used herein, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless expressly stated otherwise. The terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or electronic device that comprises a list of steps or elements is not limited to the list of steps or elements but may, alternatively, include other steps or elements not listed or inherent to such process, method, article, or electronic device.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments. The term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The foregoing disclosure is illustrative of the present application and is not to be construed as limiting the scope of the application, which is defined by the appended claims.

Claims

1. A method of data type conversion, the method comprising:

acquiring source data to be converted, an original data type of the source data and a target data type; the original data type is integer or floating point type, and the target data type is integer or floating point type;

if the source data is determined to be shifted according to the original data type and the target data type, determining a shifting direction and a shifting amount of the source data based on the original data type and the target data type;

If the shift direction is the target direction, carrying out shift operation of the target direction on the target sequence of the source data according to the shift amount to obtain shifted data; if the original data type is integer, the target sequence is the source data; if the original data type is floating point type, the target sequence is the mantissa digit of the source data; the target direction is left or right; if the original data type is floating point type, the shifted data also comprises data after modifying the numerical value of the exponent bit of the source data based on the shift quantity;

and obtaining the target data of the target data type based on the shifted data.

2. The method of claim 1, wherein the deriving the target data of the target data type based on the shifted data comprises:

determining a data bit width of the shifted data;

If the data bit width is smaller than or equal to the target bit width corresponding to the target data type, obtaining the target data based on the shifted data;

if the data bit width is larger than the target bit width, determining low-bit data with the data bit width being the target bit width in the shifted data as reserved data; and obtaining the target data based on the reserved data.

3. The method of claim 2, wherein the obtaining the target data based on the retained data comprises:

determining the data rounding amount of the reserved data based on a preset rounding mode and the discard data; the discard data is data except the reserved data in the shifted data;

and correcting the reserved data based on the data rounding amount, and obtaining the target data based on the corrected reserved data.

4. A method according to any one of claims 1 to 3, wherein if the raw data type is integer, the method further comprises:

The determining a shift direction and a shift amount of the source data based on the original data type and the target data type includes:

and if the target data type is floating point type, determining that the shift quantity is the leading zero quantity in the sequence with the set bit width, and determining that the shift direction is leftward.

5. A method according to any one of claims 1 to 3, wherein the floating point type comprises at least one first type, and wherein if the original data type is any one of the first types, the determining the shift direction and shift amount of the source data based on the original data type and the target data type comprises:

if the target data type is integer, determining that the shift amount is the numerical value of the exponent of the source data, and determining that the shift direction is leftward;

if the target data type is another first type, determining the shift amount based on the numerical value of the exponent bits of the source data and a target exponent bit numerical value range corresponding to the target data type; and determining the shift direction based on the original exponent bit value range corresponding to the original data type and the target exponent bit value range.

6. A method according to any one of claims 1 to 3, wherein, if the target data type is integer, the obtaining target data of the target data type based on the shifted data comprises:

determining a value of a data bit of the shifted data; if the numerical value of the data bit is in the range of the target data value corresponding to the target data type, determining the shifted data as the target data; if the numerical value of the data bit is not in the target data value range, determining the target data based on the data closest to the shifted data in the target data value range; or alternatively

Determining a data bit width of the shifted data; if the data bit width is smaller than or equal to the target bit width corresponding to the target data type, determining the shifted data as the target data; and if the data bit width is larger than the target bit width, determining the target data based on the low-order data with the data bit width being the target bit width in the shifted data.

7. A method according to any one of claims 1 to 3, wherein if the target data type is a floating point type, the obtaining target data of the target data type based on the shifted data comprises:

Acquiring a target specification form of the target data type;

and if the target protocol form is a non-protocol form and the shifted data is protocol data, adjusting the shifted data into the data of the target protocol form to obtain the target data.

8. The method of claim 1, wherein the shaping comprises at least one second type, and wherein the deriving the target data of the target data type based on the shifted data comprises:

and if the target data type is any second type and any second type is a signed type, performing bit reversal operation on the shifted data to obtain the target data.

9. A processor, which is characterized by comprising a processor input interface, a shift amount and index calculating unit, a shifter, a first sequence reversing unit, a second sequence reversing unit and a processor output interface;

the processor input interface and the shift amount are connected with the input interface of the index calculation unit, the output interface of the shift amount and the output interface of the index calculation unit are respectively connected with the input interface of the shifter and the input interface of the first sequence inversion unit, the output interface of the first sequence inversion unit is connected with the input interface of the shifter, the output interface of the shifter is respectively connected with the input interface of the second sequence inversion unit and the output interface of the processor, and the output interface of the second sequence inversion unit is connected with the output interface of the processor;

the shift amount and index calculation unit is used for determining a shift direction and a shift amount of the source data based on the original data type and the target data type when determining to shift the source data according to the original data type and the target data type; outputting the source data, the shift direction, and the shift amount to the shifter when the shift direction is a target direction; outputting the source data to the first sequence reversing unit and outputting the shift direction and the shift amount to the shifter when the shift direction is the opposite direction of the target direction; the target direction is left or right;

the first sequence inversion unit is used for performing sequence inversion operation on a target sequence of received data to obtain first data, and outputting the first data to the shifter; if the original data type is integer, the target sequence is the source data; if the original data type is floating point type, the target sequence is the mantissa digit of the source data;

The shifter is used for carrying out the shift operation of the target direction on the target sequence of the received data according to the shift amount to obtain second data; if the shift direction is the target direction, determining shifted data based on the second data; outputting the second data to the second sequence inversion unit if the shift direction is the reverse direction; if the original data type is floating point type, the shifted data also comprises data after modifying the numerical value of the exponent of the source data based on the shift quantity;

the second sequence inversion unit is used for performing sequence inversion operation on the target sequence of the received data to obtain shifted data;

10. The processor of claim 9, further comprising a rounding logic control unit, the output interface of the shifter and the output interface of the second sequence inversion unit being connected to the processor output interface through the rounding logic control unit, respectively; the rounding logic control unit is configured to:

Determining a data bit width of the shifted data;

11. The processor of claim 10, further comprising a sticky operation unit, the rounding logic control unit being coupled to the processor output interface via the sticky operation unit, the sticky operation unit to:

12. The processor according to any one of claims 9 to 11, further comprising a sign bit expansion unit and a leading zero detection unit; the processor input interface is connected with the shift quantity and index calculation unit through the sign bit expansion unit and the leading zero detection unit in sequence;

The sign bit expansion unit is used for outputting the source data to the shift quantity and index calculation unit if the data bit width of the source data is a set bit width when the original data type is integer; if the data bit width of the source data is not the set bit width, expanding the source data into a sequence with the set bit width according to the value of the sign bit of the source data, and outputting the sequence with the set bit width to the shift quantity and index calculating unit;

the leading zero detection unit is used for determining the leading zero number in the sequence with the set bit width and outputting the leading zero number to the shift amount and index calculation unit;

and if the target data type is floating point type, determining that the shift amount is the leading zero amount, and determining that the shift direction is leftward.

13. The processor according to any one of claims 9 to 11, further comprising a floating point number input format processing unit and a leading zero detection unit; the processor input interface is connected with the shift quantity and exponent calculation unit through the floating point number input format processing unit; the floating point type includes at least one first type;

The floating point number input format processing unit is used for determining the exponent bit and the mantissa bit of the source data and outputting the exponent bit and the mantissa bit to the shift quantity and exponent calculating unit;

if the original data type is any one of the first types and the target data type is integer, determining that the shift amount is the numerical value of the exponent of the source data, and determining that the shift direction is leftward;

if the original data type is any one of the first types and the target data type is another one of the first types, determining the shift amount based on the numerical value of the exponent of the source data and the range of the numerical value of the target exponent corresponding to the target data type; and determining the shift direction based on the original exponent bit value range corresponding to the original data type and the target exponent bit value range.

14. The processor according to any one of claims 9 to 11, further comprising a multiplexer, an integer saturation processing unit and a floating point number output format processing unit, wherein the output interface of the shifter and the output interface of the second sequence inversion unit are respectively connected with the input interface of the multiplexer, and wherein the output interface of the multiplexer is respectively connected with the processor output interface through the integer saturation processing unit or the floating point number output format processing unit;

The multiplexer is used for outputting the shifted data to the integer saturation processing unit when the target data type is integer; when the target data type is floating point type, outputting the shifted data to the floating point number output format processing unit;

the shaping saturation processing unit is used for performing a first operation or a second operation to obtain the target data and outputting the target data to the processor output interface; wherein the first operation comprises: determining a value of a data bit of the shifted data; if the numerical value of the data bit is in the range of the target data value corresponding to the target data type, determining the shifted data as the target data; if the numerical value of the data bit is not in the target data value range, determining the target data based on the data closest to the shifted data in the target data value range; the second operation includes: determining a data bit width of the shifted data; if the data bit width is smaller than or equal to the target bit width corresponding to the target data type, determining the shifted data as the target data; if the data bit width is larger than the target bit width, determining the target data based on the low-order data with the data bit width being the target bit width in the shifted data;

The floating point number output format processing unit is used for acquiring a target protocol form of the target data type; and if the target protocol form is a non-protocol form and the shifted data is protocol data, adjusting the shifted data into the data in the target protocol form to obtain the target data, and outputting the target data to the processor output interface.

15. The processor of claim 9, further comprising a bit-wise inverting unit, wherein the integer comprises at least one second type, and wherein the output interface of the shifter and the output interface of the second sequence inverting unit are respectively coupled to the processor output interface through the bit-wise inverting unit; the bit-wise inverting unit is used for:

and when the target data type is any one of the second types and the any one of the second types is a signed type, performing bit-wise inversion operation on the shifted data to obtain the target data, and outputting the target data to the processor output interface.

16. An electronic device comprising a processor and a memory, the processor and the memory being interconnected;

The memory is used for storing a computer program;

the processor is configured to perform the method of any of claims 1 to 8 when the computer program is invoked.

17. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program which, when executed by a processor, implements the method of any one of claims 1 to 8.

18. A computer program product, characterized in that the computer program product comprises a computer program which, when executed by a processor, implements the method of any one of claims 1 to 8.