CN116960069A - Chip packaging assembly and preparation method thereof - Google Patents

Chip packaging assembly and preparation method thereof Download PDF

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Publication number
CN116960069A
CN116960069A CN202310912057.8A CN202310912057A CN116960069A CN 116960069 A CN116960069 A CN 116960069A CN 202310912057 A CN202310912057 A CN 202310912057A CN 116960069 A CN116960069 A CN 116960069A
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CN
China
Prior art keywords
chip
bonding pad
bonding
thickness
welding surface
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CN202310912057.8A
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Chinese (zh)
Inventor
曹超
邱金庆
王雄虎
甘润
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Sky Chip Interconnection Technology Co Ltd
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Sky Chip Interconnection Technology Co Ltd
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Priority to CN202310912057.8A priority Critical patent/CN116960069A/en
Publication of CN116960069A publication Critical patent/CN116960069A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

The application discloses a chip packaging assembly and a preparation method of the chip packaging assembly, comprising the following steps: the packaging substrate is provided with a first welding surface and a second welding surface with height difference; the first welding surface is lower than the second welding surface in the stacking direction; the first chip and the second chip are respectively arranged on the first welding surface and the second welding surface; the thickness of the first chip is larger than that of the second chip, and the thickness difference is the same as the height difference; the first pin and the second pin are coplanar, the first pin is arranged on one side surface of the first chip far away from the first welding surface, and the second pin is arranged on one side surface of the second chip far away from the second welding surface; and the two ends of the wire are respectively arranged on the first pin and the second pin so as to interconnect the first chip and the second chip. The application can reduce the radian and the length of the lead used for connecting the two chips, thereby improving the transmission quality and the transmission rate of signals.

Description

Chip packaging assembly and preparation method thereof
Technical Field
The application relates to the field of chip packaging, in particular to a chip packaging component and a preparation method of the chip packaging component.
Background
With the development of 5G technology and electronic products, the requirements for multifunctional chips are increasing, and the requirements for signal transmission quality and transmission rate are also increasing.
In the prior art, a plurality of chips are typically attached to a package substrate, and then interconnected by a Wire Bonding (semiconductor Bonding) process.
However, if there is a large difference in thickness between two chips to be interconnected, the bond wires connecting the chips need to have a large arc and a long length, and the large arc and length of the gold wires affect signal transmission.
Disclosure of Invention
The application mainly solves the technical problems of the chip packaging assembly and the preparation method of the chip packaging assembly, and can solve the problem that the radian and the length of a wire are large and the signal transmission is influenced due to the fact that the thickness difference exists between interconnected chips.
In order to solve the above technical problems, a first technical solution adopted by the present application is to provide a chip package assembly, including: the packaging substrate is provided with a first welding surface and a second welding surface with height difference; wherein the first welding surface is lower than the second welding surface in the stacking direction; the first chip and the second chip are respectively arranged on the first welding surface and the second welding surface; the thickness of the first chip is larger than that of the second chip, and the thickness difference is the same as the height difference; the first pin and the second pin are arranged on the surface of one side of the first chip, which is far away from the first welding surface, and the second pin is arranged on the surface of one side of the second chip, which is far away from the second welding surface; wherein the first pin and the second pin are coplanar; and the two ends of the wire are respectively arranged on the first pin and the second pin so as to interconnect the first chip and the second chip.
The packaging substrate comprises a first surface and a second surface which are oppositely arranged, and the first welding surface and the second welding surface are both arranged on the first surface; the first welding surface and the second surface are provided with a first distance, the second welding surface and the second surface are provided with a second distance, and the difference value between the first distance and the second distance is a height difference.
The first surface of the packaging substrate is provided with a first bonding pad and a second bonding pad with height difference, a first bonding surface is formed on one side, far away from the first surface, of the first bonding pad, and a second bonding surface is formed on one side, far away from the first surface, of the second bonding pad; the thickness of the first bonding pad is smaller than that of the second bonding pad, and the difference between the thickness of the first bonding pad and that of the second bonding pad is equal to the height difference.
The second bonding pad comprises a conductive pad and a third bonding pad which are sequentially stacked, the third bonding pad is arranged on the first surface, and a second bonding surface is formed on one side surface of the conductive pad, which is far away from the third bonding pad; the stacking thickness of the conductive pad and the third bonding pad is the thickness of the second bonding pad.
The first surface of the packaging substrate is provided with a first step groove, and the first welding surface is arranged at the bottom of the first step groove; wherein the depth of the first step groove is the same as the height difference.
The first welding surface is formed on one side of the first welding pad far away from the bottom of the first step groove, and the second welding surface is formed on one side of the second welding pad far away from the first surface; wherein the thickness of the first bonding pad is the same as the thickness of the second bonding pad.
The first chip and the second chip are respectively bonded with the first welding surface and the second welding surface through the conductive bonding layers.
In order to solve the technical problem, a second technical scheme adopted by the application is to provide a preparation method of a chip packaging assembly, which comprises the following steps: obtaining a packaging substrate; the packaging substrate is provided with a first welding surface and a second welding surface with height difference, and the height of the first welding surface in the stacking direction is lower than that of the second welding surface; obtaining a first chip and a second chip with thickness difference; the thickness of the first chip is larger than that of the second chip, and the thickness difference is the same as the height difference; the first chip and the second chip are respectively arranged on the first welding surface and the second welding surface, so that the first pin of the first chip and the second pin of the second chip are coplanar; wires are provided on the first and second pins, respectively, to interconnect the first chip and the second chip through the wires.
Wherein, the step of obtaining the package substrate comprises the following steps: a first bonding pad and a second bonding pad with height difference are arranged on the first surface of the packaging substrate, so that a first bonding surface is formed on one side of the first bonding pad far away from the first surface, and a second bonding surface is formed on one side of the second bonding pad far away from the first surface; the thickness of the first bonding pad is smaller than that of the second bonding pad, and the difference between the thickness of the first bonding pad and that of the second bonding pad is equal to the height difference.
Wherein, the step of obtaining the package substrate comprises the following steps: a first step groove is arranged on the first surface of the packaging substrate; the depth and the height difference of the first step groove are the same; a first welding surface is formed at the bottom of the first step groove, and a second welding surface is formed at a position where the first step groove is not formed on the first surface.
The beneficial effects of the application are as follows: compared with the prior art, the chip packaging assembly and the preparation method thereof are provided, the first chip and the second chip with the same thickness difference and the same height difference are obtained by arranging the first welding surface and the second welding surface with the height difference on the packaging substrate, and the first pin of the first chip and the second pin of the second chip are coplanar by arranging the first chip with the larger thickness on the first welding surface with the lower height and the second chip with the smaller thickness on the second welding surface with the higher height. Through making first pin and second pin coplane, can reduce the radian and the length of the wire that are used for connecting first pin and second pin, avoid radian and length of wire great to improve transmission quality and the transmission rate of signal, promote product quality then.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic view of a first embodiment of a chip package assembly according to the present application;
FIG. 2 is a top view of the chip package assembly of FIG. 1;
FIG. 3 is a schematic view of a first embodiment of a second embodiment of a chip package assembly according to the present application;
FIG. 4 is a schematic diagram of a second embodiment of a chip package assembly according to the present application;
fig. 5 is a schematic flow chart of an embodiment of a method for manufacturing a chip package according to the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to fall within the scope of the present application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two, but does not exclude the case of at least one.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
It should be understood that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
In the prior art, a plurality of chips are typically attached to a package substrate, and then interconnected by a Wire Bonding (semiconductor Bonding) process. However, if there is a large difference in thickness between two chips to be interconnected, the bond wires connecting the chips need to have a large arc and a long length, and the large arc and length of the gold wires affect signal transmission.
Based on the above situation, the application provides the chip packaging assembly and the preparation method of the chip packaging assembly, which can solve the problem that the signal transmission is influenced due to the fact that the radian and the length of the lead are large due to the fact that the thickness difference exists between the interconnected chips.
The present application will be described in detail with reference to the drawings and embodiments.
Referring to fig. 1 and 2, fig. 1 is a schematic structural diagram of a first embodiment of a chip package assembly according to the present application, and fig. 2 is a top view of the chip package assembly of fig. 1. In this embodiment, the chip package 100 includes a package substrate 110, a first bonding surface 101 and a second bonding surface 102 having a height difference, a first chip 140 and a second chip 150 having a thickness difference, and a wire 160 connecting the first chip 140 and the second chip 150.
Wherein, the height of the first bonding surface 101 in the stacking direction is lower than the second bonding surface 102, the thickness of the first chip 140 is greater than the thickness of the second chip 150, and the thickness difference between the first chip 140 and the second chip 150 is equal to the height difference between the first bonding surface 101 and the second bonding surface 102, the first chip 140 is disposed on the first bonding surface 101, and the second chip 150 is disposed on the second bonding surface 102.
It will be appreciated that the difference in height between the first bonding surface 101 and the second bonding surface 102 is determined by the difference in height between the first chip 140 and the second chip 150, so that the first chip 140 and the second chip 150 can be coplanar with a side surface of the package substrate 110 away from each other when the first chip 140 and the second chip 150 are bonded.
In this embodiment, a first lead 141 is disposed on a surface of the first chip 140 away from the first bonding surface 101, and a second lead 151 is disposed on a surface of the second chip 150 away from the second bonding surface 102, where the first lead 141 is coplanar with the second lead 151. Wherein, two ends of the wire 160 are respectively disposed on the first pin 141 and the second pin 151 to interconnect the first chip 140 and the second chip 150.
As can be appreciated, since the side surface of the first chip 140 far from the first soldering surface 101 is coplanar with the side surface of the second chip 150 far from the second soldering surface 102, the first pins 141 and the second pins 151 respectively disposed on the two side surfaces are also coplanar, so that the radian and the length of the wires 160 for connecting the first pins 141 and the second pins 151 can be reduced, the radian and the length of the wires 160 are prevented from being larger, and the signal transmission quality and the signal transmission rate are improved, and the product quality is improved.
In the present embodiment, the first bonding surface 101 and the second bonding surface 102 are provided with the conductive adhesive layer 180, and the first chip 140 and the second chip 150 are bonded to the first bonding surface 101 and the second bonding surface 102 through the conductive adhesive layer 180, respectively.
The conductive adhesive layer 180 may be a solder paste, silver paste, or the like.
In this embodiment, the conductive adhesive layer 180 disposed on the first soldering surface 101 and the second soldering surface 102 have the same thickness, so as to ensure that the first lead 141 and the second lead 151 are coplanar.
In other embodiments, the conductive adhesive layer 180 disposed on the first bonding surface 101 and the second bonding surface 102 may also have different thicknesses. For example, if there is a slight difference between the height difference between the first bonding surface 101 and the second bonding surface 102 and the thickness difference between the first chip 140 and the second chip 150 due to the limitation of the process conditions, the thickness of the conductive adhesive layer 180 on one bonding surface may be appropriately increased in order to ensure coplanarity of the first and second pins 141 and 151.
In a specific implementation scenario, the thickness difference between the first chip 140 and the second chip 150 is 10mm, the height difference between the first soldering surface 101 and the second soldering surface 102 is 9.7mm, and then the thickness of the conductive adhesive layer 180 disposed on the second soldering surface 102 may be 0.5mm, and the thickness of the conductive adhesive layer 180 disposed on the first soldering surface 101 may be 0.2mm, so as to ensure that the first lead 141 and the second lead 151 are coplanar.
In another specific implementation scenario, the thickness difference between the first chip 140 and the second chip 150 is 15mm, the height difference between the first soldering surface 101 and the second soldering surface 102 is 15.2mm, and then the thickness of the conductive adhesive layer 180 disposed on the second soldering surface 102 may be 0.3mm, and the thickness of the conductive adhesive layer 180 disposed on the first soldering surface 101 may be 0.5mm, so as to ensure that the first lead 141 and the second lead 151 are coplanar.
With continued reference to fig. 1, in the present embodiment, the package substrate 110 includes a first surface 111 and a second surface 112 disposed opposite to each other, and the first bonding surface 101 and the second bonding surface 102 are disposed on the first surface 111. The first welding surface 101 and the second surface 112 have a first distance therebetween, the second welding surface 102 and the second surface 112 have a second distance therebetween, and a difference between the first distance and the second distance is a height difference.
In some embodiments, the first surface 111 of the package substrate 110 is provided with a first pad 120 and a second pad 130 having a height difference, a first bonding surface 101 is formed on a side of the first pad 120 away from the first surface 111, and a second bonding surface 102 is formed on a side of the second pad 130 away from the first surface 111. Wherein, the thickness of the first pad 120 is smaller than the thickness of the second pad 130, and the difference between the thickness of the first pad 120 and the thickness of the second pad 130 is equal to the height difference.
In some embodiments, the second pad 130 includes a conductive pad 132 and a third pad 131 that are stacked in order, the third pad 131 is disposed on the first surface 111, and a side surface of the conductive pad 132 away from the third pad 131 is formed with the second bonding surface 102. Wherein, the stacking thickness of the conductive pad 132 and the third pad 131 is the thickness of the second pad 130.
In some embodiments, the material of the conductive pad 132 may be a copper block.
It is understood that the thickness of the conductive pad 132 depends not only on the thickness difference between the first chip 140 and the second chip 150, but also on the height difference between the third pad 131 and the first pad 120.
In a specific implementation scenario, the thickness difference between the first chip 140 and the second chip 150 is 10mm, and the height difference between the first bonding pad 120 and the third bonding pad 131 is 0, and then the thickness of the conductive pad 132 is the thickness difference (10 mm) between the first chip 140 and the second chip 150.
In some embodiments, the chip package assembly 100 further includes a plastic package 170, where the plastic package 170 covers the first chip 140, the second chip 150, and the package substrate 110. In some embodiments, the material of the plastic package 170 may be an insulating material such as resin, plastic, film material, liquid epoxy, etc., which is not limited in the present application.
It will be appreciated that sealing the first and second chips 140, 150 by means of a thermoplastic such as a silk-screened resin or laminated polypropylene allows for a lower cost and ensures reliable fixing and sealing of the first and second chips 140, 150.
Unlike the prior art, the present embodiment is capable of making the first chip 140 and the second chip 150 coplanar with a side surface of the second chip 150 away from the package substrate 110 by providing the first bonding surface 101 and the second bonding surface 102 having the height difference on the package substrate 110 and obtaining the first chip 140 and the second chip 150 having the same thickness difference as the height difference, and by providing the first chip 140 having a larger thickness on the first bonding surface 101 having a lower height and providing the second chip 150 having a smaller thickness on the second bonding surface 102 having a higher height, thereby making the first pins 141 of the first chip 140 coplanar with the second pins 151 of the second chip 150. By making the first pin 141 and the second pin 151 coplanar, the radian and the length of the wire 160 for connecting the first pin 141 and the second pin 151 can be reduced, and the wire 160 is prevented from being large in radian and length, so that the signal transmission quality and the signal transmission rate are improved, and the product quality is improved.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a first embodiment of a chip package assembly according to a second embodiment of the application. In this embodiment, the chip package assembly 200 includes a package substrate 210, a first bonding surface 201 and a second bonding surface 202 with a height difference disposed on the package substrate 210, a first chip 240 and a second chip 250 with a thickness difference, and a wire 260 connecting the first chip 240 and the second chip 250.
Wherein, the height of the first bonding surface 201 in the stacking direction is lower than the second bonding surface 202, the thickness of the first chip 240 is greater than the second chip 250, and the thickness difference between the first chip 240 and the second chip 250 is equal to the height difference between the first bonding surface 201 and the second bonding surface 202, the first chip 240 is disposed on the first bonding surface 201, and the second chip 250 is disposed on the second bonding surface 102.
The first chip 240 has a first lead 141 on a surface thereof far from the first bonding surface 201, and the second chip 250 has a second lead 251 on a surface thereof far from the second bonding surface 202, and the first lead 241 is coplanar with the second lead 251. Wherein, two ends of the wire 260 are respectively disposed on the first pin 241 and the second pin 251 to interconnect the first chip 240 and the second chip 250.
The first bonding surface 201 and the second bonding surface 202 are provided with a conductive adhesive layer 280, and the first chip 240 and the second chip 250 are bonded to the first bonding surface 201 and the second bonding surface 202 respectively through the conductive adhesive layer 280.
The chip package assembly 200 further includes a plastic package 270, wherein the plastic package 270 covers the first chip 240, the second chip 250, and the package substrate 210.
The following describes a part of the present embodiment different from the first embodiment.
In this embodiment, the package substrate 210 has a first surface 211 and a second surface 212 disposed opposite to each other, the first surface 211 of the package substrate 210 is provided with a first step groove 290, and the first soldering surface 201 is disposed at the bottom of the first step groove 290. Wherein the depth of the first step groove 290 is the same as the height difference.
In some embodiments, the bottom of the first step groove 290 is provided with a first bonding pad 220, the first surface 211 is not provided with a second bonding pad 230, a side of the first bonding pad 220 away from the bottom of the first step groove 290 is formed with a first bonding surface 201, and a side of the second bonding pad 230 away from the first surface 211 is formed with a second bonding surface 202.
Wherein the thickness of the first pad 220 and the second pad 230 are the same to ensure that the first pin 241 is coplanar with the second pin 251.
Wherein the first step groove 290 has a size larger than that of the first pad 220 to accommodate the first pad 220.
As can be appreciated, by providing the first stepped groove 290 and accommodating the first pad 220 and the first chip 240 with the first stepped groove 290, not only can the thickness difference between the first chip 240 and the second chip 250 be eliminated, but also the thickness of the chip package assembly 200 can be reduced as a whole, thereby achieving a miniaturized package.
In some embodiments, a second step groove 291 may be further disposed on the first surface 211 of the package substrate 210, a metal pillar 221 is formed in the second step groove 291, and a first soldering surface 201 is formed at an end of the metal pillar 221 away from the bottom of the second step groove 291. Wherein the depth of the second step groove 291 is the same as the height difference, and the depth of the metal pillar 221 is identical to the thickness of the second pad 230. Specifically, referring to fig. 4, fig. 4 is a schematic structural diagram of a second embodiment of a chip package assembly according to the present application.
Unlike the prior art, the present embodiment is capable of making the first chip 240 and the second chip 250 coplanar with a side surface of the second chip 250 away from the package substrate 210 by providing the first bonding surface 201 and the second bonding surface 202 having the height difference on the package substrate 210 and obtaining the first chip 240 and the second chip 250 having the same thickness difference as the height difference, and by providing the first chip 240 having a larger thickness on the first bonding surface 201 having a lower height and providing the second chip 250 having a smaller thickness on the second bonding surface 202 having a higher height, thereby making the first pins 241 of the first chip 240 coplanar with the second pins 251 of the second chip 250. By making the first pin 241 and the second pin 251 coplanar, the radian and the length of the wire 160 for connecting the first pin 241 and the second pin 251 can be reduced, and the radian and the length of the wire 260 are prevented from being larger, so that the transmission quality and the transmission rate of signals are improved, and then the product quality is improved. In addition, by providing the first step groove 290 or the second step groove 291 and accommodating the first chip 240 with the first step groove 290 or the second step groove 291, not only can the thickness difference between the first chip 240 and the second chip 250 be eliminated, but also the thickness of the chip package assembly 200 can be reduced as a whole, thereby realizing a miniaturized package.
Correspondingly, the application provides a preparation method of the chip packaging component.
Specifically, referring to fig. 5, fig. 5 is a flow chart of an embodiment of a method for manufacturing a chip package according to the present application. In this embodiment, the preparation method includes:
s11: obtaining a packaging substrate; the packaging substrate is provided with a first welding surface and a second welding surface with height difference, and the height of the first welding surface in the stacking direction is lower than that of the second welding surface.
In this embodiment, the package substrate includes a first surface and a second surface disposed opposite to each other, and the first bonding surface and the second bonding surface are disposed on the first surface. The first welding surface and the second surface are provided with a first distance, the second welding surface and the second surface are provided with a second distance, and the difference value between the first distance and the second distance is a height difference.
In a specific embodiment, the step of obtaining the package substrate includes: a first bonding pad and a second bonding pad with height difference are arranged on a first surface of the packaging substrate, so that a first bonding surface is formed on one side of the first bonding pad far away from the first surface, and a second bonding surface is formed on one side of the second bonding pad far away from the first surface. The thickness of the first bonding pad is smaller than that of the second bonding pad, and the difference between the thickness of the first bonding pad and that of the second bonding pad is equal to the height difference.
In another specific embodiment, the step of obtaining the package substrate includes: a first step groove is provided on a first surface of the package substrate. Wherein the depth of the first step groove is the same as the height difference. A first welding surface is formed at the bottom of the first step groove, and a second welding surface is formed at a position where the first step groove is not formed on the first surface.
It can be appreciated that by providing the first stepped groove and accommodating the chip having a larger thickness by using the first stepped groove, not only the thickness difference between the two chips can be eliminated, but also the thickness of the chip package assembly can be reduced as a whole, thereby realizing miniaturized package.
S12: obtaining a first chip and a second chip with thickness difference; the thickness of the first chip is larger than that of the second chip, and the thickness difference is the same as the height difference.
S13: the first chip and the second chip are respectively arranged on the first welding surface and the second welding surface, so that the first pin of the first chip and the second pin of the second chip are coplanar.
In this embodiment, a plurality of first pins are disposed on a surface of the first chip away from the first bonding surface, and a plurality of second pins are disposed on a surface of the second chip away from the second bonding surface.
It is understood that, since a side surface of the first chip away from the first bonding surface is coplanar with a side surface of the second chip away from the second bonding surface, the first leads and the second leads respectively disposed on the two side surfaces are also coplanar.
S14: wires are provided on the first and second pins, respectively, to interconnect the first chip and the second chip through the wires.
It can be appreciated that by making the first pin and the second pin coplanar, the radian and length of the wire used to connect the first pin and the second pin can be reduced, and the radian and length of the wire are prevented from being larger, thereby improving the transmission quality and transmission rate of the signal.
Compared with the prior art, the first chip and the second chip are coplanar on the surface of the packaging substrate far away from the packaging substrate by arranging the first welding surface and the second welding surface with the height difference on the packaging substrate and acquiring the first chip and the second chip with the thickness difference identical to the height difference, and by arranging the first chip with the larger thickness on the first welding surface with the lower height and arranging the second chip with the smaller thickness on the second welding surface with the higher height, the first pin of the first chip and the second pin of the second chip are coplanar. Through making first pin and second pin coplane, can reduce the radian and the length of the wire that are used for connecting first pin and second pin, avoid radian and length of wire great to improve transmission quality and the transmission rate of signal, promote product quality then.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.

Claims (10)

1. A chip package assembly, comprising:
the packaging substrate is provided with a first welding surface and a second welding surface with height difference; wherein the first welding surface has a lower height in the stacking direction than the second welding surface;
the first chip and the second chip are respectively arranged on the first welding surface and the second welding surface; wherein the thickness of the first chip is larger than that of the second chip, and the thickness difference is the same as the height difference;
the first pin and the second pin are arranged on the surface of one side of the first chip, which is far away from the first welding surface, and the second pin is arranged on the surface of one side of the second chip, which is far away from the second welding surface; wherein the first pin is coplanar with the second pin;
and the two ends of the wire are respectively arranged on the first pin and the second pin so as to interconnect the first chip and the second chip.
2. The chip package assembly of claim 1, wherein the chip package assembly,
the packaging substrate comprises a first surface and a second surface which are oppositely arranged, and the first welding surface and the second welding surface are both arranged on the first surface; the first welding surface and the second surface are provided with a first distance, the second welding surface and the second surface are provided with a second distance, and the difference value between the first distance and the second distance is the height difference.
3. The chip package assembly of claim 2, wherein,
a first bonding pad and a second bonding pad with height difference are arranged on the first surface of the packaging substrate, the first bonding surface is formed on one side, far away from the first surface, of the first bonding pad, and the second bonding surface is formed on one side, far away from the first surface, of the second bonding pad;
the thickness of the first bonding pad is smaller than that of the second bonding pad, and the difference between the thickness of the first bonding pad and that of the second bonding pad is equal to the height difference.
4. The chip package assembly of claim 3, wherein,
the second bonding pad comprises a conductive pad and a third bonding pad which are sequentially stacked, the third bonding pad is arranged on the first surface, and a second bonding surface is formed on one side surface of the conductive pad, which is far away from the third bonding pad; the stacking thickness of the conductive pad and the third bonding pad is the thickness of the second bonding pad.
5. The chip package assembly of claim 2, wherein,
a first step groove is formed in the first surface of the packaging substrate, and the first welding surface is arranged at the bottom of the first step groove; wherein the depth of the first step groove is the same as the height difference.
6. The chip package assembly of claim 5, wherein,
the bottom of the first step groove is provided with a first bonding pad, a second bonding pad is arranged at a position of the first surface, where the first step groove is not arranged, one side, far away from the bottom of the first step groove, of the first bonding pad is provided with a first bonding surface, and one side, far away from the first surface, of the second bonding pad is provided with a second bonding surface; wherein the thickness of the first bonding pad is the same as the thickness of the second bonding pad.
7. The chip package assembly according to any one of claims 2 to 6, wherein,
the first welding surface and the second welding surface are provided with conductive bonding layers, and the first chip and the second chip are respectively bonded with the first welding surface and the second welding surface through the conductive bonding layers.
8. A method of manufacturing a chip package assembly, comprising:
obtaining a packaging substrate; the packaging substrate is provided with a first welding surface and a second welding surface with height difference, and the height of the first welding surface in the stacking direction is lower than that of the second welding surface;
obtaining a first chip and a second chip with thickness difference; wherein the thickness of the first chip is larger than that of the second chip, and the thickness difference is the same as the height difference;
the first chip and the second chip are respectively arranged on the first welding surface and the second welding surface, so that a first pin of the first chip and a second pin of the second chip are coplanar;
wires are respectively arranged on the first pin and the second pin so as to interconnect the first chip and the second chip through the wires.
9. The method according to claim 8, wherein,
the step of obtaining the package substrate comprises the following steps:
a first bonding pad and a second bonding pad with height difference are arranged on the first surface of the packaging substrate, so that a first bonding surface is formed on one side of the first bonding pad far away from the first surface, and a second bonding surface is formed on one side of the second bonding pad far away from the first surface; the thickness of the first bonding pad is smaller than that of the second bonding pad, and the difference between the thickness of the first bonding pad and that of the second bonding pad is equal to the height difference.
10. The method according to claim 8, wherein,
the step of obtaining the package substrate comprises the following steps:
a first step groove is formed in the first surface of the packaging substrate; wherein the depth of the first step groove is the same as the height difference;
and forming the first welding surface at the bottom of the first step groove, and forming the second welding surface at the position of the first surface where the first step groove is not arranged.
CN202310912057.8A 2023-07-21 2023-07-21 Chip packaging assembly and preparation method thereof Pending CN116960069A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310912057.8A CN116960069A (en) 2023-07-21 2023-07-21 Chip packaging assembly and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310912057.8A CN116960069A (en) 2023-07-21 2023-07-21 Chip packaging assembly and preparation method thereof

Publications (1)

Publication Number Publication Date
CN116960069A true CN116960069A (en) 2023-10-27

Family

ID=88450711

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310912057.8A Pending CN116960069A (en) 2023-07-21 2023-07-21 Chip packaging assembly and preparation method thereof

Country Status (1)

Country Link
CN (1) CN116960069A (en)

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