CN116959362A

CN116959362A - Scan driving circuit and display panel

Info

Publication number: CN116959362A
Application number: CN202310936327.9A
Authority: CN
Inventors: 曾迎祥; 肖丽娜; 王�琦; 刘杰
Original assignee: EverDisplay Optronics Shanghai Co Ltd
Current assignee: EverDisplay Optronics Shanghai Co Ltd
Priority date: 2023-07-27
Filing date: 2023-07-27
Publication date: 2023-10-27

Abstract

The invention relates to the field of display panels, and provides a scanning driving circuit and a display panel, wherein the scanning driving circuit comprises a multi-stage shift register unit and a time sequence controller, each stage of shift register unit comprises 13 transistors and 3 capacitors, and the time sequence controller comprises two time sequence control signal lines. According to the scanning driving circuit and the display panel, the novel 13T3C shift register unit is provided, so that the mutual restriction influence among transistors is solved, the scanning circuit is more stable, abnormal display phenomenon caused by fluctuation of the length-width ratio of the transistors due to threshold voltage deviation or manufacturing process errors is avoided, and the service life of the display panel is prolonged; in addition, the shift register unit solves the problem of electric floating of nodes in the circuit and improves the reliability of the display panel.

Description

Scan driving circuit and display panel

Technical Field

The invention relates to the field of display panels, in particular to a scanning driving circuit and a display panel.

Background

The display panel comprises a pixel array, a scanning driving circuit and a light-emitting driving circuit, wherein the scanning driving circuit is used for controlling the pixel array, and the display panel adopts a progressive scanning display mode, wherein the scanning driving circuit is used for generating scanning signals so that each row of pixels are sequentially conducted.

The scan driving circuit includes a plurality of cascaded shift register units, wherein the circuit of each stage of shift register unit is generally mainly composed of a plurality of transistors, and the scan signal Gout is outputted at an output terminal by inputting a clock signal CKV and a start pulse signal IN to the circuit.

Chinese patent CN105989797a provides a scanning circuit, as shown in fig. 1 and 2, fig. 1 shows a circuit diagram of a shift register unit of the prior art; fig. 2 shows waveforms of the prior art shift register unit when in operation. Wherein "H" represents a high level signal and "L" represents a low level signal. In this circuit, T5 and T6 are tied to each other, and when the threshold voltage vth of the transistor is shifted after the display panel is used for a long time, or the aspect ratio of the transistor is changed due to manufacturing process errors of the display panel, abnormal output of the scan circuit of the display panel may be caused. As shown in fig. 2, gout is an ideal output signal, and Abnormal Gout is an Abnormal output signal, so that the display panel displays an Abnormal picture. In addition, the second node N2 in the circuit of the shift register unit has a problem of floating (floating) at some time during operation, which causes abnormal display of the display panel and reduced reliability.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the invention and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.

Disclosure of Invention

In view of the above, the present invention provides a scan driving circuit and a display panel.

One aspect of the present invention provides a scan driving circuit including a multi-stage shift register unit including:

a first transistor, a first electrode of which is connected with the signal input end, a second electrode is connected with the second node, and a grid electrode is connected with the second time sequence control end;

a second transistor, a second pole of which is connected to the second node, and a gate of which is connected to the first node;

a third transistor, a first electrode of which is connected to a first power supply, a second electrode of which is connected to a first electrode of the second transistor, and a gate of which is connected to a first timing control terminal;

a fourth transistor, the first electrode of the fourth transistor is connected to a second power supply, the second electrode is connected to a fourth node, and the gate is connected to the second timing control end;

a fifth transistor having a first electrode connected to the second timing control terminal, a second electrode connected to the first node, and a gate connected to the second node;

a sixth transistor having a first electrode connected to the second node, a second electrode connected to a fifth node, and a gate connected to the second power supply;

a seventh transistor, a first pole of which is connected to the first power supply, a second pole is connected to the signal output terminal, and a gate is connected to the first node;

an eighth transistor, a first pole of which is connected to the signal output terminal, a second pole is connected to the first timing control terminal, and a gate is connected to the fifth node;

a ninth transistor having a first electrode connected to the fourth node, a second electrode connected to the first node, and a gate connected to a third node;

a tenth transistor, a first pole of which is connected to the first timing control terminal, a second pole is connected to the third node, and a gate is connected to the signal input terminal;

an eleventh transistor having a first electrode connected to the third node, a second electrode connected to the second power supply, and a gate connected to the first timing control terminal;

a twelfth transistor having a first electrode connected to the first node and a gate connected to the fourth node;

a thirteenth transistor, a first pole of the thirteenth transistor is connected to a second pole of the twelfth transistor, a second pole is connected to the second power supply, and a gate is connected to the first timing control terminal;

a first capacitor, a first pole of which is connected to the first power supply, and a second pole of which is connected to the first node;

the first electrode of the second capacitor is connected with the fifth node, and the second electrode of the second capacitor is connected with the signal output end;

and a third capacitor, wherein a first pole of the third capacitor is connected to the fourth node, and a second pole of the third capacitor is connected to the third node.

In some embodiments, a timing controller is further included, the timing controller including a first timing control signal line and a second timing control signal line.

In some embodiments, the first timing control signal line is configured to output a first timing control signal; the second timing control signal line is used for outputting a second timing control signal.

In some embodiments, the first timing control signal and the second timing control signal are square wave signals having the same output frequency and 180 ° phase difference.

In some embodiments, the shift register unit is configured to delay the signal received from the signal input terminal under the control of the first timing control signal and the second timing control signal, and the processed signal is output from the signal output terminal.

In some embodiments, the shift register unit at the previous stage outputs a scan signal to the shift register unit at the next stage, and the shift register unit at the last stage outputs a scan signal.

In some embodiments, in the shift register units of odd stages, the first timing control terminal is connected to the first timing control signal line, and the second timing control terminal is connected to the second timing control signal line.

In some embodiments, in the shift register units of even-numbered stages, the first timing control terminal is connected to the second timing control signal line, and the second timing control terminal is connected to the first timing control signal line.

In some embodiments, the first transistor to the thirteenth transistor are P-type MOS transistors.

Another aspect of the present invention also provides a display panel, which includes the scan driving circuit described in any one of the above.

Compared with the prior art, the invention has the beneficial effects that at least:

according to the scanning driving circuit and the display panel, the novel 13T3C shift register unit is provided, so that the mutual restriction influence among transistors is solved, the scanning circuit is more stable, abnormal display phenomenon caused by fluctuation of the length-width ratio of the transistors due to threshold voltage deviation or manufacturing process errors is avoided, and the service life of the display panel is prolonged; in addition, the shift register unit solves the problem of electric floating of nodes in the circuit and improves the reliability of the display panel.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 shows a circuit diagram of a prior art shift register cell;

FIG. 2 is a waveform diagram showing the operation of a prior art shift register cell;

FIG. 3 is a schematic diagram of a display panel of the present invention;

FIG. 4 shows a schematic diagram of a cascade of scan driving circuits of the present invention;

fig. 5 shows a circuit diagram of a shift register cell of the present invention;

fig. 6 shows waveforms of the shift register unit shown in fig. 5 when operated;

FIG. 7 is a schematic diagram showing the on state of the shift register unit at stage t1 in FIG. 6;

FIG. 8 is a schematic diagram showing the on state of the shift register unit at stage t2 in FIG. 6;

FIG. 9 is a schematic diagram showing the on state of the shift register unit at stage t3 in FIG. 6;

fig. 10 shows a schematic diagram of the on state of the shift register unit at stage t4 in fig. 6.

Reference numerals:

10. display panel

11. Display area

20. Time sequence controller

30. Scanning driving circuit

CKV1 first timing control signal line

CKV2 second time sequence control signal line

c1 First timing control terminal

c2 A second timing control terminal

IN signal input terminal

Gout signal output terminal

T1 first transistor

T2 second transistor

T3 third transistor

T4 fourth transistor

T5 fifth transistor

T6 sixth transistor

T7 seventh transistor

T8 eighth transistor

T9 ninth transistor

T10 tenth transistor

T11 eleventh transistor

T12 twelfth transistor

T13 thirteenth transistor

C1 First capacitor

C2 Second capacitor

C3 Third capacitor

VDD first power supply

VEE second power supply

n1 first node

n2 second node

n3 third node

n4 fourth node

n5 fifth node

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted.

The use of the terms "first," "second," and the like in the description herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Furthermore, in the description of the present invention, the orientation or positional relationship indicated by the terms "upper", "lower", etc. are based on the orientation or positional relationship shown in the drawings, which are for convenience of description only, and are not indicative or implying that the apparatus or element in question must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention.

It should be noted that, without conflict, the embodiments of the present invention and features in different embodiments may be combined with each other.

The present inventors have made intensive studies to provide a solution to the problems existing in the prior art. As shown in fig. 3 to 5, fig. 3 shows a schematic view of the display panel of the present invention;

FIG. 4 shows a schematic diagram of a cascade of scan driving circuits of the present invention; fig. 5 shows a circuit diagram of a shift register cell of the present invention. The invention discloses a scan driving circuit 30 and a display panel 10. The scan driving circuit 30 includes a plurality of shift register units and a timing controller 20, wherein each shift register unit includes 13 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Gout, and three timing control terminals. The timing controller 20 includes three timing control signal lines. According to the scanning driving circuit and the display panel, the novel 13T3C shift register unit is provided, so that the mutual restriction influence among transistors is solved, the scanning circuit is more stable, abnormal display phenomenon caused by fluctuation of the length-width ratio of the transistors due to threshold voltage deviation or manufacturing process errors is avoided, and the service life of the display panel is prolonged; in addition, the shift register unit solves the problem of electric floating of nodes in the circuit and improves the reliability of the display panel.

The following describes the embodiments of the present invention in further detail with reference to the drawings.

As shown in fig. 3, the present invention provides a display panel 10, the display panel 10 including a display region 11 and a non-display region. Wherein the scan driving circuit 30, the data driver and the light emitting driving circuit are located in the non-display area of the display panel 10. The display area 11 includes light emitting pixels and pixel circuits arranged in an array. The light emitting pixels emit light by the combined action of the scan driving circuit 30, the data driver, the light emitting driving circuit, and the pixel circuit.

As shown in fig. 3 and 4, the present invention also provides a scan driving circuit 30 including a multi-stage shift register unit and a timing controller 20.

IN some embodiments, the shift register unit includes 13 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Gout, a first timing control terminal c1, a second timing control terminal c2, and a third timing control terminal c3. Each stage of shift register unit outputs a scanning signal, and the scanning signal is input into a row of pixel circuits in the display area 11 of the display panel 10 to drive the row of pixels to emit light. The upper stage shift register unit simultaneously outputs a scan signal to the signal input terminal IN of the lower stage shift register unit as a start signal. Since the last shift register unit does not have a next stage, the output scanning signal is input to only the row of pixel circuits.

Specifically, IN fig. 4, for example, 4 cascaded shift register units are taken, and the signal input terminal IN1 of the first stage shift register unit S1 inputs the start pulse signal STV as an input signal. The signal output terminal Gout1 of the first stage shift register unit S1 outputs a scan signal as an input signal of the second stage shift register unit S2, and the signal output terminal Gout1 of the first stage shift register unit S1 is connected to the signal input terminal IN2 of the second stage shift register unit S2. The signal output terminal Gout2 of the second stage shift register unit S2 outputs a scan signal as an input signal of the third stage shift register unit S3, and the signal output terminal Gout2 of the second stage shift register unit S2 is connected to the signal input terminal IN3 of the third stage shift register unit S3. The signal output terminal Gout3 of the third stage shift register unit S3 outputs a scan signal as an input signal of the fourth stage shift register unit S4, and the signal output terminal Gout3 of the third stage shift register unit S3 is connected … … to the signal input terminal IN4 of the fourth stage shift register unit S4 to repeat the same, thereby forming the scan driving circuit 30.

In some embodiments, as shown in fig. 4, the timing controller 20 includes a first timing control signal line CKV1 and a second timing control signal line CKV2. The first timing control signal line CKV1 is configured to output a first timing control signal. The second timing control signal line CKV2 is for outputting a second timing control signal. The first time sequence control signal and the second time sequence control signal are square wave signals with the same output frequency and 180 degrees phase difference.

In some preferred embodiments, with continued reference to fig. 4, further, the first timing control terminal c1 of the odd-numbered stage shift register unit is connected to the first timing control signal line CKV1 for receiving the first timing control signal, and the second timing control terminal c2 thereof is connected to the second timing control signal line CKV2 for receiving the second timing control signal. The first timing control terminal c1 of the even-numbered stage shift register unit is connected to the second timing control signal line CKV2 for receiving the second timing control signal, and the second timing control terminal c2 thereof is connected to the first timing control signal line CKV1 for receiving the first timing control signal.

IN some embodiments, the shift register unit is configured to delay the signal received from the signal input terminal IN under the control of the first timing control signal and the second timing control signal, and the processed signal is output by the signal output terminal Gout, and the signal is output to the display area 11 or the signal input terminal IN of the next stage of shift register unit as the scan signal.

In some embodiments, referring to fig. 5 to 10, fig. 6 illustrates waveforms of the shift register unit shown in fig. 5 in operation; FIG. 7 is a schematic diagram showing the on state of the shift register unit at stage t1 in FIG. 6; FIG. 8 is a schematic diagram showing the on state of the shift register unit at stage t2 in FIG. 6; FIG. 9 is a schematic diagram showing the on state of the shift register unit at stage t3 in FIG. 6; fig. 10 shows a schematic diagram of the on state of the shift register unit at stage t4 in fig. 6.

As shown IN fig. 5, the shift register unit of the present invention includes 13 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Gout, a first timing control terminal c1 and a second timing control terminal c2. The first transistor T1 has a first pole connected to the signal input terminal IN, a second pole connected to the second node n2, and a gate connected to the second timing control terminal c2. The second transistor T2 has a second electrode connected to the second node n2 and a gate electrode connected to the first node n1. The third transistor T3 has a first pole connected to the first power supply VDD, a second pole connected to the first pole of the second transistor T2, and a gate connected to the first timing control terminal c1. The first pole of the fourth transistor T4 is connected to the second power VEE, the second pole is connected to the fourth node n4, and the gate is connected to the second timing control terminal c2. The first pole of the fifth transistor T5 is connected to the second timing control terminal c2, the second pole is connected to the first node n1, and the gate is connected to the second node n2. The first pole of the sixth transistor T6 is connected to the second node n2, the second pole is connected to the fifth node n5, and the gate is connected to the second power source VEE. The seventh transistor T7 has a first pole connected to the first power supply VDD, a second pole connected to the signal output terminal Gout, and a gate connected to the first node n1. The eighth transistor T8 has a first pole connected to the signal output terminal Gout, a second pole connected to the first timing control terminal c1, and a gate connected to the fifth node n5. The ninth transistor T9 has a first pole connected to the fourth node n4, a second pole connected to the first node n1, and a gate connected to the third node n3. The tenth transistor T10 has a first pole connected to the first timing control terminal c1, a second pole connected to the third node n3, and a gate connected to the signal input terminal IN. The eleventh transistor T11 has a first terminal connected to the third node n3, a second terminal connected to the second power source VEE, and a gate connected to the first timing control terminal c1. The twelfth transistor T12 has a first electrode connected to the first node n1 and a gate connected to the fourth node n4. The thirteenth transistor T13 has a first pole connected to the second pole of the twelfth transistor T12, a second pole connected to the second power VEE, and a gate connected to the first timing control terminal c1. The first pole of the first capacitor C1 is connected to the first power supply VDD, and the second pole is connected to the first node n1. The first pole of the second capacitor C2 is connected to the fifth node n5, and the second pole is connected to the signal output terminal Gout. The first pole of the third capacitor C3 is connected to the fourth node n4, and the second pole is connected to the third node n3. The first power supply VDD provides a positive voltage signal and the second power supply VEE provides a negative voltage signal.

In this embodiment, the first transistor T1 to the thirteenth transistor T13 are P-type MOS transistors. The control end of the PMOS transistor is a grid electrode, the first electrode is a source electrode, the second electrode is a drain electrode, or the first electrode is a drain electrode, and the second electrode is a source electrode. The PMOS transistor has a low on level and a high off level. In other embodiments, those skilled in the art can easily understand that the shift register unit provided by the present invention can be easily changed into an N-type MOS transistor. Alternatively, the shift register unit provided by the invention can be easily changed into a CMOS transistor or the like.

In the present embodiment, referring to fig. 6, 4 processes are included in the waveform diagram shown in fig. 6: t1, t2, t3 and t4. The output signal of the signal output terminal Gout of the above-described shift register unit completes one set-to-reset process in these 4 processes. For convenience of understanding, the high level signal "H" is shown in the drawing, and the low level signal is shown as "L". The relationship between the inputs and outputs of the shift register units in the above 4 processes is analyzed by combining the waveform diagram of fig. 6 and the circuit diagram of fig. 5 as follows:

IN the present embodiment, referring to fig. 6 and 7, IN the process of t1, the signal input terminal IN inputs a low level, the first timing control signal line CKV1 inputs a high level, and the second timing control signal line CKV2 inputs a low level. At this time, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, and the twelfth transistor T12 are turned on, and the third transistor T3, the ninth transistor T9, the eleventh transistor T11, and the thirteenth transistor T13 are turned off. Specifically, due to the low level of the signal input terminal IN, the second timing control signal line CKV2, and the second power supply VEE, the first transistor T1, the fourth transistor T4, the sixth transistor T6, and the tenth transistor T10 are turned on, the second node n2 is written with the low level by the signal input terminal IN through the first transistor T1, the fifth transistor T5 is turned on, the first node n1 is written with the low level by the second timing control signal line CKV2 through the fifth transistor T5, the seventh transistor T7 is turned on, and the eighth transistor T8 is turned on through the sixth transistor T6. Finally, the signal output terminal Gout outputs the high potential of the first power VDD and the first timing control signal line CKV 1.

IN the present embodiment, referring to fig. 6 and 8, IN the process of t2, the signal input terminal IN inputs a high level, the first timing control signal line CKV1 inputs a low level, and the second timing control signal line CKV2 inputs a high level. At this time, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the thirteenth transistor T13 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the tenth transistor T10, and the twelfth transistor T12 are turned off. Specifically, the eleventh transistor T11 is turned on by the low level of the first timing control signal line CKV1, the ninth transistor T9 is turned on through the eleventh transistor T11, the high level of the second timing control signal line CKV2 is refreshed to the high level through the fifth transistor T5, the seventh transistor T7 is turned off, the second node n2 maintains the low level at the previous time, and the eighth transistor T8 is turned on. Finally, the signal output terminal Gout outputs the low potential of the second timing control signal line CKV2.

IN the present embodiment, referring to fig. 6 and 9, IN the process of t3, the signal input terminal IN inputs a high level, the first timing control signal line CKV1 inputs a high level, and the second timing control signal line CKV2 inputs a low level. At this time, the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the twelfth transistor T12 are turned on, and the third transistor T3, the fifth transistor T5, the eighth transistor T8, the tenth transistor T10, the eleventh transistor T11, and the thirteenth transistor T13 are turned off. Specifically, the first transistor T1 and the fourth transistor T4 are turned on by the second timing control signal line CKV2, the first node n1 is refreshed to a low level by the second power VEE through the ninth transistor T9 and the fourth transistor T4, the seventh transistor T7 is turned on, the second node n2 is refreshed to a high level by the signal input terminal IN through the first transistor T1, the fifth transistor T5 is turned off, and the eighth transistor T8 is also turned off through the sixth transistor T6. Finally, the signal output terminal Gout outputs the high potential of the first power supply VDD through the seventh transistor T7.

IN the present embodiment, referring to fig. 6 and 10, IN the process of t4, the signal input terminal IN inputs a high level, the first timing control signal line CKV1 inputs a low level, and the second timing control signal line CKV2 inputs a high level. At this time, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are turned on, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, and the tenth transistor T10 are turned off. Specifically, the third transistor T3, the eleventh transistor T11, and the thirteenth transistor T13 are turned on by the first timing control signal line CKV1, the first transistor T1 and the fourth transistor T4 are turned off by the second timing control signal line CKV2, the ninth transistor T9 and the twelfth transistor T12 maintain the on state at the previous time through the third capacitor C3, the first node n1 is continuously written with the low level by the second power VEE through the twelfth transistor T12 and the thirteenth transistor T13, the second transistor T2 and the seventh transistor T7 are turned on, the second node n2 is continuously written with the high level by the first power VDD through the third transistor T3 and the second transistor T2, and the eighth transistor T8 is turned off. Finally, the final signal output terminal Gout outputs the high potential of the first power supply VDD through the seventh transistor T7.

The shift register unit repeats the processes from t3 to t4 IN the working steps after t4 until the next frame starts to display, and the start pulse signal STV or the signal input terminal IN inputs a low potential to reenter the next round of t 1.

In this embodiment, the relationship between the input and output of the shift register unit is: if the start pulse signal STV or the signal input terminal IN is at a low level IN a certain process, the signal output terminal Gout outputs a low level IN a next process by the first and second timing control signal lines CKV1 and CKV2. IN other processes, the start pulse signal STV or the signal input terminal IN and the signal output terminal Gout are maintained at the high level until the start pulse signal STV or the signal input terminal IN inputs the low level again, and the signal output terminal Gout outputs the low level again. The shift register unit delays the low-level signal from the start pulse signal STV or the signal input terminal IN and outputs the delayed low-level signal from the signal output terminal Gout.

In this embodiment, the 13T3C circuit of the shift register unit adds the thirteenth transistor T13 and changes part of the routing configuration, thereby solving the problem of mutual drag influence between the fifth transistor T5 and the sixth transistor T6, ensuring the correctness of the output waveform, making the scanning circuit more stable, avoiding abnormal display phenomenon caused by fluctuation of the aspect ratio of the transistors due to deviation of the threshold voltage or manufacturing process error, and prolonging the service life of the display panel; the problem of electric floating of the second node n2 is also guaranteed, and the reliability of the display panel is improved.

Based on the same inventive concept, the embodiment of the present invention also provides a display device, including the display panel 10 provided by the embodiment of the present invention. The display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The implementation of the display device can be referred to the embodiment of the display panel 10, and the repetition is not repeated.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims

1. A scan driving circuit comprising a plurality of stages of shift register units, the shift register units comprising:

2. The scan driving circuit according to claim 1, further comprising a timing controller including a first timing control signal line and a second timing control signal line.

3. The scan driving circuit according to claim 2, wherein the first timing control signal line is configured to output a first timing control signal; the second timing control signal line is used for outputting a second timing control signal.

4. The scan driving circuit according to claim 3, wherein the first timing control signal and the second timing control signal are square wave signals having the same output frequency and 180 ° phase difference.

5. A scan driving circuit according to claim 3, wherein said shift register unit is adapted to delay the signal received from said signal input terminal under the control of said first timing control signal and said second timing control signal, the processed signal being outputted from said signal output terminal.

6. The scan driving circuit according to claim 2, wherein the shift register unit at the previous stage outputs a scan signal to the shift register unit at the next stage, and the shift register unit at the last stage outputs a scan signal.

7. The scan driving circuit according to claim 6, wherein in the shift register cells of odd-numbered stages, the first timing control terminal is connected to the first timing control signal line, and the second timing control terminal is connected to the second timing control signal line.

8. The scan driving circuit according to claim 7, wherein in the shift register cells of even-numbered stages, the first timing control terminal is connected to the second timing control signal line, and the second timing control terminal is connected to the first timing control signal line.

9. The scan driving circuit according to claim 1, wherein the first transistor to the thirteenth transistor are P-type MOS transistors.

10. A display panel comprising the scan driving circuit according to any one of claims 1 to 9.