CN116955262A

CN116955262A - IP core of 8B/10B codec based on FPGA

Info

Publication number: CN116955262A
Application number: CN202310872893.8A
Authority: CN
Inventors: 周莉; 周爽; 朱岩
Original assignee: National Space Science Center of CAS
Current assignee: National Space Science Center of CAS
Priority date: 2023-07-17
Filing date: 2023-07-17
Publication date: 2023-10-27

Abstract

The invention discloses an IP core of 8B/10B encoding and decoding based on FPGA, which is used for interconnection communication between electronic devices on a spacecraft, and comprises: the coding unit is used for carrying out clock matching on the received data packet under the control of a clock, respectively coding and parallel-serial converting control characters and data characters in the data packet according to coding rules, and then entering the decoding unit; the decoding unit is used for sampling the received serial data under the control of the clock, recovering the clock and the data signal, detecting the synchronous code after serial-parallel conversion, respectively decoding the control character and the data character, outputting the decoded control character and the decoded data character, and judging the validity of the data and the correctness of the link transmission. The IP core is realized based on logic, has the advantages of less resource occupation, high portability, high flexibility, simple structure and easy development, meets the reliability requirement of data transmission of the aerospace equipment, and can obviously improve the transmission rate.

Description

IP core of 8B/10B codec based on FPGA

Technical Field

The invention relates to the technical field of aviation data communication, in particular to an 8B/10B codec IP core based on an FPGA.

Background

The satellite-borne data bus technology is a key technology for realizing acquisition, transmission, sharing and processing of information on a satellite, is honored as a neural center of a spacecraft, and is an important key technology and supporting technology for space model tasks.

At present, high-speed data transmission of interconnection communication between electronic devices on spacecrafts in China is mainly based on a serial bus based on an RS422 level and an LVDS level in a point-to-point mode. The conventional design adopts a three-wire system to respectively transmit clock signals, enable signals and data signals, and one path of LVDS requires 6 cables, so that the transmitting weight and the cost of the satellite are increased. The 8B/10B coding technology is adopted to combine and transmit the data and the clock, so that the number of cables in the process of point-to-point high-speed data transmission can be effectively reduced. The 8B/10B coding technology can effectively solve the problem of clock and data jitter generated in the transmission process, and improves the transmission efficiency. In addition, the 8B/10B coding technology also has the functions of direct current balance, high conversion density and redundancy error detection, and a series of advantages lead the technology to be widely applied.

The 8B/10B coding technology realizes the mutual conversion of 8bit data and 10bit data, and the transmission data can be divided into two types: data characters and control characters. The data character indicates that the character to be transmitted is data information, the control character indicates that the character to be transmitted is control information, and the control character has the functions of establishing byte synchronization, indicating the start and the end of a data packet and the like.

There are two main methods for implementing 8B/10B codec based on FPGA. One is a lookup table-based method, which stores all possible mapping relations between data into a memory according to coding rules, and when data to be coded is input, coding and decoding can be directly completed according to the stored mapping relations. The method has simple logic and easy development, but occupies too much memory resources, increases the power consumption of the system to a certain extent, and limits the working speed of the system. Another method is to implement the mapping relation of the encoding and decoding by using logic operation based on the logic relation. This approach reduces the occupation of resources, but is complex in logic, which also increases circuit power consumption.

Clock data recovery (Clock and Data Recovery, CDR) is the most important link of an 8B/10B decoding module, and the topology of the CDR mainly comprises three methods: a CDR based on feedback phase tracking, an oversampled CDR based on no feedback, and a CDR based on burst mode. CDRs based on feedback phase tracking are not suitable for FPGA design. The oversampling method can be divided into two methods according to the difference of sampling clocks, one is a time domain oversampling method and the other is a spatial oversampling method. The time domain oversampling method directly adopts an n-frequency clock for data transmission to oversample the data, and in the 8B/10B decoding technology based on single-wire LVDS, the clock and the data are recovered mainly by adopting a 5-frequency oversampling method.

The current implementation of 8B/10B encoding and decoding aiming at LVDS is mainly based on an 8B/10B encoding and decoding IP core of an FPGA or additionally provided with a serial/deserializing chip, a driving chip and an equalizing chip. The former is limited by copyright, has the defects of non-portability, opaque codes, high resource occupation and the like, and is subjected to a plurality of constraints when being applied to aerospace task engineering. The latter requires hardware circuitry that adds multiple chips, increasing circuit board area and cost.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides an IP core of 8B/10B encoding and decoding based on FPGA.

In order to achieve the above object, the present invention proposes an IP core for 8B/10B codec based on FPGA, for interconnection communication between electronic devices on a spacecraft, the IP core comprising:

the coding unit is used for carrying out clock matching on the received data packet under the control of a clock, respectively coding and parallel-serial converting control characters and data characters in the data packet according to coding rules, and then entering the decoding unit;

the decoding unit is used for sampling the received serial data under the control of the clock, recovering the clock and the data signal, detecting the synchronous code after serial-parallel conversion, respectively decoding the control character and the data character, outputting the decoded control character and the decoded data character, and judging the validity of the data and the correctness of the link transmission.

Preferably, the encoding unit includes: a transmitting end input interface, a transmitting end clock module, an 8B/10B coding module and a parallel-serial conversion module, wherein,

the transmitting end input interface is used for receiving the data packet to be transmitted, performing clock matching on the data packet, and then sending the data packet to the encoding module;

the sending end clock module is used for generating a clock according to the input of an external crystal oscillator, and the clock frequency is consistent with the 8B/10B transmission rate;

the 8B/10B coding module is used for realizing coding of control characters and data characters from 8 bits to 10 bits according to coding rules;

the parallel-serial conversion module is used for converting the parallel signals into serial signals and outputting the serial signals through an LVDS interface.

Preferably, the transmitting-end input interface includes: an AXIS slave interface, a synchronous code input interface, an enabling interface and a reset interface; the AXIS slave interface receives a data packet to be sent according to an AXIS protocol, realizes time sequence matching, and transmits the data packet to an 8B/10B coding module in a form of synchronous codes and data packet bytes; for the synchronous codes, the number of the synchronous codes and the transmission packet length, a user can configure through a configuration register, the transmission packet length is within 1024 bytes, more than 16 synchronous codes are transmitted among data packets, and the synchronous codes are transmitted by default when a bus is idle.

Preferably, the processing procedure of the 8B/10B coding module comprises the following steps:

when the character to be encoded is a data character, firstly performing 5B/6B encoding, realizing 6B encoding output according to the low 2 bits of the last byte 4B encoding, the input RD polarity state and the mapping relation, and sequentially reducing the priority; 3B/4B coding is carried out, 4B coding output is realized according to the low 3 bits of the byte 6B coding, the input RD polarity state and the mapping relation, and the priority is reduced in sequence;

when the character to be coded is a control character, 10B coding output is realized according to the input RD polarity state and the mapping relation, and the priority is reduced in sequence.

Preferably, the 8B/10B encoding module records the polarity state by using a 2bit register according to the polarity state replacement principle and the direct current balance requirement during encoding, wherein ' 00 ' represents the current state balance, ' 01 ' represents the current state as RD-, -11 ' represents the current state as RD+; when the polarity state replacement is contrary to the encoding DC balance requirement, the problems of continuous 5 or more '0' or '1' are preferably solved, and the problems are recorded, and the polarity compensation is performed in the following encoding process.

Preferably, the decoding unit includes: a receiving end clock module, a clock and data recovery module, a serial-parallel conversion module, a synchronous code detection module, a 10B/8B decoding module and a receiving end output interface, wherein,

the receiving end clock module is used for generating the same-frequency four-phase clock according to the input of the external crystal oscillator: 0 °, 90 °, 180 °, 270 °, clock frequency is consistent with 8B/10B transmission rate;

the clock and data recovery module is used for sampling and processing the received coded signals and recovering clock and data signals therefrom; the method is also used for eliminating the deviation of the sampling clock and accumulated errors generated by jitter by adopting a method of repositioning the optimal sampling phase when receiving the control word mark sent by the 10B/8B decoding module;

the serial-parallel conversion module is used for carrying out serial-parallel conversion on the recovered data signals;

the synchronous code detection module is used for detecting the boundary starting end of the data signal after serial-parallel conversion and aligning the data;

the 10B/8B decoding module is used for receiving the data packets, realizing the decoding of control characters and data characters from 10 bits to 8 bits according to a decoding rule, and generating a control word mark when the receiving of each data packet is finished and transmitting the control word mark to the clock and data recovery module;

the receiving end output interface is used for outputting the decoded control character and the data character, giving out valid marks and error mark signals, and further judging the validity of the received data and the correctness of link transmission.

Preferably, the processing procedure of the clock and data recovery module specifically includes:

based on the same-frequency multi-phase over-sampling method, the four-phase clock is utilized to sample the received data, and the optimal phase is judged as the recovered clock through the synchronous code so as to recover the data.

Preferably, the synchronous code detection submodule and the shift submodule; wherein,,

the synchronous code detection submodule registers 2 groups of 10bit data firstly, detects whether the 10bit code of the synchronous code is contained in the registered data, if yes, finds a character boundary starting end, enables a decoding flag register, enables the decoding flag bit to be effective, and positions a data boundary;

and the shift submodule performs alignment division on later received data according to positioning, so as to ensure correct decoding of the data.

Preferably, the 10B/8B decoding module performs the following processing when the decoding flag bit is valid:

step 1) judging whether the high 6-bit data of the data to be decoded is 001111 or 110000, if so, the data is a control character, and after the decoding processing of the control character, turning to step 4), otherwise turning to step 2);

step 2) judging whether the low 4-bit data of the data to be decoded is 1000 or 0111, if yes, turning to step 3); otherwise, the data is a data character, and after the decoding processing of the data character, the step 4) is carried out;

step 3) judging whether the high 6-bit data of the data to be decoded is "111010", "110110", "101110", "01110", "000101", "001001", "010001" or "100001", if yes, turning to step 4) after the data is the control character and the decoding process of the control character is performed, otherwise, turning to step 4) after the data is the data character and the decoding process of the data character is performed;

and 4) outputting decoding, and ending.

Preferably, the method comprises the steps of,

the output of the receiving end output interface comprises: outputting a decoding byte, a control character decoding error flag, a data character decoding error flag, a character valid flag, a control word flag and a data flag; wherein,,

the control character decoding error mark and the data character decoding error mark are used for judging whether the link transmission is normal or not; the control word mark or the data word mark and the character effective mark are used for judging whether the data is effective.

Compared with the prior art, the invention has the advantages that:

1. the 8B/10B encoding and decoding IP core based on the FPGA is realized based on logic, the lookup table is stored in the Verilog source file, the resource occupation is less, the portability is high, and the IP core can be transplanted into the FPGA, the ASIC or the SOC chip;

2. the 8B/10B encoding and decoding IP core interface based on the FPGA has the advantages that the design is reasonable, the configuration of clocks, synchronous codes and the like can be changed according to the requirements, the flexibility is high, and the reliability requirement of data transmission of aerospace equipment is met;

3. the 8B/10B codec IP core based on the FPGA is realized based on modularization, and the modules are high in cohesion and low in coupling, so that the method has the characteristics of simple structure and easiness in development;

4. according to the 8B/10B encoding and decoding IP core based on the FPGA, the four-phase sampling method is adopted to realize clock and data recovery, and the optimal phase is updated in real time by using the synchronous code, so that the transmission rate is not limited by the working frequency of the FPGA, and compared with the frequency oversampling method, the transmission rate can be remarkably improved.

Drawings

FIG. 1 is a schematic diagram of the structure of an IP core of the FPGA-based 8B/10B codec of the present invention;

FIG. 2 is a functional block connection schematic diagram of an IP core coding unit of the FPGA-based 8B/10B codec of the present invention;

FIG. 3 is a functional block connection diagram of an IP core decoding unit of the FPGA-based 8B/10B codec of the present invention;

FIG. 4 is a schematic diagram of an IP core input interface state machine based on FPGA 8B/10B codec of the present invention;

FIG. 5 is a schematic diagram of the data sampling of the IP core clock and data recovery module of the FPGA-based 8B/10B codec of the present invention;

FIG. 6 is a schematic diagram of the channel selection flow of the IP core 10B/8B decoding unit of the FPGA-based 8B/10B codec of the present invention.

Detailed Description

The invention provides an IP core of 8B/10B encoding and decoding based on FPGA, which is used for interconnection communication between electronic devices on a spacecraft, and comprises the following components: an encoding unit and a decoding unit.

1) The coding unit is used for carrying out clock matching on the received data packet under the control of a clock, respectively coding and parallel-serial converting control characters and data characters in the data packet according to coding rules, and then entering the decoding unit;

the encoding unit includes: a transmitting end input interface, a transmitting end clock module, an 8B/10B coding module and a parallel-serial conversion module, wherein,

The decoding unit includes: a receiving end clock module, a clock and data recovery module, a serial-parallel conversion module, a synchronous code detection module, a 10B/8B decoding module and a receiving end output interface, wherein,

the clock and data recovery module is used for sampling and processing the received coded signals and recovering clock and data signals therefrom;

the 10B/8B decoding module is used for decoding control characters and data characters according to a decoding rule, and adopting a method for repositioning an optimal sampling phase when receiving each data packet is finished to eliminate the deviation of a sampling clock and accumulated errors generated by jitter;

the receiving end output interface is used for outputting the decoded control character and the data character, giving out valid marks and error mark signals, and further judging the validity of the received data and the correctness of link transmission. The output of the receiving end output interface comprises: outputting a decoding byte, a control character decoding error flag, a data character decoding error flag, a character valid flag and a control word/data word flag; wherein,,

the control character decoding error mark and the data character decoding error mark are used for judging whether the link transmission is normal or not; the character valid flag and the control word/data word flag are used to determine whether data is valid.

The technical scheme of the invention is described in detail below with reference to the accompanying drawings and examples.

Examples

As shown in fig. 1, an IP core of an 8B/10B codec based on an FPGA includes a transmitting-end input interface (1), a transmitting-end clock module (2), an 8B/10B encoding module (3), a parallel-serial conversion module (4), a receiving-end clock module (5), a clock and data recovery module (6), a serial-parallel conversion module (7), a synchronization code detection module (8), a 10B/8B decoding module (9), and a receiving-end output interface (10); wherein,,

the transmitting end input interface (1) is connected to the 8B/10B coding module (3), the transmitting end clock module (2) is respectively connected to the 8B/10B coding module (3) and the parallel-serial conversion module (4), and the 8B/10B coding module (3) is connected to the parallel-serial conversion module (4); the receiving end clock module (5) is respectively connected to the clock and data recovery module (6), the serial-parallel conversion module (7), the synchronous code detection module (8) and the 10B/8B decoding module (9), the clock and data recovery module (6) is connected to the serial-parallel conversion module (7), the synchronous code detection module (8) is connected to the 10B/8B decoding module (9) and the receiving end output interface (10), and the 10B/8B decoding module (9) is connected to the clock and data recovery module (6).

As shown in fig. 2, an IP core coding portion of an FPGA-based 8B/10B codec includes 4 functional units of a transmitting-end input interface, a transmitting-end clock module, an 8B/10B coding module, and a parallel-serial conversion module, which functions as follows:

1. the sending end clock module generates a single-phase clock by using a clock management unit of the FPGA and is used for other functional modules, and the generated locked latch signal is used for resetting other functional modules.

2. The data packet to be sent enters the coding part from the input interface by taking bytes as units, and the input interface converts the data packet to the bytes to be coded with time sequence matching by using a state machine and outputs the bytes. The status bubble diagram is shown in fig. 4, and the steps are as follows:

step one, entering a state machine s0 initial state, and sending 1 group of synchronous codes, wherein an axi_ready signal is not enabled;

step two, entering an s1 waiting state, and counting 9 clock cycles;

step three, repeating the step one and the step two, and sending the synchronous codes with preset group numbers;

step four, entering a state machine s2 reading state, enabling an axi_ready signal when the axi_valid signal is valid, and receiving one byte of a data packet;

step five, entering an s1 waiting state, counting 9 clock cycles, wherein an axi_ready signal is not enabled;

step six, repeating the step four and the step five until the content of the data packet is read, wherein the axi_last signal is in an enabling state;

and step seven, entering a state machine s3 termination state.

3. The input interface is provided with a synchronous code register K_reg, a synchronous code length register K_length and a packet length register D_length; wherein the default synchronization code is K28.5; k_length defaults to 16, and the value is 16-255; D_Length defaults to 1024, which takes on a value of 1-16383. The user may configure according to the frame structure and transmission requirements.

4. After the coded data enters the coding module, channel selection is carried out according to the signal tk, and the coded data is judged to enter the d_encoder

5. If the character to be encoded is a data character, firstly performing 5B/6B encoding, realizing 6B encoding output according to the low 2 bits of the last byte 4B encoding, the input RD polarity state and the mapping relation, and sequentially reducing the priority; and 3B/4B encoding is carried out, 4B encoding output is realized according to the low 3 bits of the byte 6B encoding, the input RD polarity state and the mapping relation, and the priority is sequentially reduced.

6. And if the character to be encoded is a control character, realizing 10B encoding output according to the input RD polarity state and the mapping relation, and sequentially reducing the priority.

7. And the parallel-serial conversion module sequentially outputs 10B data in low order by utilizing a counter and logic right shift, and the interface is de_data.

As shown in fig. 3, an IP core decoding portion of an FPGA-based 8B/10B codec includes 6 functional units of a receiving end clock module, a clock and data recovery module, a serial-parallel conversion module, a synchronization code detection module, a 10B/8B decoding module, and a receiving end output interface, where the functions are as follows:

1. the receiving end clock module generates the same-frequency four-phase clock by using a clock management unit of the FPGA: 0 °, 90 °, 180 °, 270 °, wherein four-phase clocks are used for cdr modules, and other functional modules use only 0 ° clocks, and the generated locked latch signal is used for resetting all functional modules.

2. The cdr module realizes four times of sampling on the single-ended received signal by using four paths of clocks in one code element period, records sampling results in a register a, b, c, d, records 4 sampling results this time in a register data_reg [3:0] when the clock rising edge of 0 DEG phase of the next period arrives, registers 8 sampling results of the present period and the last period through the data_reg_w [7:0], and judges the optimal phase through the sampling results as shown in fig. 5 so as to recover data. In theory, the optimal phase of the recovered data remains unchanged, but the optimal sampling phase of the data changes due to the deviation and jitter of the sampling clock, and the optimal phase of the data is re-detected by using the synchronous code to eliminate accumulated errors. The principle of detecting the optimal phase is as follows:

when the system is in an initial state after reset, the clock signal is locked, no accumulated error occurs, the data jump edge can be directly judged according to the sampling data registered in the data_reg_w [7:0], and the optimal phase and the recovered data are given; and updating the optimal phase when the decoder_8b10b module continuously detects the synchronous code, enabling the rk_flag signal, starting counting the rk_flag_cnt, enabling the cdr module to enter a state machine for detecting the optimal sampling position, determining the current optimal sampling position according to the sampling value, and selecting the sampling value of the corresponding clock to perform serial-parallel conversion. The adjustment of the optimal sampling position requires 2 bytes of time, so the synchronization code for positioning needs to be greater than 2.

3. The serial-parallel conversion module outputs 10bit signals in parallel by using a counter and logic left shift, and the valid signal enables one clock period every output of a group of parallel signals.

4. The synchronous code detection module registers 2 groups of 10bit data at first, then enters the synchronous code detection unit to detect whether the registered 20 bit data contains the 10bit code of the synchronous code, if yes, the character boundary starting end is found, the decoding permission flag register is updated and the position is positioned, and the shift unit performs alignment division on the later received data according to the positioning and then outputs the data.

5. After the data to be decoded enters the decoder_8b10b module, the channel selection is performed after the enabled decoding flag bit is enabled, and the judgment flow is shown in fig. 6, and the judgment mode is as follows:

step one, whether the high 6 bit data is "001111" or "110000", if yes, it is the control character, enter the k_decoder unit, otherwise it is step two;

step two, whether the low 4-bit data is 1000 or 0111, if not, the data is a data character, entering a d_decoder unit, and if yes, the step three is performed;

step three, if the high 6 bits of the data are "111010", "110110", "101110", "01110", "000101", "001001", "010001", "100001", if so, the data are the control characters, the data enter the k_decoder unit, otherwise, the data are the data characters, and the data enter the d_decoder unit.

6. And generating character valid mark and error mark signals during decoding, and outputting the signals to an upper computer through an output interface. The upper layer of the user can monitor the error state at any time to ensure the reliability of data transmission, and if the error state prompts, measures such as resetting, retransmission and the like can be taken or the frame structure can be adjusted.

Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention and are not limiting. Although the present invention has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the appended claims.

Claims

1. An IP core of an FPGA-based 8B/10B codec for interconnecting communications between electronic devices on a spacecraft, the IP core comprising:

2. The FPGA-based 8B/10B codec IP core of claim 1, wherein the encoding unit comprises: a transmitting end input interface, a transmitting end clock module, an 8B/10B coding module and a parallel-serial conversion module, wherein,

3. The FPGA-based 8B/10B codec IP core of claim 2, wherein the sender-side input interface comprises: an AXIS slave interface, a synchronous code input interface, an enabling interface and a reset interface; the AXIS slave interface receives a data packet to be sent according to an AXIS protocol, realizes time sequence matching, and transmits the data packet to an 8B/10B coding module in a form of synchronous codes and data packet bytes; for the synchronous codes, the number of the synchronous codes and the transmission packet length, a user can configure through a configuration register, the transmission packet length is within 1024 bytes, more than 16 synchronous codes are transmitted among data packets, and the synchronous codes are transmitted by default when a bus is idle.

4. The FPGA-based 8B/10B codec IP core of claim 2, wherein the processing of the 8B/10B encoding module comprises:

5. The FPGA-based 8B/10B codec IP core of claim 2, wherein the 8B/10B encoding module, when encoding, follows a polarity state replacement principle and a dc balance requirement, records a polarity state using a 2bit register, where "00" indicates a current state balance, "01" indicates that the current state is RD-, -11 "indicates that the current state is rd+; when the polarity state replacement is contrary to the encoding DC balance requirement, the problems of continuous 5 or more '0' or '1' are preferably solved, and the problems are recorded, and the polarity compensation is performed in the following encoding process.

6. The FPGA-based 8B/10B codec IP core of claim 1, wherein the decoding unit comprises: a receiving end clock module, a clock and data recovery module, a serial-parallel conversion module, a synchronous code detection module, a 10B/8B decoding module and a receiving end output interface, wherein,

7. The FPGA-based 8B/10B codec IP core of claim 6, wherein the clock and data recovery module processing specifically comprises:

8. The FPGA-based 8B/10B codec IP core of claim 6, wherein the synchronization code detection module comprises a synchronization code detection sub-module and a shift sub-module; wherein,,

9. The FPGA-based 8B/10B codec IP core of claim 6, wherein the 10B/8B decoding module performs the following when the decode flag bit is valid:

and 4) outputting decoding, and ending.

10. The FPGA-based 8B/10B codec IP core of claim 6, wherein the output of the receiving-side output interface comprises: outputting a decoding byte, a control character decoding error flag, a data character decoding error flag, a character valid flag, a control word flag and a data flag; wherein,,