CN116941249A

CN116941249A - Digital image sensor using quantizer based on single-input comparator

Info

Publication number: CN116941249A
Application number: CN202180094764.XA
Authority: CN
Inventors: 刘新桥; 蔡宗勋; 陈松
Original assignee: Meta Platforms Technologies LLC
Current assignee: Meta Platforms Technologies LLC
Priority date: 2020-12-29
Filing date: 2021-12-24
Publication date: 2023-10-24

Abstract

One example described herein includes a digital image sensor having a pixel cell with a photodiode and a quantizer circuit coupled to the pixel cell. The quantizer circuit includes a charge storage device that generates a voltage based on charge from the photodiode. The quantizer circuit further includes a single-input comparator that is switchable from a first output state to a second output state in response to a ramp signal provided by the ramp generator. The quantizer circuit further includes a memory switch that can cause a counter value from the digital counter to be stored in the digital memory in response to the single-input comparator switching from the first output state to the second output state. The counter value may be used as a digital pixel value associated with the pixel cell.

Description

Digital image sensor using quantizer based on single-input comparator

Technical Field

The present disclosure relates generally to digital pixel sensors. More particularly, the present disclosure relates to, but is not limited to, digital pixel sensors quantized using single input comparators.

Background

A typical image sensor includes an array of pixel cells. Each pixel cell may include a photodiode to sense light by converting photons into charge (e.g., electrons or holes). An analog-to-digital converter (ADC) can then convert the amount of charge generated by the photodiode array to a digital value to generate a digital image. The digital image may be transmitted from the sensor to another system for use by the other system. Examples of other systems may include a viewing system for viewing digital images, a processing system for interpreting digital images, or a compiling system for compiling a set of digital images.

Disclosure of Invention

According to a first aspect of the present disclosure, there is provided an image sensing device comprising a pixel cell comprising a photodiode configured to generate a charge in response to light. The image sensing apparatus further includes a quantizer circuit coupled to the pixel unit. The quantizer circuit includes a charge storage device configured to generate a voltage based on a charge, the charge storage device being coupled between the pixel cell and the comparator. The quantizer circuit further includes a comparator, wherein the comparator is a single-input comparator configured to switch from the first output state to the second output state in response to the ramp signal being equal to the voltage of the charge storage device. The quantizer circuit further includes a memory switch coupled to an output of the single-input comparator, the memory switch configured to cause a counter value from the digital counter to be stored in the digital memory in response to the single-input comparator switching from the first output state to the second output state. The counter value may be used as a digital pixel value corresponding to the voltage. The image sensor device further includes a ramp generator configured to transmit a ramp signal to a node located between the pixel cell and the charge storage device for switching the comparator from the first output state to the second output state.

In some embodiments, the image sensor apparatus further includes a first switch coupled between the pixel cell and the charge storage device.

In some embodiments, the image sensor device further comprises a second switch coupled between the ramp generator and the node.

In some embodiments, the image sensor device further comprises a controller configured to transmit control signals to the first switch and the second switch to operate the quantizer circuit, the control signals configured to switch the first switch and the second switch between an open state and a closed state.

In some embodiments, the image sensor device further comprises a reset switch coupled to the input of the comparator and the output of the comparator.

In some embodiments, the controller is configured to transmit a control signal to the reset switch to reset the comparator to the trip voltage level.

In some embodiments, the image sensor apparatus further comprises a voltage protection circuit coupled to another node between the charge storage device and the comparator, wherein the voltage protection circuit is configured to discharge the input voltage at the comparator in response to the voltage of the charge storage device exceeding a threshold limit.

In some embodiments, the voltage protection circuit includes a diode coupled to ground or a transistor coupled to ground.

In some embodiments, the voltage protection circuit includes a diode coupled to the power supply or a transistor coupled to the power supply.

In some embodiments, the charge storage device comprises a capacitor.

In some embodiments, the comparator is configured to generate an output voltage in the second output state, and further comprising an amplifying circuit coupled to an output of the comparator for amplifying the output voltage from the comparator to generate an amplified digital signal for transmission to the memory switch.

In some embodiments, the pixel cell is one of a plurality of pixel cells included in an image sensor device, and wherein the image sensor device is configured to operate a plurality of switches coupled between (i) the plurality of pixel cells and (ii) a quantization circuit according to a time interleaving technique to change which of the plurality of pixel cells is coupled to the quantizer circuit at different times.

According to a second aspect of the present disclosure, there is provided a method performed by an image sensor device comprising a pixel cell coupled to a quantizer circuit comprising a single-input comparator and a charge storage device coupled between the pixel cell and the single-input comparator. The method comprises the following steps: the single input comparator is reset to the trip voltage level. The method comprises the following steps: a voltage is generated at the charge storage device based on a difference between the trip voltage level and the charge output by the pixel cell. The method comprises the following steps: the ramp signal is transmitted to a node between the pixel cell and the charge storage device. The method comprises the following steps: the single-input comparator is switched from the first output state to the second output state in response to the ramp signal being equal to the voltage at the charge storage device. The method comprises the following steps: the output voltage from the single-input comparator is transferred to the memory switch based on switching the single-input comparator from the first output state to the second output state. The method comprises the following steps: in response to the memory switch receiving the output voltage from the single input comparator, a counter value from the digital counter is stored in the digital memory, the counter value being used as a digital pixel value associated with the pixel cell.

In some embodiments, the method further comprises: a control signal is transmitted by the controller to a switch coupled between the pixel cell and the charge storage device to enable the switch to cause charge generated by the photodiode of the pixel cell to be transferred to the charge storage device.

In some embodiments, the method further comprises: a control signal is transmitted by the controller to a switch coupled between the ramp generator and the node to enable the switch to cause the ramp signal generated by the ramp generator to be transmitted to the single input comparator.

In some embodiments, the method further comprises: a reset control signal is transmitted by the controller to a reset switch coupled to the input of the single input comparator and the output of the single input comparator to reset the single input comparator to the trip voltage level.

In some embodiments, the method further comprises: the input voltage at the single-input comparator is discharged by a voltage protection circuit responsive to the voltage of the charge storage device exceeding a threshold limit, the voltage protection circuit being coupled to another node between the charge storage device and the single-input comparator.

In some embodiments, the charge storage device comprises a capacitor, and wherein the voltage protection circuit comprises a diode or a transistor.

In some embodiments, the method further comprises: the output voltage from the single-input comparator is amplified by an amplifying circuit coupled to the output of the single-input comparator to generate an amplified digital signal for transmission to the memory switch.

According to a third aspect of the present disclosure, there is provided an artificial reality system including a display device for outputting an artificial reality environment and an image sensor. The image sensor includes: a pixel array configured to generate a digital image, wherein the pixel array includes a pixel cell having a photodiode configured to generate a charge in response to light. The image sensor further includes a quantizer circuit coupled to the pixel array. The quantizer circuit includes a charge storage device configured to generate a voltage based on a charge, the charge storage device being coupled between the pixel cell and the comparator. The quantizer circuit further includes a comparator, wherein the comparator is a single-input comparator configured to switch from the first output state to the second output state in response to the ramp signal being equal to the voltage of the charge storage device. The quantizer circuit further includes a memory switch coupled to an output of the single-input comparator, the memory switch configured to cause a counter value from the digital counter to be stored in the digital memory in response to the single-input comparator switching from the first output state to the second output state. The counter value may be used as a digital pixel value corresponding to the voltage. The image sensor may further include a ramp generator configured to transmit a ramp signal to a node located between the pixel cell and the charge storage device for switching the comparator from the first output state to the second output state. The artificial reality system further includes a main processor coupled to the image sensor and the display device, the main processor configured to generate artificial reality content for display on the display device based on the digital image generated using the image sensor.

These illustrative examples are mentioned not to limit or define the scope of the disclosure, but to provide examples to aid in understanding the disclosure. Illustrative examples are discussed in the detailed description, which provides further description. The advantages provided by the various examples may be further understood by examining this specification.

It will be appreciated that any feature described herein as being suitable for incorporation into one or more aspects or embodiments of the present disclosure is intended to be generalized into any and all aspects and embodiments of the present disclosure. Other aspects of the disclosure will be appreciated by those skilled in the art from the specification, claims and drawings of the disclosure. The foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the claims.

Drawings

A number of illustrative embodiments are described with reference to the following figures.

Fig. 1 illustrates an example of an image sensor and its operation in accordance with aspects of the present disclosure.

Fig. 2 illustrates an example of a quantizer and controller according to some aspects of the present disclosure.

Fig. 3 illustrates an example of a quantizer with a voltage protection circuit including a diode, according to some aspects of the present disclosure.

Fig. 4 illustrates another example of a quantizer with a voltage protection circuit including a diode in accordance with some aspects of the present disclosure.

Fig. 5 illustrates an example of a quantizer with a voltage protection circuit including transistors, according to some aspects of the present disclosure.

Fig. 6 illustrates another example of a quantizer with a voltage protection circuit including transistors, according to some aspects of the present disclosure.

Fig. 7 illustrates an example of timing of various signals according to some aspects of the present disclosure.

Fig. 8 illustrates an example of timing of discharge using a voltage protection circuit in accordance with some aspects of the present disclosure.

Fig. 9 illustrates an example of a stacked arrangement of substrates on which a quantizer may be disposed, according to some aspects of the present disclosure.

Fig. 10 illustrates an example in which circuitry of a quantizer according to some aspects of the present disclosure is disposed between multiple substrate layers in a stacked arrangement.

Fig. 11 illustrates an example in which a quantizer may be shared among a set of pixel cells in accordance with some aspects of the present disclosure.

Fig. 12 illustrates an example of an image sensor according to some aspects of the present disclosure.

Fig. 13 illustrates an example of a process performed by an image sensor in accordance with some aspects of the present disclosure.

Fig. 14 illustrates an example of a process for manufacturing an image sensor device according to some aspects of the present disclosure.

Fig. 15 illustrates an example of a process in which digital counter values are stored in digital memory, according to some aspects of the present disclosure.

For purposes of illustration only, the drawings depict some examples of the disclosure. Those skilled in the art will readily recognize from the following description that alternative examples of the illustrated structures and methods may be employed without departing from the principles or benefits of the present disclosure.

In the drawings, similar components and/or features may have the same reference numerals. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the description, the description applies to any one of the plurality of similar components having the same first reference label without regard to the second reference label.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of certain inventive embodiments. It will be apparent, however, that the various embodiments may be practiced without these specific details. The drawings and description are not intended to be limiting.

Digital image sensors ("image sensors") typically include an array of pixel cells coupled to one or more quantizer circuits ("quantizers"). Each pixel cell includes a photodiode to sense incident light by converting photons into electrical charge. The charge generated by the photodiode of each pixel cell is then provided to a quantizer to convert the charge to a digital value. These digital values are stored in memory and used to generate a digital image. The digital images may be used for various wearable applications such as object recognition and tracking, location tracking, augmented reality (augmented reality, AR), virtual Reality (VR), etc.

A conventional quantizer of a digital image sensor may be a complex arrangement of multiple components (e.g., a differential comparator and a series of transistors). The differential comparator is the following: the comparator receives two input voltages at two input pins, compares the two input voltages to each other, and switches between output states based on a difference between the two input voltages. Such a complex arrangement of components may have a relatively large footprint that occupies a relatively large amount of space on the substrate of the image sensor. In addition, the performance of a differential comparator may degrade as its supply voltage decreases. In the context of digital image sensors, the large size and performance degradation associated with conventional quantizers can be a problem, for digital image sensors, as image sensors continue to be integrated into smaller devices, smaller physical sizes and lower supply voltages are key targets.

Some examples of the present disclosure may overcome one or more of the problems described above by providing a digital image sensor with such a quantizer: the quantizer may have less space occupation than conventional quantizers and may perform better than conventional quantizers at lower supply voltages, allowing for integration of digital image sensors into smaller devices than may be possible using conventional quantizers.

As one particular example, the quantizer of the present disclosure may include a first switch, such as a transistor. The quantizer may also include a charge storage device, such as a capacitor. The first switch is located between the pixel cell and the charge storage device for electrically coupling and decoupling the pixel cell and the charge storage device. In the quantizer, the charge storage device is coupled to a single-input comparator. A single input comparator is an integrated circuit component that has only one input pin and may have one or more output pins. As used herein, the "input pin" of a comparator refers to the following integrated circuit pins: the integrated circuit pin is configured to receive an input voltage (vin_comp) for comparison with a reference voltage (Vref) to control an output voltage at the output pin. The input pins are different from other types of pins on the comparator, such as a power supply pin (Vs), a ground pin (GND), an output pin (OUT), and a control pin (e.g., a reset pin (RST)).

The single input comparator may be reset by connecting its output pin to its input pin. When the comparator is reset, it eventually reaches a steady state called a "trip point". The input/output voltage of a comparator at a trip point is an inherent characteristic of the comparator, which is determined by the internal circuitry of the comparator (e.g., the transistor of the comparator) and the supply voltage. Therefore, the trip point (Vtrip) is not controlled by the input voltage on the input pin of the comparator. Unlike other types of comparators, which may include multiple input pins for receiving multiple input voltages and comparing the input voltages to each other, the trip point serves as a threshold voltage of the comparator with which the input voltage at the input pin is compared. Thus, in a single input comparator, the trip point is used as a reference voltage (Vref).

The quantizer further comprises a second switch operable to couple the ramp generator to the quantizer. For example, the second switch may couple the ramp generator to a node in the quantizer between the pixel cell and the charge storage device and decouple the ramp generator from a node in the quantizer between the pixel cell and the charge storage device. The ramp generator may provide a ramp signal to the single input comparator when the second switch is closed. The ramp signal is an electrical signal having a linearly increasing voltage or a linearly decreasing voltage depending on the implementation.

The quantizer may be coupled to a controller that may cause the quantizer to operate as follows. The controller may operate the reset switch to reset the single input comparator to its trip point. The controller may close the first switch to connect the pixel cell to the charge storage device when the comparator operates at its trip point. Since the controller is operating at Vtrip, the charge storage device will charge to the following voltage levels: the voltage level is the difference between Vtrip and the input voltage (Vin) from the pixel cell to the quantizer circuit. This voltage level may be referred to as a "differential voltage". Storing the differential voltage in the charge storage device may be referred to as "sampling" the differential voltage. The sampled differential voltage is then provided as an input to a single-input comparator for comparison with Vtrip. If the differential voltage is less than Vtrip (which will typically be the case), the comparator will remain in the first output state.

Next, the controller may open the first switch and close the second switch to connect the ramp generator to the single input comparator. One example of a ramp generator may include a ramp voltage generator. The ramp generator provides a ramp signal that sweeps a voltage range so that an input voltage of the comparator varies with a voltage variation of the ramp signal. When the voltage of the ramp signal crosses the trip point of the comparator, the output of the comparator will flip from the first output state to the second output state. The toggling from the first output state to the second output state causes a counter value of the digital counter, synchronized with the ramp signal, to be latched into the digital memory cell. The stored counter value may be used as a digital pixel value corresponding to the charge output by the pixel cell. In this way, the charge provided by the pixel cell is converted to a digital pixel value using a quantizer.

As described above, because a single-input comparator may include fewer internal circuits, the quantizers described herein may have less footprint than conventional quantizers and thus less overall footprint than operational transconductance amplifiers (operational transconductance amplifier, OTAs) (e.g., differential comparators) used in conventional quantizers. And, although the quantizer described herein includes first and second switches for selecting which of the pixel cells and ramp signals is coupled to the comparator, the space occupied by the first and second switches is relatively negligible in the overall footprint of the quantizer. Voltage protection circuitry may also be included in the quantizer to achieve a higher input range than possible with conventional quantizers that rely on OTA, as will be explained in more detail later. Additional inverter stages or positive feedback stages may be added for further amplification and load driving, which may achieve improved gain compared to OTA. Since a single-input comparator may consume a large amount of current only near the trip point at which the comparator toggles, the amount of current that the single-input comparator consumes during other times may be very small, thereby helping to conserve power.

The above description is provided by way of example only and does not limit or define the boundaries of the subject matter. Various other examples are described herein, and variations to these examples will be understood by those skilled in the art. The advantages provided by the various examples may be further understood by examining this specification and/or by practicing one or more examples of the claimed subject matter.

Fig. 1 illustrates an example of an image sensor 100 in accordance with aspects of the present disclosure. The image sensor 100 may include an array of pixel cells (e.g., pixel cell 101) and may generate digital intensity (intensity) data corresponding to digital pixels of an image. Each pixel unit 101 may include one or more Photodiodes (PDs), an anti-blooming gate (AB) for transferring charges from the PDs to Transfer Gates (TGs) of the FDs, a reset gate (RST) for resetting a voltage at the FD to a higher level, a Source Follower (SF) that may be used as a unit gain buffer, and/or a bias transistor (VBN) that may provide a bias current to the SF, which may prevent charges from the photodiodes from overflowing to the node FD when the FD holds a signal for ADC conversion. The pixel cell 101 may also include a quantizer 107 or be coupled to the quantizer 107. The quantizer 107 may include a charge storage device 106 coupled to other circuitry 112. In some examples, quantizer 107 may be a pixel-level ADC that is accessible only by pixel cell 101. In other examples, the quantizer 107 may be accessed by multiple pixel cells, as described in more detail later.

Photodiode 102 may comprise, for example, a P-N diode, a P-I-N diode, or a pinned (pinned) diode. The photodiode 102 may generate and accumulate charge upon receiving light during an exposure period, and the amount of charge generated during the exposure period may be proportional to the intensity of the light. In some examples, the exposure period may be defined based on the timing of the AB signal.

The image sensor 100 may be coupled to an image processor 109 configured to perform one or more processing operations on digital pixel values generated by the pixel array to generate an output digital image 110. Examples of image processing operations may include filtering, feature extraction, cropping, and the like. The digital image 110 may then be transmitted to another system, such as a viewing system for viewing the digital image, a processing system for interpreting the digital image, or a compiling system for compiling a set of digital images.

An example of the quantizer 107 is shown in fig. 2. As shown, the quantizer 107 includes a charge storage device (e.g., C1). An example of a charge storage device may be a capacitor. The charge storage device is coupled to a single input comparator (Comp). Examples of single input comparators may include common source amplifiers and inverter-based amplifiers. The common source amplifier may consume quiescent current (e.g., bias current) during the entire quantization period, and thus may be less energy efficient than an inverter amplifier that may consume large current only near the trip point.

In the example shown in fig. 2, the quantizer 107 has only a single capacitor (C1) on the input side (i.e., the input side of the comparator). This may create an advantage compared to a conventional quantizer comprising a plurality of capacitors arranged in a voltage divider (voltage-divider) on the input side, since having a plurality of capacitors on the input side increases the footprint of the quantizer. Furthermore, such a voltage divider depends on the ratio between the plurality of capacitors. Because different capacitor manufacturers may produce capacitors of different quality and stability (consistency), and because of typical capacitor tolerances, the capacitor-based voltage dividers across multiple pixel cells may be slightly different from each other, which may generate gain variations that may lead to pixel uniformity problems. The quantizer 107 described herein can avoid this problem by having only a single capacitor on the input side. Of course, in other examples, quantizer 107 may also have multiple capacitors on the input side.

In the quantizer 107, a first switch (SW 1) is coupled between the pixel cell and the charge storage device. The first switch is operable to couple and decouple the pixel cell to and from the charge storage device based on a control signal from the controller 208. The second switch (SW 2) is coupled to a circuit node (N1) located between the first switch and the charge storage device. The second switch is operable to couple and decouple the ramp generator to the node based on a control signal from the controller 208. A Reset Switch (RST) is coupled between the output and the input of the comparator. The reset switch is operable to reset the comparator to a trip point (trip voltage level) based on a control signal from the controller 208. Examples of switches may include transistors or relays.

In some examples, quantizer 107 may include an output capacitor (C2) coupled between the output of the comparator and ground. The output capacitor may be a band-limited capacitor (band-limiting capacitor) that may reduce comparator noise. In some examples, the output capacitor may be implemented as a dedicated capacitor or a parasitic capacitor, depending on the size of capacitor required to achieve the target noise level.

In some examples, quantizer 107 may include output logic 210 coupled to the output of the comparator to modify the digital signal output by the comparator. Examples of output logic 210 may include an inverter or an amplifier, such as a positive feedback stage. The output logic 210 may provide further amplification and load driving, which may enable increased gain compared to conventional quantizers.

In some examples, quantizer 107 may include voltage protection circuitry 212. For example, the voltage protection circuit 212 may be coupled to a node (N2) between the charge storage device and the single input comparator. The voltage protection circuit 212 may limit the voltage at node N2 (equal to the input voltage to the comparator) to within a predefined voltage range. This can prevent excessive voltage from being supplied to the comparator, thereby preventing the comparator from malfunctioning or being damaged.

Some examples of the voltage protection circuit 212 are shown in fig. 3-6. Fig. 3 shows an example in which the voltage protection circuit 212 includes a diode between the node N2 and ground. Such a diode configuration may be used when the ramp signal is a down ramp (voltage linearly decreasing). In some examples, the diode may be a compact antenna diode. Small antenna diodes suitable for such applications may have low leakage currents and low forward bias voltages. Fig. 4 shows an example in which the voltage protection circuit 212 includes a diode between the node N2 and the voltage supply (e.g., vdd). Such a diode configuration may be used when the ramp signal is an up ramp (voltage increases linearly). Fig. 5 shows an example in which the voltage protection circuit 212 includes a diode-connected transistor between node N2 and ground. The transistor may be an N-MOSFET transistor with a gate coupled to a source. Such a transistor configuration may be used when the ramp signal is a down ramp. Fig. 6 shows an example in which the voltage protection circuit 212 includes a diode-connected transistor between the node N2 and the voltage supply. The transistor may be a P-MOSFET transistor with a drain coupled to a gate. Such a transistor configuration may be used when the ramp signal is an up ramp.

Still referring to fig. 2, the controller 208 may operate the quantizer 107 by providing control signals to various circuit components. To avoid overcomplicating fig. 2, the connections between the controller 208 and the various circuit components are represented by three large arrows. It should be appreciated that the controller 208 is electrically coupled to at least the first switch, the second switch, and the reset switch to control the operation of the first switch, the second switch, and the reset switch. The controller 208 may operate the switches according to a predefined timing, an example of which is shown in fig. 7.

As shown in fig. 7, the controller 208 may transmit a reset control signal to operate the reset switch to reset the comparator to its trip point. The reset control signal includes a HIGH level (HIGH) signal (e.g., a number 1) applied to the reset switch between times t0 and t 1. The high signal may cause the reset switch to close to electrically connect the corresponding components. The reset control signal also includes a LOW Level (LOW) signal (e.g., digital 0) applied to the reset switch for the remainder of the timing period. The low signal may cause the reset switch to open. The controller 208 may also transmit a first control signal to operate the first switch such that charge is transmitted from the pixel cell to the quantizer 107. The first control signal includes a high level signal applied to the first switch between times t0 and t 2. The high signal may close the first switch to electrically connect the corresponding components. The first control signal further includes a low level signal applied to the first switch for a remaining time of the timing period. The low level signal may cause the first switch to open. When the reset switch and the first switch are open, the controller 208 may transmit a second control signal to operate the second switch to cause a ramp signal (Vramp) to be transmitted from the ramp generator 214 to the quantizer 107. The second control signal includes a high level signal applied to the second switch from time t3 to the remaining time of the timing period. The high signal may close the second switch to electrically connect the corresponding components. When the second switch is closed, a ramp signal (Vramp) may be applied to the quantizer 107. An example of a ramp signal is also shown. As shown, the ramp signal is low between times t0 and t4, and the ramp signal switches high at t 4. Then, the ramp signal linearly decreases back to the low level between time t5 to t6, thereby scanning the voltage range from the high level to the low level.

Referring to fig. 2 and 7 together, the controller 208 may operate the quantizer 107 according to the following two-part process. First, the controller 208 may transmit a reset control signal to operate the reset switch to reset the comparator to its trip point (Vtrip). When the comparator operates at its trip point, the controller may transmit a first control signal to operate the first switch to electrically connect the pixel cell to the charge storage device such that the voltage at node N1 is equal to Vin. The voltage at node N1 may be referred to as V1. Since the controller is operating at Vtrip, the charge storage device will charge to the following voltage levels: the voltage level is the difference between V1 and Vtrip. Thus, this process samples the differential voltage. The sampled differential voltage is then provided as an input to a single-input comparator for comparison with Vtrip. If the differential voltage is less than Vtrip, the comparator will remain in the first output state. The controller may then open the reset switch and the first switch. This completes the first part of the two-part process.

Next, the controller 208 may transmit a second control signal to operate the second switch to electrically connect the ramp generator 214 to the single input comparator. Ramp generator 214 provides a ramp signal that scans the voltage range such that the voltage at node N2 varies as the voltage of the ramp signal varies. The voltage at node N2 may be referred to as V2. When V2 crosses Vtrip, the output of the comparator will flip from the first output state to the second output state, such that the output voltage from the comparator changes. The output voltage from the comparator is equal to the voltage at node N3 (which may be referred to as V3). Once the comparator switches output states, V3 may be either high or low depending on the implementation. The output voltage may then be provided to additional output logic 210 to generate a final output signal denoted "f_out" in fig. 2. The final output signal may be a high-to-low or low-to-high transition signal that may trigger a switch (SW MEM) that connects the digital counter 216 to the digital memory 204. This may cause the current counter value 202 of the digital counter 216 to be latched in the digital memory 204, which digital memory 204 may include a plurality of digital memory cells. An example of this process is shown in fig. 15, whereby a ramp signal 1502 (Vramp) and a digital counter value 1504 are incremented until ramp signal 1502 triggers a flip of the comparator output, at which point the current counter value (e.g., 60) is stored to digital memory. The stored counter value 202 may be used as a digital pixel value 206 corresponding to the charge output by the pixel cell. In this way, the quantizer 107 converts the charge provided by the pixel cell into a digital pixel value 206. The digital pixel value 206 may be one of an array of pixel values that collectively form a digital image. The above process may be repeated as needed to generate pixel values for other images.

In some examples, the input range of quantizer 107 may be derived as follows. For ease of discussion, the following variables will be used:

vramp_h: the maximum voltage of the ramp signal;

vramp_l: a minimum voltage of the ramp signal;

vin_h: the maximum voltage acceptable to the quantizer input;

vin_l: the minimum voltage acceptable to the input of the quantizer; and

vard: the input range of the quantizer is typically vadr=vin_h-vin_l.

In some cases, the ramp signal may exhibit some nonlinearity around both vin_h and vin_l. To avoid such a nonlinear region, the ramp signal range may be selected to be beyond the input signal range with a margin (margin) left at both the high and low end points. For example:

Vramp_h＝Vin_h+VADR/8 (1)

Vramp_l＝Vin_l–VADR/8 (2)

during the reset phase, in which the comparator is reset to its trip point, the voltage (V2) at node N2 will be set to Vtrip. When the first switch is turned off, vin-Vtrip will be sampled on C1. When the second switch is on and node N1 is connected to Vramp, V2 may vary as Vramp varies. The upper boundary of V2 may be:

V2_max＝Vramp_h–(Vin_l–Vtrip) (3)

V2_min＝Vramp_l–(Vin_h–Vtrip) (4)

wherein v2_max should be less than the supply voltage and v2_min should be higher than ground (i.e., electrical ground). As a specific example, if V2_max.ltoreq.1.1 volts (V) and V2_min.gtoreq.0V is a requirement for quantizer 107, then:

V2_max–V2_min＝Vramp_h–Vramp_l+Vin_h–Vin_l (5)

After substituting the formula (1) and the formula (2) into the formula (5), the result is:

V2_max–V2_min＝2*(Vin_h–Vin_l)+VADR/4＝2.25*VADR≤1.1V (6)

this may result in VADR of 0.49V.

In the above example, the upper boundary of the VADR assumes that there is no additional voltage protection circuit 212 at node N2. By including a voltage protection circuit 212, a discharge path exists when the voltage exceeds a predefined limit. However, since node N2 needs to be left floating to hold the differential voltage sampled at C1 for quantizer 107 to function properly, the added discharge path should be engaged (engage) only when the comparator has completed its comparison (meaning that the comparator toggles between output states). When v2=vtrip or vramp=vin, the comparator toggles between the output states. Thus, when the ramp signal is a down ramp, V2 may discharge at Vramp < Vin. When the ramp signal is an up ramp, V2 may discharge when Vramp > Vin. This is shown in fig. 8. The left side of fig. 8 shows the downslope signal. Point 802 is the flip point of the comparator where vramp=vin. During time frame 804, voltage V2 may discharge to prevent V2 from becoming lower than 0V. The right side of fig. 8 shows the up ramp signal. Point 806 is the flip point of the comparator where vramp=vin. During time frame 808, voltage V2 may be discharged to prevent V2 from exceeding 1.1V.

The amount and timing of the discharge performed by the voltage protection circuit 212 may be dictated by the configuration of the voltage protection circuit. Referring to fig. 5 as an example, a voltage protection circuit configuration 502 may be used with the downslope signal. With this voltage protection circuit configuration 502, the voltage V2 will be clamped at GND-Vth, where Vth is the threshold voltage of the transistor (e.g., N-MOSFET). In other words, when V2 becomes lower than GND-Vth, V2 will discharge. If stricter voltage protection is required, the source and gate of the transistor may be connected to the bias voltage Vb instead of the Ground (GND). In this configuration, voltage V2 will be clamped at Vb-Vth. Configuring the voltage protection circuit using these techniques helps to ensure that V2 does not discharge before the comparator has flipped state, which is important for the reasons described above. This is because Vtrip >0> gnd-Vth. When a diode is used for the voltage protection circuit 212 instead of a transistor (as shown in fig. 3 and 4), vth in the above calculation may be replaced with Vd (e.g., the forward bias voltage of the diode) to achieve a similar result.

In the case of downslope, a lower Vtrip may be favored because this results in a greater VADR. This relationship can be explained by the equation VADR.ltoreq.VDD-Vtrip)/1.125. For example, if vdd=1.1V and vtrip=0.3V, vadr+.0.71V can be achieved. As described above, this is greater than VADR 0.49V when the voltage protection circuit 212 is not used. For similar reasons, when using an up-slope, a higher Vtrip may be favored, as this may result in a greater VADR.

Some digital image sensors may implement correlated double sampling (correlated double sampling, CDS) to reduce noise. Correlated double sampling is a method of acquiring two samples during a pixel readout period. One spot is acquired when the pixel is in a reset state and another spot is acquired when charge has been transferred to the readout node. These two values are then used as differential signals in a further stage (e.g. quantization stage). Correlated double sampling can be achieved in two ways. The first approach involves determining the difference between two analog signals output from a pixel and quantifying the difference. This is called analog CDS, because the subtraction occurs in the analog domain. The second approach involves quantizing two analog signals output from pixels into digital values, and then subtracting the digital values from each other. This is called digital CDS because subtraction occurs in the digital domain. To implement analog CDS with quantizer 107, a capacitor divider may be provided at the input node of the comparator, as described in U.S. patent application 17/072,840. To implement digital CDS with quantizer 107, the timing shown in fig. 7 may be performed twice. Thus, the quantizer 107 described herein may be used to implement any of a variety of correlated double sampling approaches.

In some examples, the digital image sensor including quantizer 107 may be implemented using a stacked (e.g., layered) arrangement of substrates. An example of such a configuration is shown in fig. 9. As shown, the image sensor 900 may include a primary semiconductor substrate 902, the primary semiconductor substrate 902 including some of the components of the array of pixel cells (e.g., photodiodes of the pixel cells). The image sensor 900 may also include one or more secondary semiconductor substrates 906 a-906 b including processing circuitry (e.g., buffers, quantizers 107, memory, and controllers (e.g., controller 208)) for the array of pixel cells. The secondary semiconductor substrate 906a may include processing circuitry for an array of pixel cells, while the secondary semiconductor substrate 906b may include a controller.

In some examples, the primary semiconductor substrate 902 and the one or more secondary semiconductor substrates 906 may form a stack in a vertical direction (e.g., represented by a z-axis) with vertical interconnects 904 and 908 to provide electrical connection between the substrates. Such an arrangement can reduce the wiring distance of the electrical connection between the pixel cell array, the processing circuit, and the controller, which can increase the transfer speed of data (especially pixel data) from the pixel cell array to other components, and reduce the power required for transfer.

Fig. 10 shows an example in which the circuitry of quantizer 107 is disposed between multiple substrate layers in a stacked arrangement (as described above with reference to fig. 9). The circuit 1002 may be disposed on a primary semiconductor substrate 902 to form a first portion of a pixel cell in a pixel array. The circuit 1004 may be located on one or more of the secondary semiconductor substrates 906 a-906 b to form a second portion of the pixel cell (e.g., a quantizer of the pixel cell). The digital counter 216 and the ramp generator 214 may be located external to the pixel array and shared among a plurality of pixels of the pixel array.

To further reduce the pixel size, in some examples, quantizer 107 may be shared among a set of pixel units. Fig. 11 shows an example of such an arrangement. As shown, there is a set of pixel cells 1102a through 1102n. The first switch (SW 1) is replaced by a plurality of switches sw1_1, sw1_2, … … sw1_n. Each of these switches connects the corresponding pixel cell to the same quantizer 107 and may be operated by the controller in the manner described above. The quantization of the signals from the plurality of pixel units may be time interleaved.

Fig. 12 illustrates additional components of the image sensor 100 according to some aspects of the present disclosure. As shown, the image sensor 100 includes a plurality of pixel units 101, such as pixel units 101a0 to 101a3, 101a4 to 101a7, 101b0 to 101b3, or 101b4 to 101b7, arranged in rows and columns. Each pixel cell may include one or more photodiodes. The image sensor 100 also includes quantization circuits 1220 (e.g., quantization circuits 1220a0, 1220a1, 1220b0, 1220b 1), which may be similar to the quantizer 107 described above. In some examples, quantization circuit 1220 may include processing circuit 1214 and memory 1216. Memory 1216 may be similar to digital memory 204 of fig. 2.

As shown, a block of four pixel cells may share a block-level quantization circuit 1220 via a multiplexer, which may include a block-level ADC (e.g., quantizer 107) and a block-level memory 1216. Each pixel cell may in turn be coupled to quantization circuit 1220 to quantize the charge. For example, the pixel units 101a0 to 101a3 share the quantization circuit 1220a0, the pixel units 101a4 to 101a7 share the quantization circuit 1221a1, the pixel units 101b0 to 101b3 share the quantization circuit 1220b0, and the pixel units 101b4 to 101b7 share the quantization circuit 1220b1. In other examples, each pixel cell may have its own dedicated quantization circuit.

The image sensor 100 also includes other circuitry such as a counter 1240 and a digital-to-analog converter (DAC) 1242. Counter 1240 may be similar to digital counter 216. The counter 1240 may be configured as a digital ramp circuit for providing a count value to the memory 1216. The count value may also be provided to DAC 1242 to generate an analog ramp, which may be provided to quantizer 1207 to perform a quantization operation. Thus, in some examples, counter 1240 and DAC 1242 may collectively function as a ramp generator.

The image sensor 100 also includes a buffer network 1230, which includes buffers 1230a through 1230d. The buffers 1230 a-1230 d may distribute digital and analog ramp signals representing counter values to the processing circuits 1214 of different blocks of pixel cells such that each processing circuit 1214 receives the same analog ramp voltage and the same digital counter value at any given time. This may help ensure that any differences in the digital values output by the different pixel cells are due to differences in the intensity of light received by the pixel cells, rather than due to mismatch of the digital ramp signal/counter value and the analog ramp signal received by the pixel cells.

Image data from the image sensor 100 may be transferred to a host processor to support different applications, such as an application for identifying and tracking objects in an image or an application for performing depth sensing of objects in an image. Examples of a host processor may include a Field-programmable gate array (Field-Programmable Gate Array, FPGA), an application-specific integrated circuit (ASIC), a microprocessor, a microcontroller, or a combination thereof. In some examples, the host processor may be part of an artificial reality system that may utilize images generated by the image sensor 100. Artificial reality is a form of reality that has been somehow adjusted before being presented to a user, which may include, for example, virtual Reality (VR), augmented Reality (AR), mixed Reality (MR), mixed reality (hybrid reality), or some combination and/or derivative thereof. The artificial reality content may include entirely generated content, or generated content combined with captured (e.g., real world) content. The artificial reality content may include video, audio, haptic feedback, or some combination thereof, any of which may be presented in a single channel or multiple channels (e.g., stereoscopic video generating three-dimensional effects to a viewer). Further, in some embodiments, the artificial reality may also be associated with the following applications, products, accessories, services, or some combination thereof: these applications, products, accessories, services, or some combination thereof are used, for example, to create content in and/or otherwise use in artificial reality (e.g., perform activities in artificial reality). The artificial reality system providing artificial reality content may be implemented on a variety of platforms including a head-mounted display (HMD) connected to a host computer system, a standalone HMD, a mobile device or computing system, or any other hardware platform capable of providing artificial reality content to one or more viewers. The artificial reality system may include a display device, such as a liquid crystal display (liquid crystal display, LCD) or a light-emitting diode (LED) display, for displaying augmented reality content to a user.

Fig. 13 is a flowchart of an example of a process implemented by the image sensor 100 according to some aspects of the present disclosure. Although fig. 13 illustrates a particular number of operations and order of operations, other examples contemplated herein may include more operations, fewer operations, different operations, or a different order of operations than that illustrated in fig. 13. The following steps are discussed with reference to the above components.

At block 1302, the image sensor 100 transmits a reset control signal to a reset switch (e.g., RST) of the quantizer 107. The controller 208 that is part of the quantizer 107, or the controller 208 coupled to the quantizer 107, may transmit a reset control signal.

At block 1304, the image sensor 100 resets a single-input comparator (e.g., comp) of the quantizer 107 to a trip level in response to a reset control signal.

At block 1306, the image sensor 100 transmits a first control signal to a first switch (e.g., SW 1) of the quantizer 107. The controller 208 may transmit the first control signal. The first control signal may enable the pixel cell to be electrically connected to a charge storage device (e.g., C1) of the quantizer 107.

At block 1308, the image sensor 100 samples the voltage difference onto the charge storage device of the quantizer 107. The voltage difference may be a difference between an input voltage (e.g., vin) from the pixel cell and the transition level.

At block 1310, the image sensor 100 transmits a second control signal to a second switch (e.g., SW 2) of the quantizer 107. The controller 208 may transmit a second control signal. The second control signal may cause the ramp generator to be electrically connected to the quantizer 107.

At block 1312, the image sensor 100 provides a ramp signal from a ramp generator to the quantizer 107.

At block 1314, the image sensor 100 switches the single-input comparator from the first output state to the second output state based on the ramp signal.

At block 1316, the image sensor 100 generates an output voltage (e.g., V3) at the single input comparator when the comparator is in the second output state. That is, the single input comparator may generate the output voltage when it is in the second output state. The output voltage may then be transferred from the single input comparator.

At block 1318, image sensor 100 amplifies the output voltage using an amplification circuit (e.g., output logic 210) to generate an amplified digital signal. In some examples, the image sensor 100 may apply other techniques to smooth, filter, or otherwise modify the output voltage from the comparator using the output logic 210.

At block 1320, the image sensor 100 stores the counter value 202 of the digital counter 216 in the digital memory 204. The counter value 202 may be used as a digital pixel value that may represent the charge output by the pixel cell. In response to the memory switch (sw_mem) changing state, the counter value 202 will be stored in the digital memory 204. The memory switch may change state based on an output voltage (e.g., an amplified digital signal) from the single input comparator.

At block 1322, the image sensor 100 discharges an input voltage (e.g., V2) at the comparator using the voltage protection circuit 212 coupled to the quantizer 107. The voltage protection circuit 212 may be part of the quantizer 107 or electrically coupled to the quantizer 107. Discharging the input voltages may involve dissipating at least some of the input voltages to ground.

Fig. 14 is a flowchart of an example of a process for manufacturing the image sensor 100, according to some aspects of the present disclosure. Although fig. 14 illustrates a particular number of operations and order of operations, other examples contemplated herein may include more operations, fewer operations, different operations, or a different order of operations than that illustrated in fig. 14. The following steps are discussed with reference to the above components.

At block 1402, the manufacturer provides a first switch (e.g., SW 1), a second switch (e.g., SW 2), a reset switch (e.g., RST), a charge storage device (e.g., C1), and/or a comparator (e.g., comp) on one or more substrates for the quantizer 107 of the image sensor 100. This may involve attaching some or all of these components to the one or more substrates, and/or fabricating some or all of these components on the one or more substrates by various fabrication processes. The one or more substrates may be part of a printed circuit board.

At block 1404, the manufacturer electrically couples the pixel cell of the image sensor 100 to the first switch. Electrically coupling the two components together may involve electrically connecting the two components together with wires (wire) or traces (trace). These traces may be printed traces formed from copper or other conductive material.

At block 1406, the manufacturer electrically couples the first switch to the charge storage device. The manufacturer may couple the two components together such that the first switch is located between the pixel cell and the charge storage device. For example, if the first switch has two leads (leads), one lead may be electrically coupled to the pixel cell and the other lead may be electrically coupled to the charge storage device. This configuration may allow the first switch to transfer voltage from the pixel cell to the charge storage device when the first switch is in the closed state, and may prevent the first switch from transferring voltage from the pixel cell to the charge storage device when the first switch is in the open state.

At block 1408, the manufacturer electrically couples the charge storage device to the comparator. For example, the manufacturer may electrically couple the charge storage device to an input pin of the comparator. The manufacturer may couple the two components together such that the charge storage device is located between the first switch and the comparator. For example, if the charge storage device has two leads, one lead may be electrically coupled to the first switch and the other lead may be electrically coupled to the comparator.

At block 1410, the manufacturer electrically couples a reset switch between the output and the input of the comparator. For example, if the reset switch has two leads, one lead may be electrically coupled to the output pin of the comparator and the other lead may be electrically coupled to the input pin of the comparator. This configuration may allow the reset switch to transfer voltage from the output of the comparator to the input of the comparator when the reset switch is in the closed state, thereby resetting the comparator to the tripped state.

At block 1412, the manufacturer may electrically couple the second switch to a node (e.g., N2) of the quantizer 107. The node may be located between the charge storage device and the comparator.

At block 1414, the manufacturer electrically couples the voltage protection circuit to the second switch. For example, if the second switch has two leads, one lead may be electrically coupled to the node and the other lead may be electrically coupled to the voltage protection circuit. The configuration may allow the second switch to transfer voltage between the node and the voltage protection circuit when the second switch is in a closed state, and may prevent the second switch from transferring voltage from the node to the voltage protection circuit when the second switch is in an open state. Depending on the implementation, the other side of the voltage protection circuit may be electrically coupled to ground or a power supply.

At block 1416, the manufacturer electrically couples the output logic 210 to the comparator. For example, the manufacturer may electrically couple the output logic 210 to an output pin of the comparator such that the output logic 210 operates on an output voltage at the output pin of the comparator.

At block 1418, the manufacturer electrically couples a capacitor (e.g., C2) between the comparator and ground. For example, the manufacturer may electrically couple a capacitor between the output pin of the comparator and ground.

At block 1420, the manufacturer electrically couples the controller 208 of the image sensor 100 to the reset switch, the first switch, and/or the second switch.

Some portions of this specification describe embodiments of the present disclosure in terms of algorithms and symbolic representations of operations on information. These algorithmic descriptions and representations are generally used by those skilled in the data processing arts to effectively convey the substance of their work to others skilled in the art. Although these operations are described functionally, computationally, or logically, they may be understood to be implemented by computer programs or equivalent circuits, or microcode, or the like. Furthermore, it has proven convenient at times, to refer to these arrangements of operations as modules, without loss of generality. The described operations and their associated modules may be implemented in software, firmware, and/or hardware.

The steps, operations, or processes described may be performed or implemented in one or more hardware or software modules, alone or in combination with other devices. In some embodiments, the software modules are implemented with a computer program product comprising a computer readable medium containing computer program code executable by a computer processor to perform any or all of the steps, operations, or processes described.

Embodiments of the present disclosure may also relate to an apparatus for performing the described operations. The apparatus may be specially constructed for the required purposes, and/or the apparatus may comprise a general purpose computing device selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a non-transitory, tangible computer readable storage medium, or any type of medium suitable for storing electronic instructions, which may be coupled to a computer system bus. Furthermore, any of the computing systems mentioned in the specification may include a single processor, or may be an architecture employing multiple processor designs to increase computing capability.

Embodiments of the present disclosure may also relate to products generated by the computing processes described herein. Such an article of manufacture may comprise information generated by a computing process, wherein the information is stored on a non-transitory, tangible computer-readable storage medium, and may comprise any embodiment of a computer program product or other data combination described herein.

The terminology used in the description is chosen primarily for the purpose of readability and instructional purposes, and may not have been selected to interpret or limit the subject matter of the invention. Thus, the scope of the disclosure is not intended to be limited by the specific embodiments, but rather by any claims presented on the basis of the application herein. Accordingly, the disclosure of the various embodiments is intended to be illustrative, but not limiting, of the scope of the disclosure, which is set forth in the following claims.

Claims

1. An image sensor device, comprising:

a pixel cell comprising a photodiode configured to generate a charge in response to light;

a quantizer circuit coupled to the pixel cell, the quantizer circuit comprising:

A charge storage device configured to generate a voltage based on the charge, the charge storage device coupled between the pixel cell and a comparator;

the comparator, wherein the comparator is a single-input comparator configured to switch from a first output state to a second output state in response to a ramp signal equal to the voltage of the charge storage device; and

a memory switch coupled to an output of the single-input comparator, the memory switch configured to cause a counter value from a digital counter to be stored in a digital memory, the counter value being used as a digital pixel value corresponding to the voltage, in response to the single-input comparator switching from the first output state to the second output state; and

a ramp generator configured to transmit the ramp signal to a node located between the pixel cell and the charge storage device for switching the comparator from the first output state to the second output state.

2. The image sensor apparatus of claim 1, further comprising a first switch coupled between the pixel cell and the charge storage device; and preferably the image sensor device further comprises a second switch coupled between the ramp generator and the node.

3. The image sensor device of any preceding claim, a controller configured to transmit control signals to the first and second switches to operate the quantizer circuit, the control signals being configured to switch the first and second switches between an open state and a closed state.

4. The image sensor device of any preceding claim, further comprising a reset switch coupled on an input of the comparator and an output of the comparator; and preferably wherein the controller is configured to transmit a control signal to the reset switch to reset the comparator to a trip voltage level.

5. The image sensor apparatus of any preceding claim, further comprising a voltage protection circuit coupled to another node between the charge storage device and the comparator, wherein the voltage protection circuit is configured to discharge an input voltage at the comparator in response to the voltage of the charge storage device exceeding a threshold limit; and preferably wherein the voltage protection circuit comprises a diode coupled to ground or a transistor coupled to ground; or preferably wherein the voltage protection circuit comprises a diode coupled to a power supply or a transistor coupled to the power supply.

6. An image sensor apparatus as claimed in any preceding claim, wherein the charge storage device comprises a capacitor.

7. The image sensor device of any preceding claim, wherein the comparator is configured to generate an output voltage in the second output state, and further comprising an amplifying circuit coupled to an output of the comparator for amplifying the output voltage from the comparator to generate an amplified digital signal for transmission to the memory switch.

8. The image sensor device of any preceding claim, wherein the pixel cell is one of a plurality of pixel cells included in the image sensor device, and wherein the image sensor device is configured to operate a plurality of switches coupled between (i) the plurality of pixel cells and (ii) the quantization circuit according to a time interleaving technique to change which of the plurality of pixel cells is coupled to the quantizer circuit at different times.

9. A method performed by an image sensor device comprising a pixel cell coupled to a quantizer circuit, the quantizer circuit comprising a single-input comparator and a charge storage device coupled between the pixel cell and the single-input comparator, the method comprising:

Resetting the single input comparator to a trip voltage level;

generating a voltage at the charge storage device based on a difference between the trip voltage level and a charge output by the pixel cell;

transmitting a ramp signal to a node between the pixel cell and the charge storage device;

switching the single input comparator from a first output state to a second output state in response to the ramp signal being equal to the voltage at the charge storage device;

transmitting an output voltage from the single-input comparator to a memory switch based on switching the single-input comparator from the first output state to the second output state;

in response to the memory switch receiving the output voltage from the single input comparator, a counter value from a digital counter is stored to a digital memory, the counter value being used as a digital pixel value associated with the pixel cell.

10. The method of claim 9, further comprising:

a control signal is transmitted by a controller to a switch coupled between the pixel cell and the charge storage device to enable the switch to cause charge generated by a photodiode of the pixel cell to be transferred to the charge storage device.

11. The method of claim 9 or 10, further comprising:

a control signal is transmitted by a controller to a switch coupled between a ramp generator and the node to enable the switch to cause the ramp signal generated by the ramp generator to be transmitted to the single input comparator.

12. The method of any of claims 9 to 11, further comprising:

a reset control signal is transmitted by the controller to a reset switch to reset the single-input comparator to the trip voltage level, the reset switch being coupled to an input of the single-input comparator and an output of the single-input comparator.

13. The method of any of claims 9 to 12, further comprising:

discharging, by a voltage protection circuit, an input voltage at the single-input comparator in response to the voltage of the charge storage device exceeding a threshold limit, the voltage protection circuit being coupled to another node located between the charge storage device and the single-input comparator; and preferably wherein the charge storage device comprises a capacitor and wherein the voltage protection circuit comprises a diode or transistor.

14. The method of any of claims 9 to 13, further comprising:

the output voltage from the single-input comparator is amplified by an amplifying circuit coupled to an output of the single-input comparator to generate an amplified digital signal for transmission to the memory switch.

15. An artificial reality system, comprising:

the display device is used for outputting an artificial reality environment;

an image sensor, the image sensor comprising:

a pixel array configured to generate a digital image, the pixel array comprising a pixel cell having a photodiode configured to generate a charge in response to light;

a quantizer circuit coupled to the pixel array, the quantizer circuit comprising:

a charge storage device configured to generate a voltage based on charge from a pixel cell of the pixel array, the charge storage device coupled between the pixel cell and a comparator;

a ramp generator configured to transmit the ramp signal to a node located between the pixel cell and the charge storage device for switching the comparator from the first output state to the second output state; and

a main processor coupled to the image sensor and the display device, the main processor configured to generate the artificial reality environment for display on the display device based on the digital image generated using the image sensor.