CN116936527A

CN116936527A - Integrated circuit device and method of manufacturing the same

Info

Publication number: CN116936527A
Application number: CN202310468870.0A
Authority: CN
Inventors: 林晋申; 卢永峰; 甘皓天; 廖人政
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-06-28
Filing date: 2023-04-27
Publication date: 2023-10-24

Abstract

An Integrated Circuit (IC) device includes a substrate having a power control circuit, front and back side metal layers, and first and second Feed Through Vias (FTVs). The front side metal layer has first and second front side power rails. The backside metal layer has first and second backside power rails. The first FTV extends through the substrate and couples the first front side power rail to the first back side power rail. The second FTV extends through the substrate and couples the second front side power rail to the second back side power rail. The power control circuit is coupled to the first and second front side power rails and is controllable to electrically connect the first front side power rail to the second front side power rail or to electrically disconnect the first front side power rail from the second front side power rail. Embodiments of the present application also relate to methods of manufacturing integrated circuit devices.

Description

Integrated circuit device and method of manufacturing the same

Technical Field

Embodiments of the application relate to integrated circuit devices and methods of manufacturing the same.

Background

An integrated circuit ("IC") device or semiconductor device includes one or more devices represented in an IC layout (also referred to as a "layout"). The layout is hierarchical and includes modules that perform higher-level functions according to the IC design specifications. Modules are typically constructed from a combination of units, each unit representing one or more semiconductor structures configured to perform a particular function. Cells with pre-designed layout (sometimes referred to as standard cells) are stored in a standard cell library (hereinafter "library" or "cell library" for simplicity) and can be accessed by various tools, such as Electronic Design Automation (EDA) tools, to generate, optimize, and verify the design of the IC.

Minimizing power consumption of semiconductor devices is a design consideration. One method includes including header circuitry (also referred to as "headswitches") and/or footcircuits (also referred to as "footswitches") between a power supply node (or rail) and the functional circuitry. When the functional circuit is in an inactive state, power consumption may be reduced by closing the headswitch and/or footswitch.

Disclosure of Invention

According to one aspect of an embodiment of the present application, an Integrated Circuit (IC) device is provided that includes a substrate including a power control circuit and having opposing front and back sides, a front side metal layer, a back side metal layer, a first Feed Through (FTV) and a second FTV. The front side metal layer is located on the front side of the substrate and includes a first front side power rail and a second front side power rail. The backside metal layer is located on the backside of the substrate and includes a first backside power rail and a second backside power rail. The first FTV extends through the substrate and couples the first front side power rail to the first back side power rail. The second FTV extends through the substrate and couples the second front side power rail to the second back side power rail. The power control circuit is coupled to the first front side power rail and the second front side power rail and is controllable to: the first front side power rail is electrically connected to the second front side power rail or the first front side power rail is electrically disconnected from the second front side power rail.

According to another aspect of an embodiment of the present application, there is provided a method of manufacturing an Integrated Circuit (IC) device, the method comprising: the circuit is fabricated over a substrate having opposite front and back sides. The method further includes fabricating a front side redistribution structure over the front side of the substrate. The front side redistribution structure includes: a first front side power rail and a second front side power rail extending along a first axis and coupled to the circuit; a first conductive pattern protruding from the first front side power rail along a second axis transverse to the first axis; and a second conductive pattern protruding from the second front side power rail along the second axis. The method also includes fabricating a plurality of Feed Through Vias (FTVs) extending through the substrate. The plurality of FTVs includes: a first FTV coupled to the first conductive pattern; and a second FTV coupled to the second conductive pattern. The method further includes fabricating a backside redistribution structure over the backside of the substrate. The backside redistribution structure includes: a first backside power rail coupled to the first FTV; and a second backside power rail coupled to the second FTV.

According to yet another aspect of an embodiment of the present application, there is provided an Integrated Circuit (IC) device including: a substrate including a circuit and having opposite front and back sides, first and second back side power rails on the back side of the substrate, first and second front side power rails on the front side of the substrate and coupled to the circuit, and a plurality of Feed Through Via (FTV) structures. Each FTV structure comprises: a front side conductive pattern on the front side of the substrate, a back side conductive pattern on the back side of the substrate, and FTV extending through the substrate and coupling the front side conductive pattern and the back side conductive pattern. The plurality of FTV features includes: at least one first FTV structure having a front side conductive pattern coupled to the first front side power rail and a back side conductive pattern coupled to the first back side power rail, and at least one second FTV structure having a front side conductive pattern coupled to the second front side power rail and a back side conductive pattern coupled to the second back side power rail.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a block diagram of an IC device according to some embodiments.

Fig. 2 is a schematic block diagram of a circuit area of an IC device according to some embodiments.

Fig. 3 is a schematic cross-sectional view of an IC device according to some embodiments.

Fig. 4A-4B are schematic diagrams of layers in an IC device layout, according to some embodiments.

Fig. 5A-5B are schematic diagrams of IC device layout diagrams according to some embodiments.

Fig. 5C-5E are various schematic cross-sectional views in one or more functional circuit areas of one or more IC devices according to some embodiments.

Fig. 6A is a schematic diagram of an IC device layout diagram according to some embodiments.

Fig. 6B is a schematic cross-sectional view of an IC device according to some embodiments.

Fig. 6C is a schematic diagram of an IC device layout diagram according to some embodiments.

Fig. 6D is a schematic diagram of a Feed Through (FTV) cell layout according to some embodiments.

Fig. 7-9 are schematic diagrams of one or more IC device layouts according to some embodiments.

Fig. 10A-10D are schematic diagrams of various functional circuit area layouts in one or more IC devices, according to some embodiments.

Fig. 11A-11D are schematic cross-sectional views of an IC device at various stages of a fabrication process, according to some embodiments.

Fig. 12A-12C are flowcharts of various methods according to some embodiments.

FIG. 13 is a block diagram of an Electronic Design Automation (EDA) system, according to some embodiments.

Fig. 14 is a block diagram of an IC device manufacturing system and related IC manufacturing flow in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components, materials, values, steps, and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. It is contemplated that other components, materials, values, steps, arrangements or similar elements may be present. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations shown in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly. Depending on the context, source/drain may refer to source or drain individually or collectively.

In some embodiments, an IC device includes a substrate having a power control circuit. The power control circuit includes at least one of a header circuit or a footer circuit. The IC device further includes first and second front side power rails on the front side of the substrate and first and second back side power rails on the back side of the substrate. A first Feed Through (FTV) extends through the substrate and couples the first front side power rail to the first back side power rail. A second FTV extends through the substrate and couples the second front side power rail to the second back side power rail. The power control circuit is controllable to electrically connect the first front side power rail to the second front side power rail or to electrically disconnect the first front side power rail from the second front side power rail. In at least one embodiment, the described configuration allows power to be supplied from the back side (e.g., from the first back side power rail) to the front side (e.g., to the first front side power rail), wherein power is further supplied to one or more functional circuits (e.g., through the second front side power rail) when the power control circuit is in an on state, or is disconnected from one or more functional circuits when the power control circuit is in an off state. Thus, in one or more embodiments, power may be provided from the back side of the IC device, while most of the front side of the IC device is freed up for signal routing. In at least one embodiment, the FTV is configured as various units to be incorporated or added to existing power control circuit units to obtain one or more new power control circuit units capable of receiving power supply from the back side and providing power switches on the front side as described. Thus, in one or more embodiments, power control circuitry may be quickly and/or easily provided to accommodate various conditions, power requirements, IC designs, and the like. Further advantages and/or effects of one or more embodiments are described herein.

Fig. 1 is a block diagram of an IC device 100 according to some embodiments.

In fig. 1, an IC device 100 includes a macro 102 and the like. In some embodiments, macro 102 includes one or more of a memory, a power grid, one or more cells, inverters, latches, buffers, and/or any other type of circuit arrangement that may be digitally represented in a cell library. In some embodiments, macro 102 is understood in the context of an architecture hierarchy of analog modular programming, where subroutines/programs are called by a main program (or other subroutines) to perform a given computing function. In this case, the IC device 100 performs one or more given functions using the macro 102. Thus, in this case, the IC device 100 is similar to a main program, and the macro 102 is similar to a subroutine/program in terms of architecture hierarchy. In some embodiments, macro 102 is a software macro. In some embodiments, macro 102 is a hardware macro. In some embodiments, macro 102 is a software macro described digitally in a register-transfer level (RTL) code. In some embodiments, no compositing, placing, and routing has been performed on macro 102 so that software macros may be composited, placed, and routed for various process nodes. In some embodiments, macro 102 is a hardware macro that is digitally described in a binary file format (e.g., graphic database system II (GDSII) stream format), where the binary file format represents planar geometry, text labels, other information, etc., of one or more layout diagrams of macro 102 in hierarchical form. In some embodiments, compositing, placing, and routing have been performed on macro 102 such that the hardware macro is dedicated to a particular process node.

Macro 102 includes a region 104, region 104 including a functional circuit and a power control circuit as described herein. In some embodiments, region 104 includes a substrate on which circuitry is formed in front end of line (FEOL) fabrication. Further, above and/or below the substrate, the region 104 includes various metal layers stacked above and/or below the insulating layer in back-end-of-line (BEOL) fabrication. The BEOL provides a power network and/or routing for the circuitry of the IC device 100, including the macro 102 and the region 104.

Fig. 2 is a schematic block diagram of circuit areas of an IC device 200 according to some embodiments. In at least one embodiment, the circuit region in FIG. 2 corresponds to a portion of region 104 in FIG. 1.

The IC device 200 includes a power control circuit 201, the power control circuit 201 including at least one of a header circuit or a footer circuit. In the example configuration in fig. 2, the power control circuit 201 includes a header circuit 210 and a footer circuit 220. In at least one embodiment, one of the header circuit 210 or footer circuit 220 is omitted. IC device 200 also includes functional circuitry 230, functional circuitry 230 may operate by a power supply voltage from at least one of header circuitry 210 or footer circuitry 220, as described herein.

The header circuit 210 includes different types of first transistors P1 and second transistors N1. The footer circuit 220 includes a first transistor N2 and a second transistor P2 of different types. In the example configuration of fig. 2, the transistors P1, P2 are P-type transistors and the transistors N1, N2 are N-type transistors. Examples of transistors in header circuit 210 and/or footer circuit 220 include, but are not limited to, metal Oxide Semiconductor Field Effect Transistors (MOSFETs), complementary Metal Oxide Semiconductor (CMOS) transistors, P-channel metal oxide semiconductors, N-channel metal oxide semiconductors, bipolar Junction Transistors (BJTs), high voltage transistors, high frequency transistors, P-channel and/or N-channel field effect transistors (PFETs/NFETs), finfets, planar MOS transistors with raised source/drain, nanoplatelet FETs, nanowire FETs, and the like. In some embodiments, PMOS transistors are referred to as first or second type transistors and NMOS transistors are referred to as second or first type transistors.

In header circuit 210, first transistor P1 includes a first terminal 211 electrically coupled to a first power rail 231, a second terminal 212 electrically coupled to a second power rail 232, and a gate terminal 213 configured to receive control signal CS 1. The second transistor N1 includes first and second terminals 215, 216 coupled together such that the transistor N1 is electrically coupled as a pseudo transistor. In some embodiments, transistor N1 is omitted, resulting in header circuit 210 including only P-type transistors. In some embodiments, the first terminal of the transistor is a source or drain of the transistor and the second terminal of the transistor is a drain or source of the transistor. The first and second terminals of the transistor are sometimes referred to as the source/drain of the transistor.

The transistor P1 is configured to connect the power supply rails 231, 232 or disconnect the power supply rails 231, 232 to provide or cut off the power supply to the functional circuit 230 in response to the control signal CS 1. The power supply rail 23l is configured to receive a power supply voltage true VDD (hereinafter referred to as "TVDD"). The power rail 231 is sometimes referred to as a "TVDD power rail". In some embodiments, TVDD is a positive voltage generated by an external voltage source external to IC device 200. In some embodiments, TVDD is generated by an internal voltage source contained in IC device 200. When the transistor P1 is turned on by a first logic level (e.g., logic "0") of the control signal CS1, TVDD on TVDD power rail 231 is provided as a power supply voltage virtual VDD (referred to herein as "VVDD") on power rail 232 through the turned-on transistor P1. The power rail 232 is also sometimes referred to as a "VVDD power rail". When transistor P1 is turned off by a second logic level (e.g., logic "1") of control signal CS1, VVDD power rail 232 is disconnected from TVDD power rail 231, and the power supply to functional circuit 230 is disconnected. In some embodiments, when transistor P1 is off, VVDD power rail 232 is floating. In some embodiments, control signal CS1 is generated by external circuitry external to IC device 200. In some embodiments, the control signal CSl is generated by a power management circuit included in the IC device 200.

In footer circuit 220, first transistor N2 includes a first terminal 221 electrically coupled to a first power rail 235, a second terminal 222 electrically coupled to a second power rail 236, and a gate terminal 223 configured to receive control signal CS 2. The second transistor P2 includes first and second terminals 225, 226 electrically coupled together such that the transistor P2 is electrically coupled as a pseudo transistor. In some embodiments, transistor P2 is omitted, resulting in footer circuit 220 including only N-type transistors.

The transistor N2 is configured to connect the power supply rails 235, 236 or disconnect the power supply rails 235, 236 to provide or cut off the power supply to the functional circuit 230 in response to the control signal CS 2. The power supply rail 235 is configured to receive a power supply voltage true VSS (hereinafter referred to as "TVSS"). Power rail 235 is sometimes referred to as a "TVSS power rail". In some embodiments, TVSS is ground voltage. In some embodiments, TVSS is a reference voltage rather than a ground voltage. In at least one embodiment, the reference voltages other than ground are generated by external circuitry external to the IC device 200 or by internal voltage sources contained in the IC device 200. When the transistor N2 is turned on by a first logic level (e.g., logic "1") of the control signal CS2, TVSS on the TVSS power rail 235 is provided as a power supply voltage virtual VSS (hereinafter referred to as "VVSS") on the power rail 236 through the turned-on transistor N2. The power rail 236 is sometimes referred to as a "VVSS power rail". When transistor N2 is turned off by a second logic level (e.g., logic "0") of control signal CS2, VVSS power rail 236 is disconnected from TVSS power rail 235 and the power supply to functional circuit 230 is disconnected. In some embodiments, when transistor N2 is off, VVSS power rail 236 is floating. In some embodiments, control signal CS2 is generated by external circuitry external to IC device 200. In some embodiments, control signal CS2 is generated by a power management circuit included in IC device 200. In some embodiments, control signal CS2 is the same as control signal CS1. In at least one embodiment, the control signal CS2 is different from the control signal CS1.

The functional circuit 230 is configured to be operable by VVDD and VVSS on VVDD power rail 232 and VVSS power rail 236, respectively, to perform one or more functions of the IC device 200. In at least one embodiment, when a VVDD or VVSS is removed from the respective VVDD power rail 232 or VVSS power rail 236 by turning off the respective header circuit 210 or footer circuit 220, the function circuit 230 becomes inactive or disabled and ceases to perform one or more functions. Accordingly, the power consumption of the IC device 200 may be reduced when one or more functions provided by the functional circuit 230 are not required. In some embodiments, functional circuitry 230 includes one or more active devices, passive devices, logic circuits, etc. configured to operate based on VVDD and VVSS. Examples of logic circuits include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert, OR-AND-Invert, MUX, flip-flop, BUFF, latch, delay, clock, memory, AND the like. Example memory cells include, but are not limited to, static Random Access Memory (SRAM), dynamic RAM (DRAM), resistive RAM (RRAM), magnetoresistive RAM (MRAM), read Only Memory (ROM), and the like. Examples of active devices or active elements include, but are not limited to, transistors, diodes, and the like. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, resistors, and the like.

In the example configuration of fig. 2, the power control circuit includes both a header circuit 210 and a footer circuit 220, with the power supply to the functional circuit 230 being controlled (e.g., provided or turned off) by at least one of the header circuit 210 or the footer circuit 220 in accordance with a respective control signal CS1 or control signal CS 2.

In some embodiments, the power control circuitry of IC device 200 includes header circuitry 210, but footer circuitry 220 is omitted. In one example, the VVSS power rail 236 is omitted, and the functional circuit 230 is electrically coupled with the TVSS power rail 235. In another example, the VVSS power rail 236 is electrically coupled to the TVSS power rail 235 by conductors other than switches or transistors. The supply of power to the functional circuit 230 is controlled (e.g., provided or turned off) by the head circuit 210 in accordance with the control signal CS 1.

In some embodiments, the power control circuitry of IC device 200 includes footer circuitry 220, but header circuitry 210 is omitted. In the example, the VVDD power rail 232 is omitted, and the functional circuit 230 is electrically coupled with the TVDD power rail 231. In another example, the VVDD power rail 232 is electrically coupled to the TVSS power rail 235 via conductors other than switches or transistors. The power supply to the functional circuit 230 is controlled (e.g., provided or turned off) by the footer circuit 220 in accordance with the control signal CS 2.

TVDD power supply rail 231 belongs to the TVDD power supply domain of IC device 200. In some embodiments, the TVDD power domain includes a plurality of TVDD power rails, including TVDD power rail 231. The VVDD power rail 232 belongs to the VVDD power domain of the IC device 200. In some embodiments, the VVDD power domain includes a plurality of VVDD power rails, including VVDD power rail 232. In some embodiments, IC device 200 includes a plurality of header circuits, each header circuit corresponding to header circuit 210 and configured to controllably connect or disconnect TVDD power rails to or from a respective VVDD power rail.

TVSS power rail 235 belongs to the TVSS power domain of IC device 200. In some embodiments, the TVSS power domain includes a plurality of TVSS power rails 235. The VVSS power rail 236 belongs to the VVSS power domain of the IC device 100. In some embodiments, the VVSS power domain includes a plurality of VVSS power rails, including VVSS power rail 236. In some embodiments, IC device 200 includes a plurality of footer circuits, each corresponding to footer circuit 220, and configured to controllably connect or disconnect a TVSS power rail with a corresponding VVSS power rail.

Fig. 3 is a schematic cross-sectional view of an IC device 300 having a power control circuit 301 according to some embodiments. In at least one embodiment, the power control circuit 301 corresponds to the power control circuit 201. In the example configuration of fig. 3, the power supply controller circuit 301 includes a header circuit corresponding to the header circuit 210. In some embodiments, power control circuit 301 includes a footer loop corresponding to footer circuit 220, and power control circuit 301 includes a header circuit and a footer circuit. For simplicity, one or more header circuits according to some embodiments are described in detail herein. According to some embodiments, the configuration of the footer circuit is similar to the header circuit. For example, the footer circuit may be obtained by replacing TVDD, VVDD, P type, N type, and PMOS in the header circuit with TVSS, VVSS, N type, P type, and NMOS.

The power control circuit 301 (hereinafter referred to as header circuit 301) includes one or more P-type transistors coupled together to correspond to transistor P1 in fig. 2. For simplicity, one P-type transistor (e.g., PMOS transistor P31) is shown in fig. 3. The example cross-section in fig. 3 is a combination of multiple cross-sections taken along different planes that are perpendicular to each other.

IC device 300 includes a substrate 310 over which header circuit 301 and one or more functional circuits of IC device 300 are formed. The substrate 310 has a front side 311 and a back side 312 opposite to each other along a Z-axis, which coincides with the thickness direction of the substrate 310. In some embodiments, the substrate 310 is a semiconductor substrate or a dielectric substrate. Example materials for the semiconductor substrate include, but are not limited to, silicon germanium (SiGe), gallium arsenide, or other suitable semiconductor materials. Example materials for the dielectric substrate include, but are not limited to, siO or other suitable dielectric material. In some embodiments, N-type and P-type dopants are added to doped regions of substrate 310 and/or isolation structures are formed between adjacent doped regions. For example, P-type and N-type dopants are added to the substrate 310 to form P-doped and N-doped regions corresponding to active regions of PMOS and NMOS transistors, respectively. The dopant further forms an N-type well (i.e., an N-well) in which the P-doped region is formed, and/or a P-type well (i.e., a P-well) in which the N-doped region is formed. In some embodiments, isolation structures are formed between adjacent P-well/P-doped regions and N-well/N-doped regions. The isolation structures are omitted from fig. 3 for simplicity. In the example configuration in fig. 3, the substrate 310 includes P-doped regions 313, 134, the P-doped regions 313, 134 configuring the source/drain of the transistor P31 in the header circuit 301.

IC device 300 also includes a gate stack of transistors in IC device 300. For example, the gate stack of transistor P31 of header circuit 301 includes gate dielectric layers 315, 316 and gate electrode 317. In at least one embodiment, one gate dielectric layer replaces the plurality of gate dielectric layers 315, 316. Example materials for the gate dielectric layer include HfO ₂ 、ZrO ₂ Etc. Example materials for gate electrode 317 include polysilicon, metal, and the like. The gate electrode is schematically shown in the figure with the label "PO".

IC device 300 also includes a contact structure on and in electrical contact with the source/drain of the transistor in IC device 300. The contact structure is sometimes referred to as a metal-to-device (MD) contact and is schematically illustrated in the figure with the label "MD". The MD contacts include conductive material formed on respective portions (e.g., source/drain) of the respective active regions to configure electrical connection of one or more devices formed in the active regions to internal or external circuitry of the IC device. In the example configuration in fig. 3, MD contacts 318, 319 are over the source/drains 313, 314 of the transistor P31 of the header circuit 301 and are coupled to the source/drains 313, 314 of the transistor P31 of the header circuit 301.

The IC device 300 also includes conductive vias located over and in electrical contact with the corresponding gate electrodes and MD contacts. The vias above and in electrical contact with the MD contacts are sometimes referred to as through-hole-to-device (VD) vias. The via above and in electrical contact with the gate electrode is sometimes referred to as a via-to-gate (VG) via. The VD via is schematically illustrated in the figure with the label "VD". The VG through holes are schematically shown in the figure with the label "VG". In the example configuration of fig. 3, VG vias 320 and VD vias 321, 322 are above gate electrode 317 and MD contacts 318, 319, respectively, and in electrical contact with gate electrode 317 and MD contacts 318, 319. Example materials for MD contacts, VD, and VG vias include metals. Other configurations are within the scope of the various embodiments.

The IC device 300 further includes a front side redistribution structure 330 over the VD, VG vias. The front side redistribution structure 330 includes a plurality of metal layers and a plurality of via layers that are alternately arranged in the thickness direction of the substrate 310 (i.e., along the Z-axis). The front side redistribution structure 330 also includes various inter-layer dielectric (ILD) layers (not shown) having metal layers and via layers embedded therein. The metal layer and the via layer of the front side redistribution structure 330 are configured to electrically couple the various elements or circuits of the IC device 300 to each other and to external circuitry. The lowest metal layer directly above and in electrical contact with the VD, VG vias is the M0 (metal zero) layer, the next metal layer directly above the M0 layer is the M1 layer, the next metal layer directly above the M1 layer is the M2 layer, and so on. The via layer Vn is disposed between and electrically couples the Mn layer and the mn+1 layer, where n is an integer greater than zero. For example, the via zero (V0) layer is the lowermost via layer, which is disposed between the M0 layer and the M1 layer, and electrically couples the M0 layer and the M1 layer. Other via layers are V1, V2, etc. The M0 layer is the lowest metal layer above the front side 311 of the substrate 310 or the metal layer closest to the front side 311. For simplicity, the metal layer and via layer above the M1 layer are omitted from fig. 3.

In the example configuration in fig. 3, the M0 layer includes various M0 conductive patterns including a first front side power rail 331, a second front side power rail 332, and an M0 conductive pattern 333. The first front side power rail 331 is coupled to the source/drain 313 of the transistor P31 through the MD contact 318 and the VD via 321. The second front side power rail 332 is coupled to the source/drain 314 of transistor P31 through MD contact 319 and VD via 322. The M0 conductive pattern 333 is coupled to the gate electrode 317 of the transistor P31 and configured to supply a control signal corresponding to the control signal CS1 to switch the transistor P31 on and off. Although not shown, IC device 300 includes one or more dielectric layers between the M0 layer and substrate 310.

IC device 300 also includes a backside redistribution structure 340 on the backside 312 of substrate 310. The backside redistribution structure 340 includes a plurality of backside metal layers and a plurality of backside via layers that are alternately arranged in the thickness direction of the substrate 310 (i.e., along the Z-axis). The backside redistribution structure 340 further includes various inter-layer dielectric (ILD) layers (not shown) having backside metal layers and backside via layers embedded therein. The backside metal layer and backside via layer of the backside redistribution structure 340 are configured to supply power and/or signals from external circuitry to various elements or circuits of the IC device 300. The backside metal layer next to the backside 312 of the substrate 310 is the BM0 layer, the next backside metal layer is the BM1 layer, etc. The backside via layer BVn is disposed between and electrically couples the BMn layer and the bmn+1 layer, where n is an integer greater than zero. For example, the via layer BV0 is a backside via layer disposed between the BM0 layer and the BM1 layer, and electrically couples the BM0 layer and the BM1 layer. Other backside via layers are BV1, BV2, etc. The backside metal layer furthest from the substrate 310 is designated as the BMTOP layer and the next backside metal layer is designated as the BMTOP-1 layer. The BM0 layer is the backside metal layer closest to the substrate 310. In the example configuration in fig. 3, the BM0 layer includes various BM0 conductive patterns, and the BM0 conductive patterns include a first backside power rail 341 and a second backside power rail 342.

The IC device 300 also includes a first FTV 351 and a second FTV 352. The first FTV 351 extends along the Z-axis through the substrate 310 and couples the first front side power rail 331 to the first back side power rail 341. The second FTV352 extends along the Z-axis through the substrate 310 and couples the second front side power rail 332 to the second back side power rail 342.

The IC device 300 also includes a plurality of solder bumps 355, the plurality of solder bumps 355 being located on and coupled with respective conductive patterns of the BMTOP layer. Solder bumps 355 are configured to mount IC device 300 on one or more external devices to provide a power supply to IC device 300 and/or to exchange data or signals between IC device 300 and one or more external devices. For example, TVDD is provided to one or more solder bumps 355 from an external device, then to first backside power rail 341 through a power network of conductive patterns and vias in backside redistribution structure 340, and then to first front side power rail 331 through first FTV 351.

As described herein, header circuit 301 is coupled to first front side power rail 331 and second front side power rail 332 and is controllable (e.g., by a control signal provided to gate electrode 317 of transistor P31) to electrically connect first front side power rail 331 to second front side power rail 332 or to electrically disconnect first front side power rail 331 from second front side power rail 332. When the transistor P31 is turned on, the first front side power rail 331 is electrically connected to the second front side power rail 332 corresponding to the header circuit 301 being in a conductive state. Thus, TVDD on first front side power rail 331 is provided as VVDD on second front side power rail 332.

The VVDD on the second front side power rail 332 is further provided to the second back side power rail 342 by a second FTV 352. Although not shown in fig. 3, the second front side power rail 332 and the second back side power rail 342 extend to one or more functional circuits of the IC device 300 to provide a VVDD to operate the one or more functional circuits. In some embodiments, the width of the BM0 conductive pattern is greater than the M0 conductive pattern width, such as described with reference to fig. 4A. Thus, the resistance on the second backside power rail 342 is lower than the resistance on the second front side power rail 332, and in one or more embodiments, it is possible and/or advantageous to transfer the VVDD over a wider area and/or over a greater distance on the second backside power rail 342 than on the second front side power rail 332.

The first front side power supply rail 331, the first FTV 351, and the first back side power supply rail 341 correspond to the TVDD power supply rail 231 described with respect to fig. 2, and belong to the TVDD power supply domain of the IC device 300. The power supply rail belonging to the TVDD power supply domain is referred to herein as a TVDD power supply rail. FTVs belonging to TVDD power domains are referred to herein as T-FTVs, and/or are designated in the figures with the label "T". The second front side power rail 332, the second FTV352, and the second back side power rail 342 correspond to the VVDD power rail 232 described with reference to fig. 2, and belong to the VQDD power domain of the IC device 300. The power rails belonging to the VVDD power domain are referred to herein as VVDD power rails. FTVs belonging to the VVDD power domain are referred to herein as V-FTVs, and/or are designated in the figures by the label "V". The first FTV 351, the portion of the first front side power rail 331 above the first FTV 351, and the portion of the first back side power rail 341 below the first FTV 351 collectively configure an FTV structure 361, the FTV structure 361 corresponding to the FTV cells described herein. FTV structure 361 belongs to the TVDD power domain, also referred to as a T-FTV structure. The second FTV352, a portion of the second front side power rail 332 on the second FTV352, and a portion of the second back side power rail 342 under the second FTV-352 collectively configure another FTV structure 362. The FTV structure 362 belongs to the VVDD supply domain and is also referred to as a V-FTV structure.

The configuration described with respect to fig. 3 is an example. Other configurations are within the scope of the various embodiments. For example, in at least one embodiment, IC device 300 includes a plurality of TVDD power domains, and/or each TVDD power domain of IC device 300 includes more than one TVDD power rail. In at least one embodiment, the IC device 300 includes more than one VVDD power domain, and/or each VVDD power domain of the IC device 300 includes more than one VVDD power rail. In at least one embodiment, one TVDD power rail is controllably connected or disconnected from more than one VVDD power rail by one or more header circuits.

Fig. 4A-4B are schematic diagrams of layers in an IC device layout 400, according to some embodiments. In some embodiments, the map 400 is stored on a non-transitory computer readable medium. In at least one embodiment, the layout 400 corresponds to one or more of the IC devices 100, 200, 300 described herein.

In fig. 4A, an example header circuit area 402 of a layout 400 is shown. The header circuit area is an area including one or more header units. A header unit is a layout of one or more header circuits. In some embodiments, the head unit is pre-designed and stored in a library of units on a non-transitory computer readable medium. In at least one embodiment, head units are generated from existing units of a unit library, for example, by an Electronic Design Automation (EDA) system as described herein. In the example configuration in fig. 4A, the header circuit region 402 includes two header unit cells HDR 41 and HDR 42 configured in a similar manner. A detailed description of the head unit cell HDR 41 is given herein. Certain features of head unit cell HDR 42 are described, while other features similar to head unit cell HDR 41 are omitted. The number N of head unit cells in the head circuit region 402 depends on one or more factors including, but not limited to, power requirements, design rules, etc. of the IC device corresponding to the layout 400. In the example configuration in fig. 4A, n=2. In some embodiments, the header circuit region 402 has one header unit cell (n=1), or more than two header unit cells (N > 2).

In the example configuration in fig. 4A, the head unit cell HDR 41 includes a head cell 410 and FTV cells 411, 412. Head unit cell HDR 42 comprises FTV cells 413, 414 and head unit 415. Head unit 415 corresponds to head unit 410, and detailed components of head unit 415 are omitted from fig. 4A for simplicity. FTV units 413, 414 correspond to FTV units 411, 412. In some embodiments, head unit cell HDR 42 is obtained by flipping head unit cell HDR 41 along the X-axis. In at least one embodiment, FTV units 413, 414 are obtained by flipping the respective FTV units 41, 412 along the X-axis. In at least one embodiment, the FTV units 411, 412 have the same configuration and differ in their connection with the respective TVDD and VVDD power rails (T-FTV and V-FTV, respectively), as described herein. In at least one embodiment, FTV units 413, 414 have the same configuration and differ in their connection with the respective TVDD and VVDD power rails (T-FTV and V-FTV, respectively), as described herein. In at least one embodiment, the FTV cells are stored in a cell library and depending on the placement location of the FTV cells in the layout, i.e., depending on the type of power rail (TVDD or VVDD) connecting the FTV cells, the placed FTV cells become T-FTV cells or V-FTV cells, respectively. In the example configuration in fig. 4A, FTV units 411, 413 configure T-FTV and are sometimes referred to as T-FTV units, and FTV units 412, 414 configure V-FTV and are sometimes referred to as V-FTV units.

In at least one embodiment, the head unit cell HDR41 is a new head cell obtained by placing the head cell 410 in abutment of the FTV cells 411, 412, for example using an EDA tool or system. In the example configuration in fig. 4A, the boundary of head unit 410 has a left edge that is placed adjacent (i.e., coincident) with the right edge of the boundary of FTV unit 412. The bottom edge of the boundary of FTV cell 411 is placed adjacent to the top edge of the boundary of FTV cell 411. By placing the head unit 415 and FTV units 413, 414 adjacently in a similar manner, the head unit HDR 42 can be obtained. Further head unit cell HDR 42 is placed adjacent to head unit cell HDR41, e.g. the right edge of the boundary of head unit 410 is placed adjacent to the left edge of the boundary of FTV units 413, 414. The top edges of the boundaries of FTV cell 411, head cell 410, FTV cell 414, head cell 415 are aligned along track m0_1. The bottom edges of the boundaries of FTV cell 412, head cell 410, FTV cell 413, head cell 415 are aligned along track m0_7. The top edges of FTV cells 412, 413 and the bottom edges of the boundaries of FTV cells 411, 414 are aligned along track m0_4. Although the boundaries of the different cells or arrays are placed in abutment, in FIG. 4A the boundaries are shown slightly separated for clarity. In at least one embodiment, by simply adding one or more FTV cells to a pre-existing head cell, new head cells can be quickly and/or easily provided to accommodate various situations, power requirements, IC designs, etc.

The head unit 410 in the head unit cell HDR 41 includes a plurality of active areas OD1-OD4. The active region is sometimes referred to as an Oxide Definition (OD) region and is schematically shown by the label "OD" in the figure. In at least one embodiment, the active areas OD1-OD4 are located over the front side of the substrate and include the source/drains of the transistors described with reference to FIG. 3. The active areas OD1-OD4 are elongated along a first axis (e.g. X-axis). The active areas OD1-OD4 are configured to form one or more PMOS devices, and are sometimes referred to as "PMOS active areas". The header cells are sometimes referred to as PMOS arrays. In the footer, the active areas corresponding to active areas OD1-OD4 are configured to form one or more NMOS devices, and are sometimes referred to as "NMOS active areas". The footer is sometimes referred to as an NMOS array. As described with reference to fig. 5B, in a standard cell in a functional circuit region including one or more functional circuits, an active region corresponding to one of the active regions OD1 to OD2 and one of the active regions OD3 to OD4 is an NMOS active region. In some embodiments, the PMOS active region is referred to as an active region of the first or second semiconductor type, and the NMOS active region is referred to as an active region of the second or first semiconductor type.

The head unit cell 410 in the head unit cell HDR 41 further includes a plurality of gate regions PO1-PO4 located above the active regions OD1-OD 4. The gate regions PO1-PO4 are elongated along a second axis (e.g., Y axis) perpendicular to the X axis. The gate regions PO1-PO4 are arranged along the X-axis at a regular pitch designated CPP (contacted poly pitch, contact poly pitch) in FIG. 4A. CPP is the center-to-center distance along the X-axis between two directly adjacent gate regions (e.g., gate regions PO1, PO2 in FIG. 4A). Two gate regions are considered to be directly adjacent if there are no other gate regions between them. As described with reference to fig. 3, each gate region PO1-PO4 corresponds to a gate electrode layer or gate stack. Each of the gate regions PO1-PO4 together with one of the active regions OD1-OD4 configure a PMOS transistor or PMOS device corresponding to the transistor P31 depicted in fig. 3. A plurality of PMOS devices configured by gate regions PO1-PO4 and active regions OD1-OD4 are coupled together and correspond to transistor P1 described with reference to fig. 1. The number of gate regions and/or active regions described in the head unit cell HDR 41 is an example. Other numbers of gate regions and/or active regions in the head unit are within the scope of the various embodiments and depend on one or more factors. For example, the number of gate regions in the head unit is selected according to the required driving strength of the corresponding head circuit. As the number of gate regions increases, the drive strength increases, but the chip or wafer area occupied by the header circuitry also increases. In at least one embodiment, the number of gate regions in the selected head unit is a design consideration that balances performance (e.g., increased drive strength) and area cost.

Head unit cell 410 in head unit cell HDR 41 also includes MD contacts over the corresponding source/drains in active areas OD1-OD4. In the example configuration in fig. 4A, the PMOS transistor configured by the gate region PO3 and the active region OD3 has source/drains 403, 404, the source/drains 403, 404 being located on opposite sides of the active region OD3 and the gate region PO 3. MD contact MD1 is located above source/drain 403 and is configured with an electrical connection from source/drain 403 to TVDD power rail 431 as described herein. MD contact MD2 is elongated along the Y-axis and spans all active areas OD1-OD4.MD contact MD2 is located above source/drain 404 and is configured as described herein to electrically connect from source/drain to VVDD power rails 432, 433. As a result, the transistors configured by gate region PO3 and active region OD3 are coupled to TVDD power rail 431 on the one hand, and to VVDD power rails 432, 433 on the other hand, as described herein, for controllably connecting TVDD power rail 431 to VVDD power rails 432 and 433 or disconnecting VVDD power rails 432 and 433. The MD contacts described and/or illustrated are examples, other MD contacts in the head unit cell HDR 41 being omitted for simplicity. In some embodiments, similar to MD contact MD1, MD contact MD2 is elongated along the Y-axis to lie over all active areas OD1-OD4 to couple the lower source/drain of active areas OD1-OD4 to TVDD supply rail 431. In some embodiments, head unit cell HDR 41 includes a plurality of elongated MD contacts similar to MD-contact MD1, alternating with gate regions PO1-PO4 along the X-axis. The pitch between directly adjacent MD contacts (i.e., center-to-center distance along the X-axis) is the same as the pitch CPP between directly adjacent gate regions. Two MD contacts are considered directly adjacent if there are no other MD contacts between them.

The head unit 410 in the head unit cell HDR 41 further includes a via VG over the gate region PO3, and electrical connection from the gate region PO3 to the M0 conductive pattern 434 is configured to control signals to turn on or off the corresponding head circuits. Other VG vias have been omitted for simplicity. In at least one embodiment, the M0 conductive pattern 434 is elongated along the X-axis to overlie all of the gate regions PO1-PO4, and additional VG vias are included in the head unit cell HDR 41 to configure additional electrical connections from the gate regions PO1, PO2, PO4 to the M0 conductive pattern 434. Accordingly, the control signal provided along the M0 conductive pattern 434 is applied to the gate electrodes of all PMOS transistors in the head unit cell HDR 41 to turn on or off all PMOS transistors of the head unit cell HDR 41 at the same time.

The head unit 410 in the head unit HDR 41 further includes a via VD1 and VD2, VD3, the via VD1 configuring an electrical connection from the MD contact MD1 to the TVDD power rail 431, and the VD2, VD3 configuring an electrical connection from the MD contact MD2 to the VVDD power rails 432, 433, respectively. Other VD vias are omitted for simplicity. In at least one embodiment, each PMOS transistor in head unit cell HDR 41 has a source/drain coupled to TVDD power rail 431 and another source/source coupled to VVDD power rails 432, 433.

The M0 layer above the header circuit region 402 of the layout 400 includes the depicted TVDD supply rail 431, VVDD supply rails 432, 433, and M0 conductive pattern 434.TVDD power rail 431 and VVDD power rails 432, 433 are elongated along the X axis. The TVDD power rail 431 is located between the VVDD power rails 432, 433 along the Y-axis. In some embodiments, TVDD power rail 431 corresponds to first front side power rail 331, and each of vvdd power rails 432, 433 corresponds to second front side power rail 332 described with respect to fig. 3.

The M0 layer above the header circuit region 402 of layout 400 also includes conductive pattern 441 protruding from TVDD power rail 431 toward TVDD power rail 433 along the Y-axis, conductive pattern 442 protruding from VVDD power rail 432 toward TVDD power rail 431 along the Y-axis, conductive pattern 443 protruding from TVDD power rail 431 toward VVDD power rail 432 along the Y-axis, and conductive pattern 444 protruding from VVDD power rail 433 toward TVDD power rail 431 along the Y-axis. In some embodiments, the conductive patterns 441-444 are referred to as "differential portions (jog)".

The header circuit region 402 also includes T-FTV 451, V-FTV 452, T-FTV 453, V-FTV-454 that overlap conductive patterns 441-454 along a third axis (e.g., Z axis) that is transverse to both the X and Y axes, respectively. In some embodiments, T-FTV 451, T-FTV 453 correspond to first FTV 351 described with reference to FIG. 3, and V-FTV 452, V-FTV 454 correspond to second FTV 352 described with reference to FIG. 3. In the example configuration of FIG. 4A, the T-FTVs and V-FTVs are staggered along the X-axis and the Y-axis. This configuration enables the FTV to service multiple head units on opposite sides of the FTV. For example, each of T-FTV 453 and V-FTV 454 are configured to service both head unit 410 and head unit 415.

The header circuit region 402 of the layout 400 also includes various BM0 conductive patterns in the BM0 layer. For simplicity, the BM0 conductive pattern is not shown in fig. 4A, but is shown and described in fig. 4B.

In fig. 4B, the M0 conductive pattern, BM0 conductive pattern, and several FTVs in the header circuit area 402 of the layout 400 are shown. In the header circuit region 402, the pattern or arrangement of BM0 conductive patterns is the same as the corresponding M0 conductive pattern or arrangement. For example, the BM0 layer includes BM0TVDD power rail 461, BM0VVDD power rails 462, 463, and BM0 conductive patterns (or BM0 differential portions) 471-474, which correspond to and overlap with conductive patterns 441-444 of TVDD power rail 431, VVDD power rails 432, 433, and M0 layer, for example, along the Z-axis. In the example configuration in fig. 4B, the entirety of the M0 conductive patterns 431-433, 441-444 overlaps with the respective BM0 conductive patterns 461-463, 471-474 above the head circuit region 402.

The difference between the M0 conductive pattern and the BM0 conductive pattern is that the BM0 conductive pattern is larger (or wider) than the corresponding M0 conductive pattern. For example, the VVDD power rail 433 and the BM0VVDD power rail 463 extend along the X-axis and have respective widths W1, W2 along the Y-axis. The width W2 of BM0VVDD power rail 463 is greater than the width W1 of the corresponding VVDD power rail 433 in the M0 layer. The respective differential portions, i.e., conductive pattern 444 and BM0 conductive pattern 474, extend along the Y-axis and have respective widths W3, W4 along the X-axis. The width W4 of the BM0 conductive pattern 474 is greater than the width W3 of the corresponding conductive pattern 444 in the M0 layer. Similarly, the widths of the BM0TVDD power rail 461, the BM0VVDD power rail 462, and the BM0 conductive patterns 471-473 are greater than the widths of the corresponding TVDD power rail 431, the VVDD power rail 432, and the conductive patterns 441-443 of the M0 layer. In some embodiments, the wider BM0 conductive pattern reduces the resistance and/or power consumption of the power supply network on the back side of the IC device corresponding to the layout 400.

As shown in fig. 4B, the T-FTV 451 overlaps the conductive pattern 441 and the BM0 conductive pattern 471. In an IC device corresponding to the layout 400, for example, in the IC device 300, the first FTV 351 corresponds to the T-FTV 451, a portion of the first front side power rail 331 directly above the first FTV 351 corresponds to the conductive pattern 441, and a portion of the first back side power rail 341 directly below the first FTV 351 corresponds to the BM0 conductive pattern 471. Conductive pattern 441, T-FTV 451, and BM0 conductive pattern 471 are included in FTV cell 411, FTV cell 411 configured with a T-FTV structure coupling a backside power rail (e.g., BM0 TVDD power rail 461) to a front side power rail (e.g., TVDD power rail 431). In some embodiments, the T-FTV structure configured by FTV unit 411 corresponds to T-FTV structure 361.

In a similar manner, V-FTV 452 overlaps conductive pattern 442 and BM0 conductive pattern 472. In an IC device corresponding to layout 400, for example in IC device 300, second FTV352 corresponds to V-FTV 452, the portion of second front side power rail 332 directly above second FTV352 corresponds to conductive pattern 442, and the portion of second back side power rail 342 directly below second FTV352 corresponds to BM0 conductive pattern 472. Conductive pattern 442, V-FTV 452, and BM0 conductive pattern 472 are included in FTV cell 412, FTV cell 412 configuring a V-FTV structure that couples a backside power rail (e.g., BM0 VVDD power rail 462) to a front side power rail (e.g., VVDD power rail 432). In some embodiments, the V-FTV structure configured by FTV unit 412 corresponds to V-FTV structure 362.FTV unit 413 is configured similar to FTV unit 411 and FTV unit 414 is configured similar to FTV unit 421. A detailed description and/or illustration of FTV unit 4103, FTV unit 1414 is omitted for simplicity.

The front side power rails 431, 432, 433 in the M0 layer and the back side power rails 461, 462, 463 in the BM0 layer are elongated along the corresponding tracks m0_1, m0_4, m0_7 in the plurality of tracks m0_1, m0_2, … m0_7 in the map 400. The plurality of tracks mp_1, mp_2, … … m0_7 are M0 tracks regularly spaced from each other along the Y-axis. In the functional circuit area of the layout 400, standard cells (e.g., cells other than head and foot cells) include one or more M0 conductive patterns along the tracks M0 (such as tracks m0_1, m0_2, … m0_7). For example, although in the header circuit region 402, the tracks m0_2, m0_3, m0_5, m0_6 are not occupied by the M0 conductive pattern, one or more of these tracks m0_2, m0_3, m0_5, and m0_6 are occupied by one or more corresponding M0 conductive patterns in standard cells in the functional circuit region for signal and/or power routing. For example, as described with respect to fig. 5B, in the standard cell of the functional circuit area, the front side and back side power rails along the track m0_4 are disconnected from the TVDD power rails 431, BM0 TVDD power rail 461, respectively, and are configured to supply VSS. The number of tracks depicted in fig. 3 is an example. Other M0 track configurations are within the scope of the various embodiments.

Referring to both fig. 4A-4B, the power transfer path in header circuit region 402 is from BM0TVDD power rail 461 to BM0 conductive pattern 471, then to T-FTV 451, then to conductive pattern 441, then to TVDD power rail 431, then to MD contact MD1 through VD1, then to source/drain 403, then to source or drain 404 when the corresponding PMOS transistor is on, then to MD contact MD2, then to via VD2, then to VVDD power rail 432, then to conductive pattern 442, then to V-FTV 452, then to BM0 conductive pattern 472, and finally to BM0 VVDD power rail 462. In some embodiments, this power transfer path in header circuit region 402 corresponds to the power transfer path in IC device 300 of fig. 2 from first backside power rail 341, then to first FTV 351, then to first front side power rail 331, then to via VD321, then to MD contact 318, then to source/drain 313, then to source/drain 314 when transistor P31 is on, then to MD contact 319, then to VD via 322, then to second front side power rail 332, then to second FTV 352, then to second backside power rail 342.

Returning to FIG. 4A, each of the FTV cells 411-414 has a height H (or single cell height) along the Y-axis and a width W_FTV along the X-axis. Each of the head units 410, 415 has a dual unit height 2H along the Y-axis and a width w_pmos along the X-axis. The cell height H corresponds to the height of a standard cell having two active regions (e.g., one PMOS active region and one NMOS active region) along the Y-axis. The dual cell height 2H corresponds to the combined height of two single cell height standard cells stacked along the Y-axis, or the height of a standard cell having four active regions (e.g., two PMOS active regions and two NMOS active regions) along the Y-axis. Although all of the active areas OD1-OD4 in the head cell 410 are PMOS active areas, the height of the head cell 310 corresponds to the height of a dual cell height standard cell having four active areas. The height of the FTV cell and/or head cell is exemplary. Other cell heights are within the scope of the various embodiments.

In some embodiments, the width W_pmos of each head unit 410, 415 is from 1CPP to 100 CPP, i.e., each head unit 410, 415 includes 1 gate region to 100 gate regions. In some embodiments, the width w_pmos of head unit 410 is different than the width of head unit 415. The width w_pmos of each head cell (or the number of gate regions therein) and/or the number N of head unit cells in the head circuit region 402 may depend on various power requirements and/or other design considerations of the IC device corresponding to the layout 400. For example, as the number N of head unit cells in the head circuit region 402 is higher, the ratio of FTV cells per standard cell increases, power transfer performance improves, but chip area cost is higher. In some embodiments, the width W_ FTV of each FTV cell 411-414 ranges from 1CPP to 10CPP. At larger widths W FTV, the resistance and associated power consumption of the corresponding FTV decreases, but the chip area occupied by the FTV increases. In at least one embodiment, the width W ftv is determined as a balance between power transfer performance and chip area cost. In a particular example, the width W_pmos is 6CPP and the width W_ ftv is 3CPP. The size of the FTV in the FTV cell depends on various factors including, but not limited to, manufacturing process capability, width W FTV, etc. Larger FTVs have lower resistance and provide better power supply performance. In some embodiments, the FTV is circular with a diameter of 0.5CPP to 10CPP.

Fig. 5A is a schematic diagram of an IC device layout diagram 500 according to some embodiments. In some embodiments, the map 500 is stored on a non-transitory computer readable medium. In at least one embodiment, the layout 500 corresponds to one or more of the IC devices 100, 200, 300 described herein. Components in the layout 500 that correspond to components in the layout 400 are designated by the same reference numbers or by a hundred increase in the reference numbers of the layout 400.

The layout 500 includes a header circuit region 502 corresponding to the header circuit region 402. The header circuit region 502 includes header unit cells HDR 51, HDR 52 corresponding to the header unit cells HDR 41, HDR 42. Head units HDR 51 and HDR 52 comprise head units 510, 515 and FTV units 511-514 corresponding to head units 410, 415 and FTV units 411-414. The M0 layer in the header circuit region 502 includes TVDD power rails 531, VVDD power rails 532, 533 and conductive patterns 541-544 corresponding to the TVDD power rails 431, VFDD power rails 432, 433 and conductive patterns 441-444. Header circuit area 502 also includes FTVs 551-554 corresponding to FTVs 451-454. The BM0 layer in the header circuit region 502 includes BM0 power rails (i.e., backside power rails) and BM0 conductive patterns (or differential portions) that overlap in a manner similar to that described in fig. 4B and have the same pattern or configuration as the M0 power rails 531-533 and the M0 conductive patterns 541-544. Each FTV cell 511-514 includes a respective M0 conductive pattern (or differential) 541-544, a respective FTV 551-554, and a respective BM0 conductive pattern.

The difference between head units 510, 515 and head units 410, 415 is that each of head units 540, 5150 includes six gate regions schematically indicated by respective tracks PO1-PO6 in FIG. 5A. Other components of the head units 510, 515, such as MD contacts, VD vias, VG vias, are omitted for simplicity. The number of six gate regions in each head unit 510, 515 described is an example. The number of other gate regions in the head unit is within the scope of the various embodiments.

The difference between the FTV cells 511-514 and the FTV cells 411-414 is that each of the M0 conductive patterns 541-544 occupies the entire width W_ FTV of the respective FTV cell 511-514, while each of the M0 conductive patterns 441-444 does not occupy the entire width W_ FTV of the respective FTV cell 441-444. Thus, in one or more embodiments, at the same width W_ FTV, M0 conductive patterns 541-544 are wider than M0 conductive patterns 441-444, which in turn allows the respective FTVs 551-554 to be larger than FTVs 451-454. Although not shown in fig. 5A, in FTV cells 511-514, the corresponding BM0 conductive patterns (or differential portions) under FTVs 551-554 have at least the same width as BM0 conductive patterns 471-474 or are wider than BM0 conductive patterns 471-474. Thus, the FTV units 511-514 provide better power transfer performance than the FTV units 411-414 for the same area cost (i.e., the same height H and the same width W FTV). In at least one embodiment, one or more of the advantages described herein may be realized by the layout 500 and/or an IC device corresponding to the layout 500.

Fig. 5B is a schematic diagram of a layout 500, the layout 500 including a header circuit area 502 and a functional circuit area 505, according to some embodiments.

The functional circuit region 505 includes a plurality of transistors formed over the active regions OD51-OD 54. Two of the active areas OD51-OD54 are PMOS active areas for forming PMOS transistors, and the other two of the active areas OD51-OD54 are NMOS active areas for forming NMOS transistors. For example, the active areas OD51, OD54 are PMOS active areas, and the active areas OD52, OD53 are NMOS active areas. Other configurations are within the scope of the various embodiments. For example, in one or more embodiments, functional circuit area 505 includes more than four active areas. The functional circuit area 505 includes other components (not shown) that configure and/or couple transistors of the functional circuit area 50 into one or more functional circuits and/or couple one or more functional circuits of the functional circuit area 505 to other circuits of the IC device and/or external circuits. Examples of components of functional circuit region 505 that are not shown include, but are not limited to, gate regions, MD contacts, VD vias, VG vias, conductive patterns and vias in one or more metal layers and/or via layers of a front side redistribution structure, and the like.

One or more of the functional circuits in functional circuit area 505 require a power supply to operate. In the example configuration in fig. 5B, VVDD power rails 532, 533 extend along respective tracks m0_1, m0_7 from head circuit region 502 to functional circuit region 505 to provide VVDD for operating one or more functional circuits in functional circuit region 505. In some embodiments, VVDD is further supplied by a BM0 VVDD power rail below the VVDD power rails 532, 533. The M0 layer of layout 500 also includes an M0 conductive pattern 506, M0 conductive pattern 506 along the same track m0_4 as TVDD power rail 531 but disconnected from TVDD power rail 531. The M0 conductive pattern 506 is configured as a VSS power rail for supplying VSS to one or more functional circuits in the functional circuit region 505. In some embodiments, VSS is a ground voltage or a predetermined reference voltage.

Fig. 5C-5E are various schematic cross-sectional views in one or more functional circuit areas of one or more IC devices according to some embodiments. The schematic cross-sectional views in fig. 5C-5E show various examples in which VVDD from the header circuit region is transferred to a transistor in the functional circuit region.

In fig. 5C, a transistor P51 in a functional circuit region of the IC device 570 is formed over a substrate 571 of the IC device 571. In some embodiments, transistor P51, IC device 570, and substrate 571 correspond to transistor P31, IC device 300, and substrate 310. In the example configuration in fig. 5C, the power supply is supplied to the transistor P51 from the front side. For example, a front side VVDD power rail 572 extends from the header circuit area into the functional circuit area of the IC device 570 to provide VVDD to various transistors in the functional circuit area of the IC device 570. Front side VFDD power rail 722 is coupled to source/drain 575 of transistor P51 through VD via 573, MD contact 574, to provide VVDD to transistor P51. In some embodiments, the front side VVDD power rail 572 corresponds to one or more of the front side VVDD power rails described herein.

In fig. 5D, a transistor P52 in a functional circuit region of the IC device 580 is formed over the substrate 581 of the IC device 581. In some embodiments, transistor P52, IC device 580, and substrate 581 correspond to transistor P31, IC device 300, and substrate 310. In the example configuration in fig. 5D, a power supply is provided to the backside transistor P52. For example, the backside VVDD power rail 582 extends from the head circuit region into the functional circuit region of the IC device 580 to provide VVDD to various transistors in the functional circuit region of the IC device 588. The backside VVDD power rail 582 is coupled to the source/drain 585 of the transistor P52 through a backside via 583 to provide VVDD from the backside to the transistor P52. In some embodiments, the backside VVDD power rail 582 corresponds to one or more backside VDD power rails described herein. In at least one embodiment, the backside VVDD power rail 582 is wider than the front side power rail, thereby reducing power consumption in the power delivery network.

In fig. 5E, a transistor P53 in a functional circuit region of an IC device 590 is formed over a substrate 591 of an IC device 591. In some embodiments, transistor P53, IC device 590, and substrate 591 correspond to transistor P31, IC device 300, and substrate 310. In the example configuration in fig. 5E, the power supply is delivered on the backside of the substrate 591 to near the transistor P53 and then provided to the front side of the substrate 591 for subsequent supply from the front side to the transistor P53. For example, the backside VVDD power rail 592 extends from the head circuit region into the functional circuit region, or to a location near the functional circuit region of the integrated circuit device 590. The backside VVDD power rail 592 is coupled to the front side power rail 594 by an FTV 593 to provide VVDD to the front side power rail 594. The front side VVDD power rail 594 is coupled to the source/drain 597 of the transistor P53 through the VD via 595, MD contact 596 to provide VVDD to the transistor P53. In some embodiments, the backside VVDD power rail 592 corresponds to one or more of the backside VVDD power rails described herein, and/or the FTV 593 corresponds to one or more of the FTVs described herein. In at least one embodiment, the backside VVDD power rail 592 is wider than the front side power rail, thereby reducing power consumption in the power delivery network.

Fig. 6A is a schematic diagram of an IC device layout 600A according to some embodiments. In some embodiments, map 600A is stored on a non-transitory computer-readable medium. In at least one embodiment, the layout 600A corresponds to one or more IC devices 100, 200 described herein.

In fig. 6A, the layout of the head unit cell is shown. The head unit cells include head unit 610 with a first row 601 of FTV cells 611-616 placed adjacent the top edge of head unit 310 and a second row 602 of FTV cells 621-626 placed adjacent the bottom edge of head unit 410. Each adjacent FTV cell in the first row 601 and the second row 601 is placed adjacent. For example, the right edge of FTV cell 611 abuts the left edge of FTV cell 621. Each of the first row 601 and the second row 602 of FTV cells includes T-FTV cells and V-FTV cells alternately arranged along the X-axis. For example, FTV unit 611, FTV unit 613, FTV unit 615, FTV unit 621, FTV unit 623, FTV unit 625 are V-FTV units, FTV unit 612, FTV unit 614, FTV unit 616, FTV unit 622, FTV unit 624, FTV unit 626 are T-FTV units. In at least one embodiment, all of the FTV units 611-616, 621-626 have the same configuration as the FTV units stored in the unit library. Depending on the location of the FTV cell in the layout, i.e. depending on which type of power rail (TVDD or VVDD) the FTV cell is coupled to, the placed FTV cell becomes a T-FTV cell or a V-FTV cell, respectively. Each of the FTV cells 611-616, 621-626 has a single cell height H.

The header cell 610 corresponds to the header cells 410, 510 and includes PMOS active regions OD1-OD4. The number of gate regions in the head unit is determined based on various factors, such as power requirements and/or area costs as described herein. Other components of the head unit 610, such as MD contacts, VD vias, VG vias, are omitted for simplicity. The head unit 610 has a dual unit height 2H and width w_pmos (not shown in fig. 6A).

On the front side, the layout 600A includes a plurality of M0 conductive patterns, a plurality of V0 vias, and a plurality of M1 conductive patterns.

The M0 conductive patterns in layout 600A include TVDD supply rail 631, VVDD supply rails 632, 633, and a plurality of SM0 conductive patterns, each SM0 conductive pattern representing a respective one of the FTV cells 611-616, 621-626. For example, SM0 conductive patterns 637, 641 are contained in FTV cells 621, 622, respectively. For simplicity, other SM0 conductive patterns are not numbered in fig. 6A. The SM0 conductive patterns of the FTV cells in the first row 601 are arranged along the M0 track 608 and the SM0 conductive patterns of the FTV cells in the second row 602 are arranged along the M0 track 609. The cell height between M0 tracks 608, 609 is 3H. As described with respect to fig. 6C, SM0 conductive patterns (e.g., SM0 conductive patterns 637, 641) in adjacent FTV cells are spaced from each other along the X-axis by one or more design rule defined pitches to avoid shorting.

The layout 600A further includes a plurality of M1 conductive patterns m1_1, m1_2, … m1_6 extending along the Y axis and arranged side by side along the X axis.

Layout 600A also includes a plurality of V0 vias, each V0 via coupling one M0 conductive pattern to a corresponding M1 conductive pattern. For example, V0 via 635 couples TVDD power rail 631 to m1 conductive pattern m1_2, V0 via 636 is included in FTV cell 622, SM0 conductive pattern 637 is coupled to m1 conductive pattern m1_2, V0 via 640 is included in FTV cell 621, and SM0 conductive pattern 641 is coupled to m1 conductive pattern m1_1, V0 via 639 couples VVDD power rail 632 to m1 conductive pattern m1_1. For simplicity, other V0 vias are not numbered in fig. 6A.

Although not shown in fig. 6A, on the back side, the layout 600A further includes a plurality of BM0 conductive patterns, a plurality of BV0 vias, and a plurality of BM1 conductive patterns, which correspond to the M0 conductive patterns, V0 vias, and M1 conductive patterns overlapped on the front side. In at least one embodiment, when M0 is replaced with BM0, V0 is replaced with BV0, and M1 is replaced with BM1 in the layout of the front side of fig. 6A, a layout of the BM0 conductive pattern, BV0 via, and BM1 conductive pattern of the back side may be obtained. For example, the BM0 conductive pattern on the backside includes a BM0 TVDD power rail corresponding to and overlapping TVDD power rail 631, two BM0 VVDD power rails corresponding to and overlapping VVDD power rails 632, 633, and a plurality of SBM0 conductive patterns, each SBM0 conductive pattern corresponding to and overlapping one of the SM0 conductive patterns in FTV cells 611-616, 621-626. The BM1 conductive pattern on the back side includes a plurality of BM1 conductive patterns each extending along the Y-axis corresponding to and overlapping one of the m1 conductive patterns m1_1, m1_2, … m1_6. The BV0 via on the backside includes a plurality of BV0 vias, each of the plurality of BV0 vias coupling one of the BV0 conductive patterns to a corresponding BM1 conductive pattern. For example, a BV0 via corresponding to V0 via 635 couples a BM0 TVDD power rail corresponding to TVDD power rail 631 with a BM1 conductive pattern corresponding to M1 conductive pattern M1_2. In at least one embodiment, the distinction between the front side and the back side is that the BM0 conductive pattern and the BM1 conductive pattern on the back side are wider or larger than the corresponding M0 conductive pattern and M1 conductive pattern on the front side in a similar manner as described with reference to fig. 4B.

Layout 600A also includes a plurality of FTVs, each of which is contained in a corresponding one of FTV units 611-616, 621-626. For example, FTVs 638, 642 are contained in FTV units 622, 621, respectively. For simplicity, other FTVs are not numbered in fig. 6A. The FTVs in each of the FTV cells 611-616, 621-626 couple a respective SM0 conductive pattern and a respective BSM0 conductive pattern. For example, FTV 638 in FTV unit 622 couples SM0 conductive pattern 637 to a corresponding BSM0 conductive pattern under SM0 conductive pattern 637. In at least one embodiment, one or more of the advantages described herein may be realized by the layout 600A and/or the IC device corresponding to the layout 600A.

Fig. 6B is a schematic cross-sectional view in a header circuit region of an IC device 600B according to some embodiments. In at least one embodiment, IC device 600B corresponds to layout 600A. The cross-sectional view in fig. 6B shows the components, conductive patterns, vias, and connections associated with transistor P61 in the header cell formed above the substrate 650 of IC device 600B. In at least one embodiment, the head unit formed over the substrate 650 corresponds to the head unit 610, and the transistor P61 corresponds to a transistor in the head unit 610 and/or the transistor P31 in fig. 3.

Referring to both fig. 6A-6B, the first portion of the power transmission path in IC device 600B is from BM0 TVDD power rail 651 to BV0 via 652, then to BM1 conductive pattern 653, then to BV0 via 654, then to BSM0 conductive pattern 655, then to FTV 656, then to SM0 conductive pattern 657. The BSM0 conductive pattern 655, FTV 656, SM0 conductive pattern 657 together form an FTV structure 658, the FTV structure 658 being a T-FTV structure. In some embodiments, the first portion of the power delivery path in IC device 600B corresponds to the first portion of the power delivery path in layout 600A, from the BM0 TVDD power rail (not shown) corresponding to TVDD power rail 631 to the BV0 via (not shown) corresponding to V0 via 635, then to the BM1 conductive pattern (not shown) corresponding to m1 conductive pattern m1_2, then to BV0 (not shown) corresponding to V0 via 636, then to the BSM0 conductive pattern (not shown) corresponding to SM0 conductive pattern 637, then to FTV 638, then to SM0 conductive pattern 637. BSM0 conductive pattern (not shown) corresponding to SM0 conductive pattern 637, FTV 638, and SM0 conductive pattern 637 in T-FTV unit 622 in fig. 6A correspond to T-FTV structure 658 in fig. 6B.

The second, subsequent, portion of the power delivery path in IC device 600B is from SM0 conductive pattern 657 to V0 via 659, then to M1 conductive pattern 660, then to V0 pass 661, then to TVDD power rail 662. In some embodiments, the second portion of the power transfer path in IC device 600B corresponds to the second portion of the power transfer path in layout 600A, which reaches V0 via 636 from SM0 conductive pattern 637, then M1 conductive pattern m1_2, then V0 via 635, then TVDD power rail 631.

The subsequent third portion of the power supply transmission path in IC device 600B further extends from TVDD power rail 662 through the VD via and MD contact to source/drain 663 of transistor P61, then to the other source/drain 664 of transistor P61 when transistor P61 is on, then to VVDD power rail 665 through the other MD contact and the other VD via. In some embodiments, the third portion of the power supply transmission path in IC device 600B corresponds to the first portion of the power supply transmission path in layout diagram 600A, which passes from TVDD power supply rail 631, through VD vias and MD contacts (e.g., as described with reference to vias VD1 and MD contacts MD1 in fig. 4A) to the source/drain of the transistor corresponding to transistor P61, then to the other source/drain of the respective transistor when the respective transistor is turned on, and then through the other MD contact and the other VD via (e.g., as described with reference to vias VD2 and MD contacts MD2 in fig. 4A) to VVDD power supply rail 632.

The subsequent fourth portion of the power transfer path in IC device 600B further reaches V0 via 666, then M1 conductive pattern 667, then V0 via 668, then SM0 conductive pattern 669, then FTV 670, then BSM0 conductive pattern 671 from VVDD power rail 665. Together, SM0 conductive pattern 669, FTV 670, and BSM0 conductive pattern 671 form FTV structure 672, FTV structure 672 being a V-FTV structure. In some embodiments, the fourth portion of the power delivery path in IC device 600B corresponds to the fourth portion of the power delivery path in layout 600A, which reaches V0 via 639 from VVDD power rail 632, then M1 conductive pattern m1_1, then V0 via 640, then SM0 conductive pattern 641, then FTV 642, then BSM0 conductive pattern (not shown) corresponding to SM0 conductive pattern 641. SM0 conductive patterns 641, FTV 642 in T-FTV unit 621 in fig. 6A, and BSM0 conductive patterns (not shown) corresponding to SM0 conductive patterns 641, correspond to V-FTV structure 672 in fig. 6B.

The next fifth portion of the power supply path in the IC device 600B is from the BSM0 conductive pattern 671 to the BV0 via 673, then to the BM1 conductive pattern 674, then to the BV0 via 675, then to the BM0 VVDD power rail 676. In some embodiments, the fifth portion of the power supply path in IC device 600B corresponds to the fifth portion of the power supply path in layout diagram 600A from the BSM0 conductive pattern (not shown) corresponding to SM0 conductive pattern 641, then to the BV0 via (not shown) corresponding to V0 via 640, then to the BM1 conductive pattern (not shown) corresponding to M1 conductive pattern m1_1, then to the BV0 via (not shown) corresponding to V0 via 639, then to the BM0 VVDD power rail (not shown) corresponding to VVDD power rail 632.

Fig. 6C is a schematic diagram of an IC device layout 600C according to some embodiments. In some embodiments, map 600C is stored on a non-transitory computer-readable medium. In at least one embodiment, the layout 600C corresponds to one or more IC devices 100, 200, 600B described herein.

The maps 600C each include two head unit cells HDR 61, HDR 62 corresponding to the map 600A. Specifically, head unit cell HDR 61 includes first and second rows 601 and 602 of FTV cells, head unit 610, TVDD power rail 631, and VVDD power rails 632, 633. Head unit cell HDR 62 shares a second row 602 of FTV cells with head unit cell HTR 61. Head unit cell HDR 62 also includes FTV cells of third row 603, head cell 680, TVDD power rail 681, and VVDD power rails 682, 683. In head unit cell HDR 62, second and third rows 602 and 603 of FTV cells, head unit 680, TVDD power supply rail 681, and VVDD power supply rails 682 and 683 correspond to first and second rows 601 and 602 of FTV cells, head unit 610, TVDD power supply rail 631, and VFDD power supply rails 632, 633 in head unit cell HDR 61. In some embodiments, one or more additional head unit cells similar to head unit cells HDR 61, HDR 62 are added at the top or bottom of layout 600C along the Y-axis in the manner described, i.e., two adjacent head unit cells share a row of FTV cells. In at least one embodiment, one or more of the advantages described herein may be realized by the layout 600C and/or the IC device corresponding to the layout 600C.

Fig. 6D is a schematic diagram of FTV cell layout 600D according to some embodiments. In some embodiments, the map 600D is applicable to at least one or any one of the following: FTV units 611-616 in fig. 6A, FTV units 621-626 and/or FTV units in fig. 6C. For example, layout 600D as shown in fig. 6D is described with reference to FTV cell 621 in fig. 6A.

The FTV unit 621 includes an SM0 conductive pattern 641, an FTV 642, and a BSM0 conductive pattern 691 corresponding to the SM0 conductive pattern 641 and located below the SM0 conductive pattern 641. In an example IC device (e.g., IC device 600B) including FTV unit 631, SM0 conductive pattern 641, FTV 642, and BSM0 conductive pattern 691 correspond to SM0 conductive pattern 669, FTV 670, and BSM0 conductive pattern 671. The height of the FTV cell 621 is H, which is the distance along the Y-axis between the upper and lower edges of the FTV cell 62 1. The upper edge of FTV cell 621 coincides with track m0_7. The lower edge of the FTV cell 621 coincides with line 689. In at least one embodiment, line 689 is another M0 track. The width W FTV of the FTV cell 621 along the X-axis is as described with respect to fig. 4A.

As described with respect to fig. 6A, to meet one or more design rules that prevent shorting between SM0 conductive pattern 641 and the SM0 conductive pattern of an FTV cell 621 that is adjacent along the X-axis, SM0 conductive pattern 641 is spaced from the left and right edges of FTV cell 62l by a spacing, i.e., an M0 gap. The size (dimension) of the M0 gap depends on one or more design rules. In at least one embodiment, the size of the M0 gap is from 1nm to 5CPP. In the example configuration in fig. 6D, the same M0 gap applies to the SM0 conductive pattern 641 and the BSM0 conductive pattern 691. In at least one embodiment, the BSM0 conductive pattern 691 is spaced from the left and right edges of the FTV cell 621 along the X-axis by a different spacing than the M0 gap. In some embodiments, the BSM0 conductive pattern 691 is spaced 1nm to 5CPP from the left and right edges of the FTV cell 621.

Fig. 7 is a schematic diagram of an IC device layout diagram 700, according to some embodiments. In some embodiments, the layout 700 is stored on a non-transitory computer readable medium. In at least one embodiment, the layout 700 corresponds to one or more of the IC devices 100, 200, 300 described herein. Components in the layout 700 that correspond to components in the layout 400 are designated by the same reference numbers or by the addition of three hundred to the reference numbers of the layout 400.

Layout 700 includes a header circuit area 702 corresponding to header circuit area 402. The header circuit domain 702 includes header unit cells HDR 71, HDR 72 corresponding to the header unit cells HDR 41, HDR 42. In some embodiments, the head unit cells HDR 71 and HDR 72 have the same configuration. The head unit cell HDR 71 includes a head cell 710, a T-FTV cell 711, and a V-FTV cell 71 corresponding to the head cell 410. Head unit cell HDR 72 includes head unit 715, T-FTV-unit 713, and V-FTV unit 714 corresponding to head unit 415. In some embodiments, the T-FTV units 711, 713 have the same configuration and/or the V-FTV units 712, 714 have the same configuration.

The M0 layer in the header circuit area 702 corresponds to TVDD power rails 731, 734 in the header unit cells HDR 71, HDR 72. The M0 layer in the header circuit region 702 also includes VVDD power rails 732, 733 shared by the header unit cells HDR 71HDR 72, and M0 conductive patterns 741-744 located in the FTV cells 711-714, respectively. Header circuit area 702 also includes FTVs 751-754 located in FTV units 731-714, respectively. The BM0 layer in the header circuit region 702 includes BM0 power rails (i.e., backside power rails) and BM0 conductive patterns that overlap with the M0 power rails 731-734 and M0 conductive patterns 741-744 and have the same pattern or configuration as the M0 power rails 731-734 and M0 conductive patterns 741-744 in a similar manner as described with reference to fig. 4B. Each of the FTV cells 711-714 includes a respective M0 conductive pattern 741-744, a respective FTV 751-754, and a respective BM0 conductive pattern (not shown).

In the T-FTV unit 711, the M0 conductive pattern 741 protrudes from the TVDD power supply rail 731 toward the two VVDD power supply rails 732, 733 along the Y-axis without contacting the VVDD power supply rails 732 and 733.TVDD power supply rail 731 extends along the X-axis from M0 conductive pattern 741 to head unit cell HDR 72 and is interrupted within head unit cell 710 without reaching head unit cell HDR 72. The BM0 power rail below TVDD power rail 731 is interrupted in a similar manner. In the V-FTV cell 712, the M0 conductive pattern 742 extends along the Y-axis to connect the VVDD supply rails 732, 733. Each of the T-FTV cell 71 and the V-FTV cell 712 has a width of half the cell height H and width W FTV.

In the T-FTV cell 713, the M0 conductive pattern 743 protrudes along the Y-axis from the TVDD power rail 734 toward the two VVDD power rails 732, 733 without contacting the VVDD power rails 732 and 733.TVDD power rail 734 extends along the X-axis from M0 conductive pattern 743 away from head unit cell HDR 71 and is interrupted within head unit 715. The BM0 power rail below TVDD power rail 734 is also interrupted in a similar manner. In the V-FTV unit 714, the M0 conductive pattern 744 extends along the Y-axis to connect the VVDD supply rails 732, 733. Each of the T-FTV cell 733 and V-FTV cell 714 has a width that is half the cell height H and width W FTV.

The TVDD power supply rail 731 and the underlying BM0 power supply rail are configured to provide TVDD to the head unit 710, but not to the head unit 715 or another head unit arranged to the left of the V-FTV unit 712. The TVDD power supply rail 734 and the underlying BM0 power supply rail are configured to provide TVDD to the head unit 715 but not to the head unit 710 or another head unit arranged to the right of the head unit 715. To prevent a short circuit, the pitch between the M0 conductive patterns 742, 741, the pitch between the TVDD power supply rail 731 and the M0 conductive pattern 744, and the pitch between the M0 conductive patterns 744, 743 correspond to the M0 gap described with reference to fig. 6D.

In some embodiments, TVDD is provided from the backside to TVDD power rails 731, 734 through respective FTVs 751, 753 in a manner similar to that described with respect to fig. 3, 4A, 4B. When the head units 710, 715 are on, the VVDD is provided to the shared VVDD power rails 732, 733, and then returned to the backside via the FTVs 752, 754. In at least one embodiment, one or more of the advantages described herein may be realized by the layout 700 and/or an IC device corresponding to the layout 700.

Fig. 8 is a schematic diagram of an IC device layout 800 according to some embodiments. In some embodiments, the map 800 is stored on a non-transitory computer readable medium. In at least one embodiment, the layout 800 corresponds to one or more of the IC devices 100, 200, 300 described herein. Components in the layout 800 that correspond to components in the layout 400 are designated by the same reference numbers or by four hundred increases in the reference numbers of the layout 400.

The layout 800 includes a header circuit area 802 corresponding to the header circuit area 402. The header circuit region 802 includes header unit cells HDR 81, HDR 82 corresponding to the header unit cells HDR 41, HDR 42. In some embodiments, the head unit cells HDR 81 and HDR 82 have the same configuration. Head unit cell HDR 81 includes head unit 810, T-FTV unit 811, and V-FTV unit 822 corresponding to head unit 410. Head unit cell HDR 82 includes a head unit 815, a T-FTV unit 813, and a V-FTV unit 814 corresponding to head unit 415. In some embodiments, the T-FTV units 811, 813 have the same configuration and/or the V-FTV units 812, 814 have the same configuration.

The M0 layer in header circuit region 802 includes TVDD power supply rail 831 and VVDD power supply rails 832, 833, all TVDD power supply rails 831 and VVDD power supply rails 832, 833 being shared by header unit cells HDR 81 and HDR 82. The M0 layer in head unit cell HDR 81 also includes M0 conductive pattern 841 in T-FTV cell 811 and M0 conductive patterns 842, 862 in V-FTV cell 812. The head unit cell HDR 81 also includes FTVs 851, 852, 872 located under the M0 conductive patterns 841, 842, 862, respectively. The BM0 layer in the head unit cell HDR 81 includes BM0 power rails (i.e., backside power rails) and BM0 conductive patterns that overlap the M0 power rails 831-833 and the M0 conductive patterns 841, 842, 862 and have the same pattern or configuration as the M0 power rails 831-833 and the M0 conductive patterns 841, 842, 862 in a similar manner as described with reference to fig. 4B. The T-FTV cell 811 includes an M0 conductive pattern 841, an FTV 851, and a BM0 conductive pattern (not shown) corresponding to the M0 conductive pattern 841. The V-FTV cell 822 includes M0 conductive patterns 842, 862, FTVs 852, 872, and BM0 conductive patterns (not shown) corresponding to the M0 conductive patterns 842, 862.

In the T-FTV cell 811, the M0 conductive pattern 841 protrudes along the Y-axis from the TVDD power rail 831 toward the two VVDD power rails 832, 833 without contacting the VVDD power rails 832 and 833. The TVDD power rail 831 extends along the X-axis and is shared by the two head unit cells HDR 81, HDR 82. In the V-FTV cell 812, the M0 conductive patterns 842, 862 extend along the Y-axis from the respective VVDD power rail 832, 833 toward the TVDD power rail 831 without contacting the TVDD power rail 831. Each of the T-FTV cell 811 and the V-FTV cell 822 has a width of half the cell height H and width W FTV. The T-FTV unit 813 has a similar configuration to the T-FTV unit 811 and is not described in detail herein. The V-FTV unit 814 has a similar configuration to the V-FTV unit 812, and is not described in detail herein.

In some embodiments, TVDD is provided from the backside to TVDD power rail 831 by respective FTVs in FTV 751 and T-FTV unit 813 in a manner similar to that described with respect to fig. 3, 4A, and 4B. When the head units 810, 815 are turned on, the VVDD is provided to the VVDD power rails 832, 833 and then returned to the back side through the respective ones of the FTVs 852, 872 and V-FTV units 824. In the layout 700, the VVDI power supply rails 732, 733 are electrically connected to each other through the M0 conductive patterns 742, 744. In layout 800, the VVDD power rails 832, 833 are electrically connected to each other in the head units 810, 815 (e.g., via MD contacts) in a manner similar to that described with reference to fig. 4A. In at least one embodiment, one or more of the advantages described herein may be realized by the layout 800 and/or an IC device corresponding to the layout 800.

Fig. 9 is a schematic diagram of an IC device layout 900 according to some embodiments. In some embodiments, the map 900 is stored on a non-transitory computer readable medium. In at least one embodiment, the layout 900 corresponds to one or more IC devices 100, 200, 300 described herein. Components in the layout 900 that correspond to components in the layout 400 are designated by the same reference numerals or by five hundred increases in the reference numerals of the layout 400.

The layout 900 includes a header circuit area 902 corresponding to the header circuit area 402. The header circuit region 902 includes a header unit 910, the header unit 910 including active regions OD91, OD92, the active regions OD91, OD92 configured to form PMOS transistors of the header circuits described herein. The M0 layer in header circuit region 902 includes TVDD power supply rail 931 and VVDD power supply rails 932, 933. The BM0 layer of the header circuit region 902 includes BM0 TVDD power rail 961 and BM0 VVDD power rails 962, 963.BM0 power rails 961-963 are located below power rails 931-933, respectively, and are wider than power rails 931-933.

The head circuit region 902 also includes slots FTV 981-983 that extend continuously along the X-axis substantially across the width of the head unit 910. Slots FTV 981-983 couple BM0 power rails 961-963 on the back side to power rails 931-933 on the front side, respectively. In an IC device corresponding to layout 900, each of slots FTV 981-983 is a wall extending along the Z-axis from BM0 layer through the substrate to M0 layer and also extending continuously along the X-axis. In at least one embodiment, since the BM0 power rails 961-963 on the back side are wider than the power rails 931-933 on the front side, the width of the slots FTVs 981-983 is limited to the width of the power rails 931-1933.

In some embodiments, TVDD is provided from BM0 TVDD power rail 961 to TVDD power rail 931 by slot FTV 981 in a manner similar to that described with respect to fig. 3, 4A, and 4B. When the head unit 910 is turned on, VVDD is provided to the VVDD power rails 932, 933 and then returned to the BM0 VVDD power rails 962, 963 on the back side through the respective slots FTV 982, 983. In some embodiments, the FTVs described herein (including slot FTVs) do not occupy the area of the active area. Thus, in one or more embodiments, power may be supplied from the backside without affecting the chip area available for transistors and/or other active devices. In at least one embodiment, one or more of the advantages described herein may be realized by the layout 900 and/or the IC devices corresponding to the layout 900.

10A-10D are schematic diagrams of various functional circuit areas in one or more IC device layouts, according to some embodiments. In some embodiments, the layout diagrams in fig. 10A-10D correspond in one or more aspects to the layout diagrams in fig. 5A, 6C, 9.

Fig. 10A is a schematic diagram of an IC device layout 1000A according to some embodiments. In some embodiments, map 1000A is stored on a non-transitory computer readable medium. In at least one embodiment, the layout 1000A corresponds to one or more of the IC devices 100, 200, 300 described herein.

Layout 1000A includes VDD supply rail 1001, VSS supply rail 1002, functional circuit areas 1003, 1004, and FTV cells 1005, 1006. The boundary of the functional circuit region is designated as "MOS region boundary" in fig. 10A. In some embodiments, the voltage VDD on VDD supply rail 1001 is VVDD or a voltage derived from VVDD. In at least one embodiment, when the head circuit is turned off and the VVDD is removed, VDD is also removed from the corresponding VDD power rail that becomes floating. In some embodiments, the voltage VSS on VSS supply rail 1002 is or is derived from VVSS. In at least one embodiment, when the footer circuit is turned off and VVSS is removed, VSS is also removed from the corresponding VSS power rail that would become floating. In at least one embodiment, VDD power rail 1001 is on the same M0 rail as the VVDD power rail and is continuous with the VVDD power rail, and/or VSS power rail 1002 is on the same M0 rail as the TVDD power rail and is disconnected from the TVDD power rail, as described with respect to fig. 5B.

The functional circuit region 1003 includes active regions OD11, OD12, and has a cell height H. One of the active areas OD11, OD12 is a P-type active area, and the other is an N-type active area. For example, the active region OD11 is a PMOS active region, and the active region OD12 is an NMOS active region. The depicted active area configuration and cell height H of the functional circuit region 1003 are examples. Other configurations are within the scope of the various embodiments. In some embodiments, functional circuit area 1004 is similar to functional circuit area 100 in active area configuration and cell height. In the example configuration in fig. 10A, the functional circuit regions 1003, 1004 have the same width w_mos along the X-axis. In at least one embodiment, the functional circuit regions 1003, 1004 have different widths along the X-axis. In some embodiments, functional circuit regions 1003, 1004 are configured to form different functional circuits having different operations and/or functions. In some embodiments, the width W_mos ranges from 1CPP to 100CPP, and is determined by one or more factors discussed with respect to the width W_pmos.

The M0 layer in layout 1000A includes power rails 1001, 1002 and M0 conductive patterns (or differential portions) 1007, 1009. The M0 conductive pattern 1007 protrudes from the power supply rail 100l toward the power supply rail 1002 along the Y axis but does not reach the power supply rail 1002. The M0 conductive pattern 1009 protrudes along the Y-axis from the power rail 1002 toward the power rail 1001, but does not reach the power rail 1001. The BM0 layer in layout 1000A includes BM0 power rails (i.e., backside power rails) and BM0 conductive patterns (or differential portions) that overlap with M0 power rails 1001, 1002 and M0 conductive patterns 1007, 1009 and have the same pattern or configuration as M0 power rails 1001, 1002 and M0 conductive patterns 1007, 1009 in a manner similar to that described with reference to fig. 4B. Layout 1000A also includes FTV structures 1008, 1010, FTV structures 1008, 1010 coupling M0 conductive patterns 1007, 1009, respectively, to underlying BM0 conductive patterns (not shown). Each of the FTV cells 1005, 1006 includes a respective M0 conductive pattern (or differential) 1007, 1009, a respective FTV 1008, 1010, and a respective BM0 conductive pattern.

In some embodiments, FTV cells 1005, 1006 have the same configuration and differ in their connection with the respective VDD and VSS power rails. In at least one embodiment, the FTV cells are stored in a cell library and depending on where the FTV cells are placed in the layout (i.e., which type of power rail, VDD or VSS, the FTV cells are coupled to), the FTV cells placed become VDD FTV cells (e.g., FTV cell 1005) or VSS FTV cells (e.g., FTV cell 1006), respectively. In some embodiments, at least one of FTV units 1005, 1006 has the same configuration as at least one of FTV units 511-514.

In some embodiments, VDD is provided on the backside. For example, VDD is supplied from the head circuit in the on state to the BM0 power rail below the VDD power rail 1001, then to the BM0 conductive pattern below the M0 conductive pattern 1007, then to the FTV 1008, then to the M0 conductive pattern 1007 on the front side, then to the VDD power rail 1001, the VDD power rail 1001 being used to supply VDD to one or more functional circuits in the functional circuit areas 1003, 1004.

In some embodiments, VDD is provided on the front side. VDD is supplied, for example, from a header circuit in an on state to VDD power rail 1001 and then to one or more of the functional circuit areas 1003, 1005. VDD is further provided from VDD supply rail 1001 through FTV 1008 to BM0 supply rail below backside VDD supply rail 1001 for further distribution to other circuits.

In some embodiments, when the footer circuit is on, VSS is provided on the back side or front side and then further distributed in a manner similar to VDD. In at least one embodiment, one or more of the advantages described herein may be realized by the layout 1000A and/or IC devices corresponding to the layout 1000A.

Fig. 10B is a schematic diagram of an IC device layout 1000B according to some embodiments. In some embodiments, map 1000B is stored on a non-transitory computer readable medium. In at least one embodiment, the layout 1000B corresponds to one or more of the IC devices 100, 200, 600B described herein.

The layout 1000B includes functional circuit regions corresponding to the functional circuit regions 1003, 1004, and includes active regions OD11, OD12. For simplicity, the boundaries of the functional circuit areas are not shown in fig. 10B. Layout 1000B also includes VDD supply rail 1021 and VSS supply rail 1022 in the M0 layer, and BM0VSS supply rail located below VDD supply rail 1021 and BM0VSS supply rail 1022 in the BM0 layer. Layout 1000B also includes FTV cells 1031-1036 of a first row 1023 positioned along VDD supply rail 1021 and abutting top edge 1028 of the functional circuit area, and FTV cells 1041-1046 of a second row 1024 positioned along VSS supply rail 1022 and abutting bottom edge 1029 of the functional circuit area. In at least one embodiment, edges 1028, 1029 are M0 tracks. In some embodiments, each of the FTV units 1031-1036, 1041-1046 has the configuration described with respect to FIG. 6D.

Layout 1000B also includes m1 conductive patterns m1_11, m1_12, … m1_16 and various V0 vias, V0 vias coupling m1 conductive patterns m1_11, m1_12, … m1_16 to power supply rails 1021, 1022 and SM0 conductive patterns in FTV cells 1031-1036, 1041-1046 in a manner similar to that described with reference to fig. 6A. The layout 1000B also includes corresponding BM1 conductive patterns, BV0 vias, BSM0 conductive patterns, BM0 power rails on the backside as described with respect to fig. 6A.

In some embodiments, VDD is provided on the backside when the head circuit is on. VDD is then supplied from the back side to the front side VDD supply rail 1021 in a manner similar to that described for the first and second portions of the power supply transmission path in IC device 600B (i.e., as described with respect to the right side portion of transistor P61 in fig. 6B).

In some embodiments, VDD is provided on VDD power rail 1021 at the front side when the head circuit is on. Then, VDD is supplied from the front side to the back side for further distribution to other circuits in a manner similar to that described for the fourth and fifth portions of the power supply transfer path in IC device 600B (i.e., as described with respect to the left portion of transistor P61 in fig. 6B).

In some embodiments, when the footer circuit is on, VSS is provided on the back side or front side and then further distributed in a manner similar to that described with reference to VDD. In at least one embodiment, since the layout 1000B includes multiple FTVs, the resistance of the power delivery path between the backside and front side power rails is reduced, thereby improving performance. This advantage may also be realized in one or more embodiments described with respect to the layout diagrams 600A, 600C. In at least one embodiment, one or more of the advantages described herein may be realized by the layout 1000B and/or IC devices corresponding to the layout 1000B.

Fig. 10C is a schematic diagram of an IC device layout 1000C according to some embodiments. In some embodiments, map 1000C is stored on a non-transitory computer-readable medium. In at least one embodiment, the layout 1000C corresponds to one or more IC devices 100, 200, 600B described herein.

The map 1000C includes first and second units 1047, 1048, the first and second units 1047, 1048 each corresponding to the map 1000B in fig. 10B. Specifically, the first unit 1047 includes a first row 1023 and a second row 1024 of FTV cells, functional circuit areas including active areas OD11, OD12, VDD supply rail 1021, and VSS supply rail 1022. The second unit 1048 shares FTV cells of the second row 1024 with the first unit 1047. The second unit 1048 also includes a third row 1025 of FTV cells, another functional circuit area including active areas OD13, OD14, VDD supply rail 1051 and VSS supply rail 1052. In the second unit 1048, the second and third rows 1024 and 1025 of FTV cells, the active areas OD12, OD13, VDD supply rail 1051, and VSS supply rail 1052 correspond to the first and second rows 1023 and 1024 of FTV cells, the active areas OD11, OD12, VDD supply rail 1021, and VSS supply rail 1022 in unit 1047. In some embodiments, one or more additional cells similar to the first or second units 1047, 1048 are added along the Y-axis at the top or bottom of the layout 1000C in the manner described, i.e., two adjacent cells share a row of FTV cells. As described with respect to fig. 10B, VDD and VSS are supplied from the front side to the back side, or from the back side to the front side. In at least one embodiment, one or more of the advantages described herein may be realized by the layout 1000C and/or IC devices corresponding to the layout 1000C.

Fig. 10D is a schematic diagram of an IC device layout 1000D according to some embodiments. In some embodiments, map 1000D is stored on a non-transitory computer-readable medium. In at least one embodiment, the layout 1000D corresponds to one or more of the IC devices 100, 200, 300 described herein.

Layout 1000D includes functional circuit area 1080, functional circuit area 1080 corresponding to functional circuit areas 1003, 1004 and including active areas OD11, OD12. Layout 1000D also includes VDD supply rail 1061 and VSS supply rail 1062 in the M0 layer. The BM0 layer in layout 1000D includes a BM0 VDD supply rail 1063 and a BM0 VSS supply rail 1064. The BM0 power rails 1063-1064 on the backside are located below the front side power rails 1061-1062, respectively, and are wider than the front side power rails 1061-1062. Layout 1000D also includes slots FTV 1081, 1082 that extend continuously along the X-axis over substantially the entire width of functional circuit region 1080. The slots FTV 108, 1082 couple the backside BM0 power rails 1063, 1064 with the front side power rails 1061, 1062, respectively, in a similar manner as described with reference to fig. 9.

In some embodiments, VDD is provided on the backside when the head circuit is on. VDD is then supplied from BM0 VDD power rail 1063 on the back side through slot FTV 1081 to VDD power rail 1061 on the front side to power one or more functional circuits in functional circuit area 1080.

In some embodiments, VDD is provided on VDD power rail 1061 at the front side when the head circuit is on. VDD on VDD power rail 1061 provides a power supply for one or more functional circuits in functional circuit area 1080. VDD is further supplied from VDD supply rail 106l on the front side to BM0 VDD supply rail 1063 on the back side through slot FTV 1081 for further distribution to other circuits.

In some embodiments, when the footer circuit is on, VSS is provided on the back side or front side and then further distributed in a similar manner as described with reference to VDD. In at least one embodiment, one or more of the advantages described herein may be realized by the layout 1000D and/or the IC devices corresponding to the layout 1000D.

Fig. 11A-11D are schematic cross-sectional views of an IC device 1100 at various stages of a fabrication process, according to some embodiments. In some embodiments, IC device 1100 corresponds to IC device 300. As depicted in one or more of fig. 5C-5E, 6D, various ones of the IC devices or structures are fabricated using similar processes. Components of the IC device 1100 that correspond to components of the IC device 300 are designated by the same reference numerals.

In fig. 11A, the fabrication process begins with a substrate 310 having opposite front 311 and back 312 sides. In at least one embodiment, substrate 310 comprises a silicon substrate. In at least one embodiment, substrate 310 comprises silicon germanium (SiGe), gallium arsenide, or other suitable semiconductor material. In some embodiments, substrate 310 comprises an insulating substrate or a silicon-on-insulator (SOI) substrate. Active regions, such as PMOS active regions and/or NMOS active regions, are formed within or over front side 311 of substrate 310 using one or more masks corresponding to one or more active regions in the layout described or illustrated herein. An insulating structure (not shown) is formed in the substrate 310, for example, by etching a corresponding region of the substrate 310 and filling the etched region with an insulating material.

In a front end of line (FEOL) process, various transistors are formed on the front side 311 of the substrate 310. For example, at least one layer of gate dielectric material is deposited on the substrate. Example materials for the gate dielectric material layer include, but are not limited to, high-k dielectric layers, interfacial layers, and/or combinations thereof. In some embodiments, the layer of gate dielectric material is deposited over the substrate by Atomic Layer Deposition (ALD) or other suitable techniques. A gate electrode layer is deposited over the gate dielectric material layer. Example materials for the gate electrode layer include, but are not limited to, polysilicon, metal, al, alTi, ti, taN, ta, taC, taSiN, W, WN, moN, and/or other suitable conductive materials. In some embodiments, the gate electrode layer is deposited by Chemical Vapor Deposition (CVD), physical vapor deposition (PVD or sputtering), plating, atomic Layer Deposition (ALD), and/or other suitable processes. A patterning process is then performed to pattern the gate dielectric layer and gate electrode layer into a plurality of gate structures (or gate stacks) using one or more masks, each gate structure including a gate electrode (e.g., gate electrode 317) and one or more underlying gate dielectric layers, such as gate dielectric layers 315, 316. The gate electrode corresponds to the various gate regions described herein. In some embodiments, the patterning of the gate dielectric material and the gate material includes a lithographic operation.

In at least one embodiment, the deposition and patterning of each gate electrode is performedThe opposite side forms a spacer. Example materials for the spacers include, but are not limited to, silicon nitride, oxynitride, silicon carbide, and other suitable materials. Exemplary deposition processes include, but are not limited to, plasma Enhanced Chemical Vapor Deposition (PECVD), low Pressure Chemical Vapor Deposition (LPCVD), sub-atmospheric pressure chemical vapor deposition (SACVD), atomic Layer Deposition (ALD), and the like. Example patterning processes include, but are not limited to, wet etching processes, dry etching processes, or combinations thereof. Drain/source electrodes, such as drain/source electrodes 313, 314, are formed in the active area of the substrate. In at least one embodiment, the drain/source is formed by using the gate electrode and the spacer as a mask. The drain/source formation is performed, for example, by an ion implantation or diffusion process. Depending on the type of device or transistor, the drain/source is doped with a P-type dopant (such as boron or BF ₂ ) An N-type dopant (such as phosphorus or arsenic), and/or combinations thereof. As a result, P-type and N-type transistors are formed in one or more functional circuit regions, P-type transistors are formed in one or more header circuit regions, and N-type transistors are formed in one or more footer circuit regions.

MD contacts and VD/VG vias are formed over the source/drain and gate electrodes. In one example fabrication process, a conductive layer (such as metal) is deposited over a substrate on which a transistor is formed, electrically connecting to the drain/source of the transistor. A planarization process is performed to planarize the conductive layer, thereby creating MD contacts, such as MD contacts 318, 319. Various VD vias (such as 321, 322) and VG vias (such as 320) are formed over the MD contacts and gate electrode, respectively. The resulting structure 1100A is obtained at the end of the FEOL process.

In fig. 11B, after the FEOL process, a back-end-of-line (BEOL) process is performed to form a redistribution structure 330 over the transistors to electrically couple the various elements or circuits of the IC device 1100 to each other and to external circuitry. In at least one embodiment, the redistribution structure 330 includes a metal layer and a via layer that are sequentially overlaid. The overlying metal layers and via layers include metal layers M0, M1, etc., via layers V0, V1, etc., respectively. For example, the formation of the M0 layer includes depositing and patterning a metal material deposited to form various power rails (e.g., power rails 331, 332), differential and/or SM0 conductive patterns in one or more head/foot circuit regions, and/or other M0 conductive patterns for power or signals in one or more functional circuit regions.

In at least one embodiment, the redistribution structure 330 is further fabricated layer by layer from the patterned M0 layer up, for example, by repeatedly performing a damascene process. In such a damascene process, a dielectric layer is deposited over a patterned Mk layer (k zero and above). The dielectric layer is patterned to form a damascene structure having underlying via holes corresponding to conductive vias of later formed via layer Vk, and overlying recessed features corresponding to conductive patterns of later formed metal layer mk+1. An example patterning process for forming a damascene structure includes two or more photolithographic patterns and anisotropic etching steps to first form an underlying via hole and then an overlying recessed feature. A conductive material is deposited to fill the damascene structure to obtain a conductive via in the via layer Vk and an overlying conductive pattern in the metal layer mk+1. One or more damascene processes are performed to sequentially form higher via layers of the redistribution structure 330 and vias and conductive patterns of the metal layer until the top metal layer is completed. Thereby resulting in structure 1100B.

In fig. 11C, structure 1100B is inverted and bonded to a carrier (not shown) by an adhesive to expose backside 312 of substrate 310. In some embodiments, the thickness portion of the substrate 310 is removed, for example, by an etching or mechanical polishing process. The via openings of the FTV are formed, for example, by etching or laser drilling, to extend through the ground substrate 310 at different locations, exposing corresponding M0 conductive patterns, such as power rails, differential and/or SM0 conductive patterns. In some embodiments in which the FTV is formed as a slot FTV, the via openings are slots formed along and exposing the respective M0 power rails. In some embodiments, the via openings of the FTV are formed in a damascene process that also forms recessed features in the dielectric layer deposited on the backside 312 that overlie the via openings and correspond to the various BM0 conductive patterns to be formed. Conductive material, such as metal, is deposited to fill the damascene structure to obtain FTVs (e.g., FTVs 351, 352) and various BM0 conductive patterns. The BM0 conductive patterns include BM0 power rails (e.g., BM0 power rails 341, 342) in one or more header/footer circuit regions, differential and BSM0 conductive patterns, and/or other BM0 conductive patterns for power or signals in one or more functional circuit regions. Resulting in structure 1100C, structure 1100C includes FTV structures 361, 362 coupled to front-side TVDD, VVDD power rails, respectively.

In fig. 11D, one or more damascene processes are performed to sequentially form vias and conductive patterns of the higher backside via layers (e.g., BV0, BV1, etc.) and backside metal layers (e.g., BM1, etc.) of the backside redistribution structure 340 until the top backside metal layer is completed. The backside interconnect structure 340 includes backside TVDD, VVDD power rails coupled to the FTV structures 361, 362, respectively. After the backside metallization process is completed, solder bumps 355 are bonded over the corresponding BMTOP conductive patterns to provide power and/or signal input and/or output to the IC device 1100. The fabrication process of the IC device 1100 is completed. Other structures for mounting and providing input/output of the IC device 1100 are within the scope of the various embodiments. In some embodiments, the solder bumps (or other mounting structures) are located on the back side of the IC device 1100, rather than on the front side. In at least one embodiment. One or more of the advantages described herein may be realized by an IC device fabricated by the processes described with respect to fig. 11A-11D.

Fig. 12A is a flow diagram of a method 1200A of generating a layout and using the layout to fabricate an IC device, in accordance with some embodiments.

According to some embodiments, the method 1200A may be implemented, for example, using the EDA system 1300 (fig. 13, discussed below) and the Integrated Circuit (IC) manufacturing system 1400 (fig. 14, discussed below). With respect to method 1200A, examples of layouts include the layouts disclosed herein or similar layouts. Examples of IC devices fabricated according to method 1200A include the IC devices disclosed herein. In fig. 12A, a method 1200A includes operations 1202, 1204.

At operation 1202, a layout is generated that includes a pattern representing one or more circuit regions as described with respect to one or more of fig. 4A-4B, 5A-5B, 6A, 6C, 7-9, 10A-10D, and the like. Beginning at operation 1202, flow proceeds to operation 1204.

At operation 1204, at least one of the following is performed according to the layout: (a) performing one or more photolithographic exposures, or (B) fabricating one or more semiconductor masks, or (C) fabricating one or more components in a layer of an IC device.

Fig. 12B is a flow diagram of a method 1200B of generating a layout, according to some embodiments. More specifically, the flowchart of FIG. 12B illustrates additional operations of one example of a program that may be implemented in operation 1202 of FIG. 12A in accordance with one or more embodiments. In fig. 12B, operation 1202 includes operations 1212, 1214.

At operation 1212, an FTV cell is selected from a plurality of FTV cells having different configurations. In some embodiments, FTV units having different configurations include, but are not limited to, one or more of FTV units 411-414, one or more of FTV units 511-514, one or more of FTV units 611-616, 621-626, one or more of FTV units 711-714, one or more of FTV units 811-814, and the like. In at least one embodiment, FTV cells having different configurations are included in a cell library for selection by a user and/or a processor (e.g., a processor of an EDA system as described herein). One or more criteria for selecting FTV cells from FTV cells having different configurations are described herein, including but not limited to design rules, power requirements of the designed IC device, balancing considerations between resistance, performance, and area cost, and the like.

At operation 1214, placement of the selected FTV cell is associated with circuitry in the IC device layout. The FTV cells are positioned to provide at least one electrical connection between the circuitry of the IC device and the backside power rail. In some embodiments, the EDA system performs placement and routing operations to place the selected FTV cells in the layout. In at least one embodiment, the circuitry associated with the selected FTV cell is a power control circuit, e.g., a header circuit as described with respect to fig. 1-9. In at least one embodiment, the circuitry associated with the selected FTV cell is functional circuitry, as described with respect to fig. 10A-10D. In some embodiments, multiple instances of selected FTV cells are placed in association with the circuit to provide various electrical connections from the circuit to the backside power rail, e.g., as described with respect to fig. 4A, 4B, 5A, 6C, 10A, 10B, 10C. In some embodiments, a number of differently configured FTV cells are selected and placed in a layout of an IC device such as described with respect to fig. 7-8. In at least one embodiment, one or more of the advantages described herein may be realized by the layout diagrams generated by method 1200B and/or by the IC devices corresponding to the generated layout diagrams.

Fig. 12C is a flowchart of a method 1200C of fabricating one or more components of an IC device based on a layout, in accordance with some embodiments. More specifically, the flow diagram of FIG. 12C illustrates additional operations of one example of a program that may be implemented in operation 1204 of FIG. 12A in accordance with one or more embodiments. In fig. 12C, operation 1204 includes operations 1222, 1224.

At operation 1222, in a FEOL process, a plurality of transistors of a circuit area are formed over a substrate, for example as described with respect to fig. 11A. In some embodiments, the circuit area includes a power control circuit area, such as a header circuit area or a footer circuit area. In at least one embodiment, the circuit region includes a functional circuit region.

At operation 1224, in the BEOL process, front side redistribution structures are fabricated on the front side of the substrate, FTV structures are formed to extend through the substrate and couple to front side power rails of the front side redistribution structures, and back side redistribution structures are fabricated on the back side of the substrate to include back side power rails coupled to the FTV structures.

For example, as described with respect to fig. 11B, after the FEOL process, the back-end-of-line (BEOL) process includes fabricating the front-side redistribution structure 330, for example, by repeatedly performing a damascene process. As described with respect to fig. 11C, the BEOL process further includes forming FTV structures (e.g., 361, 362) that extend through the substrate and are coupled to front side power rails, such as front side TVDD or VVDD power rails, of the front side redistribution structure 330. As described with respect to fig. 11D, the BEOL process further includes fabricating the backside redistribution structure 340, for example, by repeatedly performing a damascene process. The fabricated backside redistribution structure 340 includes a backside TVDD or VVDD power rail coupled to an FTV structure (e.g., 361 or 362). In at least one embodiment, an IC device fabricated according to method 1200C may realize one or more of the advantages described herein.

The methods described include example operations, but are not necessarily required to be performed in the order shown. Operations may be added, replaced, altered in order, and/or deleted as appropriate according to the spirit and scope of embodiments of the invention. Embodiments combining different features and/or different embodiments are also within the scope of the present disclosure and will be apparent to those of ordinary skill in the art upon reading this disclosure.

In some embodiments, at least one of the methods discussed above is performed in whole or in part by at least one EDA system. In some embodiments, the EDA system may be used as part of a design room of an IC manufacturing system discussed below.

Fig. 13 is a block diagram of an Electronic Design Automation (EDA) system 1300 in accordance with some embodiments.

In some embodiments, the EDA system 1300 includes an APR system. According to some embodiments, for example using the EDA system 1300, the method of designing a layout described herein represents that a routing device according to one or more embodiments is achievable.

In some embodiments, the EDA system 1300 is a general-purpose computing device that includes a hardware processor 1302 and a non-transitory computer-readable storage medium 1304. The storage medium 1304 is encoded with (i.e., stores) computer program code 1306 (i.e., a set of executable instructions). The execution of instructions 1306 by hardware processor 1302 represents (at least in part) an EDA tool that implements part or all of a method described herein (hereinafter referred to as the process and/or method) in accordance with one or more embodiments.

The processor 1302 is electrically coupled to a computer-readable storage medium 1304 via a bus 1308. The processor 1302 is also electrically coupled to an I/O interface 1310 via a bus 1308. A network interface 1312 is also electrically coupled to the processor 1302 via bus 1308. The network interface 1312 is connected to a network 1314, enabling the processor 1302 and computer-readable storage medium 1304 to be connected to external elements via the network 1314. The processor 1302 is configured to execute computer program code 1306 encoded in a computer-readable storage medium 1304 to make the system 1300 available for performing part or all of the described processes and/or methods. In one or more embodiments, the processor 1302 is a Central Processing Unit (CPU), multiprocessor, distributed processing system, application Specific Integrated Circuit (ASIC), and/or suitable processing unit.

In one or more embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or device or apparatus). For example, computer-readable storage media 1304 includes semiconductor or solid state memory, magnetic tape, removable computer diskette, random Access Memory (RAM), read-only memory (ROM), rigid magnetic disk and/or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1304 includes a compact disk read only memory (CD-ROM), compact disk read/write (CD-R/W), and/or Digital Video Disk (DVD).

In one or more embodiments, the storage medium 1304 stores computer program code 1306, the computer program code 1306 configured to make the system 1300 operable to execute (wherein the execution represents (at least part of) the EDA tool) some or all of the described processes and/or methods. In one or more embodiments, the storage medium 1304 also stores information that facilitates performing part or all of the described processes and/or methods. In one or more embodiments, the storage medium 1304 stores a standard cell library 1307, the standard cell library 1307 comprising such standard cells disclosed herein.

The EDA system 1300 includes an input/output interface 1310. The input/output interface 1310 is coupled to external circuitry. In one or more embodiments, the I/O interface 1310 includes a keyboard, a mouse, a trackball, a trackpad, a touch screen, and/or cursor direction keys for communicating information and commands to the processor 1302.

The EDA system 1300 also includes a network interface 1312 coupled to the processor 1302. The network interface 1312 allows the system 1300 to communicate with a network 1314, with one or more other computer systems connected to the network 1314. The network interface 1312 includes: wireless network interfaces such as bluetooth, WIFI, WIMAX (worldwide interoperability for microwave access ), GPRS or WCDMA (wideband code division multiple access, wideband code division multiple access); or a wired network interface such as ETHERNET, USB (universal serial bus ) or IEEE-1364 (institute of electrical and electronics engineers-1364,Institute of Electrical and Electronic Engineers-1364). In one or more embodiments, some or all of the processes and/or methods are implemented in two or more systems 1300.

The system 1300 is configured to receive information via the I/O interface 1310. The information received via I/O interface 1310 includes one or more instructions, data, design rules, libraries of standard cells, and/or other parameters processed by processor 1302. Information is transferred over bus 1308 to processor 1302. The EDA system 1300 is configured to receive information related to a UI through an I/O interface 1310. Information is stored as User Interface (UI) 1342 on computer-readable medium 1304.

In some embodiments, some or all of the described processes and/or methods are implemented as separate software applications executed by a processor. In some embodiments, some or all of the described processes and/or methods are implemented as software applications that are part of additional software applications. In some embodiments, some or all of the described processes and/or methods are implemented as plug-ins to software applications. In some embodiments, at least one of the described processes and/or methods is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the described processes and/or methods are implemented as software applications for use by the EDA system 1300. In some embodiments, a method such as provided by regular script design systems company (CADENCE DESIGN SYSTEMS, inc.) is used Such as a tool or another suitable layout generation tool to generate a layout containing standard cells.

In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of the non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory units, such as one or more of optical disks (e.g., DVD), magnetic disks (e.g., hard disk), semiconductor memories (e.g., ROM), RAM, memory cards, and the like.

Fig. 14 is a block diagram of an Integrated Circuit (IC) manufacturing system 1400 and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on the layout, at least one of the following is manufactured using the manufacturing system 1400: (A) One or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

In fig. 14, an IC fabrication system 1400 includes entities such as a design chamber 1420, a mask chamber 1430, and an IC manufacturer/factory ("fab") 1450 that interact in design, development, and manufacturing cycles and/or services associated with the fabrication of an IC device 1460. The entities in system 1400 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and/or wireless communication channels. Each entity interacts with and provides services to and/or receives services from one or more other entities. In some embodiments, two or more of the design chamber 1420, mask chamber 1430, and IC wafer 1450 are owned by a larger company. In some embodiments, two or more design chambers 1420, mask chambers 1430, and IC fabrication facility 1450 coexist in a common facility and use common resources.

The design room (or design team) 1420 generates an IC design layout 1422.IC design layout diagram 1422 includes various geometries designed for IC device 1460. The geometry corresponds to the pattern of metal, oxide, or semiconductor layers that make up the various components of the IC device 1460 to be fabricated. The layers are combined to form various IC components. For example, portions of the IC design layout 1422 include various IC components such as active areas, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for pads formed in a semiconductor substrate (e.g., a silicon wafer), as well as various material layers disposed on the semiconductor substrate. Design chamber 1420 performs appropriate design procedures to form an IC design layout 1422. The design program includes one or more logical designs, physical designs or arrangements, and routing operations. The IC design layout 1422 is presented in one or more data files with geometry information. For example, the IC design layout 1422 may be represented in a GDSII file format or a DFII file format.

Mask chamber 1430 includes data preparation 1432 and mask fabrication 1444. Mask chamber 1420 uses IC design layout 1422 to fabricate one or more masks 1445 for fabricating the various layers of IC device 1460 according to IC design layout 1422. Mask room 1430 performs mask data preparation 1432 in which the IC design layout 1422 is converted into a representative data file ("RDF"). Mask data preparation 1432 provides RDF for mask fabrication 1444. Mask fabrication 1444 includes a mask writer. The mask writer converts RDF into an image on a substrate, such as a mask (reticle) 1445 or a semiconductor wafer 1453. The design layout 1422 is manipulated by mask data preparation 1432 to meet the particular characteristics of the mask writing process and/or requirements of the IC fabrication facility 1450. In fig. 14, mask data preparation 1432 and mask fabrication 1444 are shown as separate elements. In some embodiments, mask data preparation 1432 and mask fabrication 1444 may be collectively referred to as mask data preparation.

In some embodiments, the mask data preparation 1432 includes Optical Proximity Correction (OPC) that uses lithographic enhancement techniques to compensate for image errors, such as errors that may occur due to diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout 1422. In some embodiments, the mask data preparation 1432 includes further Resolution Enhancement Techniques (RET), such as off-axis illumination, sub-resolution assist functions, phase shift masks, other suitable techniques, or the like, or combinations thereof. In some embodiments, a reverse lithography technique (ILT) is also used, which regards OPC as a reverse imaging problem.

In some embodiments, mask data preparation 1432 includes a Mask Rule Checker (MRC) that checks IC design layout 1422 processed in OPC with a set of mask creation rules that include certain geometric and/or connection constraints to ensure adequate margin to accommodate variability in the semiconductor manufacturing process, and the like. In some embodiments, the MRC modifies the IC design layout 1422 to compensate for limitations during mask fabrication 1444, which may undo some of the modifications made by the OPC to meet the mask creation rules.

In some embodiments, mask data preparation 1432 includes a lithography process inspection (LPC) that simulates the processing performed by IC fabrication facility 1450 to fabricate IC device 1460. The LPC is simulated from the IC design layout 1422 to create a simulated fabricated device, such as IC device 1460. The process parameters in the LPC simulation may include parameters related to various processes of the IC manufacturing cycle, parameters related to the tools used in IC manufacturing, and/or other aspects of the manufacturing process. The LPC accounts for various factors such as aerial image contrast, focal length ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and the like, or combinations thereof. In some embodiments, after the LPC creates a simulated device, OPC and/or MRC are repeated to further refine the IC design layout 1422 if the simulated device is not sufficiently close in shape to meet the design rules.

It should be appreciated that the description of the mask data preparation 1432 above is simplified for clarity. In some embodiments, data preparation 1432 includes additional functions, such as Logic Operations (LOPs), to modify IC design layout 1422 according to manufacturing rules. Further, the processes applied to the IC design layout 1422 during data preparation 1432 may be performed in a variety of different orders.

After mask data preparation 1432 and during mask fabrication 1444, a mask 1445 or set of masks 1445 is fabricated according to the modified IC design layout 1422. In some embodiments, mask fabrication 1444 includes performing one or more photolithographic exposures in accordance with IC design layout 1422. In some embodiments, a mask (photomask or reticle) 1445 is patterned using an electron beam (e-beam) or multiple e-beam mechanism according to the modified IC design layout 1422. Mask 1445 may be formed using various techniques. In some embodiments, mask 1445 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an Ultraviolet (UV) beam, used to expose a layer of image sensitive material (e.g., photoresist) applied to a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary mask version of mask 1445 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) applied to opaque regions of the binary mask. In another example, a mask 1445 is formed using a phase shift technique. In the Phase Shift Mask (PSM) version of mask 1445, the various features in the pattern formed on the phase shift mask are configured with appropriate phase differences to improve resolution and imaging quality. In various examples, the phase shift mask may be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 1444 is used for various processes. Such a mask may be used, for example, in an ion implantation process to form various doped regions in the semiconductor wafer 1453, in an etching process to form various etched regions in the semiconductor wafer 1453, and/or in other suitable processes.

IC manufacturing facility 1450 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC foundry 1450 is a semiconductor foundry. For example, there may be one fabrication facility for front-side fabrication (front-end-of-line (FEOL) fabrication) of multiple IC products, while a second fabrication facility may provide back-side fabrication (back-end-of-line (BEOL) fabrication) for interconnections and packaging of IC products, and a third fabrication facility may provide other services to the fabrication facility.

The IC fab 1450 includes a fabrication tool 1452, the fabrication tool 1452 being configured to perform various fabrication operations on the semiconductor wafer 1453 to fabricate an IC device 1460 in accordance with a mask (e.g., mask 1445). In various embodiments, the fabrication tool 1451 includes a wafer stepper, an ion implanter, a photoresist applicator, a process chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more of the suitable fabrication processes herein.

IC fabrication facility 1450 uses masks 1445 fabricated in mask chamber 1430 to fabricate IC device 1460. Thus, IC fabrication facility 1450 uses, at least indirectly, IC design layout 1422 to fabricate IC device 1460. In some embodiments, semiconductor wafer 1453 is fabricated by IC fabrication facility 1450 using mask 1445, forming IC device 1460. In some embodiments, IC fabrication includes performing one or more lithographic exposures based at least indirectly on the IC design layout 1422. The semiconductor wafer 1453 includes a silicon substrate or other suitable substrate with a material layer formed thereon. The semiconductor wafer 1453 also includes one or more various doped regions, dielectric features, multilevel interconnects, and the like (formed in subsequent manufacturing steps).

Details regarding Integrated Circuit (IC) manufacturing systems (e.g., system 1400 of fig. 14) and IC manufacturing processes associated therewith are found, for example, in U.S. patent No. 9,256,709 issued on day 2016, 2, 9, 2015, 10, 1, 20150278429, pre-grant bulletin No. 20140040838 issued on day 2014, 2, 6, and U.S. patent No. 7,260,442 issued on day 2007, 8, 21, the entire contents of which are incorporated herein by reference.

For example, in U.S. patent No. 9,256,709, an IC design layout is generated in a design room (or design team). The IC design layout includes various geometric patterns designed for the IC device. The geometric pattern corresponds to the pattern of the metal, oxide or semiconductor layers that make up the various components of the IC device to be fabricated. The individual layers are combined to form various IC functions. For example, portions of the IC design layout include various IC components, such as active areas, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for pads to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The design chamber performs the appropriate design process to form the IC design layout. The design process may include logic design, physical design, and/or place and route. The IC design layout is presented in one or more data files with geometric pattern information. The mask blank is used to fabricate one or more masks using the IC design layout, the masks being used to fabricate various layers of the IC device according to the IC design layout. The mask shop performs mask data preparation in which the IC design layout is converted into a form that can be physically written by a mask writer, wherein the design layout prepared by the mask data preparation is modified to conform to a particular mask manufacturer and/or mask vendor and then manufactured. In the present embodiment, the mask data preparation and the mask manufacturing are illustrated as separate elements, however, the mask data preparation and the mask manufacturing may be collectively referred to as mask data preparation. Mask data preparation typically includes Optical Proximity Correction (OPC) that uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other processing effects. Mask data preparation may include other Resolution Enhancement Techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, or combinations thereof. Mask data preparation 132 also includes a Mask Rule Checker (MRC) that checks IC design layouts that have been processed in OPC using a set of mask creation rules that may contain some geometry and connectivity constraints to ensure adequate margin.

For example, in U.S. pre-grant publication No. 20150278429, in one embodiment, an IC manufacturing system may employ maskless lithography techniques, such as e-beam lithography or optical maskless lithography. In such a system, mask fabrication is bypassed and the IC design layout is modified by data preparation suitable for wafer processing using specific maskless lithography techniques. The data preparation modifies the design layout suitable for subsequent operations in the IC manufacturing system. The results of the data preparation are represented in one or more data files, such as files in GDSII file format or DFII file format. The one or more data files include information of geometric patterns, such as polygons representing the primary design pattern and/or the secondary components. In this embodiment, the one or more data files also include auxiliary data that is prepared for generation by the data. The auxiliary data will be used to enhance various operations of the IC fabrication system, such as mask fabrication by the mask blank and wafer exposure by the IC manufacturer.

For example, in pre-authorization bulletin number 20140040838, the IC design layout is presented in one or more data files with geometric pattern information. In one example, the IC design layout is represented in a "GDS" format as known in the art. In alternative embodiments, the IC design layout may be transferred between components in the IC manufacturing system in alternative file formats, such as DFII, CIF, OASIS or any other suitable file type. The IC design layout 300 includes various geometric patterns that represent components of an integrated circuit. For example, an IC design layout may include major IC components such as active areas, gate electrodes, source and drain electrodes, metal lines, inter-layer interconnect vias, and openings for bonding pads to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The IC design layout may also include some ancillary components, such as those for imaging effects, processing enhancements, and/or mask identification information.

For example, in U.S. patent No. 7,260,442, a mask manufacturing system includes: a processing tool for processing the mask; a metrology tool coupled to the processing tool for inspecting the mask and obtaining an inspection result; and a controller coupled to the processing tool and the metrology tool for generating a manufacturing model of the processing tool and calibrating the manufacturing model based on the tool data, the material data, and the inspection results of the mask. The mask manufacturing system may include at least one processing tool, a metrology tool, a controller, a database, and a manufacturing execution system. The processing tool may be an exposure tool, a developer, an etcher, or a photoresist stripper. The metrology tool performs a post-etch inspection or a post-strip inspection and obtains a post-etch inspection result or a post-strip inspection result, respectively. The controller is configured to process tool run-to-run control, including feed-forward control and feed-back control. The controller receives post-etch or post-strip inspection results from the metrology tool and retrieves device and material data from the database. A controller coupled to the manufacturing execution system generates a manufacturing model of the processing tool and calibrates the manufacturing model based on the equipment data, the material data, and the inspection results of the mask. The controller also monitors the operating conditions of the process tool and adjusts the manufacturing model of the process tool during processing.

In some embodiments, an Integrated Circuit (IC) device includes a substrate including a power control circuit and having opposing front and back sides, a front side metal layer, a back side metal layer, a first Feed Through (FTV) and a second FTV. The front side metal layer is located on the front side of the substrate and includes a first front side power rail and a second front side power rail. The backside metal layer is located on the backside of the substrate and includes a first backside power rail and a second backside power rail. The first FTV extends through the substrate and couples the first front side power rail to the first back side power rail. The second FTV extends through the substrate and couples the second front side power rail to the second back side power rail. The power control circuit is coupled to the first front side power rail and the second front side power rail, and the power control circuit is controllable to: the first front side power rail is electrically connected to the second front side power rail or the first front side power rail is electrically disconnected from the second front side power rail.

In the above-described IC device, the power supply control circuit is a header circuit including a P-type transistor, and the P-type transistor includes: a first source/drain coupled to the first front side power rail, and a second source/drain coupled to the second front side power rail.

In the above-described IC device, the power supply control circuit is a footer circuit including an N-type transistor, and the N-type transistor includes: a first source/drain coupled to the first front side power rail, and a second source/drain coupled to the second front side power rail.

In the above IC device, further comprising: and a functional circuit located on the front side of the substrate and coupled to at least one of the second front side power rail or the second back side power rail, wherein the functional circuit is operated by a power supply voltage supplied from the first back side power rail to the at least one of the second front side power rail or the second back side power rail in response to the power control circuit being in an on state in which the power control circuit electrically connects the first front side power rail to the second front side power rail, and wherein the functional circuit is disabled and the second front side power rail and the second back side power rail float in response to the power control circuit being in an off state in which the power control circuit electrically disconnects the first front side power rail from the second front side power rail.

In the above IC device, the first front side power rail and the second front side power rail extend along a first axis, and the front side metal layer further includes: a first conductive pattern protruding from the first front side power rail along a second axis transverse to the first axis, and a second conductive pattern protruding from the second front side power rail along the second axis, and a first FTV coupling the first back side power rail to the first conductive pattern, the second FTV coupling the second back side power rail to the second conductive pattern.

In the above IC device, the first backside power rail and the second backside power rail extend along a first axis, and the backside metal layer further includes: a third conductive pattern protruding from the first backside power rail along a second axis, and a fourth conductive pattern protruding from the second backside power rail along the second axis, and the first FTV couples the first conductive pattern on the front side metal layer to the third conductive pattern on the backside metal layer, and the second FTV couples the second conductive pattern on the front side metal layer to the fourth conductive pattern on the backside metal layer.

In the above-described IC device, the first conductive pattern protrudes from the first front side power supply rail toward the second front side power supply rail along the second axis, and the second conductive pattern protrudes from the second front side power supply rail toward the first front side power supply rail along the second axis.

In the above IC device, the front side metal layer further includes: a third front side power rail extending along the first axis and electrically connected to the second front side power rail, wherein the first front side power rail is located between the second front side power rail and the third front side power rail along the second axis, a third conductive pattern protruding from the third front side power rail toward the first front side power rail along the second axis, and a fourth conductive pattern protruding from the first front side power rail toward the third front side power rail along the second axis, the back side metal layer further comprising: a third backside power rail extending along the first axis and electrically connected to the second backside power rail, wherein, along the second axis, the first backside power rail is located between the second backside power rail and the third backside power rail, and the IC device further comprises: a third FTV extends through the substrate and couples the third backside power rail to the third conductive pattern on the front side metal layer, and a fourth FTV extends through the substrate and couples the first backside power rail to the fourth conductive pattern on the front side metal layer.

In the above IC device, the substrate further comprises a further power control circuit coupled to the first front side power rail, the second front side power rail, and the third front side power rail and controllable to: the first front side power rail is electrically connected to the second front side power rail and the third front side power rail, or the first front side power rail is electrically disconnected from the second front side power rail and the third front side power rail, and along a first axis, the power control circuit is located between (i) the first conductive pattern and the third conductive pattern on one side and (ii) the second and fourth conductive patterns on the other side, and the first conductive pattern and the third conductive pattern are located between the power control circuit and the further power control circuit.

In the above IC device, further comprising: an additional front side metal layer; and a further backside metal layer, wherein the front side metal layer further comprises: the first front side conductive pattern is coupled to the first front side power rail through the additional front side metal layer, and the second front side conductive pattern is coupled to the second front side power rail through the additional front side metal layer, the back side metal layer further comprising: a first backside conductive pattern coupled to the first backside power rail through the additional backside metal layer, and a second backside conductive pattern coupled to the second backside power rail through the additional backside metal layer, the first FTV coupling the first front side conductive pattern to the first backside conductive pattern, and the second FTV coupling the first front side conductive pattern to the first backside conductive pattern.

In the above IC device, further comprising: a plurality of first FTVs including a first FTV; a plurality of second FTVs including a second FTV; a plurality of first front side conductive patterns including a first front side conductive pattern; a plurality of first backside conductive patterns including a first backside conductive pattern; a plurality of second front side conductive patterns including a second front side conductive pattern; a plurality of second backside conductive patterns including a second backside conductive pattern; a plurality of first FTV structures, each first FTV structure comprising: one of the plurality of first front side conductive patterns, one of the plurality of first back side conductive patterns, and a first FTV of the plurality of first FTVs that couples the one first front side conductive pattern and the one first back side conductive pattern; and a plurality of second FTV structures, each second FTV structure comprising: one of the plurality of second front side conductive patterns, one of the plurality of second back side conductive patterns, and one of the plurality of second FTVs coupled to the one second front side conductive pattern and the one second back side conductive pattern, wherein the plurality of first FTV structures and the plurality of second FTV structures are alternately arranged along the first axis.

In the above IC device, the first front side power rail and the second front side power rail extend along a first axis, and the front side metal layer further includes: a third front side power rail extending along the first axis, wherein the first front side power rail is located between the second front side power rail and the third front side power rail along a second axis transverse to the first axis, and a first conductive pattern extending along the second axis and coupling the second front side power rail and the third front side power rail, and a second FTV couples the first conductive pattern to the second back side power rail.

In the above IC device, the front side metal layer further includes: the second conductive pattern projects from an end of the first front side power rail toward the second front side power rail and the third front side power rail along a second axis, the first FTV couples the second conductive pattern to the first back side power rail, and the first front side power rail extends from the second conductive pattern away from the first conductive pattern along the first axis.

In the above IC device, the first front side power rail and the second front side power rail extend along a first axis, and the front side metal layer further includes: a third front side power rail extending along the first axis, wherein the first front side power rail is located between the second front side power rail and the third front side power rail along a second axis transverse to the first axis, a first conductive pattern protruding from the first front side power rail toward the second front side power rail and the third front side power rail along the second axis, a second conductive pattern protruding from the second front side power rail toward the first front side power rail and the third front side power rail along the second axis, and a third conductive pattern protruding from the third front side power rail toward the first front side power rail and the second front side power rail along the second axis, the backside metal layer further comprising: a third backside power rail extending along the first axis, wherein along the second axis the first backside power rail is located between the second backside power rail and the third backside power rail, the first FTV couples the first conductive pattern to the first backside power rail, the second FTV couples the second conductive pattern to the second backside power rail, and the IC device further comprises a third FTV coupling the third conductive pattern to the third backside power rail.

In the above-described IC device, the first front side power rail and the first back side power rail extend along a first axis, and the first FTV is a slot FTV elongated along the first axis.

In some embodiments, a method of fabricating an Integrated Circuit (IC) device includes fabricating a circuit over a substrate having opposite front and back sides. The method further includes fabricating a front side redistribution structure over the front side of the substrate. The front side redistribution structure includes: a first front side power rail and a second front side power rail extending along a first axis and coupled to the circuit; a first conductive pattern protruding from the first front side power rail along a second axis transverse to the first axis; and a second conductive pattern protruding from the second front side power rail along the second axis. The method also includes fabricating a plurality of Feed Through Vias (FTVs) extending through the substrate. The plurality of FTVs includes: a first FTV coupled to the first conductive pattern; and a second FTV coupled to the second conductive pattern. The method further includes fabricating a backside redistribution structure over the backside of the substrate. The backside redistribution structure includes: a first backside power rail coupled to the first FTV; and a second backside power rail coupled to the second FTV.

In the above method, the circuit includes at least one of a power control circuit or a functional circuit.

In the above method, the backside redistribution structure further includes: a third conductive pattern protruding from the first backside power rail along the second axis; and a fourth conductive pattern protruding from the second backside power rail along a second axis, the first backside power rail and the second backside power rail extending along a first axis, the first FTV coupling the first conductive pattern to the third conductive pattern, and the second FTV coupling the second conductive pattern to the fourth conductive pattern.

In some embodiments, an Integrated Circuit (IC) device includes: a substrate including a circuit and having opposite front and back sides, first and second back side power rails on the back side of the substrate, first and second front side power rails on the front side of the substrate and coupled to the circuit, and a plurality of Feed Through Via (FTV) structures. Each FTV structure comprises: a front side conductive pattern on the front side of the substrate, a back side conductive pattern on the back side of the substrate, and FTV extending through the substrate and coupling the front side conductive pattern and the back side conductive pattern. The plurality of FTV features includes: at least one first FTV structure having a front side conductive pattern coupled to the first front side power rail and a back side conductive pattern coupled to the first back side power rail, and at least one second FTV structure having a front side conductive pattern coupled to the second front side power rail and a back side conductive pattern coupled to the second back side power rail.

In the above-described IC device, the at least one first FTV structure includes a plurality of first FTV structures, the at least one second FTV structure includes a plurality of second FTV structures, and the plurality of first FTV structures and the plurality of second FTV structures are alternately arranged along a first axis along which the first front side power rail and the second front side power rail extend.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device, comprising:

a substrate including a power control circuit and having opposite front and back sides;

a front side metal layer on a front side of the substrate and comprising:

A first front side power rail, and

a second front side power rail;

a backside metal layer on a backside of the substrate and comprising:

a first backside power rail, and

a second backside power rail;

a first feed-through hole extending through the substrate and coupling the first front side power rail to the first back side power rail; and

a second feed-through hole extending through the substrate and coupling the second front side power rail to the second back side power rail,

wherein the power control circuit is coupled to the first front side power rail and the second front side power rail, and the power control circuit is controllable to:

electrically connecting the first front side power rail to the second front side power rail, or

And electrically disconnecting the first front side power rail from the second front side power rail.

2. The integrated circuit device of claim 1, wherein

The power supply control circuit is a header circuit including a P-type transistor, and

the P-type transistor includes:

a first source/drain coupled to the first front side power rail, and

a second source/drain coupled to the second front side power rail.

3. The integrated circuit device of claim 1, wherein

The power supply control circuit is a foot circuit including an N-type transistor, and

the N-type transistor includes:

a first source/drain coupled to the first front side power rail, and

a second source/drain coupled to the second front side power rail.

4. The integrated circuit device of claim 1, further comprising:

a functional circuit located on the front side of the substrate and coupled to at least one of the second front side power rail or the second back side power rail, wherein

In response to the power control circuit being in an on state in which the power control circuit electrically connects the first front side power rail to the second front side power rail, the functional circuit operates by a power supply voltage supplied from the first back side power rail to at least one of the second front side power rail or the second back side power rail, and

in response to the power control circuit being in an off state in which the power control circuit electrically disconnects the first front side power rail from the second front side power rail, the functional circuit is disabled and the second front side power rail and the second back side power rail float.

5. The integrated circuit device of claim 1, wherein

The first front side power rail and the second front side power rail extend along a first axis,

the front side metal layer further includes:

a first conductive pattern protruding from the first front side power rail along a second axis transverse to the first axis, and

a second conductive pattern protruding from the second front side power rail along the second axis, and

the first feed-through couples the first backside power rail to the first conductive pattern and the second feed-through couples the second backside power rail to the second conductive pattern.

6. The integrated circuit device of claim 5, wherein

The first backside power rail and the second backside power rail extend along the first axis,

the backside metal layer further includes:

a third conductive pattern protruding from the backside power rail along the second axis, and

a fourth conductive pattern protruding from the second backside power rail along the second axis, and

the first feed-through couples the first conductive pattern on the front side metal layer to the third conductive pattern on the back side metal layer, and

The second feed-through couples the second conductive pattern on the front side metal layer to the fourth conductive pattern on the back side metal layer.

7. The integrated circuit device of claim 5, wherein

The first conductive pattern protrudes from the first front side power rail toward the second front side power rail along the second axis, and

the second conductive pattern protrudes from the second front side power rail toward the first front side power rail along the second axis.

8. The integrated circuit device of claim 7, wherein

The front side metal layer further includes:

a third front side power rail extending along the first axis and electrically connected to the second front side power rail, wherein along the second axis the first front side power rail is located between the second front side power rail and the third front side power rail,

a third conductive pattern protruding from the third front side power rail toward the first front side power rail along the second axis, and

a fourth conductive pattern protruding from the first front side power rail toward the third front side power rail along the second axis,

the backside metal layer further includes:

A third backside power rail extending along the first axis and electrically connected to the second backside power rail, wherein along the second axis the first backside power rail is located between the second backside power rail and the third backside power rail, and

the integrated circuit device further includes:

a third feed-through hole extending through the substrate and coupling the third backside power rail to the third conductive pattern on the front side metal layer, and

a fourth feed-through hole extends through the substrate and couples the first backside power rail to the fourth conductive pattern on the front side metal layer.

9. A method of manufacturing an integrated circuit device, the method comprising:

fabricating a circuit over a substrate having opposite front and back sides;

fabricating a front side redistribution structure over the front side of the substrate, the front side redistribution structure comprising:

a first front side power rail and a second front side power rail extending along a first axis and coupled to the circuit;

a first conductive pattern protruding from the first front side power rail along a second axis transverse to the first axis; and

A second conductive pattern protruding from the second front side power rail along the second axis;

fabricating a plurality of feed-through holes extending through the substrate, the plurality of feed-through holes comprising:

a first feed-through hole coupled to the first conductive pattern; and

a second feed-through hole coupled to the second conductive pattern; and

fabricating a backside redistribution structure over the backside of the substrate, the backside redistribution structure comprising:

a first backside power rail coupled to the first feed-through hole; and

a second backside power rail is coupled to the second feed-through hole.

10. An integrated circuit device, comprising:

a substrate comprising circuitry and having opposite front and back sides;

a first backside power rail and a second backside power rail located on the backside of the substrate;

first and second front side power rails located on the front side of the substrate and coupled to the circuit; and

a plurality of feed-through structures, each feed-through structure comprising:

a front side conductive pattern on the front side of the substrate,

a backside conductive pattern on the backside of the substrate, and

A feed through hole extending through the substrate and coupling the front side conductive pattern and the back side conductive pattern,

wherein the plurality of feed-through structures comprises:

at least one first feed-through structure having the front side conductive pattern coupled to the first front side power rail and the back side conductive pattern coupled to the first back side power rail, and

at least one second feed-through structure has the front side conductive pattern coupled to the second front side power rail and the back side conductive pattern coupled to the second back side power rail.