CN116931167A

CN116931167A - Adapter plate, optical chip package, calculation accelerator and manufacturing method thereof

Info

Publication number: CN116931167A
Application number: CN202210369385.3A
Authority: CN
Inventors: 达迪.塞蒂亚迪; 苏湛; 吴建华; 孙可烨; 苏森德兰.贾亚钱德兰; 孟怀宇; 沈亦晨
Original assignee: Nanjing Guangzhiyuan Technology Co ltd
Current assignee: Nanjing Guangzhiyuan Technology Co ltd
Priority date: 2022-04-08
Filing date: 2022-04-08
Publication date: 2023-10-24
Also published as: TW202340774A; WO2023193780A1

Abstract

The present disclosure provides an interposer, an optical chip package, a computing accelerator, and methods of manufacturing the same. The adapter plate includes: a glass substrate including one or more conductive vias including a via through the glass substrate and a conductive material filled in the via; and an optical waveguide structure disposed on the first surface of the glass substrate, wherein the optical waveguide structure includes one or more optical waveguides and a cladding layer cladding the one or more optical waveguides, the one or more optical waveguides are used for optically interconnecting the plurality of optical chips packaged on the interposer, and refractive index of the one or more optical waveguides is greater than refractive index of the cladding layer and the glass substrate, and the optical waveguide structure further includes one or more first conductive structures penetrating the optical waveguide structure and electrically connected with the one or more conductive vias, respectively.

Description

Adapter plate, optical chip package, calculation accelerator and manufacturing method thereof

Technical Field

The present disclosure relates to the field of semiconductor packaging, and in particular, to an interposer for optical chip packaging, an optical chip packaging structure, a computation accelerator, and methods of manufacturing the interposer and the optical chip packaging structure.

Background

In packaging a photonic integrated circuit (PIC, also referred to as an optical chip), a photonic-electronic hybrid integrated circuit (photonic-electronic hybrid chip) is typically formed by stacking an electronic integrated circuit (EIC, also referred to as an electrical chip) on the photonic integrated circuit to form a photonic-electronic hybrid system, which achieves computational acceleration. To compress the chip volume, electrical connections may be transferred to a substrate or Printed Circuit Board (PCB) through vertical interconnects, such as Through Silicon Vias (TSVs).

However, the silicon interposer with embedded TSVs presents a cost challenge because silicon wafers are semiconductor substrates with low resistivity and high dielectric constant, thin silicon wafers are difficult to handle, and manufacturing TSVs remains expensive because of the long time to drill and fill vias with electroplated copper. In addition, additional optical fibers are often required in the prior art to achieve optical interconnection between different optical chips, which also creates the problem of oversized package sizes of the opto-electronic hybrid module.

Disclosure of Invention

In view of the above, the present disclosure is directed to providing an interposer based on a glass substrate (e.g., a glass wafer) and a method of manufacturing the same, and an optical chip package structure using the interposer and a method of manufacturing the same. Since the glass substrate has high resistivity, low electrical loss, and thermal expansion of an adjustable coefficient and good mechanical strength, the interposer based on the glass substrate is low in manufacturing cost and can be effectively used for packaging of optical chips. In addition, the disclosure also aims to provide an optical chip packaging structure for realizing coupling between the optical waveguide on the adapter plate and the optical waveguide on the optical chip by adopting an adiabatic coupling mode and a manufacturing method thereof. The coupling mode occupies a small area, can realize the close arrangement of waveguides, improves the integration level, and reduces the packaging size.

A first aspect of the present disclosure provides a interposer for optical chip packaging, comprising: a glass substrate comprising one or more conductive vias, the conductive vias comprising a via through the glass substrate and a conductive material filled in the via; and an optical waveguide structure disposed on the first surface of the glass substrate, wherein the optical waveguide structure includes one or more optical waveguides and a cladding layer cladding the one or more optical waveguides, the one or more optical waveguides are used for optically interconnecting a plurality of optical chips packaged on the interposer, and refractive index of the one or more optical waveguides is greater than refractive index of the cladding layer and the glass substrate, and the optical waveguide structure further includes one or more first conductive structures penetrating the optical waveguide structure and electrically connected with the one or more conductive vias, respectively.

In some embodiments, the one or more optical waveguides are silicon nitride optical waveguides and the material of the cladding layer is silicon dioxide.

In some embodiments, the interposer further comprises: a dielectric layer disposed on the second surface of the glass substrate; one or more conductive bumps disposed on a surface of the dielectric layer on a side remote from the glass substrate, wherein the dielectric layer includes one or more second conductive structures penetrating the dielectric layer and electrically connected to the one or more conductive vias, respectively, and the one or more conductive bumps are electrically connected to the one or more second conductive structures, respectively.

A second aspect of the present disclosure provides another interposer for optical chip packaging, comprising: a glass substrate comprising one or more conductive vias, the conductive vias comprising a via through the glass substrate and a conductive material filled in the via; and an optical coupling structure disposed on the first surface of the glass substrate, wherein the glass substrate further comprises a three-dimensional waveguide network for optically interconnecting the plurality of optical chips packaged on the interposer, the optical coupling structure comprises a coupling optical waveguide covering an optical input/output port of the three-dimensional waveguide network and a cladding layer cladding the coupling optical waveguide, and the optical coupling structure further comprises one or more first conductive structures penetrating the optical coupling structure and electrically connected with the one or more conductive vias, respectively.

In some embodiments, the refractive index of the coupled optical waveguide is lower than the refractive index of the three-dimensional waveguide network and higher than the refractive index of the cladding layer.

In some embodiments, the coupling optical waveguide is a silicon nitride optical waveguide and the material of the cladding layer is silicon dioxide.

In some embodiments, the three-dimensional waveguide network is a network structure configured by inducing a localized glass inside the glass substrate such that the refractive index of the localized glass is increased.

A third aspect of the present disclosure provides another interposer for optical chip packaging, comprising: a glass substrate comprising one or more first conductive vias, the first conductive vias comprising a via through the glass substrate and a conductive material filled in the via; and an electrical interconnect structure disposed on the first surface of the glass substrate, wherein the electrical interconnect structure includes one or more wiring layers and a cladding layer cladding the one or more wiring layers, the cladding layer being a dielectric material, the one or more wiring layers being for electrically interconnecting a plurality of electrical chips over an optical chip packaged on the interposer, and the electrical interconnect structure further includes one or more first conductive structures penetrating the electrical interconnect structure and electrically connected with the one or more first conductive vias, respectively.

In some embodiments, at least two of the plurality of wiring layers are electrically connected by a second conductive structure.

In some embodiments, the cladding layer is a multilayer structure formed by alternately stacking silicon nitride layers and silicon dioxide layers.

In some embodiments, the interposer further comprises: the optical waveguide structure is arranged on the surface of the electric interconnection structure, which is far away from one side of the glass substrate, wherein the optical waveguide structure comprises one or more layers of optical waveguides and an enclosing layer enclosing the one or more layers of optical waveguides, the one or more layers of optical waveguides are used for carrying out optical interconnection on a plurality of optical chips packaged on the adapter plate, the refractive index of the optical waveguides is larger than that of the enclosing layer, and the optical waveguide structure further comprises one or more third conductive structures penetrating through the optical waveguide structure and respectively and electrically connected with the one or more first conductive structures.

In some embodiments, the interposer further comprises: a dielectric layer disposed on the second surface of the glass substrate; one or more conductive bumps disposed on a surface of the dielectric layer on a side remote from the glass substrate, wherein the dielectric layer includes one or more fourth conductive structures penetrating the dielectric layer and electrically connected to the one or more first conductive vias, respectively, and the one or more conductive bumps are electrically connected to the one or more fourth conductive structures, respectively.

A fourth aspect of the present disclosure provides a method of manufacturing an interposer for optical chip packaging, comprising: providing a glass substrate and forming one or more conductive through holes in the glass substrate; disposing an optical waveguide structure on a first surface of the glass substrate, wherein the optical waveguide structure includes one or more layers of optical waveguides and a cladding layer cladding the one or more layers of optical waveguides; and forming one or more first conductive structures penetrating the optical waveguide structure in the cladding layer and electrically connecting the first conductive structures with the one or more conductive through holes, respectively, wherein the refractive index of the one or more layers of optical waveguides is larger than that of the cladding layer.

In some embodiments, disposing an optical waveguide structure on the first surface of the glass substrate comprises: a. forming a network of optical waveguides on a first surface of the glass substrate using wafer level nanoimprint lithography; b. a cladding material is deposited over the optical waveguide.

In some embodiments, the method of manufacturing an interposer further comprises: disposing a dielectric layer on a second surface of the glass substrate; forming one or more second conductive structures in the dielectric layer through the dielectric layer and electrically connecting them with the one or more conductive vias, respectively; and disposing one or more conductive bumps on a surface of the dielectric layer on a side away from the glass substrate, wherein the one or more conductive bumps are electrically connected with the one or more second conductive structures, respectively.

In some embodiments, forming one or more conductive vias in the glass substrate includes: forming one or more through holes in the glass substrate by etching; and disposing a layer of conductive material on an inner surface of the one or more vias to form the one or more conductive vias.

In some embodiments, disposing a layer of conductive material on an inner surface of the one or more vias to form the one or more conductive vias comprises: and filling conductive metal on the inner surfaces of the one or more through holes by adopting an electroplating method.

A fifth aspect of the present disclosure provides another method of manufacturing an interposer for optical chip packaging, comprising: providing a glass substrate, and forming a three-dimensional waveguide network in the glass substrate, wherein the three-dimensional waveguide network is used for optically interconnecting a plurality of optical chips packaged on the adapter plate; forming one or more conductive vias in the glass substrate; arranging a coupling optical waveguide on the first surface of the glass substrate to cover the optical input/output port of the three-dimensional waveguide network; coating a coating layer on the coupling optical waveguide to coat the coupling optical waveguide; and forming one or more first conductive structures in the cladding layer, penetrating the cladding layer, and electrically connecting the first conductive structures with the one or more conductive vias, respectively.

In some embodiments, forming a three-dimensional waveguide network within the glass substrate comprises: and irradiating a preset position of the glass substrate by using femtosecond laser to improve the refractive index of the preset position of the glass substrate, wherein the preset position is the position where the three-dimensional waveguide network structure is formed.

A sixth aspect of the present disclosure provides another method for manufacturing an interposer for optical chip packaging, comprising: providing a glass substrate, and forming one or more first conductive through holes in the glass substrate; arranging an electrical interconnection structure on the first surface of the glass substrate, wherein the electrical interconnection structure comprises one or more wiring layers and a coating layer for coating the one or more wiring layers, the coating layer is made of dielectric materials, and the one or more wiring layers are used for electrically interconnecting a plurality of electrical chips packaged above the adapter plate; and forming one or more first conductive structures in the electrical interconnect structure that extend through the electrical interconnect structure and are electrically connected with the one or more first conductive vias, respectively.

In some embodiments, disposing an electrical interconnect structure on the first surface of the glass substrate comprises: disposing a first wiring layer on a first surface of the glass substrate; forming a first silicon nitride sub-layer around the first wiring layer; and covering the first silicon nitride sub-layer with a first silicon oxide sub-layer.

In some embodiments, disposing an electrical interconnect structure on the first surface of the glass substrate further comprises: disposing a second wiring layer on the first surface of the first silicon oxide sub-layer; forming a second silicon nitride sub-layer around the second wiring layer; and covering a second silicon dioxide sub-layer on the second silicon nitride sub-layer.

In some embodiments, disposing an electrical interconnect structure on the first surface of the glass substrate further comprises: and forming a second conductive structure between the first wiring layer and the second wiring layer to electrically connect the first wiring layer and the second wiring layer.

In some embodiments, the method of manufacturing an interposer further comprises: arranging an optical waveguide structure on the surface of the electric interconnection structure, which is far away from the glass substrate side, wherein the optical waveguide structure comprises one or more layers of optical waveguides and an enclosing layer enclosing the one or more layers of optical waveguides, the one or more layers of optical waveguides are used for carrying out optical interconnection on a plurality of optical chips packaged on the adapter plate, and the refractive index of the optical waveguides is larger than that of the enclosing layer; and forming one or more third conductive structures penetrating the optical waveguide structure in the optical waveguide structure and electrically connecting the third conductive structures with the one or more first conductive structures, respectively.

In some embodiments, the method of manufacturing an interposer further comprises: disposing a dielectric layer on a second surface of the glass substrate; forming one or more fourth conductive structures in the dielectric layer through the dielectric layer and electrically connected with the one or more first conductive vias, respectively; and disposing one or more conductive bumps on a surface of the dielectric layer on a side away from the glass substrate, wherein the one or more conductive bumps are electrically connected with the one or more fourth conductive structures, respectively.

A seventh aspect of the present disclosure provides an optical chip package structure including the interposer as described above, and a plurality of optical chips arranged on the interposer, the interposer being for optically interconnecting the plurality of optical chips arranged on the interposer.

In some embodiments, the optical chip package structure further includes: one or more electrical chips disposed on the plurality of optical chips; the optical chip comprises one or more interconnection structures, wherein the interconnection structures comprise through holes penetrating through the optical chip and conductive materials filled in the through holes; the one or more interconnect structures are electrically connected to the one or more first conductive structures or electrical interconnect structures, respectively, on the interposer.

An eighth aspect of the present disclosure provides an optical chip package structure, including: a patch panel including one or more first optical waveguides embedded therein; and a plurality of optical chips, each optical chip including one or more second optical waveguides embedded therein, wherein the plurality of optical chips are attached to the upper surface of the interposer at different positions and optically interconnected by the one or more first optical waveguides, each first optical waveguide includes a first optical coupling portion, each second optical waveguide includes a second optical coupling portion, and the first optical coupling portion and the second optical coupling portion are stacked and spaced apart from each other by a predetermined distance in a direction perpendicular to the upper surface of the interposer such that the first optical coupling portion and the second optical coupling portion achieve adiabatic coupling of light.

In some embodiments, the first and second light coupling portions are each tapered in shape.

In some embodiments, the first and second light coupling portions each have a shape formed by a concatenation of two differently sized tapered shapes.

In some embodiments, the predetermined distance is less than or equal to 600nm.

In some embodiments, the optical chip package structure further includes: a plurality of electrical chips disposed on a plurality of first optical chips of the plurality of optical chips, wherein each first optical chip has one or more first electrical connectors on an upper surface thereof, each electrical chip has one or more second electrical connectors on a lower surface thereof, and the one or more first electrical connectors are electrically connected with the one or more second electrical connectors, respectively.

In some embodiments, the first optical chip further includes one or more second conductive vias extending therethrough, the one or more second conductive vias electrically connected to one or more conductive structures in the interposer, respectively.

In some embodiments, the first optical chip is directly bonded to the electrical chip; or the first optical chip and the electric chip are bonded by flip-chip bonding.

In some embodiments, the plurality of optical chips are separated optical chips obtained by dividing a photonic wafer, gaps between the separated optical chips are filled with injection molding material on the upper surface of the interposer, and a dielectric layer for blocking outward transmission of light in the interposer is disposed between the injection molding material and the upper surface of the interposer.

In some embodiments, the plurality of optical chips are undivided plurality of optical chips in the same photonic wafer.

In some embodiments, the plurality of optical chips are unsingulated optical chips in a same photonic wafer, the plurality of optical chips have a plurality of first optical chips therein, each first optical chip has an electrical chip disposed thereon, the plurality of electrical chips on the plurality of first optical chips are unsingulated electrical chips in a same electronic wafer, and the photonic wafer is directly bonded to the electronic wafer.

In some embodiments, all of the plurality of optical chips have corresponding electrical chips disposed thereon, and the corresponding electrical chips on all optical chips are a plurality of electrical chips that are not segmented in the same electronic wafer, and wherein the plurality of optical chips have the same structure, and the plurality of electrical chips also have the same structure.

In some embodiments, the interposer is as previously described, and the one or more first optical waveguides are one or more layers of optical waveguides in an optical waveguide structure of the interposer as previously described.

In some embodiments, the interposer is as described above, and the one or more first optical waveguides are a three-dimensional waveguide network in the interposer as described above and a coupled optical waveguide covering an optical input/output port of the three-dimensional waveguide network.

A ninth aspect of the present disclosure provides a computing accelerator comprising: one or more light sources disposed on a first surface of the interposer in the optical chip package structure as previously described and configured to provide light waves to the computational accelerator; one or more computing units implemented by the optical chip in the optical chip package structure as described above, or by the optical chip and the electrical chip in the optical chip package structure as described above, or by the electrical chip in the optical chip package structure as described above, and configured to perform a computing function; one or more memory units implemented by an electrical chip in an optical chip package structure as described above and configured to perform a memory function.

In some embodiments, the interposer is an interposer as previously described.

A ninth aspect of the present disclosure provides a computing accelerator comprising: one or more edge optocouplers configured to optically interconnect the computational accelerator with other devices; one or more light sources configured to provide light waves to the computing accelerator, the light waves coupled to the one or more edge light couplers through a light guide structure; one or more computing units implemented by the optical chip in the optical chip package structure as described above, or by the optical chip and the electrical chip in the optical chip package structure as described above, or by the electrical chip in the optical chip package structure as described above, and configured to perform a computing function; and one or more memory units implemented by an electrical chip in the optical chip package structure as described above and configured to perform a memory function.

In some embodiments, each compute unit and corresponding memory unit is implemented by each optical chip and corresponding electrical chip in the optical chip package structure as described previously as a compute-memory unit.

In some embodiments, the interposer in the optical chip package structure is the interposer as described above.

In some embodiments, the computing accelerator further comprises: a plurality of High Bandwidth Memory (HBM) chips stacked on the optical chip in the optical chip package structure configured to perform a memory computation function.

A tenth aspect of the present disclosure provides a method for manufacturing an optical chip package structure, including: providing an adapter plate comprising one or more first optical waveguides embedded therein, each of said first optical waveguides comprising a first optical coupling portion; and attaching a plurality of optical chips to different positions on the upper surface of the interposer, each optical chip including one or more second optical waveguides embedded therein, each of the second optical waveguides including a second optical coupling portion, wherein the first optical coupling portion and the second optical coupling portion are stacked and spaced apart from each other by a predetermined distance in a direction perpendicular to the upper surface of the interposer such that the first optical coupling portion and the second optical coupling portion achieve adiabatic coupling of light, and the plurality of optical chips are optically interconnected by the one or more first optical waveguides.

In some embodiments, the predetermined distance is less than or equal to 600nm.

In some embodiments, prior to attaching the plurality of optical chips to the interposer at different locations on the upper surface, further comprising: an electrical chip is arranged on a first optical chip of the plurality of optical chips such that the first optical chip and the electrical chip thereon form an electron-photon hybrid chip, wherein the first optical chip has one or more first electrical connectors on an upper surface thereof, the electrical chip has one or more second electrical connectors on a lower surface thereof, and the one or more first electrical connectors are electrically connected with the one or more second electrical connectors, respectively.

In some embodiments, disposing an electrical chip on a first optical chip of the plurality of optical chips comprises: preparing a photon wafer and an electron wafer, wherein the photon wafer comprises a plurality of first optical chips, and the electron wafer comprises a plurality of electric chips; bonding the electronic wafer directly to the photonic wafer so that the plurality of first optical chips and the plurality of electrical chips are bonded to obtain an electronic-photonic hybrid wafer; removing the substrate of the photonic wafer; and dicing the electron-photon hybrid wafer into a plurality of electron-photon hybrid chips.

In some embodiments, disposing an electrical chip on a first optical chip of the plurality of optical chips comprises: preparing a photon wafer and an electron wafer, wherein the photon wafer comprises a plurality of optical chips, and the electron wafer comprises a plurality of electric chips; dicing the electronic wafer into the plurality of electrical chips; bonding or flip-chip bonding one or more of the plurality of electrical chips directly to a first optical chip in the photonic wafer to obtain an electron-photon hybrid wafer; filling injection molding materials in gaps, which are not occupied by the electronic chips, on the photonic wafer; removing the substrate of the photonic wafer; and dicing the electron-photon hybrid wafer into the electron-photon hybrid chips.

In some embodiments, the method further comprises: and after removing the substrate of the photonic wafer, thinning the buried oxide layer at the bottom of the photonic wafer to a preset thickness before cutting the electronic-photonic mixed wafer into the electronic-photonic mixed chips.

In some embodiments, the method further comprises: after removing the substrate of the photonic wafer, thinning the buried oxide layer of the bottom surface of the photonic wafer, and forming a connection waveguide on the surface of the photonic wafer away from the electrical chip, wherein the connection waveguide and the second optical coupling part of the second optical waveguide and the first optical coupling part of the first waveguide are overlapped and spaced apart in the vertical direction of the lower surface of the photonic wafer; and covering the connection waveguide with a dielectric to cover the connection waveguide. In some embodiments, the method further comprises: forming one or more second conductive vias in the photonic wafer after preparing the photonic wafer; and after removing the substrate of the photonic wafer, thinning the buried oxide layer at the bottom of the photonic wafer to a predetermined thickness to enable the one or more second conductive holes to penetrate up and down so as to form one or more second conductive through holes.

In some embodiments, attaching the plurality of optical chips to different locations on the upper surface of the interposer further comprises: and respectively and electrically connecting the one or more second conductive through holes with one or more conductive structures in the adapter plate.

In some embodiments, the plurality of electronic-photonic hybrid chips are spaced apart from each other on the upper surface of the interposer, and the method further comprises: forming a dielectric layer on an upper surface of the interposer and in gaps between the plurality of electron-photon hybrid chips for blocking light in the interposer from being transmitted outwards; and filling injection molding material on the dielectric layer and in the gap of the electron-photon chiplet.

In some embodiments, disposing an electrical chip on a first optical chip of the plurality of optical chips comprises: preparing a photon wafer and an electron wafer, wherein the photon wafer comprises a plurality of first optical chips, the electron wafer comprises a plurality of electric chips, and the electron wafer is directly bonded to the photon wafer, so that the plurality of first optical chips are bonded with the plurality of electric chips to obtain an electron-photon mixed wafer; and attaching a plurality of optical chips to different locations on the upper surface of the interposer includes: the electron-photon hybrid wafer is directly bonded to the upper surface of the interposer.

In some embodiments, the interposer is a interposer manufactured by a method as described above, and the one or more first optical waveguides are one or more layers of optical waveguides in an optical waveguide structure in the interposer manufactured by a method as described above.

In some embodiments, the interposer is a interposer manufactured by a method as described above, and the one or more first optical waveguides are a three-dimensional waveguide network in the interposer manufactured by a method as described above and a coupled optical waveguide covering an optical input/output port of the three-dimensional waveguide network.

Drawings

Fig. 1 shows a cross-sectional view of a first example of a interposer for an optical chip package in accordance with an embodiment of the present disclosure.

Fig. 2 shows a cross-sectional view of a second example of a interposer for an optical chip package in accordance with an embodiment of the present disclosure.

Fig. 3 shows a cross-sectional view of a third example of a interposer for optical chip packaging in accordance with an embodiment of the present disclosure.

Fig. 4 shows a cross-sectional view of a fourth example of a interposer for an optical chip package in accordance with an embodiment of the present disclosure.

Fig. 5 shows a process flow diagram of a method of manufacturing an interposer in a first example of an embodiment of the present disclosure.

Fig. 6 shows a process flow diagram of a method of manufacturing an interposer in a second example of an embodiment of the present disclosure.

Fig. 7A shows a process flow diagram of a method of manufacturing an interposer in a third example of an embodiment of the present disclosure.

Fig. 7B shows a process flow diagram of a method of manufacturing an interposer in a fourth example of an embodiment of the present disclosure.

Fig. 8 shows a cross-sectional view of an optical chip package structure incorporating the interposer in the first example of an embodiment of the present disclosure.

Fig. 9 shows a cross-sectional view of an optical chip package structure incorporating a interposer in a second example of an embodiment of the present disclosure.

Fig. 10 shows a cross-sectional view of an optical chip package structure incorporating a interposer in a third example of an embodiment of the present disclosure.

Fig. 11 shows a cross-sectional view of an optical chip package structure incorporating a interposer in a fourth example of an embodiment of the present disclosure.

Fig. 12A and 12B show a cross-sectional view and a top view, respectively, of a photo chip package structure of an embodiment of the present disclosure.

Fig. 13 and 14 show schematic side and top views, respectively, of an optical coupling portion in an optical chip package structure, and a corresponding diagram of an optical mode field, in an embodiment of the present disclosure.

Fig. 15 shows graphs of optical transmission rates of optical coupling parts at different lengths in an optical chip package structure of an embodiment of the present disclosure.

Fig. 16 shows graphs of optical transmission rates of optical coupling parts at different pitches in an optical chip package structure of an embodiment of the present disclosure.

Fig. 17 shows graphs of optical transmission rates of optical coupling parts at different thicknesses in an optical chip package structure of an embodiment of the present disclosure.

Fig. 18 and 19 show another schematic side and top views, respectively, of an optical coupling portion in an optical chip package structure, and a corresponding diagram of an optical mode field, in an embodiment of the present disclosure.

Fig. 20 and 21 show a cross-sectional view and a top view, respectively, of a photo chip package structure of an embodiment of the present disclosure.

Fig. 22 shows a cross-sectional view of an optical chip and an electrical chip in an optical chip package structure of an embodiment of the present disclosure.

Fig. 23 shows a cross-sectional view of an optical chip and an electrical chip in an optical chip package structure of an embodiment of the present disclosure.

Fig. 24 shows a cross-sectional view of a photo chip package structure of an embodiment of the present disclosure.

Fig. 25 shows a cross-sectional view of a photo chip package structure of an embodiment of the present disclosure.

Fig. 26 and 27 show a cross-sectional view and a top view, respectively, of a photo chip package structure of an embodiment of the present disclosure.

Fig. 28, and fig. 29A-29B show cross-sectional and top views, respectively, of a photo chip package structure of an embodiment of the present disclosure.

FIG. 30 illustrates a schematic diagram of a computational accelerator of an embodiment of the present disclosure.

FIG. 31A shows a schematic diagram of another computing accelerator of an embodiment of the present disclosure.

Fig. 31B shows a schematic diagram of yet another computational accelerator of an embodiment of the present disclosure.

Fig. 32-37 illustrate a flow chart of a method of manufacturing an optical chip package structure according to an embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While the drawings illustrate some embodiments of the present disclosure, it should be understood, however, that the present disclosure should not be construed as limited to the embodiments set forth herein, but rather, that these embodiments are provided so that this disclosure will be more thorough and complete. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order and/or performed in parallel. In addition, method embodiments may include other steps and/or omit certain steps.

Embodiments of the present disclosure provide an interposer for optical chip packaging. Fig. 1 shows a cross-sectional view of a interposer 100 for optical chip packaging in accordance with an embodiment of the present disclosure. Fig. 5 shows a process flow diagram of a method of manufacturing the interposer 100 of an embodiment of the present disclosure. For a clearer description of the present disclosure, a specific structure and a manufacturing method of the interposer 100 will be described below with reference to fig. 1 and 5, respectively.

As shown in fig. 1, the interposer 100 may be divided into three layers in the overall structure, namely, a dielectric layer 103, a glass substrate 101, and an optical waveguide structure 102 in this order from bottom to top.

The material of the glass substrate 101 is typically silicon dioxide, which includes one or more conductive vias, only one conductive via 101-1 being shown in fig. 1 for ease of description. As shown, the conductive via 101-1 includes a via hole penetrating the glass substrate 101 and a conductive material filled in the via hole (indicated by a lateral hatching in the drawing).

The optical waveguide structure 102 is arranged on a first surface (upper surface as shown) of the glass substrate 101. Typically, the optical waveguide structure 102 includes one or more optical waveguides and a cladding layer that cladding the one or more optical waveguides. In fig. 1, only one layer of optical waveguide 102-1 and cladding layer 102-2 cladding the optical waveguide are shown for ease of description. In the case of multiple optical chips packaged on interposer 100, one or more layers of optical waveguides in optical waveguide structure 102 may be used to optically interconnect the multiple optical chips packaged thereon. The refractive index of one or more optical waveguides in the optical waveguide structure 102 is greater than the refractive index of the cladding layer 102-2 and the glass substrate 101, for example, the one or more optical waveguides may be silicon nitride optical waveguides having a higher refractive index, and the materials of the cladding layer 102-2 and the glass substrate 101 may be silicon dioxide having a relatively lower refractive index.

As shown in fig. 1, the optical waveguide structure 102 further includes one or more first conductive structures 102-3 penetrating the optical waveguide structure, which are electrically connected to the one or more conductive vias 101-1 in the glass substrate, respectively. One or more first conductive structures 102-3 as shown may be used to make vertical electrical connections to an optical or electrical chip packaged on a interposer. The first conductive structure 102-3 may be a plug (plug) structure, such as a copper plug, although other metallic or conductive materials may be included.

A dielectric layer 103 is disposed on a second surface (lower surface as shown) of the glass substrate 101, which includes one or more second conductive structures extending through the dielectric layer. On the surface of the dielectric layer 103 on the side remote from the glass substrate 101 (i.e., the lower surface as shown), one or more conductive bumps 104 are arranged, which are electrically connected to the one or more second conductive structures, respectively. For example, the second conductive structure may include a rewiring layer 103-3 and an underlying conductive via structure 103-2 as shown, depending on the needs of the electrical connection. Conductive bumps 104 may be controlled collapse chip connection (C4) bumps, ball Grid Array (BGA) connectors, solder balls, metal posts, micro bumps, and the like. The conductive bumps 104 may comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive bumps 104 may be formed by first forming a solder layer by conventional methods such as evaporation, electroplating, printing, and the like. In some embodiments, the conductive bumps 104 are metal pillars, such as copper pillars, formed by sputtering, electroplating, electroless plating, or the like.

Note that, the interposer 100 may not include the dielectric layer 103 and the conductive bump 104.

The specific structure of the interposer 100 for optical chip package is described above in connection with fig. 1, and a method of manufacturing the interposer 100 will be described in detail in connection with fig. 5.

As shown in fig. 5, in step (a), a glass substrate 101 is first provided, and one or more conductive vias 101-1 are formed in the glass substrate 101. In some embodiments, the conductive via 101-1 may be formed in the glass substrate 101 by etching and electroplating. For example, one or more vias may first be formed in a glass substrate by laser drilling etching, and then a layer of conductive material is provided on the inner surface of the one or more vias to form the one or more conductive vias. Specifically, the conductive via may be formed by filling the inner surfaces of one or more vias with a conductive metal, for example, using a bottom-up plating method.

After the conductive via 101-1 is formed in the glass substrate 101, in steps (b) - (c), an optical waveguide structure may be disposed on the first surface (upper surface as shown) of the glass substrate 101. For example, as shown in (b) - (c), the optical waveguide structure includes one or more optical waveguides 102-1 and a cladding layer 102-2 cladding the one or more optical waveguides. For ease of description, only an example of a single layer optical waveguide is shown in fig. 5.

Specifically, in step (b), the optical waveguide 102-1 may be formed on the first surface of the glass substrate 101 using, for example, a wafer-level nanoimprint lithography technique.

It should be noted that, compared to the nanoimprint lithography of the prior art, the wafer level nanoimprint lithography employed in the present disclosure is improved as follows. To achieve wafer level waveguide routing without the reticle size limitations of typical stepper lithography, the present disclosure uses wafer level maskless lithography techniques, such as e-beam or laser writing. For example, an imprint master may first be fabricated using an oxide, nitride stack that is patterned using e-beam lithography. Then, by using the imprint master, a step-and-repeat operation is performed to generate a polymer (e.g., PDMS, polydimethylsiloxane) -based nano-stamp on the polymer. The nano-stamp is wafer-level, that is, the entire optical waveguide pattern is formed integrally and coherently in the same nano-stamp by the step-and-repeat operation as described above. When nanoimprinting is performed on a nitride deposited glass wafer using the resulting wafer level nano-stamp, the resist pattern is transferred to the glass wafer at one time, facilitating the formation of an integrally formed nitride waveguide, as compared to conventional amorphous wafer level stamps. The conventional amorphous wafer level stamp needs to be stamped for multiple times to splice waveguides, and misalignment is easy to occur in the multiple stamping process, so that the quality of the optical waveguide is affected, and further optical signal loss is caused.

By the wafer-level nanoimprint method, the formed optical waveguide is continuous in the whole glass wafer, waveguide splicing is not needed in the middle, and optical signal loss can be avoided to the greatest extent.

Then in step (c), cladding material is deposited over optical waveguide 102-1 to form cladding layer 102-2. The above steps (b) - (c) may be repeated depending on the specific needs, thereby enabling the formation of an optical waveguide structure having a multilayer optical waveguide. In addition, in the step (c), one or more first conductive structures 102-3 penetrating the optical waveguide structure may be formed in the clad layer 102-2 and electrically connected to one or more conductive vias 101-1 in the glass substrate 101, respectively.

As described above, the refractive index of the optical waveguide 102-1 is larger than that of the clad layer 102-2 and the glass substrate 101, for example, the optical waveguide 102-1 may be a silicon nitride optical waveguide having a higher refractive index, and the materials of the clad layer 102-2 and the glass substrate 101 may be silicon dioxide having a relatively lower refractive index.

Optionally, the method for manufacturing the interposer 100 may further include: a dielectric layer 103 is arranged on the second surface of the glass substrate 101, one or more second conductive structures penetrating the dielectric layer 103 are formed in the dielectric layer and electrically connected with the one or more conductive vias 101-1, respectively, and one or more conductive bumps 104 are arranged on the surface of the dielectric layer 103 on the side remote from the glass substrate.

Steps (d) - (f) in fig. 5 illustrate exemplary detailed steps of the process flow described above.

For example, in the step (d), the rewiring layer 103-3 may be formed on the bottom surface of the glass substrate 101 for electrical connection. Next, in step (e), a dielectric layer 103 is disposed on the bottom surface of the glass substrate 101 and is made to cover a portion of the rewiring layer 103-3 formed in (d), while a notch 103-4 corresponding to the rewiring layer 103-3 and the conductive via 101-1 needs to be formed in the dielectric layer 103, so that the conductive via structure 103-2 is electrically connected to the rewiring layer 103-3 and the conductive via 101-1 in the glass substrate by filling a conductive material in the notch 103-4 to form a conductive via structure 103-2 in step (f). In this case, the conductive via structure 103-2 and the rewiring layer 103-3 together constitute the above-described second conductive structure, which penetrates the dielectric layer 103 and is electrically connected to the conductive via 101-1 in the glass substrate 101.

In step (f), one or more conductive bumps 104 are arranged on the surface of the dielectric layer 103 on the side away from the glass substrate, and the conductive bumps 104 are electrically connected with the second conductive structures (i.e., the conductive via structures 103-2 and the rewiring layer 103-3).

To this end, a specific structure and manufacturing method of the interposer 100 used in the first example of the optical chip package are described with reference to fig. 1 and 5. By arranging the optical waveguide structure on the surface of the glass substrate, optical interconnection between optical chips packaged on the adapter plate can be realized, so that the cost problem and the process difficulty problem of manufacturing the silicon adapter plate of the embedded TSV are avoided. In addition, since the optical waveguide is formed in the glass substrate using the wafer-level nanoimprint method as described above, the formed optical waveguide is continuous throughout the glass wafer, and waveguide splicing is not required in the middle, so that optical signal loss can be maximally avoided.

A specific structure and a manufacturing method of another example of the interposer for optical chip package will be described below with reference to fig. 2 and 6, respectively. Fig. 2 shows a cross-sectional view of a interposer 200 for optical chip packaging in accordance with an embodiment of the present disclosure. Fig. 6 shows a process flow diagram of a method of manufacturing an interposer 200 of an embodiment of the present disclosure.

As shown in fig. 2, the interposer 200 may be similarly divided into three layers in the overall structure, namely, a dielectric layer 203, a glass substrate 201, and an optical coupling structure 202 in this order from bottom to top.

The material of the glass substrate 201 is typically silicon dioxide, which includes one or more conductive vias, only one conductive via 201-1 being shown in fig. 2 for ease of description. As shown, the conductive via 201-1 includes a via penetrating the glass substrate 201 and a conductive material filled in the via (indicated by a lateral hatching in the drawing).

In addition, the glass substrate 201 further includes a three-dimensional waveguide network 201-2 (as shown in the graph) for optically interconnecting the plurality of optical chips packaged on the interposer 201. The three-dimensional waveguide network 201-2 is configured by inducing a partial glass inside the glass substrate 201 to increase the refractive index of the partial glass, and has a three-dimensional network structure formed by a plurality of channels distributed throughout the inside of the glass substrate 201. For example, an ultrafast (e.g., femtosecond) laser inscription process can be used to create an embedded three-dimensional waveguide network inside a glass substrate.

The optical coupling structure 202 is disposed on a first surface (e.g., an upper surface) of the glass substrate 201. As shown, the optical coupling structure 202 includes a coupling optical waveguide 202-1 covering the optical input/output ports of the three-dimensional waveguide network 201-2 and a cladding layer 202-2 cladding the coupling optical waveguide 202-1. Furthermore, the optical coupling structure 202 comprises one or more first conductive structures 202-3 extending through the optical coupling structure, which are electrically connected to one or more conductive vias 201-1 in the glass substrate 201, respectively.

It should be noted that the refractive index of the coupling optical waveguide 202-1 may be lower than the refractive index of the three-dimensional waveguide network 201-2, but higher than the refractive index of the cladding layer 202-2. For example, the coupling optical waveguide 202-1 may be a silicon nitride optical waveguide and the material of the cladding layer 202-2 may be silicon dioxide. In addition, the interposer 200 includes the embedded optical waveguide 202-1 similar to the interposer 100 shown in fig. 1, but the functions of the two are different. In the interposer 100 shown in fig. 1, the optical waveguides 102-1 in the optical waveguide structure 102 are used for optical interconnection between different optical chips, but in the interposer 200 shown in fig. 2, the coupled optical waveguides 202-1 in the optical coupling structure 202 are used for optical "coupling" action, which can improve optical coupling efficiency between the three-dimensional waveguide network and the optical chips.

Similar to the interposer 100, the dielectric layer 203 in the interposer 200 is disposed on a second surface (lower surface as shown) of the glass substrate 201, which includes one or more second conductive structures extending through the dielectric layer. On the surface of the dielectric layer 203 on the side remote from the glass substrate 201 (i.e. the lower surface as shown) one or more conductive bumps 204 are arranged, which are electrically connected to the one or more second conductive structures, respectively. The second conductive structure may include a rewiring layer 203-3 and an underlying conductive via structure 203-2 as shown, as desired for electrical connection. The conductive bumps 204 may be controlled collapse chip connection (C4) bumps, ball Grid Array (BGA) connectors, solder balls, metal pillars, micro bumps, etc., which are similar to the conductive bumps 104 described in fig. 1 and will not be described again here.

Note that, the interposer 200 may not include the dielectric layer 203 and the conductive bump 204.

The specific structure of the interposer 200 for optical chip package is described above in connection with fig. 2, and a method of manufacturing the interposer 200 will be described in detail below in connection with fig. 6.

As shown in fig. 6, first, in step (a), a glass substrate 201 is provided, and a three-dimensional waveguide network 201-2 for optically interconnecting a plurality of optical chips packaged on an interposer is formed within the glass substrate 201. In some examples, an ultrafast (e.g., femtosecond) laser inscription process may be used to create an embedded three-dimensional waveguide network inside the glass substrate. For example, a predetermined position of the glass substrate 201 may be irradiated with a femtosecond laser to increase the refractive index of the predetermined position of the glass substrate 201, thereby forming the three-dimensional waveguide network 201-2. For example, the preset position may be a position where a three-dimensional waveguide network structure is formed.

Then, in step (b), one or more conductive vias 201-1 are formed in the glass substrate 201. In some embodiments, the conductive via 201-1 may be formed in the glass substrate 201 by etching and electroplating. For example, one or more vias may first be formed in a glass substrate by laser drilling etching, and then a layer of conductive material is provided on the inner surface of the one or more vias to form the one or more conductive vias. Specifically, the conductive via may be formed by filling the inner surfaces of one or more vias with a conductive metal, for example, using a bottom-up plating method.

After the conductive via 201-1 is formed in the glass substrate 201, in steps (c) - (d), an optical coupling structure may be disposed on the first surface (upper surface as shown) of the glass substrate 201. For example, as shown, the optical coupling structure includes a coupled optical waveguide 202-1 and a cladding layer 202-2 cladding the coupled optical waveguide. Specifically, in step (c), the coupling optical waveguide 202-1 may be formed on the first surface of the glass substrate 201 using a photolithography technique so as to cover the optical input/output port of the three-dimensional waveguide network 201-2. Then in step (d), cladding material is deposited over the coupled optical waveguide 202-1 to form cladding layer 202-2. In addition, in the step (d), one or more first conductive structures 202-3 penetrating the optical coupling structure may be formed in the clad layer 202-2 and electrically connected to one or more conductive vias 201-1 in the glass substrate 201, respectively.

It should be noted that the refractive index of the coupling optical waveguide 202-1 may be larger than the refractive index of the cladding layer 202-2 and the glass substrate 201, for example, the coupling optical waveguide 202-1 may be a silicon nitride optical waveguide having a higher refractive index, and the materials of the cladding layer 202-2 and the glass substrate 201 may be silicon dioxide having a relatively lower refractive index.

Optionally, the method for manufacturing the interposer 200 may further include: a dielectric layer 203 is disposed on a second surface of the glass substrate 201, one or more second conductive structures penetrating the dielectric layer 203 are formed in the dielectric layer and electrically connected with the one or more conductive vias 201-1, respectively, and one or more conductive bumps 204 are disposed on a surface of the dielectric layer 203 on a side remote from the glass substrate.

Steps (e) - (g) in fig. 6 show example detailed steps of the above-described process flow.

For example, first, in step (e), the rewiring layer 203-3 may be formed on the bottom surface of the glass substrate 201 for electrical connection. Next, in step (f), a dielectric layer 203 is disposed on the bottom surface of the glass substrate 201 and is made to cover a portion of the rewiring layer 203-3 formed in (e), while a notch 203-4 corresponding to the rewiring layer 203-3 and the conductive via 201-1 needs to be formed in the dielectric layer 203, so that the conductive via structure 203-2 is electrically connected to the rewiring layer 203-3 and the conductive via 201-1 in the glass substrate by filling a conductive material in the notch 203-4 to form a conductive via structure 203-2 in step (g). In this case, the conductive via structure 203-2 and the rewiring layer 203-3 together constitute the second conductive structure described above, which penetrates the dielectric layer 203 and is electrically connected to the conductive via 201-1 in the glass substrate 201.

In step (g), one or more conductive bumps 204 are disposed on the surface of the dielectric layer 203 on the side remote from the glass substrate, and the conductive bumps 204 are electrically connected to the second conductive structures (i.e., the conductive via structures 203-2 and the rewiring layer 203-3).

Thus far, a specific structure and manufacturing method of the interposer 200 used in the second example of the optical chip package are described in conjunction with fig. 2 and 6. The interposer 200 interconnects the plurality of optical chips packaged above the interposer 200 by forming a three-dimensional optical waveguide network inside the glass substrate, so that a richer and more efficient three-dimensional optical waveguide path can be formed without increasing the thickness of the interposer, thereby effectively compressing the volume of the optical chip package. In addition, as the silicon nitride coupling optical waveguide is further arranged at the optical input and output positions of the three-dimensional optical waveguide network, the optical coupling efficiency between the optical chip and the adapter plate can be greatly improved.

A specific structure and a manufacturing method of another example of the interposer for optical chip package will be described below with reference to fig. 3 and 7A, respectively. Fig. 3 illustrates a cross-sectional view of an interposer 300 for an optical chip package in accordance with an embodiment of the present disclosure. Fig. 7A shows a process flow diagram of a method of manufacturing an interposer 300 of an embodiment of the present disclosure.

As shown in fig. 3, the interposer 300 may be divided into three layers in the overall structure, namely, a dielectric layer 303, a glass substrate 301, and an electrical interconnect structure 302 in order from bottom to top.

Similarly, the material of the glass substrate 301 is typically silicon dioxide, which includes one or more conductive vias, only one conductive via 301-1 being shown in FIG. 3 for ease of description. As shown, the conductive via 301-1 includes a via penetrating the glass substrate 301 and a conductive material filled in the via (indicated by a lateral hatching in the drawing).

The electrical interconnect structure 302 is disposed on a first surface (upper surface as shown) of the glass substrate 301. In some examples, the electrical interconnect structure 302 may include one or more wiring layers 302-1a, 302-1b, 302-1c and a cladding layer 302-2 cladding the one or more wiring layers. For example, the cladding layer 302-2 may be a dielectric material and one or more wiring layers 302-1a, 302-1b, 302-1c are used to electrically interconnect a plurality of electrical chips on an optical chip packaged on a interposer. The electrical chip may be packaged vertically with the optical chip, i.e. the electrical chip is packaged on the optical chip, so that the electrical chip may be electrically connected to the wiring layer through conductive vias in the optical chip to achieve electrical interconnection of the electrical chip. In addition, the optical chips disposed on the interposer may be active optical chips, and the respective active optical chips may be electrically connected through the above-described electrical interconnection structure 302.

FIG. 3 shows an example of an electrical interconnect structure 302 having three wiring levels (302-1 a,302-1b,302-1 c). As shown, each wiring layer is covered by a respective covering layer. For example, with respect to the wiring layer 302-1a, it is covered with a multilayer structure formed by alternately stacking the silicon nitride layers 302-2a and the silicon oxide layers 302-2 b. As for the wiring layers 302-1b and 302-1c, they are also covered with a multilayer structure formed by alternately stacking similar silicon nitride layers and silicon oxide layers. It should be understood that the three wiring levels shown in fig. 3 are merely exemplary, and that more (e.g., four or more) or fewer (e.g., two or more) wiring levels may be selected as desired.

In addition, as shown, the electrical interconnect structure 302 also includes one or more first conductive structures 302-3 extending through the electrical interconnect structure that are electrically connected with one or more first conductive vias 301-1, respectively, in the glass substrate.

Fig. 3 also shows a second conductive structure 302-4 for making electrical connection between at least two of the multiple wiring levels. The second conductive structure 302-4 may be formed in a similar manner or material as the first conductive structure 302-3, for example, may be a conductive via or copper plug, or may include other metallic or conductive materials.

A dielectric layer 303 is disposed on a second surface (lower surface as shown) of the glass substrate 301, which includes one or more second conductive structures extending through the dielectric layer. On the surface of the dielectric layer 303 on the side remote from the glass substrate 301 (i.e. the lower surface as shown) one or more conductive bumps 305 are arranged, which are electrically connected to the one or more second conductive structures, respectively. The second conductive structure may include a rewiring layer 303-3 and an underlying conductive via structure 303-2 as shown, as desired for electrical connection. Conductive bumps 305 may be controlled collapse chip connection (C4) bumps, ball Grid Array (BGA) connectors, solder balls, metal posts, micro bumps, and the like. The conductive bump 305 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive bump 305 may be formed by first forming a solder layer by conventional methods such as evaporation, electroplating, printing, and the like. In some embodiments, the conductive bump 305 is a metal pillar, such as a copper pillar, formed by sputtering, electroplating, electroless plating, or the like.

Note that the interposer 300 may not include the dielectric layer 303 and the conductive bump 305.

The specific structure of the interposer 300 for optical chip package is described above in connection with fig. 3, and a method of manufacturing the interposer 300 will be described in detail below in connection with fig. 7A.

As shown in fig. 7A, in step (a), a glass substrate 301 is first provided, and one or more conductive vias 301-1 are formed in the glass substrate 301. In some embodiments, the conductive via 301-1 may be formed in the glass substrate 301 by etching and electroplating. For example, one or more vias may first be formed in a glass substrate by laser drilling etching, and then a layer of conductive material is provided on the inner surface of the one or more vias to form the one or more conductive vias. Specifically, the conductive via may be formed by filling the inner surfaces of one or more vias with a conductive metal, for example, using a bottom-up plating method.

In step (e), an electrical interconnect structure 302 is disposed on a first surface (i.e., an upper surface as shown) of the glass substrate 301. As shown, the electrical interconnect structure 302 includes one or more wiring layers (302-1 a,302-1b,302-1 c) and a cladding layer that encapsulates the one or more wiring layers. For example, the cladding layer may be a dielectric material and one or more wiring layers (302-1 a,302-1b,302-1 c) are used to electrically interconnect the plurality of electrical chips over the optical chips packaged on the interposer.

FIG. 7A shows an example of an electrical interconnect structure 302 having three wiring levels (302-1 a,302-1b,302-1 c). As shown, each wiring layer is covered by a respective covering layer. For example, with respect to the wiring layer 302-1a, it is covered with a multilayer structure formed by alternately stacking the silicon nitride layers 302-2a and the silicon oxide layers 302-2 b. As for the wiring layers 302-1b and 302-1c, they are also covered with a multilayer structure formed by alternately stacking similar silicon nitride layers and silicon oxide layers. It should be understood that the three wiring levels shown in fig. 3 are merely exemplary, and that more (e.g., four or more) or fewer (e.g., two or more) wiring levels may be selected as desired.

Specifically, taking (e) in fig. 7A as an example, disposing the electrical interconnection structure 302 on the first surface of the glass substrate 301 may include the following specific steps: first, a first wiring layer 302-1a is arranged on the upper surface of a glass substrate 301; then, a first silicon nitride sub-layer 302-2a is formed around the first wiring layer 302-1a, the thickness of the first silicon nitride sub-layer 302-2a being smaller than the thickness of the first wiring layer 302-1a; next, the first silicon nitride sub-layer 302-2a is covered with the first silicon oxide sub-layer 302-2b, and the total thickness of the first silicon nitride sub-layer 302-2a plus the first silicon oxide sub-layer 302-2b is made equal to the thickness of the first wiring layer 302-1 a. Thereafter, the above steps may be repeated as necessary, again sequentially disposing the second wiring layer 302-1b on the first silicon oxide sub-layer 302-2b, forming a second silicon nitride sub-layer around the second wiring layer 302-1b, covering the second silicon oxide sub-layer on the second silicon nitride sub-layer, and so on, thereby forming an electrical interconnect structure having a plurality of wiring layers.

Further, disposing the electrical interconnect structure 302 on the first surface of the glass substrate 301 may further include: a second conductive structure 302-4 is formed between the first wiring layer 302-1a and the second wiring layer 302-1b to electrically connect the first wiring layer 302-1a and the second wiring layer 302-1 b. For example, one or more vias may first be formed by laser drilling etching at locations in the electrical interconnect structure 302 that include a wiring layer, and then a layer of conductive material may be disposed on an inner surface of the one or more vias to form one or more second conductive structures 302-4. Specifically, the second conductive structure 302-4 may be formed by filling the inner surfaces of one or more of the vias with a conductive metal, for example, using a bottom-up plating method. Furthermore, as shown, in the case where the electrical interconnect structure 302 includes three wiring layers (302-1 a,302-1b,302-1 c), the second conductive structure 302-4 is also present between the second wiring layer 302-1b and the third wiring layer 302-1c, thereby electrically connecting the second wiring layer 302-1b and the third wiring layer 302-1c as well.

Further, disposing the electrical interconnect structure 302 on the first surface of the glass substrate 301 may further include: one or more first conductive structures 302-3 extending through the electrical interconnect structure are formed in the electrical interconnect structure 302 and electrically connected with one or more first conductive vias 301-1 in the glass substrate 301, respectively.

Optionally, in some embodiments, the method of manufacturing the interposer 300 may further include: a dielectric layer 303 is disposed on the second surface of the glass substrate 301, one or more fourth conductive structures penetrating the dielectric layer 303 are formed in the dielectric layer and electrically connected to the one or more conductive vias 301-1, respectively, and one or more conductive bumps 305 are disposed on the surface of the dielectric layer 303 on the side remote from the glass substrate.

Steps (b) - (d) in fig. 7A show detailed steps of the above-described process flow.

For example, in the step (b), a rewiring layer 303-3 may be formed on the second surface of the glass substrate 301 first for electrical connection. Next, in step (c), a dielectric layer 303 is disposed on the bottom surface of the glass substrate 301 and is made to cover a portion of the rewiring layer 303-3 formed in (b), while notches 303-4 corresponding to the rewiring layer 303-3 and the conductive vias 301-1 need to be formed in the dielectric layer 303, so that the conductive hole structures 303-2 are electrically connected to the rewiring layer 303-3 and the conductive vias 301-1 in the glass substrate by filling conductive material in the notches 303-4 to form conductive hole structures 303-2 in step (d). In this case, the conductive via structure 303-2 and the rewiring layer 303-3 together constitute the fourth conductive structure described above, which penetrates the dielectric layer 303 and is electrically connected to the conductive via 301-1 in the glass substrate 301.

In step (d), one or more conductive bumps 305 are disposed on the surface of the dielectric layer 303 on the side remote from the glass substrate, and the conductive bumps 305 are electrically connected to the fourth conductive structures (i.e., the conductive via structures 303-2 and the rewiring layer 303-3).

To this end, a specific structure and manufacturing method of the interposer 300 used in the first example of the optical chip package have been described in conjunction with fig. 3 and 7A. By arranging the electrical interconnect structure on the surface of the glass substrate, electrical interconnection between the electrical chips over the optical chips packaged on the interposer can be achieved.

A specific structure and a manufacturing method of another example of the interposer for optical chip package will be described below with reference to fig. 4 and fig. 7A-7B, respectively. Fig. 4 shows a cross-sectional view of a interposer 400 for optical chip packaging in accordance with an embodiment of the present disclosure. Fig. 7A-7B illustrate a process flow diagram of a method of manufacturing an interposer 400 of an embodiment of the present disclosure.

As shown in fig. 4, the interposer 400 may be divided into four layers in the overall structure, from bottom to top, which are the dielectric layer 303, the glass substrate 301, the electrical interconnection layer 302, and the optical waveguide structure 304 in order, wherein the arrangement and functions of the dielectric layer 303, the glass substrate 301, and the electrical interconnection layer 302 are similar to those of the interposer 300 shown in fig. 3, and will not be repeated herein.

The interposer 400 shown in fig. 4 additionally includes an optical waveguide structure 304 as compared to the interposer 300 shown in fig. 3. As shown, the optical waveguide structure 304 is arranged on a surface (i.e., upper surface) of the electrical interconnect structure 302 on a side away from the glass substrate 301. In some examples, optical waveguide structure 304 may include one or more layers of optical waveguide 304-1 and an enclosing layer 304-2 enclosing one or more layers of optical waveguide 304-1. It should be noted that, for simplicity of explanation, only an example of the optical waveguide structure having one layer of the optical waveguide 304-1 is shown in fig. 4, but this is merely exemplary, and two, three, or more layers of the optical waveguide may be arranged as needed. The optical waveguide 304-1 is shown for optically interconnecting a plurality of optical chips packaged on the interposer 400, and the refractive index of the optical waveguide 304-1 is greater than the refractive index of the surrounding layer 304-2.

In addition, as shown, the optical waveguide structure 304 also includes one or more third conductive structures 304-3 extending therethrough that are respectively electrically connected to one or more first conductive structures in the electrical interconnect structure 302.

The manufacturing method of the interposer 400 shown in fig. 4 includes step (f) shown in fig. 7B in addition to steps (a) - (e) shown in fig. 7A. Steps (a) - (e) have been described in detail in relation to the method of manufacturing the adapter plate 300, and are not described here again.

After the interposer including the electrical interconnect structure 302 is formed as shown in (e) of fig. 7A, the method of manufacturing the interposer 400 further includes: in step (f), an optical waveguide structure 304 is arranged on a surface of the electrical interconnect structure 302 on a side away from the glass substrate 301. As described above with respect to fig. 4, optical waveguide structure 304 may include one or more optical waveguides 304-1 and an enclosing layer 304-2 enclosing one or more optical waveguides 304-1. Optical waveguide structure 304 may be formed using similar techniques as described with respect to fig. 5, for example, an encasing layer material may first be deposited over electrical interconnect structure 302, then optical waveguide 304-1 may be formed over the deposited encasing layer material using wafer-level nanoimprint lithography techniques, and then encasing layer material may be deposited over optical waveguide 304-1 again to completely encase optical waveguide 304-1 to form encasing layer 304-2. For simplicity of illustration, only an example of an optical waveguide structure having one layer of optical waveguide 304-1 is shown in fig. 7B, but this is merely exemplary, and two, three, or more layers of optical waveguides may be arranged as desired. The one or more optical waveguides 304-1 are used to optically interconnect a plurality of optical chips packaged on the interposer, and the refractive index of the optical waveguides 304-1 is greater than the refractive index of the surrounding layer 304-2. For example, one or more of optical waveguides 304-1 may be a silicon nitride optical waveguide and the material surrounding layer 304-2 is silicon dioxide.

Also, it should be noted that with respect to the method of forming the optical waveguide 304-1, the wafer level nanoimprint lithography technique employed by the present disclosure is improved as follows over nanoimprint techniques of the prior art. To achieve wafer level waveguide routing without the reticle size limitations of typical stepper lithography, the present disclosure uses wafer level maskless lithography techniques, such as e-beam or laser writing. For example, an imprint master may first be fabricated using an oxide, nitride stack that is patterned using e-beam lithography. Then, by using the imprint master, a step-and-repeat operation is performed to generate a polymer (e.g., PDMS, polydimethylsiloxane) -based nano-stamp on the polymer. The nano-stamp is wafer-level, that is, the entire optical waveguide pattern is formed integrally and coherently in the same nano-stamp by the step-and-repeat operation as described above. When nanoimprinting is performed on a nitride deposited glass wafer using the resulting wafer level nano-stamp, the resist pattern is transferred to the glass wafer at one time, facilitating the formation of an integrally formed nitride waveguide, as compared to conventional amorphous wafer level stamps. The conventional amorphous wafer level stamp needs to be stamped for multiple times to splice waveguides, and misalignment is easy to occur in the multiple stamping process, so that the quality of the optical waveguide is affected, and further optical signal loss is caused.

In addition, the manufacturing method of the interposer 400 may further include: in step (f), one or more third conductive structures 304-3 extending through the optical waveguide structure are formed in the optical waveguide structure 304 and electrically connected to one or more first conductive structures in the electrical interconnect structure 302, respectively.

Thus far, a specific structure and manufacturing method of the interposer 400 used in the first example of the optical chip package have been described in connection with fig. 4 and fig. 7A-7B. By disposing the electrical interconnection structure on the surface of the glass substrate and disposing the optical waveguide structure on the electrical interconnection structure, it is possible to make electrical interconnection between the electrical chips packaged on the interposer and make optical interconnection between the optical chips packaged on the interposer. In addition, by the wafer-level nanoimprint method, the formed optical waveguide is continuous in the whole glass wafer, waveguide splicing is not needed in the middle, and optical signal loss can be avoided to the greatest extent.

It should be understood that the various steps recited in the method embodiments and figures of the present disclosure may be performed in a different order, and/or performed in parallel, as desired. In addition, method embodiments may include other steps and/or omit certain steps.

It should be noted that, in the description above for the interposer, although the corresponding conductive structures and the method of manufacturing the same are described for each layer of the interposer (e.g., the optical waveguide structure 102 and the dielectric layer 103 in fig. 1), such as the first conductive structure 102-3 in the optical waveguide structure 102 and the second conductive structure 103-2 in the dielectric layer 103 in fig. 1, these conductive structures need not be separate and may be integrally formed, such as the first conductive structure 102-3 and the second conductive structure 103-2 in the dielectric layer 103 may be integrally formed copper plugs throughout the interposer 100 in some embodiments. Such an integrally formed copper plug is equally applicable to other adaptor plates as shown in fig. 2-4.

Some embodiments of the structure and manufacturing method of the glass wafer-based interposer of the present disclosure are described above. Compared with a silicon adapter plate with embedded TSVs, the glass wafer-based adapter plate is simple in structure, low in manufacturing cost and easy to implement, can be effectively used for optical interconnection of optical chips and electrical interconnection of electrical chips, and provides a good platform for integration of the optical chips.

By using the interposer in the various embodiments described above, a compact, three-dimensional package structure including an optical chip and an electrical chip can be achieved. Fig. 8-11 illustrate cross-sectional views of various optical chip package structures incorporating interposer in embodiments of the present disclosure.

As shown in fig. 8, the package structure 800 includes the interposer 100 and the optical chip 500. For example, the interposer 100 may be an interposer 100 with embedded optical waveguides as shown in fig. 1, and the interposer 100 may be used to optically interconnect optical chips of a plurality of photonic-electronic hybrid chips disposed thereon, and electrically interconnect electrical chips of the plurality of photonic-electronic hybrid chips. Preferably, the optical chip is prepared on the SOI substrate, after the front end preparation process of the optical chip is completed, the bottom silicon substrate in the SOI substrate is removed, the thickness of the buried oxide layer is controlled, the optical chip is bonded to the interposer 100, and the optical signal is adiabatically coupled into the optical waveguide on the optical chip through the embedded optical waveguide on the interposer 100, and vice versa, so that on-chip optical network communication is realized. It should be understood that for simplicity of illustration, only one optical chip 500 is shown in fig. 8, and in practical applications, two or more optical chips may be disposed on interposer 100, which may be optically interconnected by embedded optical waveguides in interposer 100. Further, as shown, the optical chip 500 also includes one or more interconnect structures 501, the interconnect structures 501 including vias extending through the optical chip and conductive material filling the vias. As shown, the interconnect structure 501 is electrically connected to one or more of the first conductive structures 102-3, respectively, on the interposer 100 as previously described.

In some examples, the package structure 800 may also include one or more optical chips, each having one or more electrical chips (EIC's in fig. 8-11) disposed thereon. Typically, one or more electrical chips EIC are arranged above the optical chip 500 and are electrically connected vertically with conductive structures in the interposer by conductive structures in the electrical chip (UBM or other connection structures as shown, such as direct bonding, etc.).

Fig. 9 to 11 show example structures of packages in which the interposer corresponding to fig. 2 to 4 is applied to an optical chip, respectively. The optical chip 500 is similar to that in fig. 8, and will not be described here. It should be noted that, as shown in fig. 10, when the interposer 300 having the electrical interconnect structure shown in fig. 3 is applied to the package structure 1000, the interconnect structure 501 in the optical chip 500 may be electrically connected to the conductive structure 302-3 in the electrical interconnect layer of the interposer 300.

Further, as described above, the conductive structures in the various layers of the interposer need not be separate, but may be integrally formed, e.g., the conductive structures in the various layers may be integrally formed copper plugs that extend through the entire interposer, thereby facilitating electrical connection between the interposer and the electrical chip.

It should be noted that, in the interposer described above in connection with fig. 1-2 and 4, optical waveguides for optically interconnecting a plurality of optical chips disposed on the interposer, such as the optical waveguide 102-1 in fig. 1, 202-1 and 202-2 in fig. 2, and 304-1 in fig. 4, are disposed. The optical coupling between the optical waveguide and the optical chip in the interposer may be achieved by, for example, externally connecting an optical fiber, which occupies a space that is not conducive to miniaturization of the package structure. The embodiment of the disclosure provides a mode of coupling the optical chip and the optical waveguide in the adapter plate by adopting adiabatic coupling so as to realize miniaturization of products. Various embodiments of a light chip package structure and a method of manufacturing the same employing adiabatic coupling technology of such an optical waveguide will be described in detail below. It should be noted that, in the present disclosure, the interposer for adiabatic coupling is not limited to the interposer described in the present disclosure, but may be any interposer capable of realizing optical interconnection of optical chips.

Fig. 12A and 12B show a cross-sectional view and a top view, respectively, of a photo chip package structure 1200 of an embodiment of the disclosure.

As shown in fig. 12A, the optical chip package structure 1200 includes an interposer 1210 and a plurality of optical chips (PICs) disposed on the interposer 1210, and typically, the optical chips are fabricated using an SOI substrate, and optical waveguides in the optical chips are disposed on a buried oxide layer of the SOI substrate. For example, since fig. 12A shows a sectional view cut from a specific position, only two optical chips PIC1 and PIC2 can be seen in fig. 12A. In practice, however, as shown in the top view of fig. 12B, the microchip package structure 1200 may include six optical chips PIC1-PIC 6. It should be understood that the six photo-chips described above are merely exemplary and not limiting, and that in practical applications, the photo-chip package structure 1200 may include more or fewer photo-chips.

As shown in fig. 12A, the interposer 1200 includes one or more first optical waveguides embedded therein, such as the optical waveguides WG1-1 and the optical waveguides WG1-2 shown in fig. 12A, wherein the optical waveguides WG1-1 and the optical waveguides WG1-2 may be a waveguide network formed by an array of a plurality of optical waveguides arranged. The optical waveguides WG1-1 and WG1-2 may be optical waveguides in an interposer as previously described, such as optical waveguide 102-1 in FIG. 1, optical waveguides 202-1 and 202-2 in FIG. 2, or optical waveguide 304-1 in FIG. 4. Further, the materials of the optical waveguide WG1-1 and the optical waveguide WG1-2 may be silicon nitride as described above, and a cladding layer of silicon oxide is covered over the silicon nitride.

Each of the optical chips PIC 1 and PIC 2 includes one or more second optical waveguides (only a single optical waveguide is shown for each PIC in fig. 12A for simplicity of illustration), that is, the optical waveguides WG2-1 and the optical waveguides WG2-2, embedded therein. In some examples, the material of optical waveguides WG2-1 and WG2-2 may be silicon. As shown in fig. 12B, a plurality of optical chips (PIC 1, …, PIC 6) are attached to the upper surface of the interposer 1210 at different positions. As shown, PIC 1-PIC 6 are attached to interposer 1210 at different locations in square region R1 and spaced apart from each other.

The optical chips PIC1 and PIC2, or any two of the plurality of optical chips (PIC 1, …, PIC 6) as shown in fig. 12B, may be optically interconnected by one or more first optical waveguides in the interposer 1210. For example, as shown by the arrowed dashed line in FIG. 12A, light may originate from PIC1, then couple through WG2-1 into optical waveguide WG1-1 in interposer 1210, then transmit through other optical waveguide network (not shown) into optical waveguide WG1-2, and then couple into optical waveguide WG2-1 in PIC 2. Specifically, each of the first optical waveguides may include a first optical coupling portion, and each of the second optical waveguides may include a second optical coupling portion (not shown in the drawings), and for simplicity, the end portions of the optical waveguides WG2-1 and WG1-1 may be regarded as respective optical coupling portions, for example. For example, the optical coupling portions of the optical waveguides WG2-1 and WG1-1 are stacked and spaced apart by a predetermined distance (e.g., less than 600 nm) in a direction perpendicular to the upper surface of the interposer 1210, so that adiabatic coupling of light between the optical coupling portions of the optical waveguides WG2-1 and WG1-1 can be achieved. Of course, the optical chip PIC1 and the optical chip PIC2 may be optically interconnected by one first optical waveguide, for example, the optical waveguide WG1-1 and the optical waveguide WG1-2 in fig. 12A may be different portions of one first optical waveguide. In case there are a plurality of first optical waveguides, different first optical waveguides may enable optical interconnection between different optical chips. For example, one first optical waveguide may be used to connect PIC1 and PIC2, and the other first optical waveguide may be used to connect PIC1 and PIC 3 or PIC 3 and PIC4.

Fig. 13 and 14 show schematic side and top views, respectively, of an optical coupling portion in an optical chip package structure 1200 of an embodiment of the present disclosure, and a corresponding diagram of an optical mode field.

As shown in fig. 13, the coupling portion of the optical waveguide WG2-1 in the optical chip PIC 1 and the coupling portion of the optical waveguide WG1-1 in the interposer are stacked one above the other and spaced apart by a predetermined distance H.

In addition, in order to achieve high coupling efficiency, as shown in fig. 14, the coupling portion of the optical waveguide WG2-1 in the optical chip PIC 1 and the coupling portion of the optical waveguide WG1-1 in the interposer may have a tapered shape. Ideally, the coupling portion of the optical waveguide WG2-1 in the optical chip PIC 1 and the coupling portion of the optical waveguide WG1-1 in the interposer (i.e., two tapers as shown in fig. 14) should be aligned in both the lateral and longitudinal directions, so as to obtain maximum coupling efficiency. However, in real manufacturing, due to the limitation of the process, it is impossible to completely align the coupling portion of the optical waveguide WG2-1 in the optical chip PIC 1 with the coupling portion of the optical waveguide WG1-1 in the interposer in both the lateral and longitudinal directions, and in general, there are lateral misalignment LM and longitudinal misalignment TM as shown in fig. 14.

Taking the substrate of the optical chip as SOI and the optical waveguide on the adapter plate as SiN as an example, the main parameters with great influence on the coupling efficiency between the optical chip and the adapter plate are as follows: the width W4 of the optical waveguide WG1-1, the length L of the coupling portion of the optical waveguide WG2-1 and the coupling portion of the optical waveguide WG1-1, the distance H, and the thickness tSiN of the optical waveguide WG1-1 in the interposer.

For the width W4 of the optical waveguide WG1-1 in the adapter plate, the wider the W4 is, the better the coupling effect is on the basis of ensuring that the optical waveguide WG1-1 is a single-mode waveguide. Preferably, W4<1 μm can be chosen, since more than 1 μm easily becomes a multimode waveguide.

As for the length L of the coupling portion, the longer L is, the better the coupling effect, and fig. 15 is a graph of the coupling efficiency versus the lateral misalignment of different L in the case where w4=1 μm, h=200 nm, and when l=200 μm, the coupling loss can be controlled within 1dB when the lateral misalignment is 1 μm, and when l=1800 μm, the lateral misalignment is 1.5 μm, and the coupling loss can also be controlled within 1 dB.

For the distance H between the coupling portion of the optical waveguide WG2-1 and the coupling portion of the optical waveguide WG1-1, the smaller H is the better the coupling effect, but H includes the sum of the thickness after the buried oxide layer is thinned in the SOI of the optical chip and the thickness of the silicon oxide covered over the silicon nitride waveguide in the interposer, if the set H is too small, the buried oxide layer in the SOI is required to be thinner, and the thickness of the buried oxide layer is not uniform due to the limitation of the thinning process, so that the coupling efficiency is affected, and therefore, h=100 nm to 600nm is preferable. Fig. 16 is a graph showing the relationship between the coupling efficiency and lateral misalignment of different H in the case of w4=1 μm, l=200 μm, and tsin=200 nm. It can be seen that the coupling effect is optimal around h=200 nm, and that the coupling efficiency decreases more when the pitch is larger than 200nm and the same lateral misalignment occurs.

For the thickness tSiN of the optical waveguide WG1-1, too small a thickness of tSiN causes uneven thickness of the optical waveguide, and too large a thickness causes cracking due to internal stress, and therefore, tsin=100 nm to 300nm is preferable. Fig. 17 is a graph showing the relationship between the coupling efficiency and lateral misalignment of different tSiN in the case of w4=1 μm, l=200 μm, and h=200 nm. As can be seen from the figure, the coupling effect is optimal when tsin=200 nm.

In addition to the tapered coupling portions described above, in some embodiments, the coupling portions of the optical waveguides of the optical chip and the coupling portions of the optical waveguides of the interposer may have a shape formed by a concatenation of two tapered shapes of different sizes. Fig. 18 and 19 show a schematic diagram of such a coupling part having a shape formed by a concatenation of two differently sized conical shapes and a diagram of the corresponding optical mode field, respectively.

As shown in fig. 19, compared with the previous taper structure, the coupling portion of the optical waveguide of the optical chip and the coupling portion of the optical waveguide of the interposer are both increased by one taper transition structure with a length l_taper, that is, the optical coupling portion is formed by a cascade of a single taper structure and a two-stage taper structure. The tapered transition structure is added because there is a coincidence point between the silicon waveguide WG2-1 and the silicon nitride waveguide WG1-1 at a length of about 700nm for the silicon waveguide WG2-1 and about 300nm for the silicon nitride waveguide WG1-1, such as at the dashed line location shown in FIG. 19, with a dielectric constant n _{eff_Si} ≈n _{eff_SiN} At this coincidence point, both can be coupled quickly, and the structural coupling length l_trans can be greatly reduced from that of the previous cone-shaped structure, and optical coupling can be completed at about 10 μm. Also, in the same case, the silicon waveguide WG2-1 and the silicon nitride waveguide WG1-1 may also allow for longitudinal alignment misalignment and lateral alignment misalignment over a larger angle (the previous taper structure requires that the two waveguides have a small angular alignment error in the parallel direction).

An embodiment of an optical chip package structure according to the present disclosure is described above in connection with fig. 12A to 19, in which a plurality of optical chips can be optically connected to an interposer through adiabatic coupling by controlling a distance between an optical waveguide in the optical chip and an optical waveguide on the interposer and changing a structure of a coupling portion of the two waveguides, thereby realizing optical interconnection between the plurality of optical chips through an optical waveguide network on the interposer. Compared with an external interconnection mode such as an optical fiber array, the packaging structure for optically interconnecting a plurality of optical chips by using the adiabatic coupling technology can greatly compress the volume of the packaging structure.

Optionally, electrical chips may also be arranged in the package structure as described above, thereby forming an optical chip package structure capable of performing electrical operation (e.g., logic computation, storage, etc.) functions.

Fig. 20 and 21 show a cross-sectional view and a top view, respectively, of an optical chip package structure 2000 containing an electrical chip in accordance with an embodiment of the present disclosure.

As shown in fig. 20, in addition to including interposer 1210 and optical chips PIC 1 and PIC2 similar to fig. 12A-12B, package structure 2000 also includes a plurality of electrical chips disposed on a first plurality of optical chips, e.g., EIC 1 and EIC2 disposed on PIC 1 and PIC2, respectively. Alternatively, as shown in fig. 21, EIC 1, EIC2, EIC 5, EIC 6 are disposed on PIC 1, PIC2, PIC 5, PIC 6, respectively. Fig. 20 may be regarded as a cross-sectional view cut from a position penetrating EIC 1 and EIC2 of the package structure 2000 shown in fig. 21. In fig. 21, PIC 1, PIC2, PIC 5, PIC 6 have been covered by corresponding EIC 1, EIC2, EIC 5, EIC 6, respectively, and are therefore not shown. Further, as shown in fig. 21, it is not necessary to provide a corresponding EIC for each PIC, for example, the EICs may not be arranged above the PICs 3 and 4 as needed.

Specifically, each first optical chip (for example, PIC 1 and PIC2 as shown in fig. 20) may have one or more first electrical connectors on an upper surface thereof, and each electrical chip (for example, EIC 1 and EIC2 as shown in fig. 20) may have one or more second electrical connectors on a lower surface thereof, and the one or more first electrical connectors are electrically connected to the one or more second electrical connectors, respectively, so as to achieve connection of PIC and EIC.

Fig. 22 and 23 show cross-sectional views of an optical chip and an electrical chip in an optical chip package structure of an embodiment of the present disclosure.

As shown in (a) of fig. 22, the upper surface of the PIC has a plurality of first electrical connectors C1, and the lower surface of the EIC has a plurality of second electrical connectors C2, and the PIC and the EIC are directly bonded through the first electrical connectors C1 and the second electrical connectors C2.

In some examples, the first optical chip (i.e., the PIC with the EIC disposed thereon) described above further includes one or more second conductive vias extending therethrough, e.g., TDVs as shown in fig. 22 (a), through which electrical connection between the EIC and the interposer may be made, e.g., the TDVs shown are connected into conductive structures of the interposer as previously shown, as will be described in detail later in the description with respect to fig. 24-25.

Fig. 22 (a) shows a schematic diagram of a single EIC disposed on one PIC. In other embodiments, multiple EICs may be arranged on one PIC. For example, as shown in fig. 22 (b), an analog electrical chip a-EIC may be arranged on the PIC, while a digital electrical chip D-EIC is arranged. It is also possible to arrange a plurality of analog electric chips a-EIC at one PIC, or a plurality of digital electric chips D-EIC at one PIC, or a plurality of analog electric chips a-EIC and a plurality of digital electric chips D-EIC at one PIC, as required. In the case where a plurality of EICs are arranged on the same PIC, each EIC is connected to the conductive structure of the interposer through the TDV as described above to achieve an electrical connection therebetween.

The optical chip PIC and the electrical chip EIC may be bonded by flip-chip bonding (flip-chip) in addition to the direct bonding method described above. Fig. 23 shows an optical chip PIC and an electrical chip EIC bonded by flip-chip bonding. In this example, instead of using direct bonding techniques, the EIC and PIC are connected by copper pillars and cured between the EIC and PIC using an underfill, using a conventional flip-chip process. Fig. 23 (a) shows an example in which only one EIC is flipped over one PIC, and (b) shows an example in which one D-EIC and one a-EIC are flipped over one PIC. Similarly, multiple analog electrical chips A-EIC may be flipped over in one PIC, multiple digital electrical chips D-EIC may be flipped over in one PIC, or multiple analog electrical chips A-EIC and multiple digital electrical chips D-EIC may be flipped over in one PIC. In the case of multiple EICs flipped over on the same PIC, each EIC is connected to the conductive structure of the interposer through a TDV as described above to make an electrical connection between the two.

To more clearly disclose the optical chip package structure of the present disclosure, fig. 24-25 show cross-sectional views of the optical chip package structure of the embodiment of the present disclosure. It should be noted, however, that only one PIC and one EIC are shown in fig. 24-25 for further presentation of detail. Specifically, fig. 24 shows a cross-sectional view of an optical chip package structure employing the interposer shown in fig. 1. Fig. 25 shows a cross-sectional view of a photo chip package structure employing the interposer shown in fig. 4.

As shown in fig. 24, in the case of using the interposer shown in fig. 1, the entire package structure may be divided into three layers from bottom to top, that is, a layer where the interposer 1210 is located, a layer where the PIC is located, and a layer where the EIC is located. For example, in fig. 24, the entire package structure is divided into three layers by two parallel dashed lines, the dashed line between EIC and PIC defines a connection interface IF1 of EIC and PIC, and the dashed line between PIC and interposer 1210 defines a connection interface IF2 between PIC and interposer 1210. It should be understood that the above-described division is only for the purpose of describing the present invention more clearly, and is not intended to limit the present invention to the three-layer structure as described above.

Assuming that the optical chip PIC shown in fig. 24 is PIC 1 as shown in fig. 20, the EIC disposed thereon corresponds to EIC 1 as shown in fig. 20. In this case, it can be seen that the optical waveguide WG2-1 in the optical chip PIC is located near the lower surface of the optical chip PIC and is covered with a transparent dielectric layer (e.g., a buried silicon oxide layer). The optical waveguide WG1-1 in the interposer 1210 is located on the upper surface of the interposer 1210 and is also covered with a cladding layer (e.g., a silicon oxide layer). The optical chip PIC has a conductive via TDV passing therethrough, and the conductive via TDV in the optical chip PIC is electrically connected to the conductive structure CC in the interposer 1210. For example, in the case where the interposer 1210 in fig. 24 is similar to the interposer 100 shown in fig. 1, the optical waveguide WG1-1 may correspond to the optical waveguide 102-1 in the interposer 100 shown in fig. 1, and the conductive structure CC may correspond to the first conductive structure 102-3 in the interposer 100 shown in fig. 1.

Similarly, as shown in fig. 25, in the case of using the interposer shown in fig. 4, the entire package structure may be divided into three layers from bottom to top, that is, a layer where the interposer 1210 is located, a layer where the PIC is located, and a layer where the EIC is located. For example, in fig. 25, the whole package structure is also divided into three layers by two parallel dashed lines, the dashed line between EIC and PIC defines a connection interface IF1 of EIC and PIC, and the dashed line between PIC and interposer 1210 defines a connection interface IF2 between PIC and interposer 1210. It should also be understood that the above-described division is only for the purpose of describing the present invention more clearly, and is not intended to limit the present invention to the three-layer structure as described above.

Similarly, assuming that the optical chip PIC shown in fig. 25 is PIC 1 as shown in fig. 20, the EIC disposed thereon corresponds to EIC 1 as shown in fig. 20. In this case, it can be seen that the optical waveguide WG2-1 in the optical chip PIC is located near the lower surface of the optical chip PIC and is covered with a dielectric layer (e.g., a silicon oxide layer). The optical waveguide WG1-1 in the interposer 1210 is located on the upper surface of the interposer 1210 and is also covered with a cladding layer (e.g., a silicon oxide layer). The optical chip PIC has a conductive via TDV passing therethrough, and the conductive via TDV in the optical chip PIC is electrically connected to the conductive structure CC in the interposer 1210. For example, in the case where the interposer 1210 in fig. 25 is similar to the interposer 400 shown in fig. 4, the optical waveguide WG1-1 may correspond to the optical waveguide 304-1 in the interposer 400 shown in fig. 4, and the conductive structure CC may correspond to the third conductive structure 304-3 in the interposer 400 shown in fig. 4.

In the example depicted in fig. 12A-25, the plurality of optical chips shown are all separate optical chips resulting from the singulation of the photonic wafer and are attached at different locations on the upper surface of the interposer and spaced apart from each other (as shown in fig. 12A-12B and fig. 20-21), so that after the optical chips are attached to the interposer, the gaps between the different optical chips and the different electrical chips on the upper surface of the interposer need to be filled with an injection molding material for further encapsulation to enhance structural stability and strength.

Alternatively, before filling the injection molding material, a dielectric layer for blocking outward transmission of light in the interposer may be first disposed on a connection interface of the optical chip and the interposer, and then injection molding may be performed on the dielectric layer to form an injection molding material layer. Such a dielectric layer is disposed between the interposer and the optical chip because the dielectric layer (e.g., a silicon oxide layer) covering over the waveguide (e.g., WG1-1 as shown in fig. 24 or 25) in the interposer is thin, and the optical signal is transmitted in the waveguide between different optical chips, the thin silicon oxide layer may cause light to overflow during transmission, resulting in optical loss. Therefore, before injection molding, a dielectric layer can be prepared in the gap of the adapter plate, which is not attached to the optical chip, preferably the dielectric layer is the same as the material and the preparation process of the dielectric layer covered on the waveguide, for example, the material of the dielectric layer can be silicon oxide, so that the light transmitted in the waveguide between different optical chips is ensured not to leak outwards. Alternatively, for example, a dielectric layer having a thickness of about several micrometers may be prepared.

The encapsulation structures shown in fig. 24 and 25 each show the injection molded material layer and the dielectric layer for blocking light as described above. For example, the injection molding material layer MLD and the dielectric layer SHD in fig. 24 or 25. The dielectric layer SHD is located between the interposer and the injection molded material layer MLD and has a greater thickness than the thin silicon oxide layer over the optical waveguide WG1-1, thereby ensuring that light transmitted between different optical chips can be maximally confined within the interposer.

It should be understood that while examples of optical chip packages employing the interposer shown in fig. 1 and 4 are shown in fig. 24 and 25, respectively, this is merely exemplary and it is not meant that the optical chip packages described in the present disclosure can only employ the interposer shown in fig. 1 and 4. For example, the optical chip package structure described in the present disclosure may also employ the interposer 200 having the three-dimensional waveguide network as shown in fig. 2, and in the case of employing the interposer 200 having the three-dimensional waveguide network as shown in fig. 2, the optical waveguide (e.g., optical waveguide WG 1-1) in the interposer as described above may correspond to the three-dimensional waveguide network 201-2 in the interposer 200 as shown in fig. 2 and the coupling optical waveguide 202-1 covering the optical input/output port of the three-dimensional waveguide network. In addition, various variations or modifications of the various patch panels discussed in connection with the present disclosure may also be employed, and are not listed herein.

The case where a plurality of optical chips attached to the interposer are used as separate optical chips obtained by dividing the photonic wafer is described above with reference to fig. 12A to 25. The plurality of optical chips bonded to the interposer may be a plurality of optical chips that are not divided in the same photonic wafer.

Fig. 26-27 show schematic diagrams of a photo chip package structure 2600 with multiple photo chips attached on an interposer on the same photonic wafer.

As shown in fig. 26, the optical chip package structure 2600 includes an interposer 1210 and a plurality of optical chips (PICs) disposed on the interposer 1210. For example, since fig. 26 shows a sectional view cut from a specific position, only two optical chips PIC 1 and PIC 2 can be seen in fig. 26. In practice, however, as shown in the top view of fig. 27, the optical chip package structure 2600 may include six optical chips PIC 1-PIC 6. It should be understood that the six optical chips described above are merely exemplary and not limiting, and that in practical applications, optical chip package structure 2600 may include more optical chips.

As shown in fig. 26, the patch panel 2600 includes a plurality of first optical waveguides embedded therein, such as the optical waveguides WG1-1 and the optical waveguides WG1-2 shown in fig. 26. The optical waveguides WG1-1 and WG1-2 may be optical waveguides in an interposer as previously described, such as optical waveguide 102-1 in FIG. 1, 202-1 and 202-2 in FIG. 2, or 304-1 in FIG. 4. Further, the materials of the optical waveguide WG1-1 and the optical waveguide WG1-2 may be silicon nitride as previously described.

Each of the optical chips PIC 1 and PIC 2 includes one or more second optical waveguides (only a single optical waveguide is shown for each PIC in fig. 26 for simplicity of illustration), that is, the optical waveguides WG2-1 and the optical waveguides WG2-2, embedded therein. In some examples, the material of optical waveguides WG2-1 and WG2-2 may be silicon. As shown in fig. 27, a photonic wafer PWF including a plurality of optical chips (PIC 1, …, PIC 6) is attached to the upper surface of the interposer 1210, and the plurality of optical chips (PIC 1, …, PIC 6) are located at different positions on the interposer 1210 and spaced apart from each other.

The optical chips PIC 1 and PIC 2 shown in fig. 26, or any two of the plurality of optical chips (PIC 1, …, PIC 6) shown in fig. 27, may be optically interconnected by the first optical waveguides in the plurality of interposer 1210. For example, as shown by the arrowed dashed lines in fig. 26, light may originate from PIC 1, then couple through WG2-1 into optical waveguide WG1-1 in interposer 1210, then transmit through a series of optical waveguide networks (not shown) into optical waveguide WG1-2, and then couple into optical waveguide WG2-1 in PIC 2. Specifically, each of the first optical waveguides may include a first optical coupling portion, and each of the second optical waveguides may include a second optical coupling portion (not shown in the drawings), and for simplicity, the end portions of the optical waveguides WG2-1 and WG1-1 may be regarded as respective optical coupling portions, for example. For example, the optical coupling portions of the optical waveguides WG2-1 and WG1-1 are stacked and spaced apart by a predetermined distance (e.g., less than 600 nm) in a direction perpendicular to the upper surface of the interposer 1210, so that adiabatic coupling of light between the optical coupling portions of the optical waveguides WG2-1 and WG1-1 can be achieved.

With reference to fig. 13 to 19 and the description thereof, the optical coupling portion of the first optical waveguide in the interposer and the optical coupling portion of the second optical waveguide in the optical chip are designed, and the optical coupling portion of the optical waveguide suitable for the case of separating the optical chip is designed for the case of an undivided photonic wafer, unless otherwise specified or clearly unsuitable. For example, the optical coupling portion of the first optical waveguide (e.g., WG1-1 or WG 1-2) in the interposer and the optical coupling portion of the second optical waveguide (e.g., WG2-1 or WG 2-2) in the optical chip may have a tapered shape as shown in FIG. 14, or may have a shape formed by cascading two tapered shapes of different sizes as shown in FIG. 19.

Note that, in order to distinguish from the optical chip package structure 1200 in fig. 12A, the gap between PIC 1 and PIC 2 in the optical chip package structure 2600 shown in fig. 26 is shown as not being filled with hatching, thereby indicating that PIC 1 and PIC 2 are located in the same uncut wafer, instead of being filled with injection molding material between PIC 1 and PIC 2 as shown in fig. 12A.

Similar to the case of using separate optical chips, in the case of using an undivided photonic wafer, the electrical chips may be arranged accordingly on a specific optical chip or all optical chips in the photonic wafer.

Fig. 28-29 show schematic diagrams of a photo-chip package structure 2600 with electrical chips arranged simultaneously with an undivided photonic wafer.

As shown in fig. 28, in addition to including interposer 1210 similar to fig. 26-27 and photonic wafer PWF including optical chips PIC1 and PIC 2, package structure 2800 also includes a plurality of electrical chips disposed on a plurality of first optical chips (e.g., PIC1 and PIC 2) of the plurality of optical chips, e.g., EIC 1 and EIC 2 disposed on PIC1 and PIC 2, respectively. Alternatively, as shown in fig. 29A, the package structure 2800 may include EIC 1, EIC 2, EIC5, EIC 6 disposed on PIC1, PIC 2, PIC 5, PIC 6, respectively. Fig. 28 may be regarded as a cross-sectional view taken from a position of the package structure 2000 shown in fig. 29A penetrating EIC 1 and EIC 2. In fig. 29A, PIC1, PIC 2, PIC 5, PIC 6 have been covered by corresponding EIC 1, EIC 2, EIC5, EIC 6, respectively, and are therefore not shown. Further, as shown in fig. 29A, it is not necessary to provide a corresponding EIC for each PIC, for example, the EICs may not be arranged above the PICs 3 and 4 as needed. It should be noted that, here, not disposing an EIC above PIC 3 and PIC 4 does not mean that PIC 3 and PIC 4 are not covered by an electronic wafer, but rather, it is understood that a "dummy chip" having no specific structure is covered at a corresponding position of an electronic wafer above PIC 3 and PIC 4, rather than a die or chip having a specific structure and capable of performing a specific function as referred to by EIC 1, EIC 2, EIC5, EIC 6, or the like.

Alternatively, in some examples, an EIC may be disposed over each PIC. For example, fig. 29B shows a schematic diagram in which EIC (EIC 1 to EIC 6 as shown) is arranged on each optical chip PIC. In this case, for example, the corresponding electrical chips on all the optical chips may be a plurality of electrical chips that are not segmented in the same electronic wafer, and the plurality of optical chips may have the same structure, and the plurality of electrical chips (e.g., EIC 1-EIC 6 as shown) may also have the same structure, such that each PIC-EIC pair stacked one above the other forms the same PIC-EIC hybrid chip. In this case, the plurality of first optical chips are equivalent to all the optical chips.

It should be noted that in the case of using an undivided photonic wafer, the plurality of electric chips (for example, EIC 1, EIC 2, EIC3, EIC4, EIC 5, EIC 6 in fig. 29B) on the plurality of first optical chips are a plurality of electric chips undivided in the same electronic wafer EWF, and in this case, the photonic wafer PWF as shown in fig. 29A to 29B and the electronic wafer EWF are connected together in a direct bonding manner and then commonly arranged on the interposer 1210. In this case, the manner similar to flip-chip bonding shown in fig. 23 is no longer applicable to the connection of a photonic wafer and an electronic wafer.

In addition, it should be noted that, in order to distinguish from the optical chip package structure 2000 in fig. 20, the gaps between PIC 1 and PIC 2 and between EIC 1 and EIC 2 in the optical chip package structure 2800 shown in fig. 28 are shown as not filled with hatching, thereby indicating that PIC 1 and PIC 2 are located in the same photonic wafer and EIC 1 and EIC 2 are located in the same electronic wafer, instead of the gaps between PIC 1 and PIC 2 and between EIC 1 and EIC 2 being filled with an injection molding material as shown in fig. 20.

Likewise, for the embodiments shown in fig. 28-29, the design of the optical coupling portion for the first optical waveguide in the interposer and the optical coupling portion for the second optical waveguide in the optical chip can also be referred to in fig. 13-19 and the description thereof, and the design of the optical coupling portion for the optical waveguide suitable for the case of separating the optical chip is equally applicable to the case of an undivided photonic wafer unless otherwise specified or clearly unsuitable. For example, the optical coupling portion of the first optical waveguide (e.g., WG1-1 or WG 1-2) in the interposer and the optical coupling portion of the second optical waveguide (e.g., WG2-1 or WG 2-2) in the optical chip as shown in fig. 28 may have a tapered shape as shown in fig. 14, or may have a shape formed by cascading two tapered shapes of different sizes as shown in fig. 19, which will not be described again.

In addition, it should be noted that in the case of using an undivided photonic wafer, the optical chip package structure as shown in fig. 26 to 29 may be equally employed with the interposer 100 and 400 previously described with respect to fig. 1 and 4, as well as the interposer 200 having a three-dimensional waveguide network as shown in fig. 2, and in the case of using the interposer 200 having a three-dimensional waveguide network as shown in fig. 2, the optical waveguide (e.g., the optical waveguide WG 1-1) in the interposer as shown in fig. 26 or 28 may correspond to the three-dimensional waveguide network 201-2 in the interposer 200 and the coupled optical waveguide 202-1 covering the optical input/output port of the three-dimensional waveguide network as shown in fig. 2. In addition, various variations or modifications of the various patch panels discussed in connection with the present disclosure may also be employed, and are not listed herein.

Various embodiments of the optical chip package according to the present disclosure are described above. In summary, for the optical chip package structures depicted in fig. 12A-12B and fig. 20-21, separate optical chips are used, the waveguides of the optical chips and the waveguides of the interposer are coupled in an adiabatic manner, and the degree of freedom in the placement of the chips in such package structures is extremely high, greatly compressing the size of the package structure. For the optical chip package structure shown in fig. 26-29, the optical chip is not separated from the same photonic wafer, and although the layout flexibility is inferior to that of the separated optical chip, the direct bonding process from the wafer to the glass adapter plate is used, the process is simple, and the alignment accuracy is higher, so that the coupling efficiency between the optical chip and the optical waveguide of the adapter plate is higher. Those skilled in the art may select an appropriate embodiment according to actual needs or combine the embodiments with each other, and the combination is also within the scope of the present disclosure.

By adopting various optical chip package structures as described above, various calculation accelerators can be realized, for example, for realizing calculation such as matrix multiplication in a neural network. Fig. 30 shows a schematic diagram of a computing accelerator 3000 of an embodiment of the present disclosure. Fig. 31A shows a schematic diagram of another computing accelerator 3100A of an embodiment of the disclosure. FIG. 31B shows a schematic diagram of yet another computing accelerator 3100B in accordance with an embodiment of the disclosure

The computational accelerator 3000 shown in fig. 30 may be implemented using a package structure with separate optical chips as shown in fig. 12A-12B or as shown in fig. 20-21. For example, as shown in fig. 30, the calculation accelerator 3000 may include one or more light sources LS, one or more calculation units CL, and one or more storage units MO. For clarity, different fill patterns are used to distinguish between different functional units, e.g. a pure white filled unit (block as shown) represents a storage unit MO, a grid filled unit represents a calculation unit CL, and a scatter filled unit represents a light source LS.

Some of the elements in the computing accelerator 3000 may be implemented in the optical chip packages as previously described with respect to fig. 12A-12B and/or with respect to fig. 20-21. For example, one or more computing units CL are configured to perform computing functions, which may be implemented by optical chips in the optical chip package structure 1200 as described previously with respect to fig. 12A-12B. For example, matrix multiplication may be implemented with a mach-zehnder MZI interferometer or the like in an optical chip. Alternatively, one or more of the computing units CL may be implemented by an electrical chip in the optical chip package structure 1200 as described previously with respect to fig. 20-21, e.g. the optical chip in the optical chip package structure 1200 performs mainly the communication function, the electrical chip performs the computing function; alternatively, one or more of the computing units CL may be implemented jointly by the optical chip and the electrical chip in the optical chip package structure 1200 as described previously with respect to fig. 20-21, e.g. the optical chip in the optical chip package structure 1200 performs both the communication function and part of the computing function, and the electrical chip performs the further computing function. The one or more memory cells MO are configured to perform a memory function and may be implemented by an electrical chip in the optical chip package structure 1200 as described previously with respect to fig. 20-21.

Furthermore, preferably, in case the computing accelerator 3000 is implemented with an optical chip package as described previously with respect to fig. 12A-12B and/or with respect to fig. 20-21, one or more light sources LS may be integrated into the chip package structure. For example, one or more light sources LS may be attached to a first surface of the interposer 1210 in a manner similar to PIC 1 or PIC 2 in the optical chip package structures 1200 or 2000 as previously described, and configured to provide light waves to the computing accelerator 3000, and more specifically, to the individual optical chips in the computing accelerator 3000, through the waveguides WG in the interposer.

For example, light in the light source LS may be adiabatically coupled into the corresponding optical waveguide in the interposer in a manner similar to the adiabatic coupling between the optical chip and the interposer, thereby avoiding the additional interface required to couple light through other intermediate links (e.g., optical fibers, etc.), which light source arrangement approach also helps to further compress the volume of the computing accelerator.

Optionally, the computing accelerator 3000 may also include one or more edge optocouplers, i.e., edge optocouplers CP located around the square as shown in fig. 30, configured to optically interconnect the computing accelerator with other devices. For example, if the light source LS is not attached to the interposer in the manner described above, but is an external light source, the light source may be connected using the edge optocoupler CP in the calculation accelerator 3000.

The patch panel 1210 shown in fig. 30 in the computing accelerator may be various types of patch panels as previously described. For example, it may be the patch panels 100 and 200 as described in fig. 1-2, or the patch panel 400 as described in fig. 4. In addition, various variations or modifications of the various patch panels discussed in connection with the present disclosure may also be employed, and are not listed herein.

Furthermore, it is also to be noted that although in fig. 30 the calculation accelerator is shown as being implemented in a different chip of the same optical chip package structure, this is only illustrative. In practical applications, a plurality of different optical chip packages may be interconnected by the edge optocoupler CP as described above, and various computing units, memory units, or light sources may be implemented or arranged in the plurality of optical chip packages, thereby forming a large-sized or ultra-large-sized computing accelerator.

In contrast to the computational accelerator 3000 shown in fig. 30, the computational accelerator 3100A shown in fig. 31A may be implemented using a photonic wafer-level package structure as shown in fig. 26-29B. For example, as shown in fig. 31A, the computation accelerator 3100A may include one or more light sources LS, one or more computation units CL, and one or more storage units MO. For clarity, different fill patterns are used to distinguish between different functional units, e.g. a pure white filled unit (block as shown) represents a memory unit MO and a grid filled unit represents a calculation unit CL.

Some of the elements in the computing accelerator 3100A may be implemented in the photo-chip package structure as previously described with respect to fig. 26-29B. For example, one or more computing units CL are configured to perform computing functions, which may be implemented by optical chips in optical chip package structure 2600 as described previously with respect to fig. 26-27. For example, matrix multiplication may be implemented with a mach-zehnder MZI interferometer or the like in an optical chip. Alternatively, one or more computing units or memory units may be implemented by optical or electrical chips in optical chip package 2800 as previously described with respect to fig. 28-29A, e.g., optical chips in optical chip package 2800 perform primarily communication functions, electrical chips perform both computing and memory functions; alternatively, one or more of the computing units CL may be implemented jointly by the optical chip and the electrical chip in the optical chip package structure 2800 as described previously with respect to fig. 28-29A, e.g., the optical chip in the optical chip package structure 2800 performs both the communication function and part of the computing and storage functions, and the electrical chip performs the additional computing and storage functions.

Unlike fig. 30, since fig. 31A employs a package structure using a photonic wafer, there are redundant optical chips in addition to the square area as shown in fig. 30, and the redundant optical chips need to be cut off before the photonic wafer is bonded to the interposer.

Alternatively, the above-described calculation unit and storage unit may also be implemented using a package structure as shown in fig. 29B. For example, when the package structure 2900 shown in fig. 29B is employed to implement the compute units and the memory units in the compute accelerator, since each EIC in the package structure 2900 is the same and each PIC is also the same, each compute unit and the corresponding memory unit can be commonly implemented using each PIC and the corresponding EIC (e.g., PIC 1 and EIC 1) and treated as a compute-memory unit.

Fig. 31B shows an example of the computation accelerator 3100B in which each computation unit and the corresponding storage unit are implemented as the corresponding computation-storage unit. For example, each computing unit and corresponding memory unit may be implemented by each optical chip and corresponding electrical chip in optical chip package structure 2900 as shown in fig. 29B, such that each computing unit and corresponding memory unit is considered a compute-memory unit CL-MO.

In this case, as shown in fig. 31B, the combination of the calculation unit and the corresponding memory unit can be regarded as the same calculation-memory unit CL-MO. For ease of understanding, each compute-store cell CL-MO in fig. 31B is shown populated with a checkerboard pattern, thereby indicating that each compute-store cell CL-MO may have the same hardware resources, i.e., the same memory resources, computing resources, communication resources, etc. For example, in the case where the plurality of calculation-storage units CL-MO as shown are implemented by the optical chip package structure 2900 as described previously with respect to fig. 29B, the communication functions may be mainly performed by the optical chips in the optical chip package structure 2900, and the corresponding electrical chips perform the calculation and storage functions; alternatively, the communication function and part of the calculation and storage functions may be performed simultaneously by the optical chip, with the corresponding electrical chip performing the additional calculation and storage functions.

Furthermore, it should be understood that whether it is a computing unit, a memory unit, or a compute-memory unit as described above is intended to describe functional units in a compute accelerator, and is not intended to limit individual optical chips, electrical chips, or a combination of optical and electrical chips in an optical chip package to use for computation only, storage only, or compute-storage only. For example, individual optical chips, electrical chips, or a combination of optical and electrical chips in an optical chip package may also be used to perform other functions besides computing, storing, or computing-storing, such as data transfer, etc.

Furthermore, it should be noted that, in the computing accelerator 3100A or 3100B, due to the direct bonding of the electronic wafer to the photonic wafer, the light source LS (e.g., a laser chip) cannot be directly bonded to the interposer, light needs to be coupled into the computing accelerator through an optical fiber array or other light guiding structure, and the light source LS is configured to provide light waves to the computing accelerator 3100A or 3100B, more precisely, to the respective optical chip in the computing accelerator 3100A or 3100B through the waveguide WG in the interposer.

In addition, the computing accelerator 3100A or 3100B may further include one or more edge optocouplers, i.e., edge optocouplers CP located around the square as shown in fig. 31A or 31B, configured to optically interconnect the computing accelerator with other devices. For example, an edge optocoupler CP in the computation accelerator 3100A or 3100B may be used to connect the light sources LS.

The patch panel 1210 in the computing accelerator shown in fig. 31A or 31B may be various types of patch panels as described previously. For example, it may be the patch panels 100 and 200 as described in fig. 1-2, or the patch panel 400 as described in fig. 4. In addition, various variations or modifications of the various patch panels discussed in connection with the present disclosure may also be employed, and are not listed herein.

Further, it should be noted that although in fig. 31A or 31B, the calculation accelerator is shown as being implemented in a different chip of the same optical chip package structure, this is merely illustrative. In practical applications, a plurality of different optical chip packages may be interconnected by the edge optocoupler CP as described above, and various computing units, memory units, or light sources may be implemented or arranged in the plurality of optical chip packages, thereby forming a large-sized or ultra-large-sized computing accelerator.

Optionally, the computing accelerator as described above with respect to fig. 30-31 may further include a plurality of High Bandwidth Memory (HBM) chips stacked on the optical chip in the optical chip package structure configured to perform memory computing functions.

The above describes the optical chip package structures and the computational accelerators implemented using the various optical chip package structures in various embodiments of the present disclosure. In summary, with the optical chip package structure described in fig. 12A-12B and fig. 20-21, since separate optical chips are used, the waveguides of the optical chip and the waveguides of the interposer are coupled in an adiabatic manner, and the degree of freedom of chip arrangement in such a package structure is extremely high, which greatly compresses the size of the package structure. And the calculation accelerator implemented by the packaging structure can further integrate the light source inside the optical chip packaging structure, thereby being beneficial to further compressing the volume of the product.

In contrast, for the optical chip package structure shown in fig. 26-29B, the optical chip that is not separated on the same photonic wafer is adopted, although the scheme of the optical chip that is separated is not better in the aspect of flexibility of layout, the process is simpler and the alignment precision is higher due to the direct bonding process of the wafer to the glass adapter plate, so that the coupling efficiency between the optical chip and the optical waveguide of the adapter plate is also higher. Those skilled in the art may select an appropriate embodiment according to actual needs or combine the embodiments with each other, and the combination is also within the scope of the present disclosure.

Specific methods of manufacturing the various optical chip package structures described above will be described below in connection with fig. 32-36. Fig. 32-36 illustrate a flow chart of a method of manufacturing an optical chip package structure according to an embodiment of the present disclosure.

It should be noted that the structures and features thereof similar to the interposer, the optical chip, the electrical chip, and the like mentioned in the manufacturing method described below are similar to the various structures or features described above with respect to the embodiments of the various optical chip package structures. For simplicity of explanation, repeated descriptions of these structures or features will be omitted in some cases, and in this case, various structures or features involved in the manufacturing method as described below should not be interpreted in a narrow sense thereby.

In addition, in the following description of the manufacturing method of the optical chip package structure, in order to avoid repetition of the description, the flow steps shown in other drawings will be referred to in some flows, and in this case, various steps involved in the manufacturing method described below should not be interpreted narrowly.

Fig. 32 shows a flow chart 3200 corresponding to a method of manufacturing the optical chip package structure 1200 shown in fig. 12A-12B.

As shown in fig. 32, the method 3200 includes: an interposer is provided (S3210) and a plurality of optical chips are attached to the interposer at different locations on an upper surface thereof (S3220). For example, the interposer may be the interposer 1210 as in fig. 12A, and the plurality of optical chips may be the PICs 1 to 6 as shown in fig. 12B.

For example, the patch panel may include one or more first optical waveguides (WG 1-1, WG1-2 as shown in FIG. 12A) embedded therein, and each first optical waveguide includes a first optical coupling portion. Each optical chip may include one or more second optical waveguides (WG 2-1, WG2-2 as shown in fig. 12A) embedded therein, each of the second optical waveguides including a second optical coupling portion.

For example, the first light coupling portion and the second light coupling portion are each tapered as described above with respect to fig. 14. Alternatively, the first light coupling part and the second light coupling part may also have shapes formed by cascading two tapered shapes of different sizes as described above with respect to fig. 19, respectively.

As previously described with respect to fig. 13, the first light coupling portion and the second light coupling portion are stacked and spaced apart by a predetermined distance (e.g., less than or equal to 600 nm) in a direction perpendicular to the upper surface of the interposer such that the first light coupling portion and the second light coupling portion achieve adiabatic coupling of light, and the plurality of optical chips are optically interconnected by the plurality of first optical waveguides.

Fig. 33-35 illustrate a flow chart corresponding to a method of manufacturing the optical chip package structure 2000 illustrated in fig. 20-21.

As shown in fig. 33, the manufacturing method 3300 includes: an interposer is provided (S3310), an electrical chip is arranged on a first optical chip of the plurality of optical chips such that the first optical chip and the electrical chip thereon form an electron-photon hybrid chip (S3320), and the plurality of optical chips are attached to the interposer at different positions on an upper surface thereof (S3330).

The manufacturing method 3300 shown in fig. 33 includes more steps S3320 of forming an electron-photon hybrid chip than the manufacturing method shown in fig. 32. It should be noted that, the term "electronic-photonic hybrid chip" herein does not mean that chips other than the optical chip and the electrical chip described above are used, but may correspond to an integral structure formed by interconnecting PIC 1 and EIC 1 shown in fig. 20, or an integral structure formed by interconnecting PIC 1 and EIC 1. More closely related, the term "electronic-photonic hybrid chip" may correspond to the individual chip structures as shown in the figures with respect to 22-23.

For example, as shown in fig. 22 (a), the PIC together with the EIC disposed thereon may be referred to as an electron-photon hybrid chip or an electron-photon hybrid chiplet (chiplet). As shown in (a) of fig. 22, the upper surface of the PIC has a plurality of first electrical connectors C1, and the lower surface of the EIC has a plurality of second electrical connectors C2, and the PIC and the EIC are directly bonded through the first electrical connectors C1 and the second electrical connectors C2.

In addition, the electronic-photonic hybrid chip may be a monolithic structure including one PIC and two EICs (D-EIC and a-EIC) as shown in (b) of fig. 22, and the D-EIC, a-EIC and PIC are directly bonded through the first electrical connector C1 and the second electrical connector C2.

Likewise, the whole structure of the EIC and PIC bonded by flip-chip connection as shown in fig. 23 can also be regarded as an electronic-photonic hybrid chip as described above, and will not be described here again.

Fig. 34 and 35 illustrate two different methods of disposing an electrical chip on a first optical chip of the plurality of optical chips to form an electron-photon hybrid chip, respectively. The flow steps in fig. 34 and 35 can be regarded as sub-division steps of step S3320 in fig. 33, respectively.

As shown in fig. 34, disposing an electrical chip on a first optical chip of the plurality of optical chips includes: preparing a photonic wafer and an electronic wafer (S3410), bonding the electronic wafer directly to the photonic wafer (3420), removing a substrate of the photonic wafer (S3430), and dicing the electronic-photonic hybrid wafer into a plurality of electronic-photonic hybrid chips (S3440).

In some examples, the photonic wafer prepared in step S3410 may be similar to the photonic wafer PWF described with respect to fig. 29A, including a plurality of photo-chips PIC 1-PIC 6, and including a plurality of first photo-chips in the plurality of photo-chips PIC 1-PIC 6 for disposing corresponding electrical chips thereon. Similarly, the electronic wafer prepared in step S3410 may be similar to the electronic wafer EWF described with respect to fig. 29A, including a plurality of electrical chips (e.g., EIC 1,EIC 2,EIC 5,EIC 6).

In some examples, an electron-photon hybrid wafer may be obtained, for example, by bonding (e.g., directly bonding) the plurality of first optical chips to the plurality of electrical chips, and then dicing the electron-photon hybrid wafer into a plurality of electron-photon hybrid chips in step S3440.

It should be noted that, although the specific structures of the photonic wafer and the electronic wafer are described above in connection with fig. 29A, this is merely for convenience of description, and in fact, fig. 29A shows that the PWF and the EWF are directly bonded and then integrally disposed on the interposer without being divided into separate electronic-photonic hybrid chips. However, it should be mentioned that although it is not necessary to cut the bonded PWF and EWF into separate electronic-photonic hybrid chips, it is necessary to cut the edge redundant chips to facilitate packaging, for example, into an internal square shape as shown in fig. 31A or 31B.

Fig. 35 illustrates another method of forming an electron-photon hybrid chip. As shown in fig. 35, disposing an electrical chip on a first optical chip of the plurality of optical chips may specifically include: preparing a photonic wafer and an electronic wafer (S3510), dicing the electronic wafer into the plurality of electrical chips (S3520), directly bonding or flip chip (S) one or more of the plurality of electrical chips to a first optical chip in the photonic wafer to obtain an electron-photon hybrid wafer (S3530), filling a gap on the photonic wafer not occupied by the electronic chip with an injection molding material (S3540), removing a substrate of the photonic wafer (S3550), and dicing the electron-photon hybrid wafer into the electron-photon hybrid chip (S3560).

Similarly, the photonic wafer prepared in step S3510 may be similar to the photonic wafer PWF described with respect to fig. 29A, which includes a plurality of photo-chips PIC 1-PIC 6, and a plurality of first photo-chips are included in the plurality of photo-chips PIC 1-PIC 6 for arranging corresponding electrical chips thereon. Similarly, the electronic wafer prepared in step S3510 may be similar to the electronic wafer EWF described with respect to fig. 29A, including a plurality of electrical chips (e.g., EIC 1,EIC 2,EIC 5,EIC 6).

Unlike method 3400, in method 3500, instead of integrally bonding an electronic wafer comprising a plurality of electrical chips to a photonic wafer, it is first diced into a plurality of separate electrical chips in step S3520, and then the individual electrical chips resulting from dicing are directly bonded or flip-chip bonded (flip-chip) to a first optical chip in the photonic wafer in step S3530 to obtain an electronic-photonic hybrid wafer.

Since the individual electrical chips are separate electrical chips, rather than being located on the same electronic wafer as described in method 3400, it is also desirable to fill the gaps on the photonic wafer not occupied by the electronic chips with injection molding material after the corresponding electrical chips are disposed on the first optical chip, thereby enhancing the mechanical strength and stability of the photonic wafer.

It should also be noted that, although the specific structures of the photonic wafer and the electronic wafer are described above in connection with fig. 29A, this is merely for convenience of description, and in fact, fig. 29A shows that the PWF and the EWF are directly bonded and then integrally disposed on the interposer without being divided into separate electronic-photonic hybrid chips. However, it should be mentioned that although it is not necessary to cut the bonded PWF and EWF into separate electronic-photonic hybrid chips, it is necessary to cut the edge redundant chips to facilitate packaging, for example, into an internal square shape as shown in fig. 31A or 31B.

In addition, the method 3400 or 3500 may further include: after removing the substrate of the photonic wafer and before dicing the electron-photon hybrid wafer into the electron-photon hybrid chips, the buried oxide layer on the bottom of the photonic wafer is thinned to a predetermined thickness (not shown). In the case where the optical waveguide has been prepared in the photonic wafer, the thinning operation as described above is to reduce the thickness of the buried oxide layer of the bottom surface of the optical waveguide in the optical chip, so that the optical waveguide in the optical chip can be brought as close as possible to the optical waveguide in the interposer, thereby increasing the coupling efficiency.

The spacing between the optical waveguides in the optical chip and the optical waveguides in the interposer may be made less than or equal to 600nm by the thinning operation as described above, as described with respect to fig. 13.

In addition, the method 3400 or 3500 may further include: thinning the buried oxide layer of the bottom surface of the photonic wafer after removing the substrate of the photonic wafer, and forming a connecting waveguide on the surface of the photonic wafer away from the electrical chip; and covering the connection waveguide with a dielectric to cover the connection waveguide, the connection waveguide being stacked and spaced apart in a vertical direction of a lower surface of the photonic wafer (not shown) with a second optical coupling portion of a second optical waveguide in the optical chip and a first optical coupling portion of a first optical waveguide in the interposer, the first optical waveguide, the connection waveguide, and the second connection waveguide being in optical communication by adiabatic coupling of light. A connection waveguide is formed into the photonic wafer in the above manner, and then a dielectric is coated on the connection waveguide to cover the connection waveguide. The purpose is also to increase the coupling efficiency by adding a connecting waveguide between the optical waveguide in the optical chip and the optical waveguide in the adapter plate.

In some examples, the above methods 3400 or 3500 may further include: forming one or more second conductive vias in the photonic wafer after preparing the photonic wafer; and after removing the substrate of the photonic wafer, thinning the buried oxide layer at the bottom of the photonic wafer to a predetermined thickness, so that the one or more second conductive vias penetrate up and down to form one or more second conductive vias (not shown). For example, the second conductive via formed as described above may be a TDV on the PIC as shown in fig. 22 or 23 for electrically connecting the electrical chip EIC to the interposer.

For example, in some examples, attaching the plurality of optical chips to the interposer at different locations on the upper surface further comprises: and respectively and electrically connecting the one or more second conductive through holes with one or more conductive structures in the adapter plate. The one or more conductive structures in the interposer may be the first conductive structure 102-3 in the interposer 100 shown in fig. 1, the first conductive structure 202-3 in the interposer 200 shown in fig. 2, or the third conductive structure 304-3 in the interposer 400 shown in fig. 4. The specific details of the electrical connection between the one or more second conductive vias in the optical chip and the one or more conductive structures in the interposer may also refer to the connection manner between the TDV and the conductive structure CC in fig. 24 or 25, which are not described herein.

Returning to method 3300, after attaching the plurality of optical chips to the upper surface of the interposer at different locations, the plurality of electronic-photonic hybrid chips are spaced apart from one another on the upper surface of the interposer. Since a gap still exists in the different electronic-photonic hybrid chips at this time, it is necessary to enhance the stability and mechanical strength of the package by filling the gap with an injection molding material.

However, since the dielectric layer (e.g., a silicon oxide layer) covered over the waveguide (e.g., WG1-1 as shown in fig. 24 or 25) in the interposer is thin, optical signals are transmitted in the waveguide between different optical chips, and the thin silicon oxide layer may cause light to overflow during transmission, resulting in optical loss. Therefore, before injection molding, a dielectric layer may be first prepared in the gap where the optical chip is not attached to the interposer, so as to block light in the interposer from transmitting outwards, preferably, the material of the dielectric layer is the same as that of the dielectric layer covered above the waveguide in the interposer, and the same process is adopted.

Thus, method 3300 may further comprise: a dielectric layer (not shown) for blocking light in the interposer from being transmitted outward is formed on the upper surface of the interposer and in the gaps between the plurality of electron-photon hybrid chips before filling the injection molding material in the gaps between the optical chips. The material of the dielectric layer may also be silicon oxide and may have a predetermined thickness, for example a few microns, so as to ensure that light transmitted in the waveguide between different optical chips does not leak outwards.

The manufacturing method of the optical chip package structure corresponding to those shown in fig. 12A-12B and fig. 20-21 is described above in connection with fig. 33-35, in which the packaged optical chips and electrical chips are separated from each other, i.e., not on the same wafer. A method of manufacturing an optical chip package structure corresponding to that shown in fig. 26 to 29, in which a plurality of optical chips or a plurality of electrical chips are all located in the same photonic wafer or the same electronic wafer, will be described below with reference to the accompanying drawings.

The method shown in fig. 36 corresponds to the method of manufacturing the photo chip package structure 2600 shown in fig. 26-27.

As shown in fig. 36, the method 3600 includes: an interposer is provided (S3610), a photonic wafer is prepared (S3620), and the photonic wafer is directly bonded to an upper surface of the interposer (S3630). The adapter plate may be similar to any of the previously described adapter plates and will not be described in detail herein. The prepared photon wafer comprises a plurality of optical chips, and the photon wafer is connected to the adapter plate by a direct bonding method.

The method shown in fig. 37 corresponds to the method of manufacturing the optical chip package structure 2800 shown in fig. 28-29.

As shown in fig. 37, method 3700 includes: providing an interposer (S3710), preparing a photonic wafer and an electronic wafer (S3720), bonding the electronic wafer directly to the photonic wafer such that the plurality of first optical chips are bonded to the plurality of electrical chips to obtain an electronic-photonic hybrid wafer (S3730), and bonding the photonic wafer directly to an upper surface of the interposer (S3740). Likewise, the adapter plate may be similar to any of the adapter plates previously described. The prepared photonic wafer includes a plurality of optical chips therein, and the prepared electronic wafer may include a plurality of electrical chips, and the electronic wafer is directly bonded to the photonic wafer such that a specific optical chip (i.e., the first optical chip as described above) in the photonic wafer is bonded to the plurality of electrical chips to obtain the electronic-photonic hybrid wafer. And the photonic wafer is connected to the interposer by direct bonding,

The steps of removing the substrate of the photonic wafer, thinning the buried oxide layer of the bottom surface of the photonic wafer to a predetermined thickness, disposing and covering the connection waveguides in the photonic wafer, and forming one or more second conductive holes in the photonic wafer, as described above with respect to fig. 32-35, are equally applicable to the methods described with respect to fig. 36-37 unless otherwise indicated or clearly unsuitable.

The above describes the manufacturing method of various optical chip package structures in the embodiments of the present disclosure. It should be noted that the steps in the manufacturing method described above in connection with the flowcharts are merely exemplary, and the order of the steps shown in the flowcharts is not necessarily constant, and those skilled in the art can adjust the order of the steps, and can omit or add additional steps, on the basis of the design concept of the present application. It is also within the scope of the application for the method to be obtained by such adjustment, omission, addition steps.

In the foregoing description, embodiments of the present disclosure have been described with reference to the accompanying drawings. It is to be understood that the above-described embodiments are merely illustrative, and those skilled in the art will understand that the combination of the constituent elements and processes of the present embodiment may be modified in various ways, and that such modifications also fall within the scope of the present disclosure.

Claims

1. A interposer for optical chip packaging, comprising:

a glass substrate comprising one or more conductive vias, the conductive vias comprising a via through the glass substrate and a conductive material filled in the via; and

an optical waveguide structure disposed on a first surface of the glass substrate,

wherein the optical waveguide structure comprises one or more layers of optical waveguides and a cladding layer cladding the one or more layers of optical waveguides,

the one or more optical waveguides are used for optically interconnecting a plurality of optical chips packaged on the adapter plate, and the refractive index of the one or more optical waveguides is larger than that of the coating layer and the glass substrate, and

the optical waveguide structure further includes one or more first conductive structures extending through the optical waveguide structure and electrically connected to the one or more conductive vias, respectively.

2. The interposer of claim 1, wherein

The one or more optical waveguides are silicon nitride optical waveguides, and the material of the cladding layer is silicon dioxide.

3. The interposer of claim 1, further comprising:

a dielectric layer disposed on the second surface of the glass substrate; and

One or more conductive bumps disposed on a surface of the dielectric layer on a side remote from the glass substrate,

wherein the dielectric layer comprises one or more second conductive structures penetrating the dielectric layer and electrically connected with the one or more conductive through holes respectively, and

the one or more conductive bumps are electrically connected with the one or more second conductive structures, respectively.

4. A interposer for optical chip packaging, comprising:

an optical coupling structure disposed on a first surface of the glass substrate,

wherein the glass substrate further comprises a three-dimensional waveguide network for optically interconnecting a plurality of optical chips packaged on the interposer,

the optical coupling structure comprises a coupling optical waveguide covering an optical input/output port of the three-dimensional waveguide network and a cladding layer cladding the coupling optical waveguide, and

the optical coupling structure further includes one or more first conductive structures extending through the optical coupling structure and electrically connected to the one or more conductive vias, respectively.

5. The interposer of claim 4, wherein

The refractive index of the coupled optical waveguide is lower than the refractive index of the three-dimensional waveguide network and higher than the refractive index of the cladding layer.

6. The interposer of claim 5, wherein

The coupling optical waveguide is a silicon nitride optical waveguide, and the material of the cladding layer is silicon dioxide.

7. The interposer of claim 4, further comprising:

a dielectric layer disposed on the second surface of the glass substrate;

8. The interposer of claim 4, wherein:

the three-dimensional waveguide network is a network structure formed by inducing a partial glass inside the glass substrate to increase the refractive index of the partial glass.

9. A interposer for optical chip packaging, comprising:

a glass substrate comprising one or more first conductive vias, the first conductive vias comprising a via through the glass substrate and a conductive material filled in the via; and

An electrical interconnect structure disposed on the first surface of the glass substrate,

wherein the electrical interconnection structure comprises one or more wiring layers and a coating layer for coating the one or more wiring layers, the coating layer is made of dielectric material, the one or more wiring layers are used for electrically interconnecting a plurality of electrical chips packaged above the adapter plate, and

the electrical interconnect structure further includes one or more first conductive structures extending through the electrical interconnect structure and electrically connected with the one or more first conductive vias, respectively.

10. The interposer of claim 9, wherein

At least two wiring layers in the multi-layer wiring layers are electrically connected through a second conductive structure.

11. The interposer of claim 9, wherein

The cladding layer is a multilayer structure formed by alternately stacking silicon nitride layers and silicon dioxide layers.

12. The interposer of claim 9, further comprising:

an optical waveguide structure arranged on a surface of the electrical interconnection structure on a side remote from the glass substrate,

wherein the optical waveguide structure comprises one or more optical waveguides and an enclosing layer enclosing the one or more optical waveguides,

The one or more optical waveguides are used for optically interconnecting a plurality of optical chips packaged on the adapter plate, and have a refractive index greater than that of the surrounding layer

The optical waveguide structure further includes one or more third conductive structures extending through the optical waveguide structure and electrically connected to the one or more first conductive structures, respectively.

13. The interposer as recited in claim 12, wherein

The one or more optical waveguides are silicon nitride optical waveguides and the material of the surrounding layer is silicon dioxide.

14. The interposer of claim 9, further comprising:

a dielectric layer disposed on the second surface of the glass substrate;

wherein the dielectric layer comprises one or more fourth conductive structures penetrating the dielectric layer and electrically connected with the one or more first conductive vias respectively, and

the one or more conductive bumps are electrically connected with the one or more fourth conductive structures, respectively.

15. A method of manufacturing a interposer for optical chip packaging, comprising:

providing a glass substrate and forming one or more conductive through holes in the glass substrate;

Disposing an optical waveguide structure on a first surface of the glass substrate, wherein the optical waveguide structure includes one or more layers of optical waveguides and a cladding layer cladding the one or more layers of optical waveguides; and

forming one or more first conductive structures penetrating the optical waveguide structure in the cladding layer and electrically connecting the first conductive structures with the one or more conductive vias, respectively,

wherein the refractive index of the one or more layers of optical waveguides is greater than the refractive index of the cladding layer.

16. The method of manufacturing an interposer as claimed in claim 15, wherein

17. The method of manufacturing an interposer as claimed in claim 16, wherein disposing an optical waveguide structure on the first surface of the glass substrate comprises:

a. forming a network of optical waveguides on a first surface of the glass substrate using wafer level nanoimprint lithography; and

b. a cladding material is deposited over the optical waveguide.

18. The method of manufacturing an interposer of claim 15, further comprising:

disposing a dielectric layer on a second surface of the glass substrate;

Forming one or more second conductive structures in the dielectric layer through the dielectric layer and electrically connecting them with the one or more conductive vias, respectively; and

one or more conductive bumps are arranged on the surface of the dielectric layer on the side remote from the glass substrate,

wherein the one or more conductive bumps are electrically connected with the one or more second conductive structures, respectively.

19. The method of manufacturing an interposer as recited in claim 15, wherein forming one or more conductive vias in the glass substrate comprises:

forming one or more through holes in the glass substrate by etching; and

a layer of conductive material is disposed on an inner surface of the one or more vias to form the one or more conductive vias.

20. The method of manufacturing an interposer as recited in claim 19, wherein disposing a layer of conductive material on an inner surface of the one or more vias to form the one or more conductive vias comprises:

and filling conductive metal on the inner surfaces of the one or more through holes by adopting an electroplating method.

21. A method of manufacturing a interposer for optical chip packaging, comprising:

providing a glass substrate, and forming a three-dimensional waveguide network in the glass substrate, wherein the three-dimensional waveguide network is used for optically interconnecting a plurality of optical chips packaged on the adapter plate;

Forming one or more conductive vias in the glass substrate;

arranging a coupling optical waveguide on the first surface of the glass substrate to cover the optical input/output port of the three-dimensional waveguide network;

coating a coating layer on the coupling optical waveguide to coat the coupling optical waveguide; and

one or more first conductive structures are formed in the cladding layer and electrically connected with the one or more conductive vias, respectively.

22. The method of manufacturing an interposer as claimed in claim 21, wherein,

wherein the refractive index of the coupled optical waveguide is lower than the refractive index of the three-dimensional waveguide network and higher than the refractive index of the cladding layer.

23. The method of manufacturing an interposer as recited in claim 22, wherein

24. The method of manufacturing an interposer of claim 21, further comprising:

disposing a dielectric layer on a second surface of the glass substrate;

25. The method of manufacturing an interposer as recited in claim 21, wherein forming one or more conductive vias in the glass substrate comprises:

forming one or more through holes in the glass substrate by etching; and

26. The method of manufacturing an interposer as recited in claim 25, wherein disposing a layer of conductive material on an inner surface of the one or more vias to form the one or more conductive vias comprises:

27. The method of manufacturing an interposer as recited in claim 21, wherein forming a three-dimensional waveguide network within the glass substrate comprises:

and irradiating a preset position of the glass substrate by using femtosecond laser to improve the refractive index of the preset position of the glass substrate, wherein the preset position is the position where the three-dimensional waveguide network structure is formed.

28. A method of manufacturing a interposer for optical chip packaging, comprising:

providing a glass substrate, and forming one or more first conductive through holes in the glass substrate;

arranging an electrical interconnection structure on the first surface of the glass substrate, wherein the electrical interconnection structure comprises one or more wiring layers and a coating layer for coating the one or more wiring layers, the coating layer is made of dielectric materials, and the one or more wiring layers are used for electrically interconnecting a plurality of electrical chips packaged above the adapter plate; and

one or more first conductive structures are formed in the electrical interconnect structure through the electrical interconnect structure and are electrically connected with the one or more first conductive vias, respectively.

29. The method of manufacturing an interposer as claimed in claim 28, wherein disposing an electrical interconnect structure on the first surface of the glass substrate comprises:

disposing a first wiring layer on a first surface of the glass substrate;

forming a first silicon nitride sub-layer around the first wiring layer; and

and covering the first silicon nitride sub-layer with a first silicon oxide sub-layer.

30. The method of manufacturing an interposer as recited in claim 29, wherein disposing an electrical interconnect structure on the first surface of the glass substrate further comprises:

Disposing a second wiring layer on the first surface of the first silicon oxide sub-layer;

forming a second silicon nitride sub-layer around the second wiring layer; and

and covering a second silicon dioxide sub-layer on the second silicon nitride sub-layer.

31. The method of manufacturing an interposer as claimed in claim 30, wherein disposing an electrical interconnect structure on the first surface of the glass substrate further comprises:

and forming a second conductive structure between the first wiring layer and the second wiring layer to electrically connect the first wiring layer and the second wiring layer.

32. The method of manufacturing an interposer of claim 28, further comprising:

arranging an optical waveguide structure on the surface of the electric interconnection structure, which is far away from the glass substrate side, wherein the optical waveguide structure comprises one or more layers of optical waveguides and an enclosing layer enclosing the one or more layers of optical waveguides, the one or more layers of optical waveguides are used for carrying out optical interconnection on a plurality of optical chips packaged on the adapter plate, and the refractive index of the optical waveguides is larger than that of the enclosing layer; and

one or more third conductive structures penetrating the optical waveguide structure are formed in the optical waveguide structure and are electrically connected with the one or more first conductive structures, respectively.

33. The method of manufacturing an interposer as recited in claim 32, wherein

34. The method of manufacturing an interposer of claim 28, further comprising:

disposing a dielectric layer on a second surface of the glass substrate;

forming one or more fourth conductive structures in the dielectric layer through the dielectric layer and electrically connected with the one or more first conductive vias, respectively; and

wherein the one or more conductive bumps are electrically connected with the one or more fourth conductive structures, respectively.

35. The method of manufacturing an interposer as recited in claim 28, wherein forming one or more conductive vias in the glass substrate comprises:

forming one or more through holes in the glass substrate by etching; and

36. The method of manufacturing an interposer as recited in claim 35, wherein disposing a layer of conductive material on an inner surface of the one or more vias to form the one or more conductive vias comprises:

37. An optical chip package structure comprising the interposer of any one of claims 1-14, and a plurality of optical chips disposed on the interposer for optically and/or electrically interconnecting the plurality of optical chips disposed on the interposer.

38. The optical chip package structure of claim 37, further comprising:

one or more electrical chips disposed on the plurality of optical chips;

the optical chip comprises one or more interconnection structures, wherein the interconnection structures comprise through holes penetrating through the optical chip and conductive materials filled in the through holes;

the one or more interconnect structures are electrically connected to the one or more first conductive structures and/or the one or more electrical interconnect structures on the interposer, respectively.

39. An optical chip package structure, comprising:

a patch panel including one or more first optical waveguides embedded therein; and

a plurality of optical chips, each optical chip including one or more second optical waveguides embedded therein,

wherein the plurality of optical chips are attached to the upper surface of the interposer at different positions and optically interconnected by the one or more first optical waveguides,

Each of the first optical waveguides includes a first optical coupling portion,

each of the second optical waveguides includes a second optical coupling portion, and

the first light coupling part and the second light coupling part are overlapped in a direction perpendicular to the upper surface of the adapter plate and spaced apart by a predetermined distance such that the first light coupling part and the second light coupling part achieve adiabatic coupling of light.

40. The optical chip package structure of claim 39, wherein,

the first light coupling portion and the second light coupling portion are tapered shapes, respectively.

41. The optical chip package structure of claim 39, wherein,

the first light coupling portion and the second light coupling portion have shapes formed by cascading two tapered shapes of different sizes, respectively.

42. The optical chip package structure of any one of claims 39 to 41, wherein,

the predetermined distance is less than or equal to 600nm.

43. The optical chip package structure of claim 39, further comprising:

a plurality of electrical chips disposed on a plurality of first optical chips of the plurality of optical chips,

wherein each first optical chip has one or more first electrical connectors on its upper surface,

each electrical chip has one or more second electrical connectors on a lower surface thereof, an

The one or more first electrical connectors are electrically connected to the one or more second electrical connectors, respectively.

44. The optical chip package structure of claim 43, wherein,

the first optical chip further comprises one or more second conductive through holes penetrating through the first optical chip, and the one or more second conductive through holes are respectively and electrically connected with one or more conductive structures in the adapter plate.

45. The optical chip package structure of claim 43 or 44, wherein,

the first optical chip is directly bonded with the electrical chip; or alternatively

The first optical chip and the electric chip are bonded by flip-chip bonding.

46. The optical chip package structure of any one of claims 39 to 44, wherein,

the multiple optical chips are separated optical chips obtained by dividing photon wafer, the gaps between the optical chips are filled with injection molding material and are spaced apart from each other on the upper surface of the adapter plate

A dielectric layer for blocking light in the adapter plate from transmitting outwards is arranged between the injection molding material and the upper surface of the adapter plate.

47. The optical chip package structure of any one of claims 39 to 44, wherein,

The plurality of optical chips are not divided in the same photonic wafer.

48. The optical chip package structure of claim 43 or 44, wherein,

the plurality of optical chips are optical chips which are not segmented in the same photon wafer,

the plurality of optical chips have a plurality of first optical chips, each first optical chip having an electrical chip disposed thereon,

the plurality of electric chips on the plurality of first optical chips are a plurality of electric chips which are not divided in the same electronic wafer, and

the photonic wafer is directly bonded to the electronic wafer.

49. The optical chip package structure of claim 48, wherein,

the corresponding electric chips are arranged on all the optical chips in the plurality of optical chips, and the corresponding electric chips on all the optical chips are a plurality of electric chips which are not divided in the same electronic wafer, and

wherein the plurality of optical chips have the same structure and the plurality of electrical chips also have the same structure.

50. The optical chip package structure of any one of claims 39 to 49, wherein,

the interposer is an interposer as claimed in any one of claims 1-3 and 12-14, and the one or more first optical waveguides are one or more layers of optical waveguides in an optical waveguide structure of the interposer as claimed in any one of claims 1-3 and 12-14.

51. The optical chip package structure of any one of claims 39 to 49, wherein,

the interposer is the interposer of any one of claims 4-8, and the one or more first optical waveguides are the three-dimensional waveguide network in the interposer of any one of claims 4-8 and the coupled optical waveguides covering the optical input/output ports of the three-dimensional waveguide network.

52. A computing accelerator, comprising:

one or more light sources disposed on a first surface of the interposer in the optical chip package structure of any one of claims 43-46 and configured to provide light waves to the computational accelerator;

one or more computing units implemented by the optical chip in the optical chip package structure of any one of claims 39-42, or by the optical chip and electrical chip in the optical chip package structure of any one of claims 43-46, or by the electrical chip in the optical chip package structure of any one of claims 43-46, and configured to perform a computing function;

one or more memory cells implemented by an electrical chip in the optical chip package structure of any one of claims 43-46 and configured to perform a memory function.

53. The computational accelerator of claim 52 wherein,

the interposer is as claimed in any one of claims 1-8 and 12-14.

54. A computing accelerator, comprising:

one or more edge optocouplers configured to optically interconnect the computational accelerator with other devices;

one or more light sources configured to provide light waves to the computing accelerator, the light waves coupled to the one or more edge light couplers through a light guide structure;

one or more computing units implemented by the optical chip in the optical chip package structure of any one of claims 39-42, or by the optical chip and electrical chip in the optical chip package structure of any one of claims 47-49, or by the electrical chip in the optical chip package structure of any one of claims 47-49, and configured to perform a computing function; and

one or more memory cells implemented by an electrical chip in the optical chip package structure of any one of claims 47-49 and configured to perform a memory function.

55. The computational accelerator of claim 54 wherein,

Each calculation unit and corresponding memory unit are implemented by each optical chip and corresponding electrical chip in the optical chip package structure of claim 49 as a calculation-memory unit.

56. A computing accelerator as defined in claim 54 or 55, wherein,

the interposer in the optical chip package structure is the interposer according to any one of claims 1-8 and claims 12-14.

57. The computing accelerator of any one of claims 52 to 56, further comprising:

a plurality of High Bandwidth Memory (HBM) chips stacked on the optical chip in the optical chip package structure configured to perform a memory computation function.

58. A method of fabricating an optical chip package structure, comprising:

providing an adapter plate comprising one or more first optical waveguides embedded therein, each of said first optical waveguides comprising a first optical coupling portion; and

attaching a plurality of optical chips to the upper surface of the adapter plate at different positions, each optical chip including one or more second optical waveguides embedded therein, each second optical waveguide including a second optical coupling portion, wherein

The first light coupling portion and the second light coupling portion are stacked and spaced apart from each other by a predetermined distance in a direction perpendicular to an upper surface of the interposer such that the first light coupling portion and the second light coupling portion achieve adiabatic coupling of light, and the plurality of optical chips are optically interconnected through the one or more first optical waveguides.

59. The method of manufacturing the optical chip package structure of claim 58, wherein,

60. The method of manufacturing the optical chip package structure of claim 58, wherein,

61. The method of manufacturing a photo chip package as recited in any one of claims 58 to 60, wherein,

the predetermined distance is less than or equal to 600nm.

62. The method of manufacturing a photo chip package as defined in claim 58, further comprising, prior to attaching the plurality of photo chips to the interposer at different locations on the upper surface:

disposing an electrical chip on a first optical chip of the plurality of optical chips such that the first optical chip and the electrical chip thereon form an electron-photon hybrid chip,

wherein the upper surface of the first optical chip is provided with one or more first electric connectors,

the lower surface of the electrical chip is provided with one or more second electrical connectors, and

63. The method of manufacturing the optical chip package structure of claim 62, wherein disposing an electrical chip on a first optical chip of the plurality of optical chips comprises:

preparing a photon wafer and an electron wafer, wherein the photon wafer comprises a plurality of first optical chips, and the electron wafer comprises a plurality of electric chips;

bonding the electronic wafer directly to the photonic wafer so that the plurality of first optical chips and the plurality of electrical chips are bonded to obtain an electronic-photonic hybrid wafer;

removing the substrate of the photonic wafer; and

the electron-photon mixing wafer is cut into a plurality of electron-photon mixing chips.

64. The method of manufacturing the optical chip package structure of claim 62, wherein disposing an electrical chip on a first optical chip of the plurality of optical chips comprises:

preparing a photon wafer and an electron wafer, wherein the photon wafer comprises a plurality of optical chips, and the electron wafer comprises a plurality of electric chips;

dicing the electronic wafer into the plurality of electrical chips;

bonding or flip-chip bonding one or more of the plurality of electrical chips directly to a first optical chip in the photonic wafer to obtain an electron-photon hybrid wafer;

Filling injection molding materials in gaps, which are not occupied by the electronic chips, on the photonic wafer;

removing the substrate of the photonic wafer; and

and cutting the electron-photon mixed wafer into the electron-photon mixed chips.

65. The method of manufacturing a photo chip package of claim 59 or 64, further comprising:

and after removing the substrate of the photonic wafer, thinning the buried oxide layer at the bottom of the photonic wafer to a preset thickness before cutting the electronic-photonic mixed wafer into the electronic-photonic mixed chips.

66. The method of manufacturing a photo chip package as claimed in claim 63 or 64, further comprising:

after removing the substrate of the photonic wafer, thinning the buried oxide layer of the bottom surface of the photonic wafer, and forming a connection waveguide on the surface of the photonic wafer away from the electrical chip, wherein the connection waveguide and the second optical coupling part of the second optical waveguide and the first optical coupling part of the first waveguide are overlapped and spaced apart in the vertical direction of the lower surface of the photonic wafer; and

a dielectric is coated over the connection waveguide to encapsulate the connection waveguide.

67. The method of manufacturing a photo chip package as claimed in claim 63 or 64, further comprising:

Forming one or more second conductive vias in the photonic wafer after preparing the photonic wafer; and after removing the substrate of the photonic wafer, thinning the buried oxide layer at the bottom of the photonic wafer to a predetermined thickness to enable the one or more second conductive holes to penetrate up and down so as to form one or more second conductive through holes.

68. The method of manufacturing a photo chip package as defined in claim 66, wherein attaching the plurality of photo chips to different locations on the upper surface of the interposer further comprises:

and respectively and electrically connecting the one or more second conductive through holes with one or more conductive structures in the adapter plate.

69. The method of manufacturing the optical chip package structure of claim 62, wherein the plurality of electronic-photonic hybrid chips are spaced apart from each other on the upper surface of the interposer, and the method further comprises:

forming a dielectric layer on an upper surface of the interposer and in gaps between the plurality of electron-photon hybrid chips for blocking light in the interposer from being transmitted outwards; and

an injection molding material is filled over the dielectric layer and in the gaps of the electron-photon chiplet.

70. The method of manufacturing the optical chip package structure of claim 62, wherein,

disposing an electrical chip on a first optical chip of the plurality of optical chips includes:

preparing a photonic wafer comprising a plurality of first optical chips and an electronic wafer comprising a plurality of electrical chips, and

bonding the electronic wafer directly to the photonic wafer so that the plurality of first optical chips and the plurality of electrical chips are bonded to obtain an electronic-photonic hybrid wafer; and

attaching a plurality of optical chips to different locations on the upper surface of the interposer includes:

the electron-photon hybrid wafer is directly bonded to the upper surface of the interposer.

71. The method of manufacturing a photo chip package as claimed in any one of claims 58 to 70, wherein,

the interposer is fabricated according to the method of any one of claims 15-20 and claims 28-36, and the one or more first optical waveguides are one or more layers of optical waveguides in an optical waveguide structure in the interposer fabricated according to the method of any one of claims 15-20 and claims 28-36.

72. The method of manufacturing a photo chip package as claimed in any one of claims 58 to 70, wherein,

The interposer is fabricated according to the method of any one of claims 21-27, and the one or more first optical waveguides are a three-dimensional waveguide network in the interposer fabricated according to the method of any one of claims 21-27 and a coupled optical waveguide covering an optical input/output port of the three-dimensional waveguide network.