CN116915236A - Driving circuit and input/output port circuit - Google Patents

Abstract

The application discloses a driving circuit and an input/output port circuit, comprising: two driving branches with the same structure; each driving branch circuit comprises a corresponding level shifter and a pre-driving circuit; the level shifter of the first driving branch is connected with the pre-driving circuit; the level shifter of the second driving branch is connected with the pre-driving circuit; wherein the level shifter is configured to: converting the internal low voltage signal into a power supply voltage of an Input Output (IO) required for external driving; the pre-driving circuit comprises a first pre-driving circuit branch composed of high-voltage devices and a second pre-driving circuit branch composed of low-voltage devices, and is set as follows: and selecting the first branch of the pre-driving circuit or the second branch of the pre-driving circuit to drive the output driving tube to output driving signals according to the power supply voltage of IO obtained through conversion of the level shifter. The embodiment of the disclosure realizes the driving circuit meeting the wide voltage range and provides support for meeting the transmission speed requirement of the IO port.

Description

Driving circuit and input/output port circuit

Technical Field

The present application relates to, but is not limited to, integrated circuit technology, which relates to a driving circuit and an input-output port circuit.

Background

An input-output (IO) port circuit is one of the basic modules in a chip, and its main function is to provide an interface between a package pin and the inside of the chip, introduce an external signal into the inside of the chip to implement a logic function, and output the result to a circuit outside the chip, where a plurality of different interface standards can be supported through configuration according to requirements.

According to different signal transmission directions, the IO port circuit can be divided into a driving circuit and a receiving circuit, and the driving circuit can be divided into a single-ended driving circuit (used for supporting single-ended transmission protocols such as high-speed multimode multichannel (LVCMOS)) and a differential driving circuit (used for supporting transmission protocols such as low-voltage differential signaling (LVDS)) according to different protocol standards; the single-ended driving circuit is generally composed of a level shifter, a pre-driver and a driver three-stage structure, and the function of converting an output signal from internal low voltage to IO voltage is realized; because of the diversity of external load level standards, the design requirement of the IO is compatible with a wide power supply voltage range from 1.0V to 3.3V, so that the design of the IO circuit has to adopt a large-size metal-oxide semiconductor field effect transistor (MOS) transistor resistant to 3.3V high voltage, and when the IO power supply voltage is low (for example, 1.0V), the large-size MOS transistor is driven by a low power supply voltage, which results in significantly slow circuit speed and cannot meet the high-speed application requirement. The prior application with the application number of 2017112490908 discloses a high-speed IO circuit which realizes high voltage resistance by utilizing a low-voltage device, and an electrostatic discharge (ESD) tube is protected in a mode of connecting a resistor and an MOS tube in series so that the ESD tube can resist high voltage by utilizing the low-voltage MOS tube, but the output interface of the ESD tube is connected to the ground, and resistors are connected in series between a power supply and the ground, so that on one hand, the power consumption of the circuit is increased, and on the other hand, the realization of high-speed voltage is not facilitated due to the introduction of additional resistors and capacitors; the prior application with the application number 2020203534641 discloses a circuit with the coexistence of a high-speed IO and a high-voltage circuit of a programmer, and the prior application with the application number 2019100238489 discloses a high-voltage high-speed IO circuit based on a low-voltage device, which provides other voltage protection modes, but takes series resistance as a main means, and is similar to the scheme, so that the power consumption of the circuit is increased, and the transmission speed of the IO circuit is limited.

In summary, how to realize a single-ended driving circuit meeting application requirements becomes a problem to be solved.

Disclosure of Invention

The following is a summary of the subject matter of the detailed description of the application. This summary is not intended to limit the scope of the claims.

The embodiment of the disclosure provides a driving circuit and an input/output port circuit, which can meet the power consumption and transmission speed requirements of an IO circuit.

The embodiment of the disclosure provides a driving circuit, comprising: two driving branches with the same structure; each driving branch circuit comprises a corresponding level shifter and a pre-driving circuit; the level shifter of the first driving branch is connected with the pre-driving circuit; the level shifter of the second driving branch is connected with the pre-driving circuit; wherein,,

the level shifter is set to: converting the internal low voltage signal into a power supply voltage of an Input Output (IO) required for external driving;

the pre-driving circuit comprises a first pre-driving circuit branch composed of high-voltage devices and a second pre-driving circuit branch composed of low-voltage devices, and is set as follows: selecting a first branch of the pre-driving circuit or a second branch of the pre-driving circuit to drive an output driving tube to output a driving signal according to the power supply voltage of IO obtained through conversion of the level shifter;

the high-voltage device comprises a device with bearable voltage larger than or equal to a preset first voltage threshold value; the low-voltage device comprises a device with bearable voltage less than or equal to a preset second voltage threshold; the output drive tube includes: a first output drive tube connected to the pre-drive circuit of the first drive branch; and a second output driving tube connected with the pre-driving circuit of the second driving branch.

On the other hand, the embodiment of the disclosure also provides an input/output port circuit, which comprises the driving circuit.

Compared with the related art, the application comprises the following steps: two driving branches with the same structure; each driving branch circuit comprises a corresponding level shifter and a pre-driving circuit; the level shifter of the first driving branch is connected with the pre-driving circuit; the level shifter of the second driving branch is connected with the pre-driving circuit; wherein the level shifter is configured to: converting the internal low voltage signal into a power supply voltage of an Input Output (IO) required for external driving; the pre-driving circuit comprises a first pre-driving circuit branch composed of high-voltage devices and a second pre-driving circuit branch composed of low-voltage devices, and is set as follows: selecting a first branch of the pre-driving circuit or a second branch of the pre-driving circuit to drive an output driving tube to output a driving signal according to the power supply voltage of IO obtained through conversion of the level shifter; the high-voltage device comprises a device with bearable voltage larger than or equal to a preset first voltage threshold value; the low-voltage device comprises a device with bearable voltage less than or equal to a preset second voltage threshold; the output drive tube includes: a first output drive tube connected to the pre-drive circuit of the first drive leg, and a second output drive tube connected to the pre-drive circuit of the second drive leg. The embodiment of the disclosure realizes the driving circuit meeting the wide voltage range and provides support for meeting the transmission speed requirement of the IO port.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the principles of the application, and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain, without limitation, the principles of the application.

FIG. 1 is a flow chart of a method of image processing according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a first branch of a pre-driving circuit according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of a second branch of the pre-driving circuit according to an embodiment of the disclosure;

fig. 4 is a schematic diagram of a composition structure of a comparator according to an embodiment of the disclosure.

Detailed Description

The present application has been described in terms of several embodiments, but the description is illustrative and not restrictive, and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the described embodiments. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features and elements of the present application may also be combined with any conventional features or elements to form a unique inventive arrangement as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. It is therefore to be understood that any of the features shown and/or discussed in the present application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.

Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

Fig. 1 is a block diagram of a driving circuit according to an embodiment of the present disclosure, as shown in fig. 1, including: two driving branches with the same structure; each driving branch circuit comprises a corresponding level shifter 1-1 and a pre-driving circuit 1-2; the level shifter 1-1 of the first driving branch is connected with the pre-driving circuit 1-2; the level shifter 1-1 of the second driving branch is connected with the pre-driving circuit 1-2; wherein,,

the level shifter 1-1 is set to: converting an internal low voltage signal into a power supply Voltage (VCC) of an input/output IO required for external driving _IO )；

The pre-driving circuit 1-2 includes a pre-driving circuit first branch 1-2-1 composed of high voltage devices and a pre-driving circuit second branch 1-2-2 composed of low voltage devices, and is configured to: selecting a first branch 1-2-1 of the pre-driving circuit or a second branch 1-2-2 of the pre-driving circuit to drive an output driving tube to output a driving signal according to the power supply voltage of IO obtained through conversion of the level shifter 1-1;

the high-voltage device comprises a device with bearable voltage larger than or equal to a preset first voltage threshold value; the low-voltage device comprises a device with bearable voltage smaller than or equal to a preset second voltage threshold value; the output drive tube includes: a first output drive tube 1-3 connected to the pre-drive circuit 1-2 of the first drive branch; and a second output driving tube 2-3 connected to the pre-driving circuit 1-2 of the second driving branch.

According to the embodiment of the disclosure, the pre-driving circuit constructed by the high-voltage device and the low-voltage device is arranged, and the output driving tube is selected to drive the output driving tube to output the driving signal according to the power voltage of IO obtained through conversion of the level shifter 1-1, or the first branch 1-2-1 or the second branch 1-2-2 of the pre-driving circuit, so that the driving circuit meeting the wide voltage range is realized, and support is provided for meeting the transmission speed requirement of an IO port.

The embodiment of the disclosure can be compatible with the output level standard of a high-voltage circuit, and when the level shifter 1-1, the pre-driving circuit 1-2, the first output driving tube 1-3 and the second output driving tube 2-3 are implemented by adopting high-voltage large-size devices, the problem that the transmission speed of the IO driving circuit is slower and the transmission speed is limited due to the high-voltage large-size devices when the power supply voltage of IO is lower is avoided through the pre-driving circuit 1-2. The pre-driving circuit 1-2 of the embodiment of the disclosure comprises two parts divided according to high voltage and low voltage, namely a first branch 1-2-1 of the pre-driving circuit formed by high voltage devices and a second branch 1-2-2 of the pre-driving circuit formed by low voltage devices. The outputs of the pre-drive circuits 1-2 of the two drive branches are connected to the first output drive pipe 1-3 and the second output drive pipe 2-3 of the final output stage, respectively, in a one-to-one correspondence. When the power supply voltage of IO is high voltage (for example, 2.5V, 3.3V), the first branch 1-2-1 of the high-voltage-resistant pre-drive circuit works, so that the function of high-speed transmission of high-voltage signals is realized; when the power supply voltage of IO (VCC _IO ) When the voltage is low (for example, 1.8V and below), the second branch 1-2-2 of the low-voltage pre-driving circuit works, and the function of transmitting low-voltage signals at high speed is realized.

In one illustrative example, the pre-drive circuit 1-2 of the disclosed embodiments is configured to:

when the power supply voltage VCC of IO _IO When the voltage is smaller than or equal to a preset protection voltage (Vprotection), the first branch 1-2-1 of the pre-driving circuit is communicated through a preset first control signal;

when the power supply voltage of IO (VCC _IO ) When the voltage is greater than the protection voltage, through a preset second control signalAnd the second branch 1-2-2 of the pre-driving circuit is communicated.

The protection voltage (vpprotection) of the embodiment of the disclosure only provides a protection potential, and is not used as a power supply, so that no requirement is made on power supply capability, and the protection voltage can be generated by an on-chip linear regulator (LDO), or generated by resistor voltage division, or an external voltage, which is not higher than the withstand voltage value of the low-voltage tube, is adopted; in one illustrative example, the protection voltage is the withstand voltage value; for example, if the withstand voltage of the low-voltage-resistant MOS tube is 1.8V, the protection voltage is set to be not higher than 1.8V so as to provide protection capability; in an exemplary embodiment, when the withstand voltage of the low-voltage resistant MOS transistor is 1.8V, the protection voltage is set to 1.8V.

Fig. 2 is a schematic diagram of a first branch of a pre-driving circuit according to an embodiment of the disclosure, as shown in fig. 2, the first branch 1-2-1 of the pre-driving circuit according to the embodiment of the disclosure includes: the first MOS transistor 114 with the pull-up function and the second MOS transistor 115 with the pull-down function are connected with the output end of the first logic circuit 111 or grounded, the grid electrodes of the first MOS transistor 114 and the second MOS transistor 115 are connected with the second end of the first switch 112 after being connected, the first end of the second switch 113 is connected with the power supply voltage of IO, the second end of the second switch 113 is connected with the source stage of the first MOS transistor, the drain electrode of the first MOS transistor 114 is connected with the drain electrode of the second MOS transistor 115 and then is connected with the output driving transistor, and the source stage of the second MOS transistor 115 is grounded; the first branch 1-2-1 of the pre-drive circuit is arranged to:

the second switch 113 is turned on according to the first control signal, and the output driving pipe is driven by controlling the first switch 112 to turn on the output of the first logic circuit 111.

It should be noted that the first branch 1-2-1 of the pre-driving circuit according to the embodiments of the present disclosure may be designed and implemented based on the principles of the above examples. The embodiment of the disclosure is based on the first branch 1-2-1 of the pre-driving circuit, and the signal for driving the output driving tube is output through the first branch 1-2-1 of the gating pre-driving circuit under the high voltage condition, so that the driving signal output under the high voltage condition is realized.

In an illustrative example, the first MOS transistor 114 and the second MOS transistor 115 in the embodiment of the present disclosure are MOS transistors having a withstand voltage value greater than a preset third voltage threshold.

In an exemplary embodiment, the withstand voltage value of the embodiment of the disclosure is greater than the preset third voltage threshold, and may be regarded as a high-voltage-resistant MOS tube; in an illustrative example, the third voltage threshold and the first voltage threshold of embodiments of the present disclosure may or may not be equal;

in one illustrative example, the first switch 112 in the embodiments of the present disclosure may be a two-out switch.

In an illustrative example, the first MOS transistor 114 in the embodiments of the present disclosure may be a PMOS transistor;

in one illustrative example, the second MOS transistor 115 in the embodiments of the present disclosure may be an NMOS transistor;

in an illustrative example, the first logic circuit 111 of the disclosed embodiment is a specific logic implementation, which may be an and gate, an or gate, an inverter, or a logic circuit composed thereof;

in an illustrative example, the first switch 112 and/or the second switch 113 in the embodiments of the disclosure may be implemented by using MOS transistors, or may be implemented by using transmission transistors or logic circuits;

in one illustrative example, the implementation of the level shifter 1-1 of the presently disclosed embodiments is versatile and may be implemented with reference to related art designs; the first output drive tube 1-3 and/or the second output drive tube 2-3 in the embodiments of the present disclosure are output drive MOS tubes, which are conventional constituent parts of an IO drive circuit.

Fig. 3 is a schematic diagram of a second branch of the pre-driving circuit according to the embodiment of the disclosure, as shown in fig. 3, the second branch 1-2-2 of the pre-driving circuit according to the embodiment of the disclosure includes: the second logic circuit 123, the third logic circuit 126, the third switch 121, the fourth switch 122, the fifth switch 124, the sixth switch 125, the seventh switch 127, the eighth switch 128, the ninth switch 129, the tenth switch 1210, the third MOS transistor 1211 with pull-up function, and the fourth MOS transistor 1212 with pull-down function, wherein a first end of the third switch 121 is connected to the power supply voltage (VCC _IO ) The second end of the third switch 121 is connected toA second logic circuit 123; the first end of the fourth switch 122 is grounded, and the second end of the fourth switch 122 is connected to the second logic circuit 123; the input terminals of the second logic circuit 123 and the third logic circuit 126 are used for receiving the second control signal; the first terminal of the fifth switch 124 is connected to the power supply Voltage (VCC) _IO ) A second terminal of the fifth switch 124 is connected to the third logic circuit 126; the first end of the sixth switch 125 is grounded, and the second end of the sixth switch 125 is connected to the third logic circuit 126; a first terminal of the seventh switch 127 receives a preset protection voltage (vpprotection), and a second terminal of the seventh switch 127 is connected to an output of the second logic circuit 123; a first terminal of the eighth switch 128 receives a preset protection voltage (vpprotection), and an output of the eighth switch 128 connected to the third logic circuit 126; the first terminal of the ninth switch 129 receives the supply Voltage (VCC) of IO _IO ) The second end of the ninth switch 129 is connected with the source electrode of the third MOS tube 1211, the grid electrode of the third MOS tube 1211 is connected with the output of the second logic circuit 123, and the drain electrode of the third MOS tube 1211 is connected with the drain electrode of the fourth MOS tube and then is connected with the output driving tube; the first end of the tenth switch 1210 is grounded, and the second end of the tenth switch 1210 is connected to the source electrode of the fourth MOS transistor 1212; the second branch 1-2-2 of the pre-drive circuit is arranged to:

when receiving the second control signal, the second logic circuit 123 and the third logic circuit 126 are turned on to drive the output driving tube;

wherein the protection voltage is less than or equal to the withstand voltage value of the low-voltage device.

It should be noted that the second branch 1-2-2 of the pre-driving circuit according to the embodiments of the present disclosure may be designed and implemented based on the principles of the above examples. The embodiment of the disclosure is based on the second branch 1-2-2 of the pre-driving circuit, and realizes the output of driving signals under the low-voltage condition.

In an illustrative example, embodiments of the present disclosure may implement one or more of the following switches with one or more of MOS transistors, transmission transistors, or logic circuits: the third switch 121, the fourth switch 122, the fifth switch 124, the sixth switch 125, the eighth switch 127, the ninth switch 128, the tenth switch 129, and the eleventh switch 1210.

In an illustrative example, the third MOS transistor 1211 in the embodiment of the present disclosure may be a PMOS transistor;

in one illustrative example, fourth MOS transistor 1212 in an embodiment of the present disclosure may be an NMOS transistor.

In an illustrative example, the second logic circuit 123 and the third logic circuit 126 in the embodiments of the present disclosure are specific logic implementations, which may be and gates, or gates, inverters, or logic circuits composed thereof. In an illustrative example, the third MOS transistor 1211 and the fourth MOS transistor 1212 with a pull-down function according to the embodiment of the present disclosure are MOS transistors having a withstand voltage value lower than a fourth voltage threshold value set in advance. The withstand voltage value of the embodiment of the disclosure is lower than the preset fourth voltage threshold value, and can be regarded as a low-voltage-resistant MOS tube; in an illustrative example, the fourth voltage threshold and the second voltage threshold of embodiments of the present disclosure may or may not be equal;

in one illustrative example, the first control signal of an embodiment of the present disclosure includes a low voltage select signal of a first level; the second control signal includes a low voltage selection signal of a second level.

It should be noted that the first control signal and the second control signal in the embodiments of the present disclosure may be other signals that may be used for the gating process, and may be implemented by those skilled in the art with reference to the related principle design of the circuit design, which is not limited in the embodiments of the present disclosure.

In one illustrative example, the first control signal and the second control signal of the presently disclosed embodiments are generated by a preset comparator 401.

Fig. 4 is a schematic diagram of the composition structure of a comparator according to an embodiment of the disclosure, and as shown in fig. 4, a comparator 401 is configured to:

when the power supply voltage of IO (VCC _IO ) Generating a low voltage selection signal of a first level when the voltage is greater than a protection voltage (vpprotection);

when the power supply voltage of IO (VCC _IO ) And generating a low voltage selection signal of a second level when the voltage is smaller than the protection voltage (Vprotection).

In one illustrative example, the low voltage select signal of the first level of the disclosed embodiments is a low voltage select signal of a low levelA number; the low voltage selection signal of the second level is a low voltage selection signal of a high level. The embodiment of the disclosure can realize the automatic identification and switching functions of the power supply voltage of IO based on the low-voltage selection signal; when the power supply voltage of IO (VCC _IO ) When the voltage is larger than the protection voltage (vpprotection), the low-voltage selection signal generated by the comparator 401 is at a low level, and the pre-driving circuit 1-2 gates the low-voltage pre-driving circuit second branch 1-2-2 of the first driving branch and the second driving branch; when the power supply voltage of IO (VCC _IO ) When the voltage is smaller than the protection voltage (vpprotection), the low voltage selection signal generated by the comparator 401 is at a high level, and the pre-driving circuit 1-2 gates the high voltage pre-driving circuit first branch 1-2-1 of the first driving branch and the second driving branch. Through the selection of different paths, the pre-driving circuit 1-2 can realize high-voltage driving of a large-size high-voltage MOS tube and low-voltage driving of a small-size low-voltage MOS tube; embodiments of the present disclosure implement the supply Voltage (VCC) of IO through the circuit of FIG. 4 _IO ) And the circuit is switched to a corresponding high-voltage or low-voltage mode, so that the requirements of a power voltage range and high-speed transmission of wide IO are met.

In the embodiment of the present disclosure, when the low voltage selection signal is active high, the third switch 121, the fourth switch 122, the fifth switch 124, the sixth switch 125, the ninth switch 129, and the tenth switch 1210 are turned on; the seventh switch 127 and the eighth switch 128 are turned off, and the output driving pipe of each driving branch is controlled by the second branch 1-2-2 of the pre-driving circuit connected with the output driving pipe; in the embodiment of the disclosure, when the low voltage selection signal is valid, since the power supply voltage of the IO is low at this time, the third MOS transistor 1211 and the fourth MOS transistor 1212 have no overvoltage problem, and the first output driving transistor 1-3 and the second output driving transistor 2-3 of the first driving branch are controlled by the corresponding pre-driving circuit second branch 1-2-2 respectively; meanwhile, when the low-voltage selection signal is high-level and effective, the first switch 112 is controlled to be switched on to the ground according to the low-voltage selection signal, the second switch 113 is switched off, so that the first MOS tube 114 is disconnected from the power supply, and the second MOS tube 115 is in a high-resistance state; the first branch 1-2-1 of the pre-driving circuit is in a low-voltage mode, the first branch 1-2-1 of the pre-driving circuit of the first driving branch loses control over the first output driving tube 1-3, and the first branch 1-2-1 of the pre-driving circuit of the second driving branch loses control over the second output driving tube 2-3;

when the low voltage selection signal is inactive at a low level, the third switch 121, the fourth switch 122, the fifth switch 124, the sixth switch 125, the ninth switch 129, and the tenth switch 1210 are turned off; the seventh switch 127 and the eighth switch 128 are turned on; because the ninth switch 129 and the tenth switch 1210 are in the off state, the first branch 1-2-1 of the pre-driving circuit of the first driving branch loses control over the first output driving pipe 1-3, the first branch 1-2-1 of the pre-driving circuit of the second driving branch loses control over the second output driving pipe 2-3, the seventh switch 127 and the eighth switch 128 are conducted, the outputs of the second logic circuit 123 and the third logic circuit 126 and the gates of the third MOS pipe 1211 and the fourth MOS pipe 1212 are connected to the middle level, the voltages at any two ends of the drain, source and gate of the second logic circuit 123, the third logic circuit 126, the third MOS pipe 1211 and the second MOS pipe 1212 are not higher than the withstand voltage value of the MOS pipe, and the risk of overvoltage of the low-voltage pre-driving circuit of the second branch 1-2-2 does not occur; meanwhile, when the low level of the low voltage selection signal is invalid, the first branch 1-2-1 of the pre-driving circuit is in a high voltage mode, the low voltage selection signal controls the first switch 112 to be connected to the output of the first logic circuit 111, and the second switch 113 is turned on; the first branch 1-2-1 of the pre-drive circuit is in a low voltage mode, and the first output drive pipe 1-3 of the first drive branch and the second output drive pipe 2-3 of the second drive branch are controlled by the second branch 1-2-1 of the pre-drive circuit which is high voltage resistant.

The embodiment of the disclosure also provides an input/output port circuit, which comprises the driving circuit.

Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

Claims (9)

1. A driving circuit, comprising: two driving branches with the same structure; each driving branch circuit comprises a corresponding level shifter (1-1) and a pre-driving circuit (1-2); the level shifter (1-1) of the first driving branch is connected with the pre-driving circuit (1-2); the level shifter (1-1) of the second driving branch is connected with the pre-driving circuit (1-2); wherein,,

the level shifter (1-1) is configured to: converting the internal low-voltage signal into a power supply voltage of input/output IO required by external driving;

the pre-drive circuit (1-2) comprises a first pre-drive circuit branch (1-2-1) formed by high voltage devices and a second pre-drive circuit branch (1-2-2) formed by low voltage devices, and is configured to: selecting a first branch (1-2-1) of the pre-driving circuit or a second branch (1-2-2) of the pre-driving circuit to drive an output driving tube to output a driving signal according to the power supply voltage of IO obtained through conversion of the level shifter (1-1);

the high-voltage device comprises a device with bearable voltage larger than or equal to a preset first voltage threshold value; the low-voltage device comprises a device with bearable voltage less than or equal to a preset second voltage threshold; the output drive tube includes: a first output drive tube (1-3) connected to the pre-drive circuit (1-2) of the first drive branch, and a second output drive tube (2-3) connected to the pre-drive circuit (1-2) of the second drive branch.

2. The drive circuit according to claim 1, wherein the pre-drive circuit (1-2) is arranged to:

when the power supply voltage of the IO is smaller than or equal to a preset protection voltage, the first branch (1-2-1) of the pre-drive circuit is communicated through a preset first control signal;

when the power supply voltage of the IO is larger than the protection voltage, the second branch (1-2-2) of the pre-drive circuit is communicated through a preset second control signal.

3. The drive circuit according to claim 2, wherein the first and second control signals are generated by a pre-set comparator (401).

4. A driving circuit according to claim 3, wherein the first control signal comprises a low voltage select signal of a first level; the second control signal includes the low voltage selection signal at a second level.

5. A driving circuit according to any one of claims 2 to 4, wherein the pre-driving circuit first branch (1-2-1) comprises: the MOS device comprises a first logic circuit (111), a first switch (112), a second switch (113), a first metal-oxide semiconductor field effect transistor (MOS) tube (114) with a pull-up function and a second MOS tube (115) with a pull-down function, wherein a first end of the first switch (112) is connected with an output end of the first logic circuit (111) or grounded, grid electrodes of the first MOS tube (114) and the second MOS tube (115) are connected with a second end of the first switch (112) after being connected, a first end of the second switch (113) is connected with a power supply voltage of IO, a second end of the second switch (113) is connected with a source stage of the first MOS tube, a drain electrode of the first MOS tube (114) is connected with a drain electrode of the second MOS tube (115) and then connected with an output driving tube, and a source stage of the second MOS tube (115) is grounded; the first branch (1-2-1) of the pre-drive circuit is arranged to:

the second switch (113) is turned on according to the first control signal, and the output driving pipe is driven by controlling the first switch (112) to turn on the output of the first logic circuit (11).

6. The driving circuit according to claim 5, wherein the first MOS transistor (114) and the second MOS transistor (115) are MOS transistors having a withstand voltage value greater than a preset third voltage threshold value.

7. A driving circuit according to any one of claims 2 to 4, wherein the pre-driving circuit second branch (1-2-2) comprises: the device comprises a second logic circuit (123), a third logic circuit (126), a third switch (121), a fourth switch (122), a fifth switch (124), a sixth switch (125), a seventh switch (127), an eighth switch (128), a ninth switch (129), a tenth switch (1210), a third MOS tube (1211) with a pull-up function and a fourth MOS tube (1212) with a pull-down function, wherein a first end of the third switch (121) is connected with the power supply voltage of the IO, and a second end of the third switch (121) is connected with the second logic circuit (123); a first end of the fourth switch (122) is grounded, and a second end of the fourth switch (122) is connected with a second logic circuit (123); the input ends of the second logic circuit (123) and the third logic circuit (126) are used for receiving the second control signal; a first end of the fifth switch (124) is connected with the power supply voltage of the IO, and a second end of the fifth switch (124) is connected with the third logic circuit (126); a first end of the sixth switch (125) is grounded, and a second end of the sixth switch (125) is connected with a third logic circuit (126); a first end of the seventh switch (127) receives a preset protection voltage, and a second end of the seventh switch (127) is connected with the output of the second logic circuit (123); a first end of the eighth switch (128) receives a preset protection voltage, and the output of the eighth switch (128) connected with the third logic circuit (126); the first end of the ninth switch (129) is connected with a power supply voltage of IO, the second end of the ninth switch (129) is connected with a source electrode of the third MOS tube (1211), a grid electrode of the third MOS tube (1211) is connected with the output of the second logic circuit (123), and a drain electrode of the third MOS tube (1211) is connected with a drain electrode of the fourth MOS tube and then is connected with the output driving tube; the first end of the tenth switch (1210) is grounded, and the second end of the tenth switch (1210) is connected with the source electrode of the fourth MOS tube (1212); the second branch (1-2-2) of the pre-drive circuit is arranged to:

-upon receipt of the second control signal, switching on the second logic circuit (123) and the third logic circuit (126) to drive the output drive tube;

wherein the protection voltage is less than or equal to the withstand voltage value of the low-voltage device.

8. The driving circuit according to claim 7, wherein the third MOS transistor (1211) and the fourth MOS transistor (1212) are MOS transistors having a withstand voltage value lower than a fourth voltage threshold value set in advance.

9. An input-output port circuit comprising a drive circuit as claimed in any one of claims 1 to 8.