CN116895313A - Memory system for controlling heterogeneous clock signal delay mode, method of operating the same, and memory controller - Google Patents

Abstract

A memory system that controls delays of a plurality of clock signals and outputs at least one of read data and write data, the memory system comprising: a memory controller configured to receive a data output command from a host, generate a plurality of clock signals for outputting data, and control delays of the plurality of clock signals; and an output unit configured to output data based on the clock signal having the controlled delay.

Description

Memory system for controlling heterogeneous clock signal delay mode, method of operating the same, and memory controller

Cross Reference to Related Applications

The present application is based on and claims priority of korean patent application No.10-2022-0041913, filed on 4 th year 2022, and korean patent application No.10-2022-0087080, filed on 14 th year 2022, filed on 7 th year, the disclosures of which are incorporated herein by reference in their entireties.

Technical Field

Embodiments of the inventive concept relate to a memory system for controlling a heterogeneous (heterogeneous) clock signal delay mode, a method of operating the same, and a memory controller, and more particularly, to a memory system using a toggle signal (toggle signal) of a data clock signal as a delay control signal of a clock signal for outputting read data.

Background

Dynamic Random Access Memory (DRAM) may be designed to receive commands and addresses in synchronization with a master clock signal and to receive or transmit data in synchronization with a data clock signal. The main operation of the DRAM includes writing data to a memory cell array belonging to a core circuit unit or reading data from a memory cell array belonging to a core circuit unit. The control signal generated to control the core circuit unit based on the master clock signal, and the data input/output to the core circuit unit based on the data clock signal are set in different clock domain areas.

Disclosure of Invention

Embodiments of the inventive concept provide a method of controlling a delay of a clock signal using a flip signal of a data clock signal in a first period.

According to an embodiment of the inventive concept, a memory system that controls delays of a plurality of clock signals and outputs at least one of read data and write data, the memory system includes: a memory controller configured to receive a data output command from a host, generate a plurality of clock signals for outputting data, and control delays of the plurality of clock signals; and an output unit configured to output data based on the clock signal having the controlled delay. The memory controller includes: a first clock signal generator configured to receive a data output command from a host and generate a flip signal for transmitting a data clock signal; a second clock signal generator configured to generate a master clock signal including command/address information when generating the flip signal; a delay controller configured to utilize the flip signal as a delay control signal when a data output command is input to the first clock signal generator; and a selection circuit configured to select one of the delay control signal and the delay signal of the master clock signal generated by the second clock signal generator.

According to an embodiment of the inventive concept, a method of operating a storage system includes: a data output command is received from a host through a first clock signal generator and a flip signal for transmitting a data clock signal is generated. The method further comprises the steps of: when generating the flip signal, a master clock signal including command/address information is generated by a second clock signal generator. The method further comprises the steps of: when a data output command is input to the first clock signal generator, the flip signal is utilized as a delay control signal by the delay controller. The method further comprises the steps of: one of the delay control signal and the delay signal of the master clock signal generated by the second clock signal generator is selected by the selection circuit, and the delay of the clock signal is controlled based on the signal selection of the selection circuit, and data corresponding to the data command is output.

According to an embodiment of the inventive concept, a memory controller that receives a plurality of command signals from a host and controls an operation of a memory device, the memory controller includes: a first clock signal generator configured to receive a data output command from a host and generate a flip signal for transmitting a data clock signal; a second clock signal generator configured to generate a master clock signal including command/address information when generating the flip signal; a delay controller configured to utilize the flip signal as a delay control signal when a data output command is input to the first clock signal generator; a selection circuit configured to select one of the delay control signal and the delay signal of the master clock signal generated by the second clock signal generator; and an output unit configured to output data based on signal selection of the selection circuit.

Drawings

The above and other features of the inventive concept will become more apparent by describing in detail embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a block diagram illustrating a storage system according to an embodiment;

FIGS. 2A and 2B are block diagrams illustrating a storage system according to an embodiment;

FIGS. 3A and 3B are block diagrams illustrating a memory controller according to embodiments;

FIG. 4 is a timing diagram illustrating signals generated by a memory controller according to an embodiment;

fig. 5 is a timing diagram illustrating control delay signals in a first cycle of generating a flip signal in a memory controller according to an embodiment;

fig. 6 is a timing diagram illustrating control of the delay signal after a second period of the toggle signal is generated in the memory controller according to an embodiment;

FIG. 7 is a flow chart of a method of operating a storage system according to an embodiment;

FIG. 8 is a flow chart illustrating a storage system controlling a latency signal based upon a signal pattern generated by a host according to an embodiment;

FIG. 9 is a flow chart illustrating a memory system controlling a delay signal based on a roll-over signal according to an embodiment;

FIG. 10 is a flow chart illustrating control of a delay signal after a second toggle signal cycle in a memory system in accordance with an embodiment;

Fig. 11 and 12 are block diagrams showing an implementation example of a semiconductor memory device according to an embodiment; and

fig. 13 is a block diagram showing an example in which a storage device performing a clock synchronization operation is applied to a mobile device according to an embodiment.

Detailed Description

Embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may denote like elements throughout the drawings.

FIG. 1 is a block diagram illustrating a storage system 200 according to an embodiment.

Referring to fig. 1, a storage system 200 according to an embodiment includes a storage controller 210 and a storage device 220. The memory system 200 receives a DATA output command DATA out_cmd from the host 100, and the memory controller 210 transmits a plurality of command signals and clock signals to the memory device 220.

For example, the memory system 200 may support data communication between the memory controller 210 and the memory device 220 by using the master clock signal CK and the data clock signal WCK. The first clock signal line 21, the command bus 22, the address bus 23, the second clock signal line 24, and the data bus 25 are connected between the memory controller 210 and the memory device 220. In addition to the master clock signal CK and the data clock signal WCK, the memory system 200 may also support data communication by using various clock signals. The first clock signal line 21 may be referred to as a data clock signal line. The second clock signal line 24 may be referred to as a master clock signal line.

The master clock signal CK generated by the memory controller 210 is supplied to the memory device 220 through the second clock signal line 24. For example, the master clock signal CK may be supplied as a continuously alternating inverted signal together with the inverted master clock signal CKB. Since the rising/falling edges of the master clock signal pair CK and CKB can be detected based on the intersection therebetween, timing accuracy can be increased.

According to an embodiment, a single master clock signal CK may be supplied to the second clock signal line 24 as a continuously alternating inverted signal. In this case, in order to identify the rising/falling edge of the master clock signal CK, the master clock signal CK may be compared with the reference voltage Vref. However, when noise fluctuation or the like occurs in the reference voltage Vref, detection of the master clock signal CK may be shifted, and thus, timing accuracy may be deteriorated as compared with the case of using the master clock signal pairs CK and CKB.

Accordingly, the second clock signal line 24 can transmit the inverted signals that are complementary to each other, continuously alternating, by using the master clock signal pair CK and CKB. In this case, the second clock signal line 24 may include two signal lines for transmitting the master clock signal pair CK and CKB. The master clock signal CK may be described as corresponding to the master clock signal pair CK and CKB in embodiments of the inventive concept. For ease of illustration, the pair of master clock signals CK and CKB will be collectively referred to as master clock signal CK.

The command CMD and the address signal ADDR supplied from the memory controller 210 are supplied to the memory device 220 through the command bus 22 and the address bus 23, respectively. According to an embodiment, command CMD and address signals ADDR may be provided to the memory device 220 through a shared command/address bus. The command CMD or the address signal ADDR may be loaded onto the shared command/address bus in time series.

The data clock signal WCK and the data DQ may be sent for a data interface between the memory controller 210 and the memory device 220. The data clock signal WCK generated by the memory controller 210 is supplied to the memory device 220 through the first clock signal line 21. The data clock signal WCK may be provided as a continuously alternating inverted signal together with the inverted data clock signal WCKB. Since the rising/falling edges of the pair of data clock signals WCK and WCKB can be detected based on the intersection therebetween, timing accuracy can be increased.

The first clock signal line 21 may transmit the inverted signals complementary to each other, continuously alternating, by using the pair of data clock signals WCK and WCKB. In this case, the first clock signal line 21 may include two signal lines for transmitting the data clock signals WCK and WCKB, respectively. In embodiments of the inventive concept, it may be described that the data clock signal WCK corresponds to the pair of data clock signals WCK and WCKB. For ease of illustration, the pair of data clock signals WCK and WCKB are collectively referred to as a data clock signal WCK.

The data DQ synchronized with the data clock signal WCK is transferred between the memory controller 210 and the memory device 220 through the data bus 25. For example, the data DQ corresponding to the burst length BL supplied from the memory controller 210 is synchronized with the data clock signal WCK, and can be transmitted to the memory device 220 through the data bus 25. The data DQ read from the memory device 220 corresponding to the burst length BL may be latched in synchronization with the data clock signal WCK and then transmitted to the memory controller 210 through the data bus 25.

The data interface speed between the storage controller 210 and the storage device 220 is increasing. For example, due to the development of high-speed graphics or games, an increase in the operating speed of the memory controller 210, etc., the data interface speed of the memory device 220 is also increasing.

When the memory device 220 is implemented by a DRAM, it may be difficult to operate core circuit units in the DRAM according to the speed of the high data interface speed. In other words, it is limited to increase the frequency of the master clock signal CK applied to the core circuit unit of the DRAM. Accordingly, the DRAM may employ a technology of increasing the data interface speed while maintaining the operation speed of the core circuit unit.

Hereinafter, for convenience of explanation, the data clock signal WCK may be referred to as a first clock signal, and the master clock signal CK may be referred to as a second clock signal.

Fig. 2A and 2B are block diagrams illustrating a storage system 200 according to an embodiment.

Referring to fig. 2A, a memory controller 210 of the memory system 200 according to an embodiment includes a first clock signal generator 211, a second clock signal generator 212, a delay controller 213a, and a selection circuit 214. Referring to fig. 2B, the delay controller 213a of fig. 2A may be replaced by a pattern checker (pattern checker) 213B according to an embodiment.

Referring to fig. 2A and 2B, the first clock signal generator 211 receives the DATA output command DATA out_cmd from the host 100 and generates a flip signal for transmitting the DATA clock signal WCK. The data clock signal WCK refers to a clock signal including data information to be transmitted by the host 100. The data clock signal WCK may include a signal delay mode. When the DATA output command DATA out_cmd is changed, the DATA clock signal WCK may also be changed.

The second clock signal generator 212 generates a master clock signal CK for transmitting command/address information. The master clock signal CK may include a delay signal. The second clock signal generator 212 may transmit the master clock signal CK to the selection circuit 214 so that the memory controller 210 controls the delay of the clock signal transmitted to the memory device 220.

When the memory system 200 receives the DATA output command DATA out_cmd from the host 100, the delay controller 213a may use the flip signal generated by the first clock signal generator 211 as a delay control signal. For example, when the host 100 inputs the DATA output command DATA out_cmd to the memory system 200, the delay controller 213a may input the flip signal generated by the first clock signal generator 211, and may utilize the first period of the flip signal as the delay control signal. The host 100 may notify the start of the DATA output command DATA out_cmd to the memory controller 210 by changing a transmission mode of the DATA clock signal or changing the DATA clock signal. For example, when the memory system 200 receives the DATA output command DATA out_cmd from the host 100, the delay controller 213a may use the flip signal as a delay control signal and control the memory system 200 to output DATA at the end of a clock period of a preset period.

Referring to fig. 2B, the delay controller 213a shown in fig. 2A may be replaced by a pattern checker 213B according to an embodiment. When the delay controller 213a is replaced with the pattern checker 213b, the pattern checker 213b may detect a pattern included in the DATA output command DATA out_cmd received from the host 100 and use the first period of the flip signal generated by the first clock signal generator 211 as a delay control signal. The delay signal pattern included in the DATA output command DATA out_cmd may be a preset pattern stored in the memory controller 210. For example, when the memory system 200 receives the DATA output command DATA out_cmd from the host 100, the pattern checker 213b may use the flip signal as a delay control signal and control the memory system 200 to output DATA at the end of a clock period of a preset period.

Still referring to fig. 2A and 2B, the memory controller 210 according to an embodiment includes a selection circuit 214. The selection circuit 214 may select the flip signal generated by the first clock signal generator 211 as the delay control signal only when the first read operation is performed after the flip signal is generated by the first clock signal generator 211. Further, the selection circuit 214 selects, as the delay control signal, a delay in the master clock signal CK generated by the second clock signal generator 212 from the clock cycles in which the second read operation of the clock signal delay control is performed. In other words, the flip signal of the first clock signal generator 211 as described above may be used as a delay control signal at the first input time of the flip signal, and in a later period, when the data clock signal WCK and the master clock signal CK are synchronized with each other, a delay in the master clock signal CK generated by the second clock signal generator 212 is selected as the delay control signal. When the memory system 200 receives the DATA output command DATA out_cmd from the host 100, the selection circuit 214 may control the memory device 220 to output DATA at the end of a clock period of a preset period using a delay in the master clock signal CK generated by the second clock signal generator 212 as a delay control signal.

The memory device 220 may include an output unit 221 that outputs data based on a clock signal input from the memory controller 210.

Hereinafter, the memory controller 210 according to an embodiment will be described in more detail.

Fig. 3A and 3B are block diagrams illustrating a memory controller 210 according to an embodiment.

Referring to fig. 3A and 3B, as described above with reference to fig. 2A and 2B, the memory controller 210 includes a first clock signal generator 211, a second clock signal generator 212, a delay controller 213A or a pattern checker 213B, and a selection circuit 214. The memory controller 210 may further include a divider 215 dividing the data clock signal WCK, a domain crossing circuit 216 synchronizing the master clock signal CK with the data clock signal WCK, a data controller 217 sampling the data clock signal WCK, a data clock serializer 218, and a multiplexing circuit 219.

The first clock signal generator 211 includes a data receiver 211a and a data clock signal buffer 211b.

The data receiver 211a receives a data output command signal through the data channel DQ [5 ]. Fig. 3A and 3B show an embodiment in which the number of data lanes DQ [5] is five. However, the embodiment is not limited thereto. The data receiver 211a may receive a signal for starting detection of delay in a clock signal for outputting data.

The data clock signal buffer 211b receives the data clock signal WCK and transmits an inversion signal of the data clock signal WCK to the frequency divider 215. Hereinafter, an embodiment in which the frequency of the data clock signal WCK is about 4.8GHz will be described. When the frequency of the input data clock signal WCK is about 4.8GHz, the data clock signal buffer 211b transmits the flip signal of the data clock signal WCK to the frequency divider 215.

The second clock signal generator 212 may include a master clock signal buffer 212a, a command/address signal buffer 212b, a command decoder 212c, a delay signal counter 212d, and a delay signal buffer 212e.

The master clock signal buffer 212a receives the master clock signal CK and transmits the master clock signal CK to the command/address signal buffer 212b. According to an embodiment, the frequency of the master clock signal CK may be about half the frequency of the data clock signal WCK. For example, when the frequency of the data clock signal WCK is about 4.8GHz, the frequency of the master clock signal CK may be about 2.4GHz.

The command/address signal buffer 212b may receive the command/address information CA and the master clock signal CK, and may transmit the master clock signal CK including the command/address information CA to the command decoder 212c. The command decoder 212c may receive the master clock signal CK and generate an internal command signal ICMD including a Read signal or a Write signal according to a received Read command read_cmd or a received Write command write_cmd. The internal command signal ICMD may be provided to the delay signal counter 212d.

The delay signal counter 212d may generate the delay signal LATENCY SIG in response to the received clock synchronization command cmd_sync and the master clock signal CK provided from the master clock signal buffer 212 a.

The delay signal buffer 212e receives the delay signal LATENCY SIG included in the master clock signal CK from the delay signal counter 212d and transmits the delay signal LATENCY SIG to the domain crossing circuit 216.

The delay controller 213a or the pattern checker 213B detects a flip signal included in the data clock signal WCK as described above with reference to fig. 2A and 2B, and uses a first read cycle of the flip signal as the delay control signal LATENCY CTRL SIG.

The selection circuit 214 receives the delay control signal LATENCY CTRL SIG from the delay controller 213a or the pattern checker 213b, and receives the delay signal of the master clock signal CK from the domain crossing circuit 216. The selection circuit 214 selects any one of the delay control signal LATENCY CTRL SIG and the delay signal of the master clock signal CK, and controls the delay in the clock signal for outputting the read data by using the selected signal. In the first data read period in which the data clock signal WCK starts the inversion operation, the selection circuit 214 may use the inversion signal of the data clock signal WCK as a delay control signal. In this case, the frequency of the delay control signal is the same as the frequency of the data clock signal WCK. After performing the flip operation of the data clock signal WCK, from the second reading period, the selection circuit 214 selects the delay signal LATENCY SIG of the master clock signal CK input from the domain crossing circuit 216 as a signal for controlling the delay in reading data.

Since the frequency of the data clock signal WCK and the frequency of the master clock signal CK are different from each other, the frequency of the data clock signal WCK needs to be adjusted by the frequency divider 215. A plurality of frequency dividers 215 may be provided. For example, when there are two frequency dividers 215, the frequency of the data clock signal WCK may first be frequency attenuated from about 4.8GHz to about 2.4GHz by the frequency divider 215 and then again frequency attenuated from about 2.4GHz to about 1200MHz by the frequency divider 215. When the frequency-attenuated data clock signal WCK and the delayed signal LATENCY SIG of the master clock signal CK are input to the domain crossing circuit 216, the domain crossing circuit 216 may input the delayed signal LATENCY SIG of the master clock signal CK to the selection circuit 214, thereby transmitting the delayed signal LATENCY SIG of the master clock signal CK to the domain of the data clock signal WCK.

The data clock signal WCK may be divided by four. For example, the flip signal of the data clock signal WCK may be input to the data controller 217 as a delay control signal, and the first frequency division of the data clock signal WCK may be input to the data controller 217.

A plurality of data clock serializers 218 may be provided. For example, when two data clock serializers 218 are provided, the second division and the third division of the data clock signal WCK may be input to each of the data clock serializers 218. Further, the fourth division of the data clock signal WCK may be input to the multiplexing circuit 219.

In other words, when the flip signal of the data clock signal WCK is used as the delay control signal, since the delay control signal is included in the flip signal, the number of the data clock signals WCK for outputting the read data may be 16. When the number of the data clock signals WCK for outputting the read data is 16, a period corresponding to the WCK is consumed for the inversion of the data clock signals WCK.

Fig. 4 is a timing diagram illustrating signals generated by the memory controller 210 according to an embodiment.

Referring to fig. 4, the slave memory controller 210 transmits a master clock signal CK, and transmits a command CMD and an address signal ADDR based on the master clock signal CK. The data DQ is transmitted based on the data clock signal WCK. For a high-speed data interface, the frequency of the data clock signal WCK may be set to about twice the frequency of the master clock signal CK.

When a data Write operation is performed in the memory device 220, the memory device 220 receives the master clock signal CK from a time point T1 among the time points T1 to T5, and may receive the Write command write_cmd and the Write address signal ADDR at a time point T2 based on the master clock signal CK. Then, at a time point T2, the memory device 220 may receive the Write data write_dq based on the data clock signal WCK.

According to an embodiment, it is described that the memory device 220 receives the Write command write_cmd and the Write data write_dq at the time point T2. It should be appreciated that this is an example provided for convenience in explaining the clock synchronization operation between the master clock signal CK and the data clock signal WCK, and the embodiment is not limited thereto. After receiving the Write command CMD, the memory device 220 may receive the Write data write_dq after a Write delay expressed as a multiple of the period of the master clock signal CK.

According to an embodiment, it is assumed that a data read operation is performed in the storage device 220. The memory device 220 may receive the master clock signal CK from the time point T1, and may receive the Read command read_cmd and the Read address signal read_addr based on the master clock signal CK at the time point T2. After receiving the Read command read_cmd, the Read data read_dq may be transmitted based on the data clock signal WCK after a Read delay expressed as a multiple of the period of the master clock signal CK.

During a write operation, the memory device 220 samples data DQ input from the memory controller 210 by using the data clock signal WCK, and may store the sampled data into the memory cell array by using the master clock signal CK. During a read operation, the memory device 220 reads data from the memory cell array by using the master clock signal CK, and transmits the read data to the memory controller 210 by using the data clock signal WCK. As described above, the memory device 220 may operate in different clock domains (i.e., multiple clock domains).

In the memory device 220, data will move between an area operating based on the master clock signal CK and an area operating based on the data clock signal WCK. In this case, a domain crossing occurs between the master clock signal CK and the data clock signal WCK, wherein missing data may occur. To prevent such occurrence of lost data, a clock synchronization operation may be performed between the master clock signal CK and the data clock signal WCK according to an embodiment. Hereinafter, a timing chart of a process of controlling delay in a clock signal for outputting read data by using a flip signal of the data clock signal WCK and a delay signal of the master clock signal CK will be described.

Fig. 5 is a timing diagram illustrating control delay signals in a first period of generating a flip signal in the memory controller 210 according to an embodiment.

Referring to fig. 5, when a point of time at which read data is first read is defined as a first inversion signal period and a second inversion signal period is defined as a period after the first inversion signal period, in the first inversion signal period, the memory controller 210 detects a delay in the data clock signal WCK (delay in the WCK domain) and divides the data clock signal WCK by four. The first period of the flip signal may be a period corresponding to a half period of the divided data clock signal WCKn when the data clock signal WCK is divided by n. For convenience of description, the four divided data clock signals WCK4 will be referred to as first to fourth data clock signals. The memory controller 210 may use a flip signal period corresponding to a period of the first data clock signal among the flip signals wck_t and wck_c as the delay control signal. When the memory system 200 according to the embodiment receives data through the eight data lanes DQ [7], the first period of the flip signal input to the data lanes DQ may be utilized as a synchronization signal Sync Key for controlling the delay of the data clock signal WCK.

Fig. 6 is a timing diagram illustrating control of the delay signal after the second period of the flip signal is generated in the memory controller 210 according to an embodiment.

Referring to fig. 6, the memory controller 210 may detect a Delay of the master clock signal CK after the first inversion signal period and define the Delay of the master clock signal CK as Delay (α). The memory controller 210 may sample the four divided data clock signals WCK4 and extract the delay signal. For example, the first data clock signal may be sampled up to "2/3×delay (α)" with respect to the master clock signal CK to control the Delay of the master clock signal CK, and may be sampled up to "1/3×delay (α)" by the domain crossing circuit to control the Delay of the master clock signal CK. In this case, 16 flip signals may be used up to a point of time t_fastened at which control of the master clock signal CK is completed, and a delay of 16tCK may occur.

FIG. 7 is a flowchart of a method of operating the storage system 10, according to an embodiment.

Referring to fig. 7, the host 100 transmits a request data_out REQ for outputting read DATA to the storage system 200 (operation S110).

When the request data_out REQ for outputting the read DATA is input to the memory system 200, the first clock signal generator 211 generates a flip signal for outputting the DATA (operation S120). The first clock signal generator 211 is a device that generates the DATA clock signal WCK, and a request data_out REQ for outputting read DATA may be input to the memory controller 210 of the memory system 200.

The second clock signal generator 212 generates a master clock signal CK (operation S130). The master clock signal CK is a clock signal for transmitting command/address information CA, and the second clock signal generator 212 is a device that generates the master clock signal CK.

When generating the flip signal of the data clock signal WCK and the master clock signal CK, the delay controller 213a generates a delay control signal at a point of time when the flip signal is generated (operation S140). As described above, according to an embodiment, the delay controller 213a may be replaced with the pattern checker 213 b. At the point in time when the flip signal is generated, the read data may be in the first flip signal period. In the first inversion signal period, the delay controller 213a may use the inversion signal itself of the data clock signal WCK as a delay control signal. The second clock signal generator 212 may generate a delay with respect to the master clock signal CK.

When the delay control signal LATENCY CTRL SIG is generated by the delay controller 213a, the selection circuit 214 selects any one of the delay signal generated by the second clock signal generator 212 and the delay signal generated by the first clock signal generator 211 (operation S150). As described above, the delay controller 213a may use the flip signal of the data clock signal WCK as the delay control signal LATENCY CTRL SIG in the first period in which the read data is read, and may use the delay signal of the master clock signal CK as the control signal of the clock signal for reading the read data after the second period in which the read data is read. When the delayed signal of the master clock signal CK is utilized as a control signal for a clock signal for reading read data, the delayed signal of the master clock signal CK can be transmitted to the selection circuit 214 through the domain crossing circuit 216.

When any one of the delay control signal of the data clock signal WCK and the delay signal of the master clock signal CK is selected, the delay of the clock signal for outputting the read data is controlled and the data is outputted (operation S160).

Fig. 8 is a flowchart illustrating the control of the latency signal by the storage system 200 based on the signal pattern generated by the host 100 according to an embodiment.

Referring to fig. 8, when the delay controller 213a of fig. 2A is replaced with the mode checker 213B of fig. 2B, a DATA output command DATA out_cmd is input to the memory controller 210 (operation S210).

When the DATA output command data_out CMD is input to the memory controller 210, the mode checker 213b detects a mode of the delay signal included in the DATA output command data_out CMD (operation S220). The mode of the delay signal may be preset and stored in the memory controller 210. For example, the mode of the delay signal may include, but is not limited to, starting a flip of the data clock signal, or changing a transmission mode of the data clock signal.

When the mode of the delay signal included in the DATA output command data_out CMD is detected, the memory controller 210 controls the delay of the clock signal for outputting the read DATA (operation S230). The delay of the clock signal for outputting the read data can be controlled by using the flip signal of the data clock signal WCK as a delay control signal.

Fig. 9 is a flowchart illustrating the control of the delay signal by the memory system 200 based on the flip signal according to an embodiment.

Referring to fig. 9, a flip signal is generated as the data clock signal WCK is generated (operation S310).

When the inversion signal is generated, the delay controller 213a or the pattern checker 213b of the storage controller 210 may detect the start of the inversion signal (operation S320). When determining that the flip signal starts, the delay controller 213a or the pattern checker 213b may use the first flip signal period as a delay control signal to control the delay of the clock signal for outputting the read data. The first inversion signal period may be a period corresponding to a half period of the divided data clock signal WCKn when the data clock signal WCK is divided by n.

When the start of the flip signal is detected, the memory controller 210 may use the above-described start flip signal as a delay control signal and control the delay of the clock signal for outputting the read data (operation S330).

Fig. 10 is a flowchart illustrating the delayed signals after the second toggle signal cycle is controlled in the memory system 10, in accordance with an embodiment.

Referring to fig. 10, the flip signal of the data clock signal WCK enters a second flip signal period after the first flip signal period (operation S410). Here, the second inversion signal period may include a period after a period corresponding to a half period of the divided data clock signal WCKn when the data clock signal WCK is divided by n (where n is a positive integer).

When the flip signal of the data clock signal WCK enters the second flip signal period, the domain crossing circuit 216 transmits the master clock signal CK to the selection circuit 214 (operation S420). The master clock signal CK may also include a delayed signal of the master clock signal CK. As described above, the Delay signal of the master clock signal CK may be defined as Delay (α). Further, the domain crossing circuit 216 may receive the n-divided data clock signal WCKn, sample the n-divided data clock signal WCKn, and transmit the sampled n-divided data clock signal WCKn to the selection circuit 214. Sampling for the divide-by-n data clock signal WCKn may include dividing Delay (α) by an appropriate ratio.

When the master clock signal CK and the data clock signal WCK are transmitted to the selection circuit 214, in the second inversion signal period, the selection circuit 214 selects the delay signal of the master clock signal CK and controls the clock signal for outputting the read data. For example, delay (α) may be controlled as a result of sampling, and the data clock signal WCK and the master clock signal CK may be synchronized with each other.

Fig. 11 and 12 are block diagrams showing an implementation example of a semiconductor memory device according to an embodiment.

Referring to fig. 11, a system 1000 may include a camera 1100, a display 1200, an audio processor 1300, a modem 1400, DRAMs 1500a and 1500b, flash memories 1600a and 1600b, I/O devices 1700a and 1700b, and an application processor (hereinafter referred to as "AP") 1800. The system 1000 may be implemented as, for example, a laptop computer, mobile phone, smart phone, tablet Personal Computer (PC), wearable device, healthcare device, internet of things (IOT) device, server, PC, or the like.

The camera 1100 may capture a still image or video according to a user's control, and may store the captured image/video data or transmit the captured image/video data to the display 1200. The audio processor 1300 may process audio data included in the flash memories 1600a and 1600b or the network content. The modem 1400 may transmit a modulated signal for wired/wireless data transmission/reception to a receiver, and the modulated signal may be demodulated by the receiver to restore an original signal. I/O devices 1700a and 1700b may include devices that provide digital input functionality and/or digital output functionality, such as Universal Serial Bus (USB), memory, digital cameras, secure Digital (SD) cards, digital Versatile Disks (DVDs), network adapters, touch screens, and the like.

The AP 1800 may control the overall operation of the system 1000. The AP 1800 may control the display 1200 such that a portion of the content stored in the flash memories 1600a and 1600b is displayed on the display 1200. When a user input is received through the I/O devices 1700a and 1700b, the AP 1800 may perform a control operation corresponding to the user input. The AP 1800 may include an accelerator block as a circuit dedicated to the computation of Artificial Intelligence (AI) data, or may include an accelerator chip 1820 provided separately from the AP 1800. The DRAM 1500b may additionally be provided on the accelerator block or accelerator chip 1820. The accelerator block is a functional block dedicated to performing a specific function of the AP 1800, and may include, for example, a GPU as a functional block dedicated to processing graphics data, a Neural Processing Unit (NPU) as a block dedicated to AI computation and reasoning, and a Data Processing Unit (DPU) as a block dedicated to data transmission. The AP 1800 may also include a controller 1810 and an interface 1830.

The system 1000 may include a plurality of DRAMs 1500a and 1500b. The AP 1800 may establish a DRAM interface protocol and communicate with the DRAMs 1500a and 1500b to control the DRAMs 1500a and 1500b by commands conforming to, for example, the Joint Electronic Device Engineering Council (JEDEC) standard and Mode Register Set (MRS), or to use company specific functions such as low voltage/high speed/reliability and Cyclic Redundancy Check (CRC)/Error Correction Code (ECC) functions. For example, the AP 1800 may communicate with the DRAM 1500a through interfaces compliant with JEDEC standards (e.g., LPDDR4 and LPDDR 5), and the accelerator block or accelerator chip 1820 may set up and use a new DRAM interface protocol to control the DRAM 1500b for the accelerator, the DRAM 1500b having a greater bandwidth than the DRAM 1500 a.

Although fig. 11 shows only DRAMs 1500a and 1500b, embodiments of the inventive concept are not so limited. For example, other types of memory, such as PRAM, SRAM, MRAM, RRAM, FRAM or hybrid RAM, may be used as long as the bandwidth, response speed, and voltage conditions of the AP 1800 or accelerator chip 1820 are met. DRAMs 1500a and 1500b have relatively less latency and bandwidth than I/O devices 1700a and 1700b, or flash memories 1600a and 1600 b. When the system 1000 is powered on and OS and application data are loaded to the DRAMs 1500a and 1500b, the DRAMs 1500a and 1500b are initialized, and thus, the DRAMs 1500a and 1500b may be used as temporary memories for the OS and application data, or may be used as execution spaces for various software codes.

In the DRAMs 1500a and 1500b, four arithmetic operations (e.g., addition, subtraction, multiplication, and division), vector calculation, address calculation, or Fast Fourier Transform (FFT) calculation may be performed. In the DRAMs 1500a and 1500b, functions for operation of reasoning can be performed. Inference can be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm may include training operations for learning models through various data and reasoning operations for identifying the data using the trained models. According to an embodiment, an image captured by a user through the camera 1100 is signal-processed and stored in the DRAM 1500b, and the accelerator block or accelerator chip 1820 may perform AI data computation for identifying data using the data stored in the DRAM 1500b and a function for reasoning.

The system 1000 may include a plurality of memories or flash memories 1600a and 1600b having a larger capacity than the DRAMs 1500a and 1500 b. The accelerator block or accelerator chip 1820 may perform training operations and AI data calculations using the flash memories 1600a and 1600b. According to an embodiment, the flash memories 1600a and 1600b may efficiently perform training and reasoning operations for AI data computation, which are performed by the AP 1800 and/or the accelerator chip 1820 using computing devices provided in the memory controller 1610. Flash memories 1600a and 1600b may store images captured by camera 1100 or data transmitted over a data network. For example, flash memories 1600a and 1600b may store augmented reality/virtual reality content, high Definition (HD) content, or Ultra High Definition (UHD) content. Flash memories 1600a and 1600b may each include a memory controller 1610 and a flash memory 1620.

Fig. 12 is a diagram for describing a multi-chip package including a memory system 200 according to an embodiment. A multi-chip package is a semiconductor package in which a plurality of semiconductor chips or various types of semiconductor chips are stacked to realize a single package.

Referring to fig. 12, a multi-chip package 1150 may include a memory buffer 1102 disposed under stacked memory layers 1110, 1120, 1130, and 1140. Storage layers 1110, 1120, 1130, and 1140 can constitute multiple independent interfaces called channels. The storage layers 1110, 1120, 1130, and 1140 may include two channels 1111 and 1112, 1121 and 1122, 1131 and 1132, and 1141 and 1142, respectively. Each of channels 1111, 1112, 1121, 1122, 1131, 1132, 1141, and 1142 includes an independent memory bank and is independently clocked.

In an embodiment, an example is provided in which the multi-chip package 1150 includes four memory layers 1110, 1120, 1130, and 1140 stacked to form eight channels. However, the embodiment is not limited thereto. For example, two to eight memory layers may be stacked on the multi-chip package 1150 according to embodiments. According to an embodiment, the memory layers 1110, 1120, 1130, and 1140 may each include one channel or four channels. According to an embodiment, a single channel may be distributed among multiple storage layers 1110, 1120, 1130, and 1140.

Memory buffer 1102 may provide signal distribution functionality for receiving commands, addresses, clocks, and data from memory controller 210 (FIG. 1) and providing the received commands, addresses, clocks, and data to memory layers 1110, 1120, 1130, and 1140. Since the memory buffer 1102 buffers all commands, addresses, clocks, and data, the memory controller 210 may interface with the memory layers 1110, 1120, 1130, and 1140 by driving only the load of the memory buffer 1102.

The memory buffer 1102 and the memory layers 1110, 1120, 1130, and 1140 may transmit and receive signals to each other through-silicon vias TSV. The memory buffer 1102 may communicate with an external memory controller through conductive means (e.g., solder balls) formed on the outer surface of the multi-chip package 1150.

Fig. 13 is a block diagram showing an example in which a storage device performing a clock synchronization operation is applied to a mobile device according to an embodiment. The mobile device may be, for example, a mobile phone or a smart phone.

Referring to fig. 13, a mobile device 1380 includes a global system for mobile communications (GSM) block 1310, a Near Field Communication (NFC) transceiver 1320, an input/output block 1330, an application block 1340, a memory 1350, and a display 1360. The components/blocks of mobile device 1380 shown in fig. 13 are merely examples. Mobile device 1380 may include more or fewer components/blocks. Although GSM technology is used in the embodiment according to fig. 13, the embodiment is not limited thereto. For example, mobile device 1380 may be implemented using other technologies such as, for example, code Division Multiple Access (CDMA), according to an embodiment. Some or all of the blocks in fig. 13 may be implemented in the form of integrated circuits.

GSM block 1310 is connected to antenna 1311 and is operable to provide communications operations in a known manner. GSM block 1310 may include a receiver and a transmitter therein to perform corresponding receive and transmit operations.

The NFC transceiver 1320 may be configured to transmit and receive NFC signals by using inductive coupling for wireless communication. NFC transceiver 1320 may provide NFC signals to NFC antenna matching network system 1321 and NFC antenna matching network system 1321 may transmit NFC signals through inductive coupling. NFC antenna matching network system 1321 may receive an NFC signal provided from another NFC device and provide the received NFC signal to NFC transceiver 1320.

NFC signals may be transmitted and received in a time division manner through NFC transceiver 1320. Accordingly, the period of time during which the NFC transceiver 1320 transmits the NFC signal is referred to as a "transmission period", and the operation mode of the NFC transceiver 1320 corresponding to the transmission period will be referred to as a "transmission mode" or an "NFC reader transmission mode". Similarly, the period of time that the NFC transceiver 1320 receives the NFC signal is referred to as a "reception period", and the mode of operation of the NFC transceiver 1320 corresponding to the reception period will be referred to as a "reception mode" or an "NFC tag reception mode".

The NFC transceiver 1320 may operate in accordance with the provisions described in NFC interface and protocol 1 (NFCIP-1) and NFC interface and protocol 2 (NFCIP-2) and standardized in ECMA-340, ISO/IEC 18092, ETSI TS 102 190, ISO 21481, ECMA 352, ETSI TS 102 312, and the like.

Application block 1340 may include hardware circuitry (e.g., one or more processors) and may be operable to provide various user applications provided by mobile device 1380. The user applications may include, for example, applications for voice call operations, data transmission operations, data exchange operations, and the like. The application block 1340 may operate in conjunction with the GSM block 1310 and/or the NFC transceiver 1320 and provide operational features of the GSM block 1310 and/or the NFC transceiver 1320. Alternatively, the application block 1340 may include a program for a mobile point of sale (POS). Such a program may use a mobile phone (e.g., a smart phone) to provide credit card purchase and payment functions.

The display 1360 may display images in response to display signals received from the application blocks 1340. The image may be provided by the application block 1340 or may be generated by a camera embedded in the mobile device 1380. The display 1360 internally includes a frame buffer that may temporarily store pixel values and may be configured, for example, as a liquid crystal display with associated control circuitry.

Input/output block 1330 provides input functionality to the user and provides output to be received through application block 1340.

The memory 1350 stores programs (instructions) and/or data to be used by the application blocks 1340, and may be implemented as, for example, RAM, ROM, flash memory, etc. Thus, according to embodiments, memory 1350 may include not only volatile storage devices, but also non-volatile storage devices. For example, memory 1350 may correspond to storage 120 shown in fig. 6.

The memory 1350 may perform a clock synchronization operation between a first clock signal CK supplied to a core circuit unit connected to the memory cell array and a second clock signal WCK supplied to the data circuit unit. The second clock signal WCK is provided every time data is input or output, and may be configured to have a preamble period of a first clock frequency before a point of time when data is input or output, and to have a second clock frequency different from the first clock frequency after the preamble period.

The memory 1350 may generate the clock synchronization signal by receiving a clock synchronization command during a preamble period of the second clock signal WCK using the command decoder. The memory 1350 may divide the second clock signal WCK by using a frequency divider to generate first to fourth divided clock signals respectively phase shifted from the output of the frequency divider by about 0 degrees, about 90 degrees, about 180 degrees, and about 270 degrees. The memory 1350 may latch the clock synchronization signal using the clock synchronization circuit in response to each of the second to fourth divided clock signals inverted with respect to each other among the first to fourth divided clock signals. Based on the latched result, the memory 1350 may output the first to fourth divided clock signals as the internal data clock signals, or output the divided clock signals respectively inverted by about 180 degrees with respect to the first to fourth divided clock signals as the internal data clock signals.

As is common in the art of the inventive concept, embodiments are described in terms of functional blocks, units and/or modules and are shown in the drawings. Those skilled in the art will appreciate that the blocks, units, and/or modules may be physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wired connections, or the like, wherein the electronic (or optical) circuits may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where the blocks, units, and/or modules are implemented by a microprocessor or the like, they may be programmed using software (e.g., microcode) to perform the various functions recited herein, and may optionally be driven by firmware and/or software. Alternatively, each block, unit, and/or module may be implemented by dedicated hardware or as a combination of dedicated hardware performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) performing other functions.

Referring to the comparative example, when the domain crossing process is performed from the signal delay control process, an unnecessary flip signal may be used to synchronize the master clock signal and the data clock signal. As a result, according to the comparative example, the speed of the memory device may decrease, and the power consumption of the memory device may increase. Embodiments of the inventive concept may prevent or reduce the use of such unnecessary roll-over signals that result in reduced speed and increased power consumption.

While the present inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as defined by the appended claims.

Claims (20)

1. A memory system that controls delays of a plurality of clock signals and outputs at least one of read data and write data, the memory system comprising:

a memory controller configured to receive a data output command from a host, generate the plurality of clock signals for outputting data, and control delays of the plurality of clock signals; and

an output unit configured to output data based on the clock signal with a controlled delay,

wherein the memory controller includes:

a first clock signal generator configured to receive the data output command from the host and generate a flip signal for transmitting a data clock signal;

a second clock signal generator configured to generate a master clock signal including command/address information when generating the flip signal;

a delay controller configured to utilize the flip signal as a delay control signal when the data output command is input to the first clock signal generator; and

A selection circuit configured to select one of the delay control signal and the delay signal of the master clock signal generated by the second clock signal generator.

2. The storage system of claim 1, wherein the storage controller further comprises:

a pattern checker configured to check a preset delay signal pattern included in the data output command, and to use the flip signal as a delay control signal when the preset delay signal pattern is checked.

3. The memory system of claim 1, wherein the selection circuit selects the delay control signal in a first inversion signal period.

4. The memory system according to claim 3, wherein the selection circuit selects the delay signal of the master clock signal generated by the second clock signal generator in a second flip signal period.

5. The storage system of claim 4, wherein the storage controller further comprises:

a domain crossing circuit configured to control the delay signal of the master clock signal and to send a controlled delay signal to the first clock signal generator.

6. The memory system according to claim 5, wherein the domain crossing circuit divides the data clock signal according to a preset standard and controls the delayed signal of the master clock signal by repeating a sampling operation of synchronizing the delayed signal with the divided data clock signal.

7. The storage system of claim 1, wherein the host generates a data output command that includes a change in the data clock signal, and

the memory controller generates the delay control signal based on the change in the data clock signal.

8. A method of operating a storage system, the method comprising:

receiving a data output command from a host through a first clock signal generator and generating a flip signal for transmitting a data clock signal;

generating a master clock signal including command/address information by a second clock signal generator when generating the flip signal;

when the data output command is input to the first clock signal generator, using the flip signal as a delay control signal by a delay controller;

selecting one of the delay control signal and the delay signal of the master clock signal generated by the second clock signal generator by a selection circuit, and controlling delay of the clock signal based on signal selection by the selection circuit; and

outputting data corresponding to the data output command.

9. The method of claim 8, wherein receiving the data output command comprises: a preset delay signal pattern included in the data output command is checked, and the flip signal is used as the delay control signal when the preset delay signal pattern is checked.

10. The method of claim 8, wherein selecting one of the delay control signal and the delay signal comprises: the delay control signal is selected in a first flip signal period.

11. The method of claim 10, wherein selecting one of the delay control signal and the delay signal comprises: the delay signal of the master clock signal generated by the second clock signal generator is selected in a second flip signal period.

12. The method of claim 11, further comprising:

the delay signal is controlled by a domain crossing circuit by controlling the delay signal of the master clock signal and transmitting a controlled delay signal of the master clock signal to the first clock signal generator.

13. The method of claim 12, wherein controlling the delay signal comprises:

dividing the frequency of the data clock signal according to a preset standard; and

the sampling operation of synchronizing the delayed signal of the master clock signal with the divided data clock signal is repeated.

14. The method of claim 8, wherein receiving the data output command further comprises: generating the data output command, the data output command including a change in the data clock signal, and

Controlling the delay of the clock signal further comprises: the delay control signal is generated based on the change in the data clock signal.

15. A memory controller that receives a plurality of command signals from a host and controls operation of a memory device, the memory controller comprising:

a first clock signal generator configured to receive a data output command from the host and generate a flip signal for transmitting a data clock signal;

a second clock signal generator configured to generate a master clock signal including command/address information when generating the flip signal;

a delay controller configured to utilize the flip signal as a delay control signal when the data output command is input to the first clock signal generator;

a selection circuit configured to select one of the delay control signal and the delay signal of the master clock signal generated by the second clock signal generator; and

and an output unit configured to output data based on signal selection of the selection circuit.

16. The memory controller of claim 15, wherein the memory controller includes a pattern checker configured to check a preset delay signal pattern included in the data output command signal, and to utilize the roll-over signal as the delay control signal when the preset delay signal pattern is checked.

17. The memory controller of claim 15, wherein the selection circuit selects the delay control signal in a first inversion signal period.

18. The memory controller of claim 17, wherein the selection circuit selects the delayed signal of the master clock signal generated by the second clock signal generator in a second flip signal period.

19. The memory controller of claim 18, further comprising:

a domain crossing circuit configured to control the delay signal of the master clock signal and to send a controlled delay signal of the master clock signal to the first clock signal generator.

20. The memory controller of claim 15, wherein the delay controller generates the delay control signal based on a change in the data clock signal.