CN116889117A

CN116889117A - Phase change memory, manufacturing method thereof and electronic equipment

Info

Publication number: CN116889117A
Application number: CN202180093300.7A
Authority: CN
Inventors: 应成伟; 秦青; 周雪; 焦慧芳
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-05-11
Filing date: 2021-05-11
Publication date: 2023-10-13
Also published as: WO2022236707A1

Abstract

The embodiment of the application provides a phase-change memory, a manufacturing method thereof and electronic equipment, relates to the technical field of memories, and can solve the problem of increased power consumption caused by improving the phase-change speed of a phase-change material layer in the phase-change memory. The phase change memory includes a plurality of memory cells distributed in an array, the memory cells including: the heating electrode, the phase change material layer and the first electrode are sequentially stacked; the heating electrode comprises an insulating material layer and a plurality of conductive channels which are arranged in the insulating material layer and are formed by defects, and the conductive channels are in contact with the phase change material layer.

Description

Phase change memory, manufacturing method thereof and electronic equipment

Technical Field

The present application relates to the field of memory technologies, and in particular, to a phase change memory, a manufacturing method thereof, and an electronic device.

Background

Phase change memory (phase change memory, PCM) is a new type of nonvolatile memory, which has been receiving attention because of its fast read/write speed, high density, and good CMOS (complementary metal oxide semiconductor ) compatibility.

Phase change memories use current to drive crystallization and amorphization of phase change materials to store information. The phase change memory comprises a plurality of memory cells, and when the phase change material in the memory cells is in a crystallization state, the resistance of the memory cells is low, and the information stored in the memory cells can be recorded as first logic information, such as 0; when the phase change material in the memory cell is in an amorphous state, the resistance of the memory cell is high, at which time the information stored by the memory cell may be denoted as second logic information, e.g. "1". By determining the resistance of the memory cell, it can be determined whether the memory cell stores "0" or "1".

As shown in fig. 1, a memory cell 100 of the phase change memory includes a heating electrode 101, a phase change material layer 102, and a first electrode 103, which are stacked in this order. Since the phase change material layer 102 in the memory cell 100 changes phase by generating a large amount of heat by current driving the heating electrode 101, the phase change memory is an energy consumption type device. At present, a mode of increasing current can be adopted to increase the phase change speed of the phase change material layer 102 so as to increase the read-write speed of the phase change memory, but increasing the current can lead to increased power consumption. Therefore, increasing the phase change speed of the phase change material layer 102 in the phase change memory while reducing the power consumption is an urgent problem to be solved by the phase change memory.

Disclosure of Invention

The embodiment of the application provides a phase-change memory, a manufacturing method thereof and electronic equipment, which can solve the problem of increased power consumption caused by improving the phase-change speed of a phase-change material layer in the phase-change memory.

In order to achieve the above purpose, the application adopts the following technical scheme:

in a first aspect, a phase change memory is provided, the phase change memory comprising a plurality of memory cells distributed in an array, the memory cells comprising: the heating electrode, the phase change material layer and the first electrode are sequentially stacked; the heating electrode comprises an insulating material layer and a plurality of conductive channels which are arranged in the insulating material layer and are formed by defects, and the conductive channels are in contact with the phase change material layer. Since the heating electrode comprises the insulating material layer and a plurality of conductive channels arranged in the insulating material layer and formed by defects, the conductive channels play a role in conduction, and the conductive channels are formed by defects, so that the conductive channels have smaller dimensions in all directions perpendicular to the stacking direction of the memory element, for example, the dimensions L of the conductive channels are in the range of 0 < L.ltoreq.10 nm in all directions perpendicular to the stacking direction of the memory element, the contact area between the plurality of conductive channels and the phase change material layer is smaller, that is, the contact area between the conductive part of the heating electrode and the phase change material layer is smaller, and the smaller the contact area between the conductive channels and the phase change material layer is, the smaller the volume of the phase change region in the phase change material layer is, and the larger the current density is. The smaller the volume of the phase change region in the phase change material layer is, the larger the current density is, on one hand, the speed of phase change of the phase change material layer can be improved, and the read-write speed of the phase change memory is further improved; on the other hand, the current required for the phase change material layer to undergo a phase change can be reduced, and thus power consumption can be reduced. Based on the embodiment of the application, the phase change speed of the phase change material layer can be improved, so that the read-write speed of the phase change memory is improved, and the power consumption is reduced.

Compared with the heating electrode with a blade electrode structure, the heating electrode in the memory cell provided by the embodiment of the application has the conductive effect, the conductive channel 1012 is formed by defects, so that the conductive channel 1012 has smaller size along each direction perpendicular to the stacking direction of the memory element, and the contact area between the conductive channel and the phase change material layer in the heating electrode provided by the embodiment of the application is smaller, so that compared with the blade electrode structure, the embodiment of the application can further improve the phase change speed of the phase change material layer and further reduce the power consumption.

In an alternative embodiment, the conductive path extends through the layer of insulating material. The conductive channel penetrates the insulating material layer, and defects in the insulating material layer are used as conductive channels, and the size of the defects in the insulating material layer is very small and is about several nanometers, so that the size L of the conductive channel is very small along each direction perpendicular to the stacking direction of the memory element, and thus the contact area between the conductive channel in the heating electrode and the phase change material layer is small, and therefore the volume of the phase change region in the phase change material layer is small and the current density is large. Based on this, the power consumption can be reduced while the phase change speed of the phase change material layer is improved.

In an alternative embodiment, the material of the insulating material layer is a polycrystalline material and the defects include grain boundaries of the polycrystalline material. Grain boundaries within the insulating material layer are used as conductive channels such that the dimension L of the conductive channels is relatively small in each direction perpendicular to the stacking direction of the memory elements.

In an alternative embodiment, the heater electrode further comprises an electrically conductive discontinuous film layer; the discontinuous film layer comprises a plurality of mutually independent islands; the discontinuous film layer is positioned on one side of the conductive channel far away from the phase change material layer, the insulating material layer separates a plurality of islands in the discontinuous film layer, and the thickness of the insulating material layer is larger than that of the discontinuous film layer; wherein the conductive channels are in contact with islands in the discontinuous film layer. Here, the conductive path may be formed by the island tip discharge in the discontinuous thin film layer to break down the insulating material layer, and thus, the size L of the formed conductive path in each direction perpendicular to the stacking direction of the memory element may be made relatively small.

In an alternative embodiment, the material of the discontinuous film layer comprises one or more of magnesium, platinum, or aluminum. Here, the discontinuous thin film layer may be formed by controlling process parameters such as a rate of chemical vapor deposition, sputtering or spraying, a thickness of the discontinuous thin film layer, and the like according to the material properties of the discontinuous thin film layer.

In an alternative embodiment, the heater electrode further comprises an insulating discontinuous film layer; the discontinuous film layer comprises a plurality of mutually independent islands; the discontinuous film layer is positioned on one side of the insulating material layer away from the phase change material layer, and the insulating material layer separates a plurality of islands in the discontinuous film layer; wherein the conductive channels are located between the islands, the conductive channels extend through the insulating material layer, and the resistivity of the discontinuous film layer is greater than the resistivity of the insulating material layer. Here, the conductive path may be formed by partial discharge breakdown of the insulating material layer between the islands by the second electrode, and thus, the size L of the formed conductive path in each direction perpendicular to the stacking direction of the memory element may be made relatively small.

In an alternative embodiment, the heating electrode further comprises a conductive layer arranged on a side of the insulating material layer remote from the phase change material layer; the crystal structure of the material of the conductive layer is columnar crystal; wherein the conductive channel is in contact with an end of the columnar crystal. Here, the conductive path may be formed by breaking down the insulating material layer by the tip discharge of the columnar crystal, and thus, the size L of the formed conductive path in each direction perpendicular to the stacking direction of the memory element may be made relatively small.

In an alternative embodiment, the material of the conductive layer comprises titanium nitride. Wherein the crystal structure of the titanium nitride is columnar crystal.

In an alternative embodiment, the material of the insulating material layer comprises one or more of magnesium oxide, strontium oxide, aluminum oxide, tantalum oxide, titanium oxide, or hafnium oxide. The material of the insulating material layer may be selected from a few metal oxides.

In an alternative embodiment, the memory cell further comprises a second electrode arranged on a side of the heating electrode remote from the phase change material layer; wherein the conductive path is electrically connected to the second electrode. The first electrode of the memory cell is electrically connected to the bit line, and the second electrode of the memory cell is electrically connected to the gate device. When current flows to the second electrode, the current flows to the conductive channel in the heating electrode, so that a great amount of heat is generated by the conductive channel to drive the phase change material layer to change phase.

In an alternative embodiment, the phase change memory further includes: bit lines, word lines, and source lines; the memory cell further includes: a gating device; the first electrode of the gating device is electrically connected with the heating electrode, and the second electrode of the gating device is electrically connected with the source electrode wire; the third electrode of the gating device is electrically connected to the word line, and the first electrode of the memory cell is electrically connected to the bit line. The gating device may be, for example, a transistor or a gate tube, and the transistor may be, for example, a bipolar transistor, a triode, a field effect transistor, or the like. When the gating device is a transistor, the gating device can be a first electrode which is a source electrode and a second electrode which is a drain electrode; alternatively, the first electrode is a drain electrode, the second electrode is a source electrode, and the third electrode is a gate electrode.

In a second aspect, an electronic device is provided, where the electronic device includes a printed circuit board and a phase change memory electrically connected to the printed circuit board, and the phase change memory is the phase change memory provided in the first aspect. Since the electronic device has the same technical effects as the phase change memory, reference may be made to the above, and detailed description thereof will be omitted.

In a third aspect, a method for manufacturing a phase change memory is provided, where the method includes: firstly, forming a plurality of gating devices distributed in an array on a substrate; next, forming a plurality of memory elements distributed in an array on a substrate; the storage elements are electrically connected with the gating devices in a one-to-one correspondence manner; the manufacturing method of any one of the memory elements comprises the following steps: firstly, forming an auxiliary layer on a substrate; next, forming a phase change material layer on the auxiliary layer; next, forming a first electrode on the phase change material layer; next, applying a current to the auxiliary layer for initialization to form a heating electrode; the heating electrode comprises an insulating material layer and a plurality of conductive channels which are arranged in the insulating material layer and are formed by defects; the conductive via is in contact with the phase change material layer. The manufacturing method of the phase change memory has the same technical effects as those of the phase change memory provided in the first aspect, and reference may be made to the above, and details are not repeated here.

In an alternative embodiment, a method for fabricating any one of the memory elements includes: first, forming a heating electrode on a substrate; next, forming a phase change material layer on the heating electrode; next, forming a first electrode on the phase change material layer; the heating electrode comprises an insulating material layer and a plurality of conductive channels which are arranged in the insulating material layer and are formed by defects; the conductive via is in contact with the phase change material layer. The manufacturing method of the memory element has the same technical effects as those of the memory element in the phase change memory provided in the first aspect, and reference is made to the foregoing, and details are not repeated here.

In an alternative embodiment, forming an auxiliary layer on a substrate includes: forming an insulating material layer on a substrate; initializing the application of current to the auxiliary layer to form a heating electrode, comprising: and applying a current to the insulating material layer for initialization, wherein defects in the insulating material layer form conductive channels through the insulating material layer to form the heating electrode. The conductive channel penetrates the insulating material layer, and defects in the insulating material layer are used as conductive channels, and the size of the defects in the insulating material layer is very small and is about several nanometers, so that the size L of the conductive channel is very small along each direction perpendicular to the stacking direction of the memory element, and thus the contact area between the conductive channel in the heating electrode and the phase change material layer is small, and therefore the volume of the phase change region in the phase change material layer is small and the current density is large. Based on this, the power consumption can be reduced while the phase change speed of the phase change material layer is improved. In addition, the conductive channel formed by the defects is obtained, and meanwhile, the manufacturing process of the conductive channel is simple, so that the manufacturing cost of the phase change memory can be reduced.

In an alternative embodiment, the material of the insulating material layer is a polycrystalline material; initializing the application of current to the auxiliary layer to form a heating electrode, comprising: and applying current to the insulating material layer for initialization, wherein grain boundaries of the polycrystalline material penetrate through the insulating material layer to form conductive channels so as to form the heating electrode. Grain boundaries within the insulating material layer are used as conductive channels such that the dimension L of the conductive channels is relatively small in each direction perpendicular to the stacking direction of the memory elements.

In an alternative embodiment, forming a layer of insulating material on a substrate includes: forming a discontinuous thin film layer on a substrate; the discontinuous film layer comprises a plurality of mutually independent islands; and oxidizing the discontinuous film layer to form an insulating material layer. The material of the insulating-material layer thus formed is an oxide.

In an alternative embodiment, forming an auxiliary layer on a substrate includes: forming a conductive layer on a substrate; the crystal structure of the material of the conductive layer is columnar crystal; forming an insulating material layer on the conductive layer; initializing the application of current to the auxiliary layer to form a heating electrode, comprising: applying current to the conductive layer and the insulating material layer for initialization, and enabling the tip discharge of the columnar crystal to break down the insulating material layer to form a conductive channel in the insulating material layer so as to form a heating electrode; wherein the conductive channel is in contact with an end of the columnar crystal. The conductive channel is formed by the tip discharge of the columnar crystal and breaks down the insulating material layer, so that the conductive channel formed by the defects has very small size of about a few nanometers along each direction perpendicular to the stacking direction of the memory element, and thus the contact area between the conductive channel in the heating electrode and the phase change material layer is very small, the volume of the phase change region in the phase change material layer is small, the current density is high, and the power consumption can be reduced while the phase change speed of the phase change material layer is improved.

On the basis, the conducting channel formed by the defects is obtained, and meanwhile, the manufacturing process of the conducting channel is simple, so that the manufacturing cost of the phase change memory can be reduced.

In an alternative embodiment, forming an auxiliary layer on a substrate includes: forming a conductive discontinuous film layer on a substrate; the discontinuous film layer comprises a plurality of mutually independent islands; forming a layer of insulating material on the discontinuous film layer; wherein the insulating material layer separates the islands in the discontinuous film layer, and the thickness of the insulating material layer is greater than the thickness of the discontinuous film layer; initializing the application of current to the auxiliary layer to form a heating electrode, comprising: applying a current to the discontinuous film layer and the insulating material layer for initialization, and enabling the island tip discharge to break down the insulating material layer to form a conductive channel in the insulating material layer so as to form a heating electrode; wherein the conductive channels are in contact with islands in the discontinuous film. The conductive channel is formed by the island tip discharge in the discontinuous film layer to break down the insulating material layer, so that the dimension L of the conductive channel is very small, about several nanometers, along each direction perpendicular to the stacking direction of the memory element, so that the contact area between the conductive channel in the heating electrode and the phase change material layer is very small, the volume of the phase change region in the phase change material layer is small, the current density is high, and the power consumption can be reduced while the phase change speed of the phase change material layer is improved.

In an alternative embodiment, the method for manufacturing any one of the memory elements further includes, before forming the auxiliary layer on the substrate: forming a second electrode on the substrate; the conductive channel in the heating electrode is electrically connected with the second electrode. Reference may be made to the above description of the technical effects of the second electrode, which is not repeated here.

In an alternative embodiment, forming an auxiliary layer on a substrate includes: forming an insulating discontinuous thin film layer on a substrate; the discontinuous film layer comprises a plurality of mutually independent islands; forming a layer of insulating material on the discontinuous film layer; wherein the insulating material layer separates the plurality of islands in the discontinuous film layer; the resistivity of the discontinuous film layer is greater than that of the insulating material layer; initializing the application of current to the auxiliary layer to form a heating electrode, comprising: the non-continuous film layer and the insulating material layer are initialized by applying a current, and a part of the second electrode located between the islands is discharged to break down the insulating material layer, so that conductive channels are formed in the insulating material layer and penetrate through the insulating material layer to form the heating electrode. The conductive channel is formed by the partial discharge breakdown insulating material layer of the second electrode between the islands, so that the dimension L of the conductive channel is very small, about several nanometers, along each direction perpendicular to the stacking direction of the memory element, so that the contact area between the conductive channel in the heating electrode and the phase change material layer is very small, the volume of the phase change region in the phase change material layer is small, the current density is high, and the power consumption can be reduced while the phase change speed of the phase change material layer is improved.

Drawings

FIG. 1 is a schematic diagram of a memory cell according to the prior art;

fig. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of an electronic device according to another embodiment of the present application;

FIG. 4 is a schematic diagram of a phase change memory according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a memory device according to an embodiment of the present application;

FIG. 6 is a schematic diagram illustrating a structure of a memory device during fabrication according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a memory device according to another embodiment of the present application;

FIG. 8a is a schematic diagram of a phase change material layer or a first electrode according to an embodiment of the present application;

FIG. 8b is a schematic diagram illustrating a phase change material layer or a first electrode according to another embodiment of the present application;

FIG. 8c is a schematic diagram illustrating a phase change material layer or a first electrode according to another embodiment of the present application;

FIG. 9 is a schematic flow chart of a method for fabricating a memory device according to an embodiment of the present application;

FIG. 10 is a schematic diagram illustrating a memory device according to another embodiment of the present application;

FIG. 11 is a schematic diagram of a heating electrode according to an embodiment of the present application;

FIG. 12 is a flowchart of a method for fabricating a memory device according to another embodiment of the present application;

FIG. 13 is a schematic diagram illustrating a memory device according to another embodiment of the present application;

FIG. 14 is a schematic diagram of a memory device according to another embodiment of the present application;

FIG. 15 is a flowchart illustrating a method for fabricating a memory device according to another embodiment of the present application;

FIG. 16 is a schematic diagram illustrating a memory device according to another embodiment of the present application;

FIG. 17 is a schematic diagram of a memory device according to another embodiment of the present application;

FIG. 18 is a schematic diagram of a memory device according to another embodiment of the present application;

FIG. 19 is a flowchart of a method for fabricating a memory device according to another embodiment of the present application;

Fig. 20 is a schematic structural diagram of a memory device according to another embodiment of the present application in the manufacturing process.

Reference numerals: 1-an electronic device; 10-phase change memory; 11-a storage device; 12-a processor; 13-an input device; 14-an output device; 15-middle frame; 16-a rear shell; 17-a display screen; a 100-memory cell; 100A-a memory element; 101-heating an electrode; 102-a phase change material layer; 103-a first electrode; 104-a second electrode; 105-cladding layer; 106-an auxiliary layer; 107-a discontinuous film layer; 108-a conductive layer; 111-an external memory; 112-an internal memory; 121-an operator; 122-a controller; 150-bearing plates; 151-frame; 1011-a layer of insulating material; 1012-conductive channels; 1051-cladding material; 1052-bump.

Detailed Description

The following description of the technical solutions according to the embodiments of the present application will be given with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments.

Hereinafter, the terms "first," "second," and the like are used for descriptive convenience only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

In the embodiments of the present application, unless explicitly specified and limited otherwise, the term "electrically connected" may be either a direct electrical connection or an indirect electrical connection via an intermediary.

In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the embodiment of the present application, "and/or" describes the association relationship of the association object, which means that three relationships may exist, for example, a and/or B may mean: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship.

In embodiments of the application, directions of movement and construction of the various components used to explain the application are relative, such as up, down, left, right, front and rear, etc. These indications are appropriate when the component is in the position shown in the figures. However, if the description of the position of the element changes, then these directional indications will also change accordingly.

The embodiment of the application provides electronic equipment, which can be, for example, mobile phones (mobile phones), tablet computers (pads), personal digital assistants (personal digital assistant, PDAs), televisions, intelligent wearable products (such as intelligent watches and intelligent bracelets), virtual Reality (VR) terminal equipment, augmented reality (augmented reality, AR) terminal equipment, charging household small-sized appliances (such as soymilk machines and sweeping robots), unmanned aerial vehicles, radars, aerospace equipment, vehicle-mounted equipment and other user equipment or terminal equipment of different types; the electronic device may also be a network device such as a base station. The embodiment of the application does not particularly limit the specific form of the electronic device.

Fig. 2 is a schematic architecture diagram of an electronic device according to an exemplary embodiment of the present application. As shown in fig. 2, the electronic apparatus 1 includes: storage 11, processor 12, input device 13, output device 14, and the like. Those skilled in the art will appreciate that the structure of the electronic device shown in fig. 2 does not constitute a limitation of the electronic device 1, and the electronic device 1 may include more or fewer components than those shown in fig. 2, or may combine some of the components shown in fig. 2, or may be arranged differently from the components shown in fig. 2.

The storage means 11 are for storing software programs and modules. The storage device 11 mainly includes a storage program area that can store an operating system, application programs (such as a sound playing function, an image playing function, etc.) required for at least one function, and a storage data area; the storage data area may store data created according to the use of the electronic device (such as audio data, image data, phonebook, etc.), and the like. Further, the storage device 11 includes an external memory 111 and an internal memory 112. The data stored in the external memory 111 and the internal memory 112 can be transferred to each other. The external memory 111 includes, for example, a hard disk, a usb disk, a floppy disk, and the like. The internal memory 112 includes, for example, a random access memory, a read only memory, and the like. The random access memory may be, for example, a phase change memory, a magnetic memory, a ferroelectric memory, or the like.

The processor 12 is a control center of the electronic device 1, connects respective parts of the entire electronic device 1 using various interfaces and lines, and performs various functions of the electronic device 1 and processes data by running or executing software programs and/or modules stored in the storage device 11 and calling data stored in the storage device 11, thereby performing overall monitoring of the electronic device 1. Alternatively, the processor 12 may include one or more processing units. For example, the processor 12 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a flight controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and/or a neural network processor (neural-network processing unit, NPU), etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors. For example, processor 12 may integrate an application processor that primarily handles operating systems, user interfaces, applications, etc., with a modem processor that primarily handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 12. The application processor may be, for example, a central processing unit (central processing unit, CPU). In fig. 2, the processor 12 is taken as an example of a CPU, and the CPU may include an operator 121 and a controller 122. The arithmetic unit 121 acquires data stored in the internal memory 112, processes the data stored in the internal memory 112, and normally returns the processed result to the internal memory 112. The controller 122 may control the operator 121 to process the data, and the controller 122 may also control the external memory device 111 and the internal memory 112 to store the data or read the data.

The input device 13 is used to receive input numeric or character information and to generate key signal inputs related to user settings and function control of the electronic device. By way of example, the input device 13 may include a touch screen, as well as other input devices. Touch screens, also known as touch panels, collect touch operations by a user on or near the touch screen (e.g., operations by a user on or near the touch screen using any suitable object or accessory such as a finger, stylus, etc.), and actuate the corresponding connection device according to a predetermined program. Alternatively, the touch screen may comprise two parts, a touch detection device and a touch controller. The touch detection device detects the touch azimuth of a user, detects a signal brought by touch operation and transmits the signal to the touch controller; the touch controller receives touch information from the touch detection device and converts it into touch point coordinates, which are then sent to the processor 12, and can receive commands from the processor 12 and execute them. In addition, the touch screen may be implemented in various types such as resistive, capacitive, infrared, and surface acoustic wave. Other input devices may include, but are not limited to, one or more of a physical keyboard, function keys (e.g., volume control keys, power switch keys, etc.), a trackball, mouse, joystick, etc. The controller 122 in the processor 12 may also control the input device 13 to receive an input signal or not. Further, the entered number or character information received by the input device 13, as well as key signal inputs generated in connection with user settings and function controls of the electronic device, may be stored in the internal memory 112.

The output device 14 is used for outputting a signal corresponding to the data inputted from the input device 13 and stored in the internal memory 112. For example, the output device 14 outputs a sound signal or a video signal. The controller 122 in the processor 12 may also control the output device 14 to output signals or not.

The thick arrow in fig. 2 is used to indicate the transmission of data, and the direction of the thick arrow indicates the direction of data transmission. For example, a single arrow between the input device 13 and the internal memory 112 indicates that data received by the input device 13 is transferred to the internal memory 112. For another example, double-headed arrows between the operator 121 and the internal memory 112 indicate that data stored in the internal memory 112 may be transferred to the operator 121, and data processed by the operator 121 may be transferred to the internal memory 112. Thin arrows in fig. 2 represent components that the controller 122 may control. By way of example, the controller 122 may control the external memory device 111, the internal memory 112, the operator 121, the input device 13, the output device 14, and the like.

Optionally, the electronic device 1 as shown in fig. 2 may also comprise various sensors. Such as gyroscopic sensors, hygrometric sensors, infrared sensors, magnetometer sensors, etc., are not described in detail herein. Optionally, the electronic device 1 may further include a wireless fidelity (wireless fidelity, wiFi) module, a bluetooth module, etc., which will not be described herein.

It will be appreciated that in embodiments of the present application, an electronic device (e.g., the electronic device shown in fig. 2 described above) may perform some or all of the steps in embodiments of the present application, which are merely examples, and embodiments of the present application may also perform other operations or variations of the various operations. Furthermore, the various steps may be performed in a different order presented in accordance with embodiments of the application, and it is possible that not all of the operations in the embodiments of the application may be performed. The embodiments of the present application may be implemented alone or in any combination, and the present application is not limited thereto.

For convenience of further explanation of the structure of the electronic device 1, the electronic device 1 will be exemplified as a mobile phone. As shown in fig. 3, the electronic device 1 may further include a middle frame 15, a rear case 16, and a display screen 17. The rear case 16 and the display screen 17 are respectively located at both sides of the middle frame 15, and the middle frame 15 and the display screen 17 are disposed in the rear case 16. The middle frame 15 includes a carrying plate 150 for carrying the display 17, and a rim 151 surrounding the carrying plate 150 for one week. The electronic device 1 may further comprise a printed circuit board (printed circuit boards, PCB) provided on a surface of the carrier plate 150 facing the back case 16, on which printed circuit board some of the electronic components in the electronic device 1, such as the phase change memory 10 described above, may be provided; wherein the phase change memory 10 is electrically connected with a printed circuit board PCB.

The embodiment of the application also provides a phase change memory, which can be applied to the electronic device 1, for example, can be used as the internal memory 112 in the electronic device 1.

As shown in fig. 4, the structure of the phase change memory 10 according to the embodiment of the present application includes: a plurality of memory cells 100 are distributed in an array, the memory cells 100 including a gating device and a memory element 100A electrically connected to the gating device. The gating device may be, for example, a transistor or a gate tube, and the transistor may be, for example, a bipolar transistor, a triode, a field effect transistor, or the like. Wherein the gating device comprises a first pole, a second pole and a third pole. The following description and fig. 4 each illustrate a gating device as an example of a transistor T. The phase change memory 10 further includes a plurality of Word Lines (WL) and a plurality of Bit Lines (BL) arranged in parallel, and the word lines WL and the bit lines BL cross each other but are isolated from each other, for example, the word lines WL and the bit lines BL are perpendicular to each other. The bit line BL is electrically connected to the memory element 100A. The phase change memory 10 further includes a plurality of Source Lines (SL) arranged in parallel. In some examples, the source line SL is parallel to the bit line BL. Wherein the transistor T comprises a first pole, a second pole and a third pole; the first pole and the second pole are used as interfaces for current flowing in or out when the transistor is turned on, the third pole is a control pole (also called a grid) of the transistor, for example, the first pole is a source electrode, and the second pole is a drain electrode; alternatively, the first electrode is a drain electrode and the second electrode is a source electrode. The gate of the transistor T is electrically connected to the word line WL, the first pole of the transistor T is electrically connected to the memory element 100A, and the second pole of the transistor T is electrically connected to the source line SL.

In some examples, the word line WL is also electrically connected to a word line control circuit, by which a high level signal or a low level signal is provided to the word line WL to put the transistor T in an on state or an off state. In the case where the transistor T is an N-type transistor, the high level signal controls the transistor T to be turned on and the low level signal controls the transistor T to be turned off. In the case that the transistor T is a P-type transistor, the low level signal controls the transistor T to be turned on and the high level signal controls the transistor T to be turned off.

In some examples, the bit line BL is also electrically connected to a bit line control circuit by which signals are provided to the bit line BL.

In some examples, the source line SL may be grounded.

In some examples, referring to fig. 4, the second pole of the transistor T in the plurality of memory cells 100 arranged in the Y direction is electrically connected to the same source line SL, the memory element 100A in the plurality of memory cells 100 arranged in the Y direction is electrically connected to the same bit line BL, and the gate of the transistor T in the plurality of memory cells 100 arranged in the X direction is electrically connected to the same word line WL.

The structure of the memory element 100A in the above-described memory cell 100 is exemplarily described below.

In an alternative embodiment, as shown in fig. 5, the memory element 100A includes a heating electrode 101, a phase change material layer 102, and a first electrode (may also be referred to as an upper electrode) 103 that are stacked in this order; the memory element 100A further comprises a second electrode (which may also be referred to as lower electrode) 104 arranged on the side of the heating electrode 101 remote from the phase change material layer 102. Wherein the heating electrode 101 adopts a blade type electrode structure (wall architecture). For the blade electrode structure, referring to fig. 5, the thickness d of the heating electrode 101 is much smaller than the width W and the height H of the heating electrode 101.

The bit line BL is electrically connected to the memory element 100A, that is, the bit line BL is electrically connected to the first electrode 103 of the memory element 100A. The first electrode of the transistor T is electrically connected to the memory element 100A, i.e., the first electrode of the transistor T is electrically connected to the second electrode 104 of the memory element 100A. It will be appreciated that the second electrode 104 is electrically connected to the first electrode of the transistor T through a via in the insulating layer. If the heater electrode 101 is directly electrically connected to the first electrode of the transistor T through the via hole on the insulating layer, there may be a risk that the heater electrode 101 is not electrically connected to the via hole on the insulating layer due to the small area of the lower surface of the heater electrode 101, and further there may be a risk that the heater electrode 101 is not electrically connected to the first electrode of the transistor T, so that the memory element 100A may not be electrically connected to the first electrode of the transistor T. Based on this, the second electrode 104 can be provided in the memory element 100A, and the second electrode 104 is electrically connected to the first electrode of the transistor T through the via hole in the insulating layer, so that the electrical connection of the memory element 100A to the first electrode of the transistor T can be ensured. Referring to fig. 4, the first electrodes 103 in the memory elements 100A of the plurality of memory cells 100 arranged in the Y direction are electrically connected to the same bit line BL.

Based on the above-described memory cell 100 and the structure of the memory element 100A in the memory cell 100, the operation principle of the phase change memory 10 will be described below using one memory cell 100 as an example.

When the memory cell 100 is written, the transistor T is in an on state, and when the current flowing through the memory element 100A is a small current and is long pulse, the phase change material in the phase change material layer 102 is in a crystallization state, and at this time, the resistance of the memory cell 100 is low, so that the memory cell 100 can be considered to store first logic information, and the first logic information can be represented by "0", for example; when the current flowing through the memory element 100A is a large current and a short pulse, the phase change material in the phase change material layer 102 is in an amorphous state, and the resistance of the memory cell is high, the memory cell 100 may be considered to store second logic information, which may be represented by "1", for example.

In the memory cell 100, a constant current flows from the bit line BL through the memory element 100A to the second pole of the turned-on transistor T during reading, and thus a potential difference is generated across the memory element 100A. The resistance of the memory element 100A can be determined according to the magnitude of the potential difference, and it can be determined whether the information stored in the memory element 100A is the first logic information "0" or the second logic information "1".

Referring to fig. 5, since the heating electrode 101 adopts a blade electrode structure, the contact area between the heating electrode 101 and the phase change material layer 102 is small, so that the volume of the phase change region (which may also be referred to as a programming region) is small, and the current density is large, so that, on one hand, the speed of phase change of the phase change material layer 102 is high; on the other hand, the current required for the phase change of the phase change material layer 102 located in the phase change region may be reduced, and thus power consumption may be reduced. Based on this, in the case where the heating electrode 101 adopts the blade electrode structure, since the contact area of the heating electrode 101 and the phase change material 102 is small, the phase change speed of the phase change material layer 102 can be increased to increase the read/write speed of the phase change memory 10, while the power consumption can be reduced.

In some examples, the process flow of fabricating the memory device 100A shown in fig. 5 is shown in fig. 6, wherein the left diagram in fig. 6 is a schematic cross-sectional view along a direction parallel to the stacking direction Z and parallel to the X direction, and the right diagram in fig. 6 is a schematic cross-sectional view along a direction parallel to the stacking direction Z and parallel to the Y direction.

Referring to fig. 6, the memory element 100A shown in fig. 5 is fabricated, and specifically includes the following steps:

First, a plurality of second electrodes 104 distributed in an array are formed, and a coating material 1051 is filled around and above the second electrodes 104; next, the cladding material 1051 is etched to form a plurality of stripe-shaped bumps 1052 arranged in sequence along the Y direction and extending along the X direction, and the upper surface of each second electrode 104 is exposed to the gaps between the bumps 1052.

Next, growing a conductive film, and etching the conductive film by using a photolithography process to form conductive strips on the sides of each of the strip-shaped bumps 1052, wherein the conductive strips formed after etching may be L-shaped, i.e., the conductive strips may extend from the sides of the bumps 1052 to the surface of the second electrode 104; next, the conductive strips formed on the sides of the bumps 1052 are etched by a photolithography process to form a plurality of heating electrodes 101, one heating electrode 101 corresponding to each second electrode 104; next, the cladding material 1051 is filled and ground down until the heating electrode 101 is exposed.

Next, a phase change material layer 102 is formed on each heating electrode 104, and the phase change material layers 102 over a plurality of second electrodes 104 arranged in the Y direction may be electrically connected together; next, the cladding material 1051 is filled and ground down until the upper surface of the phase change material layer 102 is exposed; next, a first electrode 103 is formed on each phase change material layer 102, and the first electrodes 103 over a plurality of second electrodes 104 arranged in the Y direction may be electrically connected together; next, the cladding material 1051 is filled. Wherein all of the cladding material 1051 constitutes the cladding layer 105.

Based on the above-mentioned manufacturing process of the memory element 100A, the heating electrode 101 in the manufactured memory element 100A has a blade electrode structure. The thickness d of the heating electrode 101 may be determined by controlling the thickness of the grown conductive film, and the thickness of the grown conductive film may be as small as about ten or more nanometers, and in some examples, the thickness of the heating electrode 101 may be as small as 10nm to 15nm. The width (W) of the heating electrode 101 in the X direction may be controlled by a photolithography process. The contact area of the heating electrode 101 and the phase change material layer 102 is determined by the thickness d of the heating electrode 101 and the width W of the heating electrode 101 in the X direction. When the conductive film is formed, the thickness of the conductive film can be made smaller by controlling the growth process, so that the thickness of the formed heating electrode 101 can be controlled smaller, and the contact area between the heating electrode 101 and the phase change material layer 102 can be made smaller.

However, although the thickness of the conductive film can be controlled to be small by controlling the growth process, and thus the thickness d of the heating electrode 101 can be controlled to be small, the width W of the heating electrode 101 in the X direction is controlled by a photolithography process, based on which the width W of the heating electrode 101 in the X direction is difficult to be further miniaturized, and the width W of the heating electrode 101 in the X direction controlled by the photolithography process is generally 10nm or more. When the thickness d of the heating electrode 101 is 10nm to 15nm, the current required for phase-changing the phase-change material layer 102 is about 100 μA when the width W of the heating electrode 101 in the X direction is 30 nm; when the width W of the heating electrode 101 in the X direction is 45nm, the current required for phase-changing the phase-change material layer 102 is about 180 μa. Since the width W of the heating electrode 101 in the X direction is limited by the photolithography process, it is difficult to further shrink the area of the heating electrode 101 contacting the phase change material layer 102, and thus the current density cannot be further increased, so that the phase change speed of the phase change material layer 102 cannot be further increased, and the power consumption cannot be further reduced.

Based on the above, in order to further increase the phase change speed of the phase change material layer 102 and further reduce the power consumption, the embodiment of the present application further provides a memory element 100A, where the structure of the memory element 100A is as shown in fig. 7, and the memory element includes a second electrode 104, a heating electrode 101, the phase change material layer 102 and a first electrode 103 that are sequentially stacked; the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive vias 1012 made of defects (defects) provided in the insulating material layer 1011, the conductive vias 1012 being in contact with the phase change material layer 102, and the conductive vias 1012 being electrically connected to the second electrode 104.

It should be noted that, the working principle of the phase change memory 10 is the same as that described above, and reference is made to the above description, and the description is omitted here.

Here, the material of the insulating material layer 1011 may be crystalline or amorphous. In the case where the material of the insulating material layer 1011 is crystalline, the material of the insulating material layer 1011 may be a single crystal material or a polycrystalline material.

On this basis, defects in the insulating material layer 1011 may include, for example, dislocations, grain boundaries, vacancies (e.g., oxygen vacancies) (hole), or wires, or the like. It should be appreciated that when a defect in the insulating material layer 1011 reaches a concentration at the location of the conductive channel 1012, the conductive channel 1012 may be formed.

In addition, it is understood that conductive via 1012 includes, but is not limited to being comprised of one type of defect, and conductive via 1012 may be comprised of multiple types of defects. For example, conductive channels 1012 may be comprised of grain boundaries. For another example, the conductive channels 1012 may be composed of grain boundaries, vacancies, dislocations, and the like.

In some examples, the defect may include a wire when the material in contact with at least one of the ends of the conductive channel 1012 is an active metal. In other examples, where the material in contact with both ends of the conductive via 1012 is an inactive metal, e.g., platinum (pt) is the material in contact with one end of the conductive via 1012 and titanium nitride (TiN) is the material in contact with the other end of the conductive via 1012, the defects may include dislocations, grain boundaries, vacancies, or the like.

It will be appreciated that since the conductive via 1012 is composed of defects, the conductive via 1012 is small in size in each direction perpendicular to the stacking direction Z of the memory element 100A. In some examples, as shown in FIG. 7, the conductive via 1012 has a dimension L in a direction perpendicular to the stacking direction Z of the memory element 100A (i.e., in a direction parallel to the phase change material layer 102) in the range of 0 < L.ltoreq.10 nm, i.e., the conductive via 1012 has a radial dimension L in the range of 0 < L.ltoreq.10 nm.

Here, the dimension L of the conductive channel 1012 may be, for example, 1nm, 3nm, 5nm, 8nm, 10nm, or the like in each direction perpendicular to the stacking direction Z of the memory element 100A.

In addition, the number of the conductive channels 1012 in the heating electrode 101 is not limited, and may be set as needed.

On this basis, the conductive channels 1012 in the heater electrode 101 may be straight or curved. The conductive channels 1012 may be disposed perpendicular to the second electrode 104 or may be disposed obliquely with respect to the second electrode 104. The different conductive channels 1012 may or may not intersect.

The material of the phase change material layer 102 should have a phase change property. In some examples, the material of phase change material layer 102 may be one or more of a GeTe (germanium tellurium) alloy, a Sb2Te5 (antimony tellurium) alloy, or a Ge2Sb2Te5 (germanium antimony tellurium) alloy. The Ge2Sb2Te5 alloy may be simply referred to as GST, which is currently the most widely used phase change material in the phase change memory 10.

In some examples, the material of the first electrode 103 and the material of the second electrode 104 may include, for example, one or more of copper (Cu), silver (Ag), aluminum (Al), gold (Au). The first electrode 103 and the second electrode 104 may have a single-layer structure or a multilayer structure.

It should be understood that in the phase change memory 10, the second electrodes 104 in the plurality of memory elements 100A are independent of each other, and the heating electrodes 101 in the plurality of memory elements 100A are independent of each other. On this basis, in some examples, as shown in fig. 8a, the phase change material layers 102 in the plurality of memory elements 100A are independent of each other; in other examples, as shown in FIG. 8b, the phase change material layers 102 in the plurality of memory elements 100A are electrically connected together, i.e., the plurality of phase change material layers 102 form a monolithic structure; in still other examples, as shown in fig. 8c, the phase change material layers 102 in the plurality of memory elements 100A arranged in the Y-direction are electrically connected together, i.e., the plurality of phase change material layers 102 constitute a plurality of stripe-like structures.

Further, in some examples, as shown in fig. 8a, the first electrodes 103 in the plurality of memory elements 100A are independent of each other; in other examples, as shown in fig. 8b, the first electrodes 103 in the plurality of memory elements 100A are electrically connected together, i.e., the plurality of first electrodes 103 constitute a monolithic structure; in still other examples, as shown in fig. 8c, the first electrodes 103 in the plurality of memory elements 100A arranged in the Y-direction are electrically connected together, i.e., the plurality of first electrodes 103 constitute a plurality of stripe-like structures.

The embodiment of the present application provides a phase change memory 10, where a memory cell 100 of the phase change memory 10 includes a second electrode 104, a heating electrode 101, a phase change material layer 102 and a first electrode 103, which are sequentially stacked, and since the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive channels 1012 formed by defects and disposed in the insulating material layer 1011, the conductive channels 1012 of the heating electrode 101 perform a conductive function, and the conductive channels 1012 are formed by defects, the dimensions of the conductive channels 1012 in each direction perpendicular to a stacking direction Z of the memory element 100A are smaller, for example, the dimensions L of the conductive channels 1012 in each direction perpendicular to the stacking direction Z of the memory element 100A may range from 0 < L to 10nm, so that the contact area between the plurality of conductive channels 1012 and the phase change material layer 102 is smaller, that is, the contact area between a portion of the heating electrode 101 that performs a conductive function and the phase change material layer 102 is smaller, the volume of the phase change material layer 102 is smaller, and the current density is larger. The smaller the volume of the phase change region in the phase change material layer 102 is, the larger the current density is, on one hand, the speed of phase change of the phase change material layer 102 can be improved, and further the read-write speed of the phase change memory 10 is improved; on the other hand, the current required for the phase change material layer 102 to undergo a phase change may be reduced, and thus, power consumption may be reduced. Based on this, the embodiment of the application can increase the phase change speed of the phase change material layer 102 to increase the read-write speed of the phase change memory 10 and reduce the power consumption.

Compared with the heating electrode 101 having a blade electrode structure, the embodiment of the application provides the heating electrode 101 in the memory cell 100, in which the conductive channel 1012 has a conductive effect, and the conductive channel 1012 is formed by a defect, so that the conductive channel 1012 has a smaller dimension along each direction perpendicular to the stacking direction Z of the memory element 100A, and the contact area between the conductive channel 1012 and the phase change material layer 102 in the heating electrode 101 is smaller, so that the embodiment of the application can further improve the phase change speed of the phase change material layer 102 and further reduce the power consumption compared with the blade electrode structure.

The embodiment of the application also provides a manufacturing method of the phase change memory, which comprises the following steps:

forming a plurality of gate devices distributed in an array on a substrate; next, a plurality of memory elements 100A are formed on the substrate in an array distribution, the gate devices are electrically connected to the memory elements 100A in a one-to-one correspondence, and one memory element 100A and one gate device electrically connected thereto constitute one memory cell 100. The types of gating devices may be referred to above, and will not be described here.

The method for manufacturing the memory element 100A in any one of the memory cells 100, for example, the method for manufacturing the memory element 100A in any one of the memory cells 100 shown in fig. 7, as shown in fig. 9, may include the following steps:

S10, as shown in fig. 10, a second electrode 104 is formed on the substrate 105.

Here, the substrate 105 may be a semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate; glass (glass) substrates or substrates comprising organic materials, etc. are also possible.

In some examples, forming the second electrode 104 on the substrate 105 includes: first, a conductive film is formed on a substrate 105; next, a patterning process is performed on the conductive film to form the second electrode 104. Here, the conductive film can be formed by a chemical vapor deposition method (chemical vapor deposition, CVD), a sputtering method, a spraying method, or the like. The patterning process comprises the processes of photoresist coating, mask exposure, development, etching and the like.

The second electrode 104 may have a single-layer structure or a multilayer structure. The material of the second electrode 104 may refer to the above embodiments, and will not be described herein.

S11, as shown in fig. 10, an auxiliary layer 106 is formed on the second electrode 104.

S12, as shown in fig. 10, the phase change material layer 102 is formed on the auxiliary layer 106.

Herein, the material of the phase change material layer 102 may refer to the above embodiments, and will not be described herein.

In some examples, the phase change material layer 102 may be formed using a chemical vapor deposition method, a sputtering method, a spraying method, or the like.

S13, as shown in fig. 10, a first electrode 103 is formed on the phase change material layer 102.

In some examples, forming the first electrode 103 on the phase change material layer 102 includes: first, a conductive film is formed on a phase change material layer 102; next, a patterning process is performed on the conductive film to form the first electrode 103. Here, the conductive film may be formed by a chemical vapor deposition method, a sputtering method, a spraying method, or the like. The patterning process comprises the processes of photoresist coating, mask exposure, development, etching and the like.

Here, the first electrode 103 may have a single-layer structure or a multi-layer structure. The material of the first electrode 103 may refer to the above embodiment, and will not be described herein.

S14, as shown in fig. 10, initializing the auxiliary layer 106 by applying a current to form the heating electrode 101; wherein the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive channels 1012 formed of defects disposed within the insulating material layer 1011; the conductive via 1012 is in contact with the phase change material layer 102, and the conductive via 1012 is electrically connected with the second electrode 104.

Here, the type of the defect may be referred to above, and will not be described here again.

Since the conductive via 1012 is constituted by a defect, the conductive via 1012 is small in size in each direction perpendicular to the stacking direction Z of the memory element 100A. In some examples, the conductive via 1012 has a dimension L in each direction perpendicular to the stacking direction Z of the memory element 100A in the range of 0 < L+.10 nm.

In some examples, the dimension L of the conductive via 1012 may be, for example, 1nm, 3nm, 5nm, 8nm, 10nm, or the like, in each direction perpendicular to the stacking direction Z of the memory element 100A.

It should be appreciated that the initialization may be performed by applying a voltage to the first electrode 103 through the bit line BL, and applying a voltage to the second electrode 105 through the source line SL, thereby applying a current to the auxiliary layer 106. It will be appreciated that the applied current should be relatively large when initializing the auxiliary layer 106.

Here, the number of the conductive channels 1012 in the heating electrode 101 is not limited, and may be set as needed.

In addition, the conductive channels 1012 in the heater electrode 101 may be straight or curved. The conductive channels 1012 may be disposed perpendicular to the second electrode 104 or may be disposed obliquely with respect to the second electrode 104. The different conductive channels 1012 may or may not intersect.

In an alternative embodiment, the method for fabricating the memory element 100A in any one of the memory cells 100, for example, the method for fabricating the memory element 100A in any one of the memory cells 100 shown in fig. 7, may further include the following steps:

s20, forming a second electrode 104 on the substrate 105.

It should be noted that, the step S20 may refer to the above step S10, and will not be described herein.

S21, forming a heating electrode 101 on the second electrode 104; wherein the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive channels 1012 formed of defects disposed within the insulating material layer 1011; the conductive via 1012 is electrically connected to the second electrode 104.

It should be noted that, the dimensions L, the number of the conductive channels 1012 and the shape of the conductive channels 1012 can refer to the above step S14, and will not be described herein.

S22, forming a phase change material layer 102 on the heating electrode 101; conductive via 1012 is in contact with phase change material layer 102.

It should be noted that, the step S22 may refer to the step S12, which is not described herein.

S23, a first electrode 103 is formed on the phase change material layer 102.

It should be noted that, step S23 may refer to step S13, and will not be described herein.

It is understood that the memory element 100A in any one of the memory cells 100 in the phase change memory 10 can be manufactured by the manufacturing method of the memory element 100A provided in steps S10 to S14 or steps S20 to S23. In addition, a plurality of memory cell elements 100A in phase change memory 10 may be fabricated simultaneously.

It can be understood that the method for manufacturing the phase change memory provided in the steps S10 to S14 or the steps S20 to S23 has the same technical effects as those of the phase change memory 10, and reference may be made to the description of the technical effects of the phase change memory 10, which is not repeated herein.

Several specific embodiments are provided below to exemplarily describe the structure of the memory element 100A in the memory cell 100 and the manufacturing method of the memory element 100A.

Example 1

The structure of the memory element 100A according to the first embodiment is shown in fig. 7, and includes: a second electrode 104, a heating electrode 101, a phase change material layer 102, and a first electrode 103, which are sequentially stacked; the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive channels 1012 formed of defects disposed within the insulating material layer 1011, the conductive channels 1012 penetrating the insulating material layer 1011, the conductive channels 1012 being in contact with the phase change material layer 102, and the conductive channels 1012 being electrically connected to the second electrode 104.

Here, the type, size, etc. of the defect may be referred to the above, and will not be described here.

In some examples, the material of insulating material layer 1011 is a polycrystalline material and the defects comprising conductive via 1012 described above include grain boundaries of the polycrystalline material.

It should be understood that in the case where the material of the insulating material layer 1011 is a polycrystalline material, the material of the insulating material layer 1011 includes grain boundaries. Fig. 11 is a plan view of the heating electrode 1011, and as can be seen from fig. 11, the insulating material layer 1011 includes a plurality of grain boundaries.

In some examples, the material of insulating material layer 1011 includes magnesium oxide (MgO), strontium oxide (SrO), aluminum oxide (Al ₂ O ₃ ) Tantalum oxide (TaO) _x ) Titanium oxide (TiO) ₂ ) Or hafnium oxide (HfO) ₂ ) One or more of the following.

In the first embodiment, the conductive channel 1012 penetrates the insulating material layer 1011, and the defect in the insulating material layer 1011 is used as the conductive channel 1012, and the size L of the conductive channel 1012 is very small along each direction perpendicular to the stacking direction Z of the memory element 100A because the size of the defect in the insulating material layer 1011, such as the grain boundary, is very small, so that the contact area between the conductive channel 1012 and the phase change material layer 102 in the heating electrode 101 is small, the volume of the phase change region in the phase change material layer 102 is small, and the current density is large. Based on this, power consumption can be reduced while increasing the phase change speed of the phase change material layer 102.

The first embodiment also provides a method for manufacturing the memory element 100A, which can be used to manufacture the memory element 100A provided in the first embodiment, and the method for manufacturing the memory element 100A, as shown in fig. 12, includes the following steps:

s100, as shown in fig. 13, a second electrode 104 is formed on a substrate 105.

It should be noted that, the step S100 may refer to the above step S10, and will not be described herein.

S101, as shown in fig. 13, forming a discontinuous thin film layer 107 on the second electrode 104; the discontinuous film layer 107 comprises a plurality of islands that are independent of each other.

Here, the discontinuous thin film layer 107 may be formed by a chemical vapor deposition method, a sputtering method, a spraying method, or the like.

It should be noted that, depending on the nature of the material of the discontinuous film layer 107, the discontinuous film layer 107 may be formed by controlling the process parameters such as the rate of chemical vapor deposition, sputtering or spraying, the thickness of the discontinuous film layer 107, and the like.

In some examples, the material of the discontinuous film layer 107 includes one or more of magnesium (Mg), strontium (Sr), or aluminum (Al).

It should be appreciated that to ensure that the discontinuous film layer 107 can be formed, the thickness of the discontinuous film layer 107 should not be too great, and in some examples the thickness h of the discontinuous film layer 107 is in the range of 0 < h.ltoreq.8 nm.

For example, the thickness h of the discontinuous film layer 107 may be 1nm, 3nm, 5nm, 8nm, or the like.

As shown in fig. 13, the discontinuous thin film layer 107 is oxidized to form an insulating material layer 1011.

By way of example, the material of the insulating material layer 1011 may be one or more of magnesium oxide, strontium oxide, or aluminum oxide.

It is understood that the insulating material layer 1011 formed in step S102, in this case, the defect in the insulating material layer 1011 may or may not penetrate the insulating material layer 1011. Illustratively, the material of the insulating material layer 1011 is a polycrystalline material, and defects within the insulating material layer 1011 include grain boundaries. In this case, the plurality of grain boundaries of the insulating material layer 1011 may penetrate the insulating material layer 1011 or may not penetrate the insulating material layer 1011.

Further, in some examples, the insulating material layer 1011 formed after the oxidation treatment of the discontinuous thin film layer 107 is continuous.

S103, as shown in FIG. 13, a phase change material layer 102 is formed on the insulating material layer 1011

It should be noted that, step S103 may refer to step S12, which is not described herein.

S104, as shown in fig. 13, a first electrode 103 is formed on the phase change material layer 102.

It should be noted that, the step S104 may refer to the above step S13, and will not be described herein.

S105, as shown in fig. 13, a current is applied to the insulating material layer 1011 to initialize, and a defect in the insulating material layer 1011 forms a conductive path 1012 through the insulating material layer 1011 to form the heating electrode 101. Wherein the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive channels 1012 formed of defects disposed within the insulating material layer 1011; the conductive via 1012 is in contact with the phase change material layer 102, and the conductive via 1012 is electrically connected with the second electrode 104.

In some examples, the material of insulating material layer 1011 is a polycrystalline material; the application of a current to the insulating material layer 1011 initiates the formation of conductive channels 1012 through the insulating material layer 1011 at grain boundaries of the polycrystalline material to form the heater electrode 101.

It should be understood that the initialization can be performed by applying a voltage to the first electrode 103 through the bit line BL, and a voltage to the second electrode 105 through the source line SL, thereby applying a current to the insulating material layer 1011. It will be appreciated that the current applied during the initialization of the insulating material layer 1011 should be relatively high so that defects in the insulating material layer 1011 may penetrate the insulating material layer 1011 and thereby form the conductive vias 1012.

Although the insulating material layer 1011 formed in step S102 includes defects such as grain boundaries, the defects such as grain boundaries may not penetrate the insulating material layer 1011, and after the insulating material layer 1011 is initialized by applying a current, the defects such as grain boundaries may penetrate the insulating material layer 1011, so that the conductive paths 1012 may be formed.

The dimensions L, the number of the conductive channels 1012 and the shape of the conductive channels 1012 can refer to the above step S14, and will not be described herein.

Based on the above, the insulating material layer 1011 can be formed by step S101 and step S102. In some examples, the insulating material layer 1011 may also be formed directly on the second electrode 104.

As can be seen from the above steps S100 to S105, in the first embodiment, the conductive channel 1012 formed by the defect is obtained, and the manufacturing process of the conductive channel 1012 is simple, so that the manufacturing cost of the phase change memory 10 can be reduced.

Example two

The difference between the second embodiment and the first embodiment is that the structure of the heating electrode 101 is different.

The structure of the memory element 100A provided in the second embodiment is as shown in fig. 14, and includes: a second electrode 104, a heating electrode 101, a phase change material layer 102, and a first electrode 103, which are sequentially stacked; the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive channels 1012 formed of defects disposed within the insulating material layer 1011, the conductive channels 1012 being in contact with the phase change material layer 102, and the conductive channels 1012 being electrically connected to the second electrode 104; the heater electrode 101 also includes a conductive discontinuous film layer 107; the discontinuous film layer 107 comprises a plurality of islands that are independent of each other; the discontinuous thin film layer 107 is located on a side of the conductive channel 1012 away from the phase change material layer 102, the insulating material layer 1011 spaces apart the plurality of islands in the discontinuous thin film layer 107, and the thickness of the insulating material layer 1011 is greater than the thickness of the discontinuous thin film layer 107; conductive channels 1012 contact islands in non-continuous film layer 107.

It should be noted that the islands in the discontinuous thin film layer 107 may be raised toward the side close to the phase change material layer 102 or may be raised toward the side far from the phase change material layer 102.

In addition, the material of the insulating material layer 1011 may refer to the first embodiment, and will not be described herein.

In some examples, the material of the discontinuous film layer 107 may include one or more of magnesium (Mg), platinum (pt), or aluminum (Al).

In some examples, the material of insulating material layer 1011 is an oxide of the material of discontinuous thin film layer 107, e.g., the material of insulating material layer 1011 is magnesium oxide and the material of discontinuous thin film layer 107 is magnesium. In other examples, the material of insulating material layer 1011 is an oxide of a metal other than the material of continuous thin film layer 107. For example, the material of the insulating material layer 1011 is tantalum oxide, and the material of the discontinuous thin film layer 107 is magnesium.

When the material of the insulating material layer 1011 is an oxide of the material of the discontinuous thin film layer 107, boundaries of islands in the discontinuous thin film layer 107 may not be clearly distinguished in the heater electrode 101. When the material of the insulating material layer 1011 is an oxide of a metal other than the material of the discontinuous thin film layer 107, boundaries of islands in the discontinuous thin film layer 107 can be distinguished in the heater electrode 101.

The second embodiment also provides a method for manufacturing the memory element 100A, for example, the method may be used for manufacturing the memory element 100A shown in fig. 14, and the method for manufacturing the memory element 100A, as shown in fig. 15, includes the following steps:

s200, as shown in fig. 16, the second electrode 104 is formed on the substrate 105.

It should be noted that, the step S200 may refer to the above step S10, and will not be described herein.

S201, as shown in fig. 16, forming a conductive discontinuous thin film layer 107 on the second electrode 104; the discontinuous film layer 107 comprises a plurality of islands that are independent of each other.

The material of the conductive discontinuous film layer 107 may be referred to above, and will not be described here.

In addition, the discontinuous thin film layer 107 may be formed by a chemical vapor deposition method, a sputtering method, a spraying method, or the like.

It will be appreciated that since the discontinuous film layer 107 is conductive, islands in the discontinuous film layer 107 are also conductive.

S202, as shown in fig. 16, an insulating material layer 1011 is formed on the discontinuous thin film layer 107; wherein the insulating material layer 1011 spaces apart the plurality of islands in the discontinuous film layer 107, the thickness of the insulating material layer 1011 is greater than the thickness of the discontinuous film layer 107.

Here, the material of the insulating material layer 1011 may be referred to above, and will not be described here again.

The insulating material layer 1011 may be formed by a chemical vapor deposition method, a sputtering method, a spraying method, or the like.

S203, as shown in fig. 16, the phase change material layer 102 is formed on the insulating material layer 1011.

It should be noted that, step S203 may refer to step S12, and will not be described herein.

S204, as shown in fig. 16, the first electrode 103 is formed on the phase change material layer 102.

It should be noted that, step S204 may refer to step S13, and will not be described herein.

S205, as shown in fig. 16, applying a current to the discontinuous thin film layer 107 and the insulating material layer 1011 to initialize, and forming a conductive path 1012 formed of a defect in the insulating material layer 1011 by the island-shaped tip discharge breakdown of the insulating material layer 1011 to form the heating electrode 101; conductive channels 1012 are in contact with islands in non-continuous thin film layer 107 and with phase change material layer 102.

It will be appreciated that when the island tip discharges break through the insulating material layer 1011, defects may form in the insulating material layer 1011, which may constitute conductive channels 1012.

It should be appreciated that a voltage may be applied to the first electrode 103 through the bit line BL and a voltage may be applied to the second electrode 105 through the source line SL, thereby initializing the application of current to the discontinuous thin film layer 107 and the insulating material layer 1011 to cause the island tip discharge to break down the insulating material layer 1011 to form the conductive channel 1012. To ensure that the island tip discharge can break down the insulating material layer 1011, the applied current should be large.

It will be appreciated that the top of the island is prone to breakdown of the insulating material layer 1011 forming the conductive channel 1012 due to the small distance of the top of the island from the surface of the insulating material layer 1011 away from the second electrode 104.

Here, the island may be protruded to a side close to the phase change material layer 102 or may be protruded to a side far from the phase change material layer 102. In the case where the island protrudes to the side close to the phase change material layer 102, the tip of the island is more likely to discharge to break down the insulating material layer 1011, forming the conductive channel 1012.

In the second embodiment, since the conductive channels 1012 are formed by the island-shaped tip discharge breakdown of the insulating material layer 1011 in the discontinuous thin film layer 107, the conductive channels 1012 formed by the defects have a very small dimension L of about several nanometers in each direction perpendicular to the stacking direction Z of the memory element 100A, so that the contact area between the conductive channels 1012 and the phase change material layer 102 in the heating electrode 101 is very small, the volume of the phase change region in the phase change material layer 102 is small, and the current density is high, thereby reducing the power consumption while increasing the phase change speed of the phase change material layer 102.

On this basis, in the second embodiment, the conductive channel 1012 formed by the defect is obtained, and meanwhile, the manufacturing process of the conductive channel 1012 is simple, so that the manufacturing cost of the phase change memory 10 can be reduced.

Example III

The difference between the third embodiment and the first and second embodiments is that the structure of the heating electrode 101 is different.

The structure of the memory element 100A provided in the second embodiment is as shown in fig. 17, and includes: a second electrode 104, a heating electrode 101, a phase change material layer 102, and a first electrode 103, which are sequentially stacked; the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive channels 1012 formed of defects disposed within the insulating material layer 1011, the conductive channels 1012 being in contact with the phase change material layer 102, and the conductive channels 1012 being electrically connected to the second electrode 104; the heater electrode 101 also includes an insulating discontinuous film layer 107; the discontinuous film layer 107 comprises a plurality of islands that are independent of each other; the discontinuous thin film layer 107 is located on a side of the insulating material layer 1011 remote from the phase change material layer 102, the insulating material layer 1011 spacing apart the plurality of islands in the discontinuous thin film layer 107; wherein the conductive channels 1012 are located between the islands, the conductive channels 1012 penetrating the insulating material layer 1011, the resistivity of the discontinuous thin film layer 107 being greater than the resistivity of the insulating material layer 1011.

Since the resistivity of the discontinuous thin film layer 107 is greater than the resistivity of the insulating material layer 1011, the insulating properties of the discontinuous thin film layer 107 are better than those of the insulating material layer 1011.

Here, the thickness of the insulating material layer 1011 may be greater than or equal to the thickness of the discontinuous thin film layer 107.

In some examples, the material of the discontinuous thin film layer 107 and the insulating material layer 1011 may include one or more of tantalum oxide, titanium oxide, magnesium oxide, aluminum oxide, strontium oxide, or hafnium oxide.

The third embodiment also provides a method for manufacturing the memory device 100A, and the method for manufacturing the memory device 100A provided in the third embodiment is similar to the method for manufacturing the memory cell 100A provided in the second embodiment, except for steps S201, S202 and S205.

In the third embodiment, the step S201 in the second embodiment may be replaced with the step S300, the step S202 in the second embodiment may be replaced with the step S301, the step S205 in the second embodiment may be replaced with the step S302, and the other steps are the same.

S300, forming an insulating discontinuous film layer 107 on the second electrode 104; the discontinuous film layer 107 comprises a plurality of islands that are independent of each other.

The material of the insulating discontinuous film layer 107 may be referred to above, and will not be described here.

Further, the formation method, thickness, and the like of the discontinuous film layer 107 can be referred to the above-described step S201.

The discontinuous thin film layer 107 formed in step S201 is conductive, and the discontinuous thin film layer 107 formed in step S300 is insulating.

S301, forming an insulating material layer 1011 on the discontinuous film layer 107; wherein the insulating material layer 1011 spaces apart the plurality of islands in the discontinuous film layer 107; the resistivity of the discontinuous film layer 107 is greater than the resistivity of the insulating material layer 1011.

In addition, the material of the insulating material layer 1011 may be referred to above, and will not be described here. The method for forming the insulating material layer 1011 may refer to step S202, which is not described herein.

In step S202, since the discontinuous thin film layer 107 is conductive, the resistivity of the insulating material layer 1011 is greater than the resistivity of the discontinuous thin film layer 107, and in step S301, the resistivity of the discontinuous thin film layer 107 is greater than the resistivity of the insulating material layer 1011.

S302, as shown in fig. 17, a current is applied to the discontinuous thin film layer 107 and the insulating material layer 1011 to initialize, and a portion of the second electrode 104 located between the islands discharges to break down the insulating material layer 1011, so that a conductive channel 1012 composed of defects is formed in the insulating material layer 1011, and the conductive channel 1012 penetrates the insulating material layer 1011 to form the heating electrode 101.

It will be appreciated that when the partial discharge of the second electrode 104 between the islands breaks down the insulating material layer 1011, defects may form in the insulating material layer 1011, which may constitute conductive channels 1012.

It should be appreciated that a voltage may be applied to the first electrode 103 through the bit line BL and a voltage may be applied to the second electrode 105 through the source line SL, thereby initializing the application of current to the discontinuous thin film layer 107 and the insulating material layer 1011 such that a partial discharge of the second electrode 104 between islands breaks down the insulating material layer 1011, forming conductive channels 1012 within the insulating material layer 1011. In order to ensure that the partial discharge of the second electrode 104 between the islands breaks down the insulating material layer 1011, the applied current should be large.

It should be noted that, since the resistivity of the discontinuous thin film layer 107 is greater than the resistivity of the insulating material layer 1011, when a current is applied, the portion of the second electrode 104 located between the islands tends to discharge and break down the insulating material layer 1011 to form the conductive channel 1012.

In the third embodiment, since the conductive channel 1012 is formed by the partial discharge breakdown of the insulating material layer 1011 between the islands of the second electrode 104, the conductive channel 1012 formed by the defect has a very small dimension L of about several nanometers along each direction perpendicular to the stacking direction Z of the memory element 100A, so that the contact area between the conductive channel 1012 and the phase change material layer 102 in the heating electrode 101 is very small, the volume of the phase change region in the phase change material layer 102 is small, the current density is high, and the phase change speed of the phase change material layer 102 is increased while the power consumption is reduced.

On this basis, the third embodiment can reduce the manufacturing cost of the phase change memory 10 due to the simple manufacturing process of the conductive channel 1012 while obtaining the conductive channel 1012 composed of defects.

Example IV

The difference between the fourth embodiment and the first, second and third embodiments is that the structure of the heating electrode 101 is different.

The structure of the memory element 100A provided in the fourth embodiment is as shown in fig. 18, and includes: a second electrode 104, a heating electrode 101, a phase change material layer 102, and a first electrode 103, which are sequentially stacked; the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive channels 1012 formed of defects disposed within the insulating material layer 1011, the conductive channels 1012 being in contact with the phase change material layer 102, and the conductive channels 1012 being electrically connected to the second electrode 104; the heating electrode 101 further comprises a conductive layer 108 arranged on the side of the insulating material layer 1011 remote from the phase change material layer 102; the crystal structure of the material of the conductive layer 108 is columnar crystals; wherein the conductive channels 1012 are in contact with the ends of the columnar crystals.

It should be understood that, since the crystal structure of the material of the conductive layer 108 is columnar crystals and the insulating material layer 1011 is provided on the conductive layer 108, when the insulating material layer 1011 is formed on the conductive layer 108, referring to fig. 18, the insulating material in the insulating material layer 1011 is filled between the columnar crystals of the conductive layer 108.

The growth direction of the columnar crystals is the same as the lamination direction Z of the plurality of layers in the memory element 100A.

Here, the type, size, material of the insulating material layer 1011, and the like of the defect may be referred to above, and will not be described here.

In some examples, the material of the conductive layer 108 includes titanium nitride (TiN). The crystal structure of titanium nitride is columnar crystal.

The fourth embodiment also provides a method for manufacturing the memory element 100A, for example, the method may be used for manufacturing the memory element 100A shown in fig. 18, and the method for manufacturing the memory element 100A, as shown in fig. 19, includes the following steps:

s400, as shown in fig. 20, the second electrode 104 is formed on the substrate 105.

It should be noted that, the step S400 may refer to the above step S10, and will not be described herein.

S401, as shown in fig. 20, forming a conductive layer 108 on the second electrode 104; the crystal structure of the material of the conductive layer 108 is columnar crystals.

In some examples, the material of the conductive layer 108 includes titanium nitride.

Here, the conductive layer 108 may be formed by growth using a physical vapor deposition method, for example.

As shown in fig. 20, an insulating material layer 1011 is formed on the conductive layer 108.

It will be appreciated that since the crystal structure of the material of the conductive layer 108 is columnar crystals, when the insulating material layer 1011 is formed, the insulating material in the insulating material layer 1011 fills between the columnar crystals of the conductive layer 108.

S403, as shown in fig. 20, the phase change material layer 102 is formed on the insulating material layer 1011.

It should be noted that, step S403 may refer to step S12, and will not be described herein.

S404, as shown in fig. 20, the first electrode 103 is formed on the phase change material layer 102.

It should be noted that, step S404 may refer to step S13, and will not be described herein.

S405, as shown in fig. 20, applying a current to the conductive layer 108 and the insulating material layer 1011 to initialize, and the tip discharge of the columnar crystal breaks down the insulating material layer 1011, forming a conductive channel 1012 composed of defects in the insulating material layer 1011 to form a heating electrode 101; wherein the conductive channels 1012 are in contact with the ends of the columnar crystals.

It will be appreciated that when the tip discharge of the columnar crystals breaks down the insulating material layer 1011, defects may form in the insulating material layer 1011, which may constitute the conductive channels 1012.

Since the crystal structure of the conductive layer 108 is columnar crystals, the tips of the columnar crystals discharge when a current is applied to the conductive layer 108.

It should be appreciated that a voltage may be applied to the first electrode 103 through the bit line BL and a voltage may be applied to the second electrode 105 through the source line SL, thereby applying a current to the conductive layer 108 and the insulating material layer 1011 for initialization so that the tip discharge of the columnar crystal breaks down the insulating material layer 1011 to form the conductive channel 1012. In order to ensure that the tip discharge of the columnar crystals can break down the insulating material layer 1011, the applied current should be large.

In the fourth embodiment, since the conductive channel 1012 is formed by breaking down the insulating material layer 1011 by the tip discharge of the columnar crystal, the size L of the conductive channel 1012 formed by the defect is very small, about several nanometers, in each direction perpendicular to the stacking direction Z of the memory element 100A, so that the contact area between the conductive channel 1012 and the phase change material layer 102 in the heating electrode 101 is very small, the volume of the phase change region in the phase change material layer 102 is small, and the current density is high, so that the phase change speed of the phase change material layer 102 can be increased while the power consumption can be reduced.

On this basis, the fourth embodiment can reduce the manufacturing cost of the phase change memory 10 due to the simple manufacturing process of the conductive channel 1012 while obtaining the conductive channel composed of the defects.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A phase change memory comprising a plurality of memory cells distributed in an array, the memory cells comprising: the heating electrode, the phase change material layer and the first electrode are sequentially stacked;

the heating electrode comprises an insulating material layer and a plurality of conductive channels which are arranged in the insulating material layer and are formed by defects, and the conductive channels are in contact with the phase change material layer.
The phase change memory of claim 1, wherein the conductive channel extends through the layer of insulating material.
The phase change memory according to claim 2, wherein the material of the insulating material layer is a polycrystalline material, and the defect comprises a grain boundary of the polycrystalline material.
The phase change memory of claim 1, wherein the heating electrode further comprises a conductive discontinuous thin film layer; the discontinuous film layer comprises a plurality of mutually independent islands;

The discontinuous thin film layer is positioned on one side of the conductive channel away from the phase change material layer, the insulating material layer is used for spacing a plurality of islands in the discontinuous thin film layer, and the thickness of the insulating material layer is larger than that of the discontinuous thin film layer;

wherein the conductive via is in contact with the island in the discontinuous film layer.
The phase change memory of claim 4, wherein the material of the discontinuous thin film layer comprises one or more of magnesium, platinum, or aluminum.
The phase change memory according to claim 1, wherein the heating electrode further comprises an insulating discontinuous thin film layer; the discontinuous film layer comprises a plurality of mutually independent islands;

the discontinuous thin film layer is positioned on one side of the insulating material layer away from the phase change material layer, and the insulating material layer spaces the islands in the discontinuous thin film layer;

wherein the conductive channels are located between the islands, the conductive channels extend through the insulating material layer, and the resistivity of the discontinuous film layer is greater than that of the insulating material layer.
The phase change memory according to claim 1, wherein the heating electrode further comprises a conductive layer disposed on a side of the insulating material layer remote from the phase change material layer; the crystal structure of the material of the conductive layer is columnar crystal;

Wherein the conductive channel is in contact with an end of the columnar crystal.
The phase change memory according to claim 7, wherein the material of the conductive layer comprises titanium nitride.
The phase change memory according to any of claims 1-8, wherein the material of the insulating material layer comprises one or more of magnesium oxide, strontium oxide, aluminum oxide, hafnium oxide, titanium oxide or tantalum oxide.
The phase change memory according to any one of claims 1-9, wherein the memory cell further comprises a second electrode arranged on a side of the heating electrode remote from the phase change material layer;

wherein the conductive channel is electrically connected with the second electrode.
The phase change memory according to any of claims 1-10, further comprising: bit lines, word lines, and source lines;

the memory cell further includes: a gating device; a first electrode of the gating device is electrically connected with the heating electrode, and a second electrode of the gating device is electrically connected with the source line; a third electrode of the gating device is electrically connected to the word line,

the first electrode of the memory cell is electrically connected to the bit line.
An electronic device comprising a printed circuit board and a phase change memory electrically connected to the printed circuit board, wherein the phase change memory is a phase change memory as claimed in any one of claims 1-11.
A method of fabricating a phase change memory, comprising: forming a plurality of gate devices distributed in an array on a substrate;

forming a plurality of memory elements distributed in an array on the substrate; the storage elements are electrically connected with the gating devices in a one-to-one correspondence manner;

the manufacturing method of any one of the memory elements comprises the following steps:

forming an auxiliary layer on the substrate;

forming a phase change material layer on the auxiliary layer;

forming a first electrode on the phase change material layer;

applying current to the auxiliary layer for initialization to form a heating electrode; wherein the heating electrode comprises an insulating material layer and a plurality of conductive channels which are arranged in the insulating material layer and are formed by defects; the conductive via is in contact with the phase change material layer.
The method of claim 13, wherein forming an auxiliary layer on the substrate comprises: forming a layer of insulating material on the substrate;

The initializing the application of current to the auxiliary layer to form a heating electrode comprises the following steps: and applying current to the insulating material layer for initialization, wherein defects in the insulating material layer penetrate through the insulating material layer to form the conductive channels so as to form the heating electrode.
The method of claim 14, wherein the material of the insulating material layer is a polycrystalline material;

the initializing the application of current to the auxiliary layer to form a heating electrode comprises the following steps: and applying current to the insulating material layer for initialization, wherein grain boundaries of the polycrystalline material penetrate through the insulating material layer to form the conductive channels so as to form the heating electrode.
The method of claim 14 or 15, wherein forming a layer of insulating material on the substrate comprises:

forming a discontinuous thin film layer on the substrate; the discontinuous film layer comprises a plurality of mutually independent islands;

and oxidizing the discontinuous film layer to form an insulating material layer.
The method of claim 13, wherein forming an auxiliary layer on the substrate comprises:

Forming a conductive layer on the substrate; the crystal structure of the material of the conductive layer is columnar crystal;

forming an insulating material layer on the conductive layer;

the initializing the application of current to the auxiliary layer to form a heating electrode comprises the following steps: applying a current to the conductive layer and the insulating material layer for initialization, wherein the tip discharge of the columnar crystal breaks down the insulating material layer, and the conductive channel is formed in the insulating material layer so as to form the heating electrode; wherein the conductive channel is in contact with an end of the columnar crystal.
The method of claim 13, wherein forming an auxiliary layer on the substrate comprises: forming a conductive discontinuous film layer on the substrate; the discontinuous film layer comprises a plurality of mutually independent islands;

forming a layer of insulating material over the discontinuous film layer; wherein the insulating material layer separates a plurality of the islands in the discontinuous film layer, the insulating material layer having a thickness greater than a thickness of the discontinuous film layer;

the initializing the application of current to the auxiliary layer to form a heating electrode comprises the following steps: initializing the discontinuous film layer and the insulating material layer by applying current, wherein the island tip discharge breaks down the insulating material layer, and a conductive channel is formed in the insulating material layer to form the heating electrode; wherein the conductive channels are in contact with the islands in the discontinuous film.
The method of any one of claims 13-18, wherein the method of fabricating any one of the memory elements further comprises, prior to forming an auxiliary layer on the substrate:

forming a second electrode on the substrate; the conductive channel in the heating electrode is electrically connected with the second electrode.
The method of claim 19, wherein forming an auxiliary layer on the substrate comprises: forming an insulating discontinuous thin film layer on the substrate; the discontinuous film layer comprises a plurality of mutually independent islands;

forming a layer of insulating material over the discontinuous film layer; wherein the insulating material layer spaces apart a plurality of the islands in the discontinuous film layer; the resistivity of the discontinuous film layer is greater than the resistivity of the insulating material layer;

the initializing the application of current to the auxiliary layer to form a heating electrode comprises the following steps: and applying a current to the discontinuous film layer and the insulating material layer for initialization, wherein partial discharge of the second electrode between the islands breaks through the insulating material layer, and conductive channels are formed in the insulating material layer and penetrate through the insulating material layer to form the heating electrode.