CN116884997B - Insulated gate bipolar transistor and preparation method thereof - Google Patents
Insulated gate bipolar transistor and preparation method thereof Download PDFInfo
- Publication number
- CN116884997B CN116884997B CN202311149652.7A CN202311149652A CN116884997B CN 116884997 B CN116884997 B CN 116884997B CN 202311149652 A CN202311149652 A CN 202311149652A CN 116884997 B CN116884997 B CN 116884997B
- Authority
- CN
- China
- Prior art keywords
- layer
- doping
- doped
- drift
- sub
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 claims description 41
- 239000000758 substrate Substances 0.000 claims description 35
- 238000004519 manufacturing process Methods 0.000 claims description 26
- 238000005468 ion implantation Methods 0.000 claims description 22
- 125000006850 spacer group Chemical group 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 14
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 description 20
- 239000000463 material Substances 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 238000000407 epitaxy Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000004377 microelectronic Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
The application provides an insulated gate bipolar transistor and a preparation method thereof. The insulated gate bipolar transistor structure includes: a collector layer having a first doping type; the drift layer is arranged on one side of the current collection layer and is provided with a second doping type; the grid structure is arranged on one side of the drift layer, which is far away from the collector layer; the first doping layer is arranged on one side of the drift layer, far away from the collector layer, and comprises a first part and a second part, a first interval region is arranged between the first part and the second part, the first interval region is positioned on one side of the grid structure, close to the drift layer, and the first doping layer is of a first doping type; the projection of the second doping layer on the first doping layer is positioned at two sides of the first interval region and is respectively in contact with the grid structure and the first doping layer, and the second doping layer has a second doping type; the emission layer is arranged on one side of the first doping layer far away from the drift layer in a contact mode, and the emission layer is provided with a first doping type.
Description
Technical Field
The application relates to the field of power semiconductor devices, in particular to an insulated gate bipolar transistor and a preparation method thereof.
Background
Currently, with the development of microelectronic devices in the directions of low power consumption, high voltage resistance and high reliability, the requirements for semiconductor materials are gradually increasing. Microelectronic devices are increasingly applied in special environments such as high temperature, high irradiation, high frequency and high power, but for example, the traditional process flow of the IGBT in the prior art is more complex, high-temperature ion implantation equipment is needed, other structures in the period of influence can be damaged during ion implantation, the performance of the devices is further influenced, and the production cost is high; the epitaxy structure mostly adopts an independent epitaxy scheme, the epitaxy process and the structure are complex and difficult to manufacture, and most of the epitaxy structure is not optimized in the aspect of structure, so that in order to meet the application of the microelectronic device in the fields of high temperature resistance, irradiation resistance and the like, new semiconductor materials need to be developed, and the performance of the microelectronic device is improved to the greatest extent.
Disclosure of Invention
The application provides an insulated gate bipolar transistor and a preparation method thereof, which are used for solving the problems of complex process flow, lower device performance and high manufacturing cost of the insulated gate bipolar transistor in the related technology.
According to one aspect of the present application, there is provided an insulated gate bipolar transistor comprising: a collector layer having a first doping type; the drift layer is arranged on one side of the current collection layer and is provided with a second doping type; the grid structure is arranged on one side of the drift layer, which is far away from the collector layer; the first doping layer is arranged on one side of the drift layer, far away from the collector layer, and comprises a first part and a second part, a first interval region is arranged between the first part and the second part, the first interval region is positioned on one side of the grid structure, close to the drift layer, and the first doping layer is of a first doping type; the projection of the second doping layer on the first doping layer is positioned at two sides of the first interval region and is respectively in contact with the grid structure and the first doping layer, and the second doping layer has a second doping type; the emission layer is arranged on one side of the first doping layer far away from the drift layer in a contact mode, and the emission layer is provided with a first doping type.
Optionally, the first doped layer includes: the first sub-doping layer is arranged on one side surface of the drift layer, which is far away from the collector layer, in a contact manner, and is divided into two parts by a first interval region; the second sub-doping layer is arranged on one side, far away from the drift layer, of the first sub-doping layer in a contact mode, and the second sub-doping layer is respectively in contact with the second doping layer and the emitting layer.
Optionally, the insulated gate bipolar transistor further comprises: and the third doping layer is arranged in the first interval region and is in contact with the drift layer, and the third doping layer has a second doping type.
Optionally, the doping concentration of the second doping layer is greater than the doping concentration of the third doping layer, and the doping concentration of the third doping layer is greater than the doping concentration of the drift layer.
Optionally, the doping concentration of the emissive layer is greater than the doping concentration of the first doping layer.
Optionally, the gate structure includes a gate and a gate oxide layer, the gate oxide layer is located between the gate and the third doped layer, the gate has a second doping type, and a doping concentration of the gate is greater than a doping concentration of the third doped layer.
According to another aspect of the present application, there is provided a method for manufacturing an insulated gate bipolar transistor, including the steps of: providing a drift layer on the substrate, wherein the drift layer has a second doping type; a first doping layer is arranged on one side of the drift layer, which is far away from the substrate, so that the first doping layer comprises a first part and a second part, a first interval region is arranged between the first part and the second part, the first interval region is positioned on one side of the grid structure, which is close to the drift layer, and the first doping layer is provided with a first doping type; an emitting layer is arranged on one side of the first doping layer far away from the drift layer, and the emitting layer has a first doping type; forming a second doping layer in contact with the first doping layer at one side of the drift layer far away from the substrate, wherein the projection of the second doping layer on the first doping layer is positioned at two sides of the first interval region, and the second doping layer is of a second doping type; a grid structure is arranged on one side of the first interval region, which is far away from the drift layer, so that the grid structure is in contact with the second doped layer; and the side of the drift layer far away from the first doping layer is provided with an exposed surface, and the collector layer is arranged on the side of the drift layer with the exposed surface.
Optionally, the preparation method further includes a step of forming a third doped layer, wherein the third doped layer is disposed in the first spacer region and contacts the drift layer, and the third doped layer has the second doping type.
The step of forming the first doped layer and the third doped layer includes: forming a first sub-doping preparation layer on a first surface of the drift layer; etching the first sub-doping preparation layer to form a first sub-doping layer with a first interval region, wherein the first sub-doping layer is divided into two parts by the first interval region; forming a third doped layer covering the drift layer in the first spacer region; forming a second doping preparation layer on the surfaces of the first sub-doping layer and the third doping layer; etching the second doping preparation layer to form a second interval region penetrating to the first sub-doping layer, wherein the projection of the second interval region on the first sub-doping layer is positioned at two sides of the third doping layer; and forming a second sub-doping layer covering the first sub-doping layer in the second interval region, wherein the first sub-doping layer and the second sub-doping layer form a first doping layer.
Optionally, the step of forming the emission layer and the second doped layer includes: forming a preliminary emission layer on the surfaces of the second doping preliminary layer and the second sub-doping layer; the preliminary emitter layer and the second doping preliminary layer are sequentially etched to form an emitter layer and a second doping layer.
Optionally, the step of forming the gate structure includes: a gate oxide layer is arranged on the exposed surfaces of the third doped layer and the second doped layer in a contact manner; and a grid electrode is arranged on the exposed surface of the grid oxide layer in a contact manner.
Through the technical scheme of this application, provide an insulated gate bipolar transistor, including collector layer, drift layer, gate structure, first doped layer, second doped layer and emitter layer, wherein: the collector layer has a first doping type; the drift layer is arranged on one side of the collector layer and has a second doping type; the grid structure is arranged on one side of the drift layer far away from the collector layer; the first doping layer is provided with a first doping type and is in contact with the side, far away from the collector layer, of the drift layer, and the first doping layer further comprises a first part and a second part, a first interval region is arranged between the first part and the second part, and the first interval region is positioned on one side, close to the drift layer, of the gate structure; the second doping layer is provided with a second doping type, and projections on the first doping layer are positioned on two sides of the first interval region and are respectively in contact with the grid structure and the first doping layer; a second doping layer is closely abutted against the grid structure to form a conducting channel with a certain resistance, when voltage is applied to the device, current flows along the conducting channel and voltage drop is generated, and the reverse voltage-withstanding function is achieved; the emission layer has a first doping type and is contacted with one side of the first doping layer far away from the drift layer. Because the collector layer, the drift layer, the gate structure, the first doping layer, the second doping layer and the emission layer in the insulated gate bipolar transistor are all epitaxial layers, the insulated gate bipolar transistor is different from a doping region formed by ion implantation in the traditional process of an IGBT, the influence on other epitaxial structures in the ion implantation process is avoided, and the device performance is improved; in addition, if the thinning step is needed after the epitaxial layer is formed by ion implantation in the traditional IGBT process, the formed epitaxial layer needs to be protected to be thinned, and the insulated gate bipolar transistor can be thinned directly in the epitaxial preparation stage, so that the step of protecting the epitaxial layer formed after ion implantation and then thinning is omitted, the manufacturing flow of the insulated gate bipolar transistor is simplified, and the production and manufacturing cost is reduced because special implantation equipment is not needed.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application, illustrate and explain the application and are not to be construed as limiting the application. In the drawings:
fig. 1 is a schematic cross-sectional view showing an insulated gate bipolar transistor provided in an embodiment of the present application;
fig. 2 is a schematic flow chart of a method for manufacturing an insulated gate bipolar transistor according to an embodiment of the present application;
fig. 3 is a cross-sectional view showing a structure of a substrate after forming a drift layer on a substrate in a method for manufacturing an insulated gate bipolar transistor according to an embodiment of the present application;
FIG. 4 shows a schematic cross-sectional view of the substrate after forming a first sub-doping preparation layer on the drift layer formed in FIG. 3;
FIG. 5 is a schematic cross-sectional view of the substrate after etching the first sub-doping preparation layer formed in FIG. 4 to form a first spacer region;
FIG. 6 shows a schematic cross-sectional view of the substrate after formation of a third doping preparation layer in the first spacer region formed in FIG. 5;
FIG. 7 is a schematic cross-sectional view of the substrate after thinning the third doped preparation layer formed in FIG. 6 to form a third doped layer;
FIG. 8 shows a schematic cross-sectional view of the substrate after forming a second doping preparation layer on the third doping layer formed in FIG. 7;
FIG. 9 is a schematic cross-sectional view of the substrate after etching the second doping preparation layer formed in FIG. 8 to form a second spacer region;
FIG. 10 shows a schematic cross-sectional view of the substrate after forming a second sub-doping preparation layer in the second spacer region formed in FIG. 9;
FIG. 11 is a schematic cross-sectional view of the substrate after thinning the second sub-doped preparation layer formed in FIG. 10 to form a second sub-doped layer;
FIG. 12 shows a schematic cross-sectional view of the substrate after forming a preliminary emissive layer on the second sub-doped layer formed in FIG. 11;
FIG. 13 is a schematic cross-sectional view of the substrate after etching the preliminary emitter layer formed in FIG. 12 and the second doped preliminary layer formed in FIG. 8 in sequence to form an emitter layer and a second doped layer;
FIG. 14 shows a schematic cross-sectional view of the substrate after removal of the substrate after the step of forming the emissive layer and the second doped layer of FIG. 13;
fig. 15 shows a schematic cross-sectional view of the substrate after forming a buffer layer and a collector layer on the surface of the removed substrate of fig. 14.
Wherein the above figures include the following reference numerals:
10. a drift layer; 20. a first doped layer; 201. a first sub-doped layer; 2010. a first sub-doping preparation layer; 202. a second sub-doped layer; 2020. a second sub-doping preparation layer; 30. a third doped layer; 301. a third doping preparation layer; 40. a second doped layer; 401. a second doping preparation layer; 50. an emissive layer; 501. preparing an emission layer; 60. a buffer layer; 70. a current collecting layer; 80. a gate structure; 801. a gate oxide layer; 802. a gate; 901. an emitter; 902. An electrode layer; 903. a collector electrode; 100. an insulating layer; 110. a substrate.
Detailed Description
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the present application described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Because the traditional technical process of the IGBT in the prior art is complex, high-temperature ion implantation equipment is needed, other structures in the influence period can be damaged during ion implantation, the performance of the device is further influenced, and the production cost is high; the epitaxy structure mostly adopts an independent epitaxy scheme, the epitaxy process and the structure are complex, the manufacture is not easy, and the structure is not optimized in most aspects.
Accordingly, the inventors studied on the above problems and proposed an insulated gate bipolar transistor, as shown in fig. 1, comprising a collector layer 70, a drift layer 10, a gate structure 80, a first doped layer 20, a second doped layer 40 and an emitter layer 50, wherein: the collector layer 70 has a first doping type, the drift layer 10 is disposed on one side of the collector layer 70 and has a second doping type, the gate structure 80 is disposed on one side of the drift layer 10 away from the collector layer 70, the first doping layer 20 has a first doping type, the contact is disposed on one side of the drift layer 10 away from the collector layer 70, the first doping layer 20 includes a first portion and a second portion, a first spacing region is disposed between the first portion and the second portion, the first spacing region is disposed on one side of the gate structure 80 close to the drift layer 10, the second doping layer 40 has a second doping type, the projection on the first doping layer 20 is disposed on two sides of the first spacing region and is respectively in contact with the gate structure 80 and the first doping layer 20, and the emitter layer 50 has the first doping type and is disposed on one side of the first doping layer 20 away from the drift layer 10.
According to the insulated gate bipolar transistor, the second doped layer 40 is tightly abutted against the gate structure 80 to form a conductive channel with a certain resistance, when voltage is applied to the device, current flows along the conductive channel and generates voltage drop, the effect of reverse voltage resistance is achieved, and the collector layer 70, the drift layer 10, the gate structure 80, the first doped layer 20, the second doped layer 40 and the emission layer 50 in the insulated gate bipolar transistor are all epitaxial layers, so that the insulated gate bipolar transistor is different from a doped region formed by ion implantation in the traditional process of an IGBT, the influence on other epitaxial structures in the ion implantation process is avoided, and the device performance is improved; in addition, if the thinning step is needed after the epitaxial layer is formed by ion implantation in the traditional IGBT process, the formed epitaxial layer needs to be protected to be thinned, and the thinning can be directly performed in the epitaxial preparation stage in the insulated gate bipolar transistor in the application, so that the step of protecting the epitaxial layer formed after ion implantation and then thinning is omitted, the manufacturing flow of the insulated gate bipolar transistor is simplified, and the production and manufacturing cost is reduced because special implantation equipment is not needed.
The first doping type may be P-type, the second doping type may be N-type, and the collector layer 70, the first doping layer 20 and the emitter layer 50 may be P-type semiconductor layers, and the drift layer 10 and the second doping layer 40 may be N-type semiconductor layers.
In some alternative embodiments, the exposed surface of the collector layer 70 is further covered with a collector 903, where the collector 903 may be a metal layer; the exposed surface of the emission layer 50 is further covered with an emitter 901, and the emitter 901 may be a metal layer; the exposed surface of the gate structure 80 is further covered with an electrode layer 902, and the electrode layer 902 may be a metal layer. The metal layer on the exposed surface of the emitter layer 50 is an emitter 901, also called a source of an insulated gate bipolar transistor, and a drift region may be provided in the drift layer 10, and the drift region corresponds to a drain region of a Metal Oxide Semiconductor (MOS) transistor, since the IGBT is equivalent to an insulated gate field effect transistor (MOS transistor) and a bipolar transistor (BJT). The epitaxial layer region with the same doping type between the emitter layer 50 and the collector layer 70 is a sub-channel region of the device, the collector layer 70 is a drain injector of the drift region (drain region), and the drain injector, the drain region and the sub-channel region together form a structure with three semiconductor layers, so that the effect of amplifying current can be generated, the collector layer 70 can conduct and modulate holes injected into the drain region, the resistance of the drain region is reduced, the device has lower on-state voltage under high voltage, and the on-state voltage of the device is further reduced.
In the above alternative embodiment, as shown in fig. 1, the insulated gate bipolar transistor may further be provided with a buffer layer 60 on a side of the drift layer 10 away from the first spacer region, so as to block expansion of the depletion layer of the device during forward blocking.
In some alternative embodiments, the epitaxial layer materials of the collector layer 70, the drift layer 10, the first doped layer 20, the second doped layer 40, and the emitter layer 50 are any one or more of Si, ga, siC, gaN, and the like, which are not specifically limited herein.
The doping elements of the epitaxial layers of the collector layer 70, the drift layer 10, the first doping layer 20, the second doping layer 40, and the emission layer 50 may be group V elements such as arsenic, phosphorus, bismuth, and the like; and may also be a group III element such as aluminum, gallium, indium, etc., and the present application is not particularly limited.
In some alternative embodiments of the present application, as shown in fig. 1, the first doped layer 20 includes a first sub-doped layer 201 and a second sub-doped layer 202, wherein: the first sub-doping layer 201 is arranged on one side surface of the drift layer 10 away from the collector layer 70 in a contact manner and is divided into two parts by a first interval region; the second sub-doping layer 202 is disposed in contact with a side of the first sub-doping layer 201 remote from the drift layer 10, and the second sub-doping layer 202 is in contact with the second doping layer 40 and the emission layer 50, respectively.
In the above alternative embodiment, the first sub-doped layer 201 and the second sub-doped layer 202 of the first doped layer 20 have the first doping type, and the contact between the second sub-doped layer 202 and the second doped layer 40 forms a structure with two semiconductor layers having different doping types, which can generate depletion effect and enhance the voltage endurance capability.
In some alternative embodiments of the present application, the insulated gate bipolar transistor further comprises a third doped layer 30, as shown in fig. 1. The third doped layer 30 is disposed in the first spacer region and contacts the drift layer 10, and has a second doping type.
In the above alternative embodiment, the third doped layer 30 with the second doping type is disposed in the first spacer region and contacts the first sub doped layer 201 with the first doping type to form a JFET region, and by adjusting the concentration of the epitaxial layer, the on-resistance can be directly adjusted, so that the threshold voltage is not affected, and the device performance is improved; since the present application does not employ conventional ion implantation during the formation of the JFET region, the impact on the semiconductor layer in the first doped layer 20 disposed thereat is avoided.
Illustratively, the third doped layer 30 is an N-type semiconductor layer, the first sub-doped layer 201 is a P-type semiconductor layer, and the third doped layer 30 is disposed in the first spacer region to contact the first sub-doped layer 201 to form a JFET region.
In some alternative embodiments of the present application, the doping concentration of the second doped layer 40 is greater than the doping concentration of the third doped layer 30, and the doping concentration of the third doped layer 30 is greater than the doping concentration of the drift layer 10.
In the above alternative embodiment, by setting the doping concentration relationship between the second doping layer 40, the third doping layer 30 and the three semiconductor layers of the drift layer 10, and the direction is that the doping concentration gradually decreases from the side away from the drift layer 10 to the direction of the drift layer 10, this concentration setting mode enhances the conduction modulation effect of the drift region and reduces the on-voltage drop of the device.
In some alternative embodiments of the present application, the doping concentration of the emissive layer 50 is greater than the doping concentration of the first doped layer 20.
In the above alternative embodiment, the doping concentration of the collector layer 70 may be close to that of the emitter layer 50, in other words, the emitter layer 50 having the first doping type and the collector layer 70 having the first doping type are located at two sides of the insulated gate bipolar transistor farthest from the drift layer 10 and are in contact with the metal layer, and the doping concentration is higher than that of the other semiconductor layers having the first doping type, so that ohmic contact may be formed with the outermost metal layer, so that an anti-blocking layer is formed between the metal layer and the emitter layer 50 and the collector layer 70, respectively, preventing the rectifying effect from being generated; the doping concentration of the first doping layer 20 is less than that of the emission layer 50 to reduce the resistance therebetween, enhancing the reverse withstand voltage capability of the region having the first doping type composed of the semiconductor layer having the first doping type between the emission layer 50 and the collector layer 70.
In some alternative embodiments of the present application, as shown in fig. 1, gate structure 80 includes a gate 802 and a gate oxide layer 801, gate oxide layer 801 being located between reduced gate 802 and third doped layer 30, gate 802 having a second doping type. Illustratively, the doping concentration of gate 802 is greater than the doping concentration of third doped layer 30.
In some alternative embodiments, the gate 802 is an N-type semiconductor layer, and the material of the gate 802 is an N-type polysilicon material, but is not limited to the above types, and those skilled in the art may reasonably select the type of gate and the type of gate material according to practical situations, which is not particularly limited in this application.
In the above-described alternative embodiment, the doping concentration of the gate electrode 802 is greater than that of the third doped layer 30, and the gate electrode 802 may form an ohmic contact when in contact with the outermost metal layer, so that an anti-blocking layer is formed between the metal layer and the gate electrode 802, preventing the occurrence of rectification.
In the above-mentioned insulated gate bipolar transistor of the embodiment of the present application, the doping concentration of each epitaxial layer may be 10 15 ~10 21 cm -3 The performance of the insulated gate bipolar transistor can be improved by meeting the above-mentioned doping concentration range, but it should be noted that, a person skilled in the art can reasonably select the doping concentration of the semiconductor layer according to the actual situation, and the embodiment of the application is not specifically limited.
As illustrated in fig. 1, the insulated gate bipolar transistor includes an emitter layer 50, a first doped layer 20, a second doped layer 40, a third doped layer 30, a gate structure 80, a drift layer 10, a buffer layer 60, and a collector layer 70, wherein the first doped layer 20 includes a first sub-doped layer 201 and a second sub-doped layer 202, and wherein: the first sub-doping layer 201 is arranged on one side surface of the drift layer 10 away from the collector layer 70 in a contact manner and is divided into two parts by a first interval region; the second sub-doped layer 202 is disposed on a side of the first sub-doped layer 201 away from the drift layer 10 in a contact manner, the second sub-doped layer 202 is respectively in contact with the second doped layer 40 and the emission layer 50, the third doped layer 30 is disposed in a first interval region in the first doped layer 20, the gate structure 80 is disposed on a side of the third doped layer 30 away from the drift layer 10, the gate structure 80 comprises a gate 802 and a gate oxide layer 801, the gate oxide layer 801 is disposed between the lowering gate 802 and the third doped layer 30, the second doped layer 40 is disposed between the first doped layer 20 and the gate structure 80, the emission layer 50 is disposed on a side of the first doped layer 20 away from the drift layer 10, the buffer layer 60 is disposed on a side of the drift layer 10 away from the first doped layer 20, and the collector layer 70 is disposed on a side of the buffer layer 60 away from the drift layer 10.
According to another embodiment of the present application, there is also provided a method for manufacturing an insulated gate bipolar transistor, as shown in fig. 2, including the steps of:
s1, arranging a drift layer on a substrate, wherein the drift layer has a second doping type;
s2, a first doping layer is arranged on one side, far away from the substrate, of the drift layer, so that the first doping layer comprises a first part and a second part, a first interval region is arranged between the first part and the second part, the first interval region is positioned on one side, close to the drift layer, of the gate structure, and the first doping layer is of a first doping type;
s3, arranging an emission layer on one side of the first doping layer far away from the drift layer, wherein the emission layer has a first doping type;
s4, forming a second doping layer in contact with the first doping layer on one side of the drift layer away from the substrate, wherein the projection of the second doping layer on the first doping layer is positioned on two sides of the first interval region, and the second doping layer is of a second doping type;
s5, arranging a grid structure on one side of the first interval region, which is far away from the drift layer, so that the grid structure is in contact with the second doped layer; and the side of the drift layer far away from the first doping layer is provided with an exposed surface, and the collector layer is arranged on the side of the drift layer with the exposed surface.
By the preparation method of the insulated gate bipolar transistor, the problems of complex process flow, lower device performance and high manufacturing cost of the insulated gate bipolar transistor in the related technology can be solved. When voltage is applied to the device, current flows along the conductive channel and generates voltage drop, so that the reverse voltage resistance is realized, and the collector layer, the drift layer, the gate structure, the first doped layer, the second doped layer and the emission layer in the insulated gate bipolar transistor are formed by adopting an epitaxial process, so that the insulated gate bipolar transistor is different from a doped region formed by ion implantation in the traditional process of an IGBT, the influence on other epitaxial structures in the ion implantation process is avoided, and the performance of the device is improved; in addition, if the thinning step is needed after the epitaxial layer is formed by ion implantation in the traditional IGBT process, the formed epitaxial layer needs to be protected to be thinned, and the insulated gate bipolar transistor can be thinned directly in the epitaxial preparation stage, so that the step of protecting the epitaxial layer formed after ion implantation and then thinning is omitted, the manufacturing flow of the insulated gate bipolar transistor is simplified, and the production and manufacturing cost is reduced because special implantation equipment is not needed.
Exemplary embodiments of a method of manufacturing an insulated gate bipolar transistor according to the present application will be described in more detail below. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be appreciated that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, as shown in fig. 3, the above step S1 is performed: a drift layer 10 is provided on the substrate 110, the drift layer 10 having a second doping type.
Illustratively, the drift layer 10 and the substrate 110 formed in the step S1 are both N-type semiconductor layers, where the materials of the substrate 110 and the drift layer 10 are any one or more of Si, ge, and SiC, and the application is not specifically limited.
In some alternative embodiments, the process of forming the drift layer 10 on the substrate 110 in the step S1 is a deposition process such as Physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD), and those skilled in the art can reasonably select the process of forming the drift layer according to the specific situation.
After the step of forming the drift layer 10 in the above step S1, as shown in fig. 4 to 11, the above step S2 is performed: the first doped layer 20 is disposed on a side of the drift layer away from the substrate 110 such that the first doped layer 20 includes a first portion and a second portion with a first spacer region therebetween, the first spacer region being located on a side of the gate structure near the drift layer, and the first doped layer 20 having a first doping type.
In some alternative embodiments of the present application, the above-mentioned preparation method further includes a step of forming a third doped layer 30, as shown in fig. 4 to 11, the third doped layer 30 is disposed in the first spacer region and is in contact with the drift layer 10, and the third doped layer 30 has the second doping type.
The steps of forming the first doped layer 20 and the third doped layer 30 include: forming a first sub-doping preparation layer 2010 on a first surface of the drift layer 10; etching the first sub-doping preparation layer 2010 to form a first sub-doping layer 201 having a first spacing region, the first sub-doping layer 201 being divided into two parts by the first spacing region; forming a third doping layer 30 covering the drift layer 10 in the first spacer region; forming a second doping preparation layer 401 on the surfaces of the first sub-doping layer 201 and the third doping layer 30; etching the second doping preparation layer 401 to form a second interval region penetrating to the first sub-doping layer 201, wherein the projection of the second interval region on the first sub-doping layer 201 is positioned at two sides of the third doping layer 30; a second sub-doping layer 202 is formed in the second spacer region covering the first sub-doping layer 201, the first sub-doping layer 201 and the second sub-doping layer 202 constituting the first doping layer 20.
Specifically, the step of preparing the first doping layer 20 in the above step S2 may include: first, a first sub-doping preparation layer 2010 is deposited on the drift layer 10, as shown in fig. 4, and then the first sub-doping preparation layer 2010 is etched to form a first sub-doping layer 201 with a first interval region, as shown in fig. 5; depositing a third doping preparation layer 301 on the drift layer 10 so that a part of the third doping preparation layer 301 fills the first interval region as shown in fig. 6, and performing a thinning treatment on the third doping preparation layer 301 to remove a part of the third doping preparation layer 301 outside the first interval region to obtain a third doping layer 30 as shown in fig. 7; depositing a second doping preparation layer 401 on the surface of the third doping layer 30, as shown in fig. 8, and etching the second doping preparation layer 401 to form a second interval region, as shown in fig. 9; a second sub-doping preparation layer 2020 is deposited on the second doping preparation layer 401 such that a portion of the second sub-doping preparation layer 2020 fills the second spacer region as shown in fig. 10, and the second sub-doping preparation layer 2020 is subjected to a thinning process to obtain a second sub-doping layer 202 as shown in fig. 11. To this end, a first doped layer having a first sub-doped layer 201 and a second sub-doped layer 202 is formed.
In some alternative embodiments, the etching process includes coating photoresist on the first sub-doped layer 201 and the second doped preparation layer 401, selecting positions of the first interval region and the second interval region by using a mask plate, performing irradiation by ultraviolet light to make the exposed region undergo chemical reaction, dissolving and removing the photoresist corresponding to the exposed region by using a developing technology, using the remaining photoresist as a mask layer, and performing dry etching to form the first interval region and the second interval region.
In some alternative embodiments, the thinning process is any one or more of Chemical Mechanical Planarization (CMP) and etching, and the application is not specifically limited.
Illustratively, the first doped layer 20 formed in the step S2 is a P-type semiconductor layer, and the material of the first doped layer 20 is GaAs and SiC, but is not limited to the above-mentioned types, and the present application is not specifically limited.
After the step of forming the drift layer 10 in the above step S2, as shown in fig. 12 to 13, the above step S3 is performed: an emission layer 50 is provided on a side of the first doping layer 20 remote from the drift layer 10, and the emission layer 50 has a first doping type.
The step of preparing the emission layer 50 in the above step S3 may include: a preliminary emitter layer 501 is deposited on the second sub-doped layer 202, and the preliminary emitter layer 501 is etched to form an emitter layer 50, as shown in fig. 12.
Illustratively, the emission layer 50 formed in the above step S3 is a P-type semiconductor layer, and the material of the emission layer 50 is any one or more of GaAs and SiC, but is not limited to the above kind, and the present application is not specifically limited.
After the step of forming the drift layer in the step S3, as shown in fig. 13, the step S4 is performed: on the side of the first doped layer 20 remote from the substrate 110, a second doped layer 40 is formed in contact with the first doped layer 20, the projection of the second doped layer 40 onto the first doped layer 20 being located on both sides of the first spacer region, the second doped layer 40 having the second doping type.
In the process of forming the second doping layer 40 in the above-described step S4, the preliminary emission layer 501 formed in the step S3 and the second doping preliminary layer 401 formed in the step S4 need to be sequentially subjected to etching treatment to form the emission layer 50 and the second doping layer 40, as shown in fig. 13.
In some alternative embodiments, the etching process sequentially coats the photoresist on the preparation emission layer 501 and the second doping preparation layer 401, irradiates the mask plate with ultraviolet light to enable the exposure area to generate chemical reaction, dissolves and removes the photoresist corresponding to the exposure area by a developing technology, takes the rest of photoresist as the mask layer, and adopts dry etching to form the first interval area and the second interval area.
Illustratively, the second doped layer 40 formed in the above step S4 is an N-type semiconductor layer, and the material of the second doped layer 40 is any one or more of GaAs, gaN, and SiC, which are not specifically limited herein.
After the step of forming the drift layer in the above step S4, as shown in fig. 14 to 15, the above step S5 is performed: the gate structure 80 is disposed at a side of the first spacer region away from the drift layer 10 such that the gate structure 80 contacts the second doped layer 40 and the drift layer 10 has an exposed surface at a side thereof away from the first doped layer 20, and the collector layer 70 is disposed at a side of the drift layer 10 having an exposed surface.
Prior to the step of forming the gate structure 80 in step S5, the substrate 110 may be removed so that the drift layer 10 has an exposed surface, as shown in fig. 14, and a buffer layer 60 may be deposited on the exposed surface, and then a collector layer 70 may be deposited on the buffer layer 60, as shown in fig. 15.
In the step of forming the gate structure 80, a gate oxide layer 801 is deposited on the surface of the third doped layer 30, and then a gate electrode 802 is deposited on the gate oxide layer 801; after the step of forming the gate structure 80, an insulating layer 100 may also be deposited between the emitter layer 50 and the gate structure 80 and on the exposed surfaces of the emitter layer 50 and the first doped layer 20, as shown in fig. 1.
It should be noted that the step of removing the substrate 110 in the embodiment of the present application is not limited to being performed before the step of forming the gate structure 80, and may be performed after the step of forming the gate structure 80, for example, depositing the gate oxide layer 801 on the surface of the third doped layer 30, then depositing the gate electrode 802 on the gate oxide layer 801, and removing the substrate 110, so that the drift layer 10 has an exposed surface, and depositing the buffer layer 60 and the collector layer 70 sequentially on the exposed surface.
Exemplary, the gate electrode 802 formed in the above step S5 is an N-type polysilicon material, and the gate oxide layer 801 is SiO 2 However, the present invention is not limited to the above-mentioned types, and is not particularly limited.
In the above alternative embodiments, the deposition process may be a conventional deposition process such as Physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD), and those skilled in the art may reasonably select the deposition process according to actual needs, which is not specifically limited herein.
From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
1. the application provides an insulated gate bipolar transistor, wherein a collector layer, a drift layer, a gate structure, a first doping layer, a second doping layer and an emission layer are all epitaxial layers, so that the insulated gate bipolar transistor is different from a doping region formed by ion implantation in the traditional process of an IGBT, further the influence on other epitaxial structures in the ion implantation process is avoided, and the device performance is improved; by forming a conductive channel with a certain resistance by adopting the second doped layer to abut against the gate structure, when voltage is applied to the device, current can flow along the conductive channel and generate voltage drop, and the reverse voltage-withstanding function is realized.
2. The preparation method of the insulated gate bipolar transistor has the advantages that after the epitaxial layer is formed by ion implantation in the traditional IGBT process, if the thinning step is needed, the formed epitaxial layer needs to be protected to be thinned, and the insulated gate bipolar transistor can be thinned directly in the epitaxial preparation stage, so that the step of protecting and thinning the epitaxial layer formed after ion implantation is omitted, the manufacturing flow of the insulated gate bipolar transistor is simplified, and the production and manufacturing cost is reduced because special implantation equipment is not needed to be increased.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises an element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and changes may be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. which are within the spirit and principles of the present application are intended to be included within the scope of the claims of the present application.
Claims (6)
1. An insulated gate bipolar transistor, comprising:
a collector layer having a first doping type;
a drift layer disposed on one side of the collector layer, the drift layer having a second doping type;
the grid structure is arranged on one side of the drift layer, which is far away from the collector layer;
the first doping layer is arranged on one side, far away from the current collecting layer, of the drift layer in a contact mode, the first doping layer comprises a first part and a second part, a first interval area is arranged between the first part and the second part, the first interval area is arranged on one side, close to the drift layer, of the gate structure, and the first doping layer is of the first doping type;
the projection of the second doping layer on the first doping layer is positioned at two sides of the first interval region, and the second doping layer is respectively in contact with the gate structure and the first doping layer and has the second doping type;
an emission layer which is arranged on one side of the first doping layer far away from the drift layer in a contact way and has the first doping type;
a third doped layer disposed in the first spacer region and in contact with the drift layer, the third doped layer having the second doping type;
the first doped layer includes:
the first sub-doping layer is arranged on one side surface of the drift layer, which is far away from the current collecting layer, in a contact manner, and the first sub-doping layer is divided into two parts by the first interval region;
the second sub-doping layer is arranged on one side, far away from the drift layer, of the first sub-doping layer in a contact manner, and the second sub-doping layer is respectively in contact with the second doping layer and the emission layer;
the doping concentration of the second doping layer is larger than that of the third doping layer, and the doping concentration of the third doping layer is larger than that of the drift layer; the collector layer, the drift layer, the gate structure, the first doped layer, the second doped layer, and the emitter layer are epitaxial layers and are not formed by ion implantation; the lower surface of the second doped layer contacts the first sub-doped layer, and the second doped layer is not in contact with the emission layer.
2. The insulated gate bipolar transistor of claim 1 wherein the doping concentration of the emissive layer is greater than the doping concentration of the first doped layer.
3. The insulated gate bipolar transistor of claim 1 wherein the gate structure comprises a gate and a gate oxide layer, the gate oxide layer being located between the gate and the third doped layer, the gate having the second doping type and a doping concentration of the gate being greater than a doping concentration of the third doped layer.
4. A method of manufacturing an insulated gate bipolar transistor according to any one of claims 1 to 3, comprising the steps of:
providing a drift layer on a substrate, the drift layer having a second doping type;
a first doping layer is arranged on one side, far away from the substrate, of the drift layer, so that the first doping layer comprises a first part and a second part, a first interval region is arranged between the first part and the second part, the first interval region is positioned on one side, close to the drift layer, of the gate structure, and the first doping layer is of a first doping type;
an emission layer is arranged on one side, far away from the drift layer, of the first doping layer, and the emission layer is provided with the first doping type;
forming a second doped layer in contact with the first doped layer on one side of the drift layer away from the substrate, wherein the projection of the second doped layer on the first doped layer is positioned on two sides of the first interval region, and the second doped layer has the second doping type;
the grid structure is arranged on one side, far away from the drift layer, of the first interval region, so that the grid structure is in contact with the second doped layer, the side, far away from the first doped layer, of the drift layer is provided with an exposed surface, and the collector layer is arranged on the side, with the exposed surface, of the drift layer;
forming a third doped layer, the third doped layer being disposed in the first spacer region and in contact with the drift layer, and the third doped layer having the second doping type;
the step of forming the first doped layer and the third doped layer includes:
forming a first sub-doping preparation layer on a first surface of the drift layer;
etching the first sub-doping preparation layer to form a first sub-doping layer with the first interval region, wherein the first sub-doping layer is divided into two parts by the first interval region;
forming the third doping layer covering the drift layer in the first interval region;
forming a second doping preparation layer on the surfaces of the first sub-doping layer and the third doping layer;
etching the second doping preparation layer to form a second interval region penetrating to the first sub-doping layer, wherein the projection of the second interval region on the first sub-doping layer is positioned at two sides of the third doping layer;
forming a second sub-doping layer covering the first sub-doping layer in the second interval region, wherein the first sub-doping layer and the second sub-doping layer form the first doping layer;
forming the collector layer, the drift layer, the gate structure, the first doped layer, the second doped layer and the emitter layer by adopting an epitaxial process; the doping concentration of the second doping layer is larger than that of the third doping layer, and the doping concentration of the third doping layer is larger than that of the drift layer; the lower surface of the second doped layer contacts the first sub-doped layer, and the second doped layer is not in contact with the emission layer.
5. The method of manufacturing according to claim 4, wherein the step of forming the emission layer and the second doped layer includes:
forming a preliminary emission layer on surfaces of the second doping preliminary layer and the second sub-doping layer;
the preliminary emitter layer and the second doped preliminary layer are sequentially etched to form the emitter layer and the second doped layer.
6. The method of manufacturing of claim 5, wherein the step of forming the gate structure comprises:
the exposed surfaces of the third doping layer and the second doping layer are contacted with a covering gate oxide layer; and covering the grid electrode on the exposed surface of the grid oxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311149652.7A CN116884997B (en) | 2023-09-07 | 2023-09-07 | Insulated gate bipolar transistor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311149652.7A CN116884997B (en) | 2023-09-07 | 2023-09-07 | Insulated gate bipolar transistor and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116884997A CN116884997A (en) | 2023-10-13 |
| CN116884997B true CN116884997B (en) | 2023-12-22 |
Family
ID=88255474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311149652.7A Active CN116884997B (en) | 2023-09-07 | 2023-09-07 | Insulated gate bipolar transistor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116884997B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113506826A (en) * | 2021-06-17 | 2021-10-15 | 重庆伟特森电子科技有限公司 | Groove type silicon carbide transistor and preparation method thereof |
| CN115579397A (en) * | 2022-10-27 | 2023-01-06 | 深圳信息职业技术学院 | Two-stage trench gate silicon carbide MOSFET and preparation method thereof |
| CN115715428A (en) * | 2020-06-19 | 2023-02-24 | 沃孚半导体公司 | Power device with hybrid gate structure |
| CN116266611A (en) * | 2021-12-16 | 2023-06-20 | 株式会社电装 | Semiconductor device and method for manufacturing the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7989882B2 (en) * | 2007-12-07 | 2011-08-02 | Cree, Inc. | Transistor with A-face conductive channel and trench protecting well region |
-
2023
- 2023-09-07 CN CN202311149652.7A patent/CN116884997B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115715428A (en) * | 2020-06-19 | 2023-02-24 | 沃孚半导体公司 | Power device with hybrid gate structure |
| CN113506826A (en) * | 2021-06-17 | 2021-10-15 | 重庆伟特森电子科技有限公司 | Groove type silicon carbide transistor and preparation method thereof |
| CN116266611A (en) * | 2021-12-16 | 2023-06-20 | 株式会社电装 | Semiconductor device and method for manufacturing the same |
| CN115579397A (en) * | 2022-10-27 | 2023-01-06 | 深圳信息职业技术学院 | Two-stage trench gate silicon carbide MOSFET and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116884997A (en) | 2023-10-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4685297B2 (en) | Trench metal oxide semiconductor device and method of manufacturing termination structure | |
| JP5379045B2 (en) | Trench metal oxide semiconductor device | |
| JP6667893B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
| US20110012132A1 (en) | Semiconductor Device | |
| JPH1093087A (en) | Transverse gate longitudinal drift region transistor | |
| CN108538717A (en) | The method and system of Floating Guard are manufactured in GaN material | |
| CN104380458A (en) | Method and system for junction termination in gallium nitride materials using conductivity modulation | |
| KR100883795B1 (en) | Symmetric trench mosfet device and method of making same | |
| CN107464837B (en) | Super junction power device | |
| US8809946B2 (en) | Wide trench termination structure for semiconductor device | |
| CN111048420A (en) | Method for manufacturing lateral double-diffused transistor | |
| US10615079B2 (en) | Semiconductor device and method for manufacturing the same | |
| US20210134989A1 (en) | Semiconductor device and method of manufacturing thereof | |
| US7948031B2 (en) | Semiconductor device and method of fabricating semiconductor device | |
| US20150255629A1 (en) | Semiconductor device | |
| CN116884997B (en) | Insulated gate bipolar transistor and preparation method thereof | |
| WO2023183215A1 (en) | Support shield structures for trenched semiconductor devices | |
| US6150671A (en) | Semiconductor device having high channel mobility and a high breakdown voltage for high power applications | |
| US20220181504A1 (en) | Semiconductor device and production method for semiconductor device | |
| CN113972261A (en) | Silicon carbide semiconductor device and preparation method | |
| TWI466302B (en) | Mos diode with termination structure and method for manufacturing the same | |
| CN107895738B (en) | Well local high-doping MOS device and preparation method thereof | |
| US9728599B1 (en) | Semiconductor device | |
| JPH11145155A (en) | Method for manufacturing power semiconductor device using semi-insulating polysilicon (sipos) film | |
| JP2004146465A (en) | Silicon carbide semiconductor device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |